microblaze: s3adsp: Instantiate CPU using QOM
[qemu/ar7.git] / hw / microblaze / petalogix_s3adsp1800_mmu.c
blob4dbbd1e5d225173409e70a4de76f5401ccf828e7
1 /*
2 * Model of Petalogix linux reference design targeting Xilinx Spartan 3ADSP-1800
3 * boards.
5 * Copyright (c) 2009 Edgar E. Iglesias.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
26 #include "hw/sysbus.h"
27 #include "hw/hw.h"
28 #include "net/net.h"
29 #include "hw/block/flash.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/devices.h"
32 #include "hw/boards.h"
33 #include "sysemu/block-backend.h"
34 #include "exec/address-spaces.h"
36 #include "boot.h"
38 #define LMB_BRAM_SIZE (128 * 1024)
39 #define FLASH_SIZE (16 * 1024 * 1024)
41 #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
43 #define MEMORY_BASEADDR 0x90000000
44 #define FLASH_BASEADDR 0xa0000000
45 #define INTC_BASEADDR 0x81800000
46 #define TIMER_BASEADDR 0x83c00000
47 #define UARTLITE_BASEADDR 0x84000000
48 #define ETHLITE_BASEADDR 0x81000000
50 #define TIMER_IRQ 0
51 #define ETHLITE_IRQ 1
52 #define UARTLITE_IRQ 3
54 static void machine_cpu_reset(MicroBlazeCPU *cpu)
56 CPUMBState *env = &cpu->env;
58 env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
61 static void
62 petalogix_s3adsp1800_init(MachineState *machine)
64 ram_addr_t ram_size = machine->ram_size;
65 DeviceState *dev;
66 MicroBlazeCPU *cpu;
67 DriveInfo *dinfo;
68 int i;
69 hwaddr ddr_base = MEMORY_BASEADDR;
70 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
71 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
72 qemu_irq irq[32];
73 MemoryRegion *sysmem = get_system_memory();
75 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
76 object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
78 /* Attach emulated BRAM through the LMB. */
79 memory_region_init_ram(phys_lmb_bram, NULL,
80 "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE,
81 &error_abort);
82 vmstate_register_ram_global(phys_lmb_bram);
83 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
85 memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram",
86 ram_size, &error_abort);
87 vmstate_register_ram_global(phys_ram);
88 memory_region_add_subregion(sysmem, ddr_base, phys_ram);
90 dinfo = drive_get(IF_PFLASH, 0, 0);
91 pflash_cfi01_register(FLASH_BASEADDR,
92 NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
93 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
94 (64 * 1024), FLASH_SIZE >> 16,
95 1, 0x89, 0x18, 0x0000, 0x0, 1);
97 dev = qdev_create(NULL, "xlnx.xps-intc");
98 qdev_prop_set_uint32(dev, "kind-of-intr",
99 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
100 qdev_init_nofail(dev);
101 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
102 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
103 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
104 for (i = 0; i < 32; i++) {
105 irq[i] = qdev_get_gpio_in(dev, i);
108 sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR,
109 irq[UARTLITE_IRQ]);
111 /* 2 timers at irq 2 @ 62 Mhz. */
112 dev = qdev_create(NULL, "xlnx.xps-timer");
113 qdev_prop_set_uint32(dev, "one-timer-only", 0);
114 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
115 qdev_init_nofail(dev);
116 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
117 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
119 qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
120 dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
121 qdev_set_nic_properties(dev, &nd_table[0]);
122 qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
123 qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
124 qdev_init_nofail(dev);
125 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
126 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
128 microblaze_load_kernel(cpu, ddr_base, ram_size,
129 machine->initrd_filename,
130 BINARY_DEVICE_TREE_FILE,
131 machine_cpu_reset);
134 static QEMUMachine petalogix_s3adsp1800_machine = {
135 .name = "petalogix-s3adsp1800",
136 .desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800",
137 .init = petalogix_s3adsp1800_init,
138 .is_default = 1,
141 static void petalogix_s3adsp1800_machine_init(void)
143 qemu_register_machine(&petalogix_s3adsp1800_machine);
146 machine_init(petalogix_s3adsp1800_machine_init);