2 * MicroBlaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "qemu/host-utils.h"
27 #if defined(CONFIG_USER_ONLY)
29 void mb_cpu_do_interrupt(CPUState
*cs
)
31 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
32 CPUMBState
*env
= &cpu
->env
;
34 cs
->exception_index
= -1;
35 env
->res_addr
= RES_ADDR_NONE
;
36 env
->regs
[14] = env
->sregs
[SR_PC
];
39 int mb_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
42 cs
->exception_index
= 0xaa;
43 cpu_dump_state(cs
, stderr
, fprintf
, 0);
47 #else /* !CONFIG_USER_ONLY */
49 int mb_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
52 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
53 CPUMBState
*env
= &cpu
->env
;
55 unsigned int mmu_available
;
60 if (cpu
->cfg
.use_mmu
) {
62 if ((cpu
->cfg
.pvr
== C_PVR_FULL
) &&
63 (env
->pvr
.regs
[11] & PVR11_USE_MMU
) != PVR11_USE_MMU
) {
68 /* Translate if the MMU is available and enabled. */
69 if (mmu_available
&& (env
->sregs
[SR_MSR
] & MSR_VM
)) {
70 target_ulong vaddr
, paddr
;
71 struct microblaze_mmu_lookup lu
;
73 hit
= mmu_translate(&env
->mmu
, &lu
, address
, rw
, mmu_idx
);
75 vaddr
= address
& TARGET_PAGE_MASK
;
76 paddr
= lu
.paddr
+ vaddr
- lu
.vaddr
;
78 qemu_log_mask(CPU_LOG_MMU
, "MMU map mmu=%d v=%x p=%x prot=%x\n",
79 mmu_idx
, vaddr
, paddr
, lu
.prot
);
80 tlb_set_page(cs
, vaddr
, paddr
, lu
.prot
, mmu_idx
, TARGET_PAGE_SIZE
);
83 env
->sregs
[SR_EAR
] = address
;
84 qemu_log_mask(CPU_LOG_MMU
, "mmu=%d miss v=%" VADDR_PRIx
"\n",
89 env
->sregs
[SR_ESR
] = rw
== 2 ? 17 : 16;
90 env
->sregs
[SR_ESR
] |= (rw
== 1) << 10;
93 env
->sregs
[SR_ESR
] = rw
== 2 ? 19 : 18;
94 env
->sregs
[SR_ESR
] |= (rw
== 1) << 10;
101 if (cs
->exception_index
== EXCP_MMU
) {
102 cpu_abort(cs
, "recursive faults\n");
106 cs
->exception_index
= EXCP_MMU
;
109 /* MMU disabled or not available. */
110 address
&= TARGET_PAGE_MASK
;
112 tlb_set_page(cs
, address
, address
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
118 void mb_cpu_do_interrupt(CPUState
*cs
)
120 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
121 CPUMBState
*env
= &cpu
->env
;
124 /* IMM flag cannot propagate across a branch and into the dslot. */
125 assert(!((env
->iflags
& D_FLAG
) && (env
->iflags
& IMM_FLAG
)));
126 assert(!(env
->iflags
& (DRTI_FLAG
| DRTE_FLAG
| DRTB_FLAG
)));
127 /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
128 env
->res_addr
= RES_ADDR_NONE
;
129 switch (cs
->exception_index
) {
131 if (!(env
->pvr
.regs
[0] & PVR0_USE_EXC_MASK
)) {
132 qemu_log_mask(LOG_GUEST_ERROR
, "Exception raised on system without exceptions!\n");
136 env
->regs
[17] = env
->sregs
[SR_PC
] + 4;
137 env
->sregs
[SR_ESR
] &= ~(1 << 12);
139 /* Exception breaks branch + dslot sequence? */
140 if (env
->iflags
& D_FLAG
) {
141 env
->sregs
[SR_ESR
] |= 1 << 12 ;
142 env
->sregs
[SR_BTR
] = env
->btarget
;
145 /* Disable the MMU. */
146 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
147 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM
| MSR_UM
);
148 env
->sregs
[SR_MSR
] |= t
;
149 /* Exception in progress. */
150 env
->sregs
[SR_MSR
] |= MSR_EIP
;
152 qemu_log_mask(CPU_LOG_INT
,
153 "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
154 env
->sregs
[SR_PC
], env
->sregs
[SR_EAR
],
155 env
->sregs
[SR_ESR
], env
->iflags
);
156 log_cpu_state_mask(CPU_LOG_INT
, cs
, 0);
157 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
158 env
->sregs
[SR_PC
] = cpu
->cfg
.base_vectors
+ 0x20;
162 env
->regs
[17] = env
->sregs
[SR_PC
];
164 env
->sregs
[SR_ESR
] &= ~(1 << 12);
165 /* Exception breaks branch + dslot sequence? */
166 if (env
->iflags
& D_FLAG
) {
167 D(qemu_log("D_FLAG set at exception bimm=%d\n", env
->bimm
));
168 env
->sregs
[SR_ESR
] |= 1 << 12 ;
169 env
->sregs
[SR_BTR
] = env
->btarget
;
171 /* Reexecute the branch. */
173 /* was the branch immprefixed?. */
175 qemu_log_mask(CPU_LOG_INT
,
176 "bimm exception at pc=%x iflags=%x\n",
177 env
->sregs
[SR_PC
], env
->iflags
);
179 log_cpu_state_mask(CPU_LOG_INT
, cs
, 0);
181 } else if (env
->iflags
& IMM_FLAG
) {
182 D(qemu_log("IMM_FLAG set at exception\n"));
186 /* Disable the MMU. */
187 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
188 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM
| MSR_UM
);
189 env
->sregs
[SR_MSR
] |= t
;
190 /* Exception in progress. */
191 env
->sregs
[SR_MSR
] |= MSR_EIP
;
193 qemu_log_mask(CPU_LOG_INT
,
194 "exception at pc=%x ear=%x iflags=%x\n",
195 env
->sregs
[SR_PC
], env
->sregs
[SR_EAR
], env
->iflags
);
196 log_cpu_state_mask(CPU_LOG_INT
, cs
, 0);
197 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
198 env
->sregs
[SR_PC
] = cpu
->cfg
.base_vectors
+ 0x20;
202 assert(!(env
->sregs
[SR_MSR
] & (MSR_EIP
| MSR_BIP
)));
203 assert(env
->sregs
[SR_MSR
] & MSR_IE
);
204 assert(!(env
->iflags
& D_FLAG
));
206 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
209 #include "disas/disas.h"
211 /* Useful instrumentation when debugging interrupt issues in either
212 the models or in sw. */
216 sym
= lookup_symbol(env
->sregs
[SR_PC
]);
218 && (!strcmp("netif_rx", sym
)
219 || !strcmp("process_backlog", sym
))) {
222 "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
223 env
->sregs
[SR_PC
], env
->sregs
[SR_MSR
], t
, env
->iflags
,
226 log_cpu_state(cs
, 0);
230 qemu_log_mask(CPU_LOG_INT
,
231 "interrupt at pc=%x msr=%x %x iflags=%x\n",
232 env
->sregs
[SR_PC
], env
->sregs
[SR_MSR
], t
, env
->iflags
);
234 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM \
236 env
->sregs
[SR_MSR
] |= t
;
238 env
->regs
[14] = env
->sregs
[SR_PC
];
239 env
->sregs
[SR_PC
] = cpu
->cfg
.base_vectors
+ 0x10;
240 //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
245 assert(!(env
->iflags
& IMM_FLAG
));
246 assert(!(env
->iflags
& D_FLAG
));
247 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
248 qemu_log_mask(CPU_LOG_INT
,
249 "break at pc=%x msr=%x %x iflags=%x\n",
250 env
->sregs
[SR_PC
], env
->sregs
[SR_MSR
], t
, env
->iflags
);
251 log_cpu_state_mask(CPU_LOG_INT
, cs
, 0);
252 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM
| MSR_UM
);
253 env
->sregs
[SR_MSR
] |= t
;
254 env
->sregs
[SR_MSR
] |= MSR_BIP
;
255 if (cs
->exception_index
== EXCP_HW_BREAK
) {
256 env
->regs
[16] = env
->sregs
[SR_PC
];
257 env
->sregs
[SR_MSR
] |= MSR_BIP
;
258 env
->sregs
[SR_PC
] = cpu
->cfg
.base_vectors
+ 0x18;
260 env
->sregs
[SR_PC
] = env
->btarget
;
263 cpu_abort(cs
, "unhandled exception type=%d\n",
264 cs
->exception_index
);
269 hwaddr
mb_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
271 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
272 CPUMBState
*env
= &cpu
->env
;
273 target_ulong vaddr
, paddr
= 0;
274 struct microblaze_mmu_lookup lu
;
277 if (env
->sregs
[SR_MSR
] & MSR_VM
) {
278 hit
= mmu_translate(&env
->mmu
, &lu
, addr
, 0, 0);
280 vaddr
= addr
& TARGET_PAGE_MASK
;
281 paddr
= lu
.paddr
+ vaddr
- lu
.vaddr
;
283 paddr
= 0; /* ???. */
285 paddr
= addr
& TARGET_PAGE_MASK
;
291 bool mb_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
293 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
294 CPUMBState
*env
= &cpu
->env
;
296 if ((interrupt_request
& CPU_INTERRUPT_HARD
)
297 && (env
->sregs
[SR_MSR
] & MSR_IE
)
298 && !(env
->sregs
[SR_MSR
] & (MSR_EIP
| MSR_BIP
))
299 && !(env
->iflags
& (D_FLAG
| IMM_FLAG
))) {
300 cs
->exception_index
= EXCP_IRQ
;
301 mb_cpu_do_interrupt(cs
);