4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
5 * Copyright (c) 2016-2020 BALATON Zoltan
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "qemu/units.h"
28 #include "qapi/error.h"
30 #include "qemu/module.h"
31 #include "hw/char/serial.h"
32 #include "ui/console.h"
33 #include "hw/sysbus.h"
34 #include "migration/vmstate.h"
35 #include "hw/pci/pci.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/i2c/i2c.h"
38 #include "hw/display/i2c-ddc.h"
39 #include "qemu/range.h"
40 #include "ui/pixel_ops.h"
41 #include "qemu/bswap.h"
44 #define MMIO_BASE_OFFSET 0x3e00000
45 #define MMIO_SIZE 0x200000
46 #define DC_PALETTE_ENTRIES (0x400 * 3)
48 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
50 /* System Configuration area */
51 /* System config base */
52 #define SM501_SYS_CONFIG (0x000000)
55 #define SM501_SYSTEM_CONTROL (0x000000)
57 #define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
58 #define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
59 #define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
61 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
62 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
63 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
64 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
65 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
67 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
68 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
69 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
70 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
72 /* miscellaneous control */
74 #define SM501_MISC_CONTROL (0x000004)
76 #define SM501_MISC_BUS_SH (0x0)
77 #define SM501_MISC_BUS_PCI (0x1)
78 #define SM501_MISC_BUS_XSCALE (0x2)
79 #define SM501_MISC_BUS_NEC (0x6)
80 #define SM501_MISC_BUS_MASK (0x7)
82 #define SM501_MISC_VR_62MB (1 << 3)
83 #define SM501_MISC_CDR_RESET (1 << 7)
84 #define SM501_MISC_USB_LB (1 << 8)
85 #define SM501_MISC_USB_SLAVE (1 << 9)
86 #define SM501_MISC_BL_1 (1 << 10)
87 #define SM501_MISC_MC (1 << 11)
88 #define SM501_MISC_DAC_POWER (1 << 12)
89 #define SM501_MISC_IRQ_INVERT (1 << 16)
90 #define SM501_MISC_SH (1 << 17)
92 #define SM501_MISC_HOLD_EMPTY (0 << 18)
93 #define SM501_MISC_HOLD_8 (1 << 18)
94 #define SM501_MISC_HOLD_16 (2 << 18)
95 #define SM501_MISC_HOLD_24 (3 << 18)
96 #define SM501_MISC_HOLD_32 (4 << 18)
97 #define SM501_MISC_HOLD_MASK (7 << 18)
99 #define SM501_MISC_FREQ_12 (1 << 24)
100 #define SM501_MISC_PNL_24BIT (1 << 25)
101 #define SM501_MISC_8051_LE (1 << 26)
105 #define SM501_GPIO31_0_CONTROL (0x000008)
106 #define SM501_GPIO63_32_CONTROL (0x00000C)
107 #define SM501_DRAM_CONTROL (0x000010)
110 #define SM501_ARBTRTN_CONTROL (0x000014)
113 #define SM501_COMMAND_LIST_STATUS (0x000024)
115 /* interrupt debug */
116 #define SM501_RAW_IRQ_STATUS (0x000028)
117 #define SM501_RAW_IRQ_CLEAR (0x000028)
118 #define SM501_IRQ_STATUS (0x00002C)
119 #define SM501_IRQ_MASK (0x000030)
120 #define SM501_DEBUG_CONTROL (0x000034)
122 /* power management */
123 #define SM501_POWERMODE_P2X_SRC (1 << 29)
124 #define SM501_POWERMODE_V2X_SRC (1 << 20)
125 #define SM501_POWERMODE_M_SRC (1 << 12)
126 #define SM501_POWERMODE_M1_SRC (1 << 4)
128 #define SM501_CURRENT_GATE (0x000038)
129 #define SM501_CURRENT_CLOCK (0x00003C)
130 #define SM501_POWER_MODE_0_GATE (0x000040)
131 #define SM501_POWER_MODE_0_CLOCK (0x000044)
132 #define SM501_POWER_MODE_1_GATE (0x000048)
133 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
134 #define SM501_SLEEP_MODE_GATE (0x000050)
135 #define SM501_POWER_MODE_CONTROL (0x000054)
137 /* power gates for units within the 501 */
138 #define SM501_GATE_HOST (0)
139 #define SM501_GATE_MEMORY (1)
140 #define SM501_GATE_DISPLAY (2)
141 #define SM501_GATE_2D_ENGINE (3)
142 #define SM501_GATE_CSC (4)
143 #define SM501_GATE_ZVPORT (5)
144 #define SM501_GATE_GPIO (6)
145 #define SM501_GATE_UART0 (7)
146 #define SM501_GATE_UART1 (8)
147 #define SM501_GATE_SSP (10)
148 #define SM501_GATE_USB_HOST (11)
149 #define SM501_GATE_USB_GADGET (12)
150 #define SM501_GATE_UCONTROLLER (17)
151 #define SM501_GATE_AC97 (18)
154 #define SM501_CLOCK_P2XCLK (24)
156 #define SM501_CLOCK_V2XCLK (16)
158 #define SM501_CLOCK_MCLK (8)
159 /* SDRAM controller clock */
160 #define SM501_CLOCK_M1XCLK (0)
163 #define SM501_PCI_MASTER_BASE (0x000058)
164 #define SM501_ENDIAN_CONTROL (0x00005C)
165 #define SM501_DEVICEID (0x000060)
168 #define SM501_DEVICEID_SM501 (0x05010000)
169 #define SM501_DEVICEID_IDMASK (0xffff0000)
170 #define SM501_DEVICEID_REVMASK (0x000000ff)
172 #define SM501_PLLCLOCK_COUNT (0x000064)
173 #define SM501_MISC_TIMING (0x000068)
174 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
176 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
179 #define SM501_GPIO (0x010000)
180 #define SM501_GPIO_DATA_LOW (0x00)
181 #define SM501_GPIO_DATA_HIGH (0x04)
182 #define SM501_GPIO_DDR_LOW (0x08)
183 #define SM501_GPIO_DDR_HIGH (0x0C)
184 #define SM501_GPIO_IRQ_SETUP (0x10)
185 #define SM501_GPIO_IRQ_STATUS (0x14)
186 #define SM501_GPIO_IRQ_RESET (0x14)
188 /* I2C controller base */
189 #define SM501_I2C (0x010040)
190 #define SM501_I2C_BYTE_COUNT (0x00)
191 #define SM501_I2C_CONTROL (0x01)
192 #define SM501_I2C_STATUS (0x02)
193 #define SM501_I2C_RESET (0x02)
194 #define SM501_I2C_SLAVE_ADDRESS (0x03)
195 #define SM501_I2C_DATA (0x04)
197 #define SM501_I2C_CONTROL_START (1 << 2)
198 #define SM501_I2C_CONTROL_ENABLE (1 << 0)
200 #define SM501_I2C_STATUS_COMPLETE (1 << 3)
201 #define SM501_I2C_STATUS_ERROR (1 << 2)
203 #define SM501_I2C_RESET_ERROR (1 << 2)
206 #define SM501_SSP (0x020000)
209 #define SM501_UART0 (0x030000)
212 #define SM501_UART1 (0x030020)
214 /* USB host port base */
215 #define SM501_USB_HOST (0x040000)
217 /* USB slave/gadget base */
218 #define SM501_USB_GADGET (0x060000)
220 /* USB slave/gadget data port base */
221 #define SM501_USB_GADGET_DATA (0x070000)
223 /* Display controller/video engine base */
224 #define SM501_DC (0x080000)
226 /* common defines for the SM501 address registers */
227 #define SM501_ADDR_FLIP (1 << 31)
228 #define SM501_ADDR_EXT (1 << 27)
229 #define SM501_ADDR_CS1 (1 << 26)
230 #define SM501_ADDR_MASK (0x3f << 26)
232 #define SM501_FIFO_MASK (0x3 << 16)
233 #define SM501_FIFO_1 (0x0 << 16)
234 #define SM501_FIFO_3 (0x1 << 16)
235 #define SM501_FIFO_7 (0x2 << 16)
236 #define SM501_FIFO_11 (0x3 << 16)
238 /* common registers for panel and the crt */
239 #define SM501_OFF_DC_H_TOT (0x000)
240 #define SM501_OFF_DC_V_TOT (0x008)
241 #define SM501_OFF_DC_H_SYNC (0x004)
242 #define SM501_OFF_DC_V_SYNC (0x00C)
244 #define SM501_DC_PANEL_CONTROL (0x000)
246 #define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
247 #define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
248 #define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
249 #define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
250 #define SM501_DC_PANEL_CONTROL_DP (1 << 23)
252 #define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
253 #define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
254 #define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
256 #define SM501_DC_PANEL_CONTROL_DE (1 << 20)
258 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
259 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
260 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
262 #define SM501_DC_PANEL_CONTROL_CP (1 << 14)
263 #define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
264 #define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
265 #define SM501_DC_PANEL_CONTROL_CK (1 << 9)
266 #define SM501_DC_PANEL_CONTROL_TE (1 << 8)
267 #define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
268 #define SM501_DC_PANEL_CONTROL_VP (1 << 6)
269 #define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
270 #define SM501_DC_PANEL_CONTROL_HP (1 << 4)
271 #define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
272 #define SM501_DC_PANEL_CONTROL_EN (1 << 2)
274 #define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
275 #define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
276 #define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
279 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
280 #define SM501_DC_PANEL_COLOR_KEY (0x008)
281 #define SM501_DC_PANEL_FB_ADDR (0x00C)
282 #define SM501_DC_PANEL_FB_OFFSET (0x010)
283 #define SM501_DC_PANEL_FB_WIDTH (0x014)
284 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
285 #define SM501_DC_PANEL_TL_LOC (0x01C)
286 #define SM501_DC_PANEL_BR_LOC (0x020)
287 #define SM501_DC_PANEL_H_TOT (0x024)
288 #define SM501_DC_PANEL_H_SYNC (0x028)
289 #define SM501_DC_PANEL_V_TOT (0x02C)
290 #define SM501_DC_PANEL_V_SYNC (0x030)
291 #define SM501_DC_PANEL_CUR_LINE (0x034)
293 #define SM501_DC_VIDEO_CONTROL (0x040)
294 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
295 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
296 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
297 #define SM501_DC_VIDEO_TL_LOC (0x050)
298 #define SM501_DC_VIDEO_BR_LOC (0x054)
299 #define SM501_DC_VIDEO_SCALE (0x058)
300 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
301 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
302 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
303 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
305 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
306 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
307 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
308 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
309 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
310 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
311 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
312 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
313 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
314 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
316 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
317 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
318 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
319 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
320 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
322 #define SM501_HWC_EN (1 << 31)
324 #define SM501_OFF_HWC_ADDR (0x00)
325 #define SM501_OFF_HWC_LOC (0x04)
326 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
327 #define SM501_OFF_HWC_COLOR_3 (0x0C)
329 #define SM501_DC_ALPHA_CONTROL (0x100)
330 #define SM501_DC_ALPHA_FB_ADDR (0x104)
331 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
332 #define SM501_DC_ALPHA_TL_LOC (0x10C)
333 #define SM501_DC_ALPHA_BR_LOC (0x110)
334 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
335 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
337 #define SM501_DC_CRT_CONTROL (0x200)
339 #define SM501_DC_CRT_CONTROL_TVP (1 << 15)
340 #define SM501_DC_CRT_CONTROL_CP (1 << 14)
341 #define SM501_DC_CRT_CONTROL_VSP (1 << 13)
342 #define SM501_DC_CRT_CONTROL_HSP (1 << 12)
343 #define SM501_DC_CRT_CONTROL_VS (1 << 11)
344 #define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
345 #define SM501_DC_CRT_CONTROL_SEL (1 << 9)
346 #define SM501_DC_CRT_CONTROL_TE (1 << 8)
347 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
348 #define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
349 #define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
351 #define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
352 #define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
353 #define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
355 #define SM501_DC_CRT_FB_ADDR (0x204)
356 #define SM501_DC_CRT_FB_OFFSET (0x208)
357 #define SM501_DC_CRT_H_TOT (0x20C)
358 #define SM501_DC_CRT_H_SYNC (0x210)
359 #define SM501_DC_CRT_V_TOT (0x214)
360 #define SM501_DC_CRT_V_SYNC (0x218)
361 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
362 #define SM501_DC_CRT_CUR_LINE (0x220)
363 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
365 #define SM501_DC_CRT_HWC_BASE (0x230)
366 #define SM501_DC_CRT_HWC_ADDR (0x230)
367 #define SM501_DC_CRT_HWC_LOC (0x234)
368 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
369 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
371 #define SM501_DC_PANEL_PALETTE (0x400)
373 #define SM501_DC_VIDEO_PALETTE (0x800)
375 #define SM501_DC_CRT_PALETTE (0xC00)
377 /* Zoom Video port base */
378 #define SM501_ZVPORT (0x090000)
381 #define SM501_AC97 (0x0A0000)
383 /* 8051 micro controller base */
384 #define SM501_UCONTROLLER (0x0B0000)
386 /* 8051 micro controller SRAM base */
387 #define SM501_UCONTROLLER_SRAM (0x0C0000)
390 #define SM501_DMA (0x0D0000)
393 #define SM501_2D_ENGINE (0x100000)
394 #define SM501_2D_SOURCE (0x00)
395 #define SM501_2D_DESTINATION (0x04)
396 #define SM501_2D_DIMENSION (0x08)
397 #define SM501_2D_CONTROL (0x0C)
398 #define SM501_2D_PITCH (0x10)
399 #define SM501_2D_FOREGROUND (0x14)
400 #define SM501_2D_BACKGROUND (0x18)
401 #define SM501_2D_STRETCH (0x1C)
402 #define SM501_2D_COLOR_COMPARE (0x20)
403 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
404 #define SM501_2D_MASK (0x28)
405 #define SM501_2D_CLIP_TL (0x2C)
406 #define SM501_2D_CLIP_BR (0x30)
407 #define SM501_2D_MONO_PATTERN_LOW (0x34)
408 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
409 #define SM501_2D_WINDOW_WIDTH (0x3C)
410 #define SM501_2D_SOURCE_BASE (0x40)
411 #define SM501_2D_DESTINATION_BASE (0x44)
412 #define SM501_2D_ALPHA (0x48)
413 #define SM501_2D_WRAP (0x4C)
414 #define SM501_2D_STATUS (0x50)
416 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
417 #define SM501_CSC_CONSTANTS (0xCC)
418 #define SM501_CSC_Y_SOURCE_X (0xD0)
419 #define SM501_CSC_Y_SOURCE_Y (0xD4)
420 #define SM501_CSC_U_SOURCE_BASE (0xD8)
421 #define SM501_CSC_V_SOURCE_BASE (0xDC)
422 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
423 #define SM501_CSC_SOURCE_PITCH (0xE4)
424 #define SM501_CSC_DESTINATION (0xE8)
425 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
426 #define SM501_CSC_DESTINATION_PITCH (0xF0)
427 #define SM501_CSC_SCALE_FACTOR (0xF4)
428 #define SM501_CSC_DESTINATION_BASE (0xF8)
429 #define SM501_CSC_CONTROL (0xFC)
431 /* 2d engine data port base */
432 #define SM501_2D_ENGINE_DATA (0x110000)
434 /* end of register definitions */
436 #define SM501_HWC_WIDTH (64)
437 #define SM501_HWC_HEIGHT (64)
439 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
440 static const uint32_t sm501_mem_local_size
[] = {
448 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
450 typedef struct SM501State
{
451 /* graphic console status */
454 /* status & internal resources */
455 uint32_t local_mem_size_index
;
457 MemoryRegion local_mem_region
;
458 MemoryRegion mmio_region
;
459 MemoryRegion system_config_region
;
460 MemoryRegion i2c_region
;
461 MemoryRegion disp_ctrl_region
;
462 MemoryRegion twoD_engine_region
;
464 uint32_t last_height
;
465 bool do_full_update
; /* perform a full update next time */
469 uint32_t system_control
;
470 uint32_t misc_control
;
471 uint32_t gpio_31_0_control
;
472 uint32_t gpio_63_32_control
;
473 uint32_t dram_control
;
474 uint32_t arbitration_control
;
476 uint32_t misc_timing
;
477 uint32_t power_mode_control
;
479 uint8_t i2c_byte_count
;
482 uint8_t i2c_data
[16];
489 uint8_t dc_palette
[DC_PALETTE_ENTRIES
];
491 uint32_t dc_panel_control
;
492 uint32_t dc_panel_panning_control
;
493 uint32_t dc_panel_fb_addr
;
494 uint32_t dc_panel_fb_offset
;
495 uint32_t dc_panel_fb_width
;
496 uint32_t dc_panel_fb_height
;
497 uint32_t dc_panel_tl_location
;
498 uint32_t dc_panel_br_location
;
499 uint32_t dc_panel_h_total
;
500 uint32_t dc_panel_h_sync
;
501 uint32_t dc_panel_v_total
;
502 uint32_t dc_panel_v_sync
;
504 uint32_t dc_panel_hwc_addr
;
505 uint32_t dc_panel_hwc_location
;
506 uint32_t dc_panel_hwc_color_1_2
;
507 uint32_t dc_panel_hwc_color_3
;
509 uint32_t dc_video_control
;
511 uint32_t dc_crt_control
;
512 uint32_t dc_crt_fb_addr
;
513 uint32_t dc_crt_fb_offset
;
514 uint32_t dc_crt_h_total
;
515 uint32_t dc_crt_h_sync
;
516 uint32_t dc_crt_v_total
;
517 uint32_t dc_crt_v_sync
;
519 uint32_t dc_crt_hwc_addr
;
520 uint32_t dc_crt_hwc_location
;
521 uint32_t dc_crt_hwc_color_1_2
;
522 uint32_t dc_crt_hwc_color_3
;
524 uint32_t twoD_source
;
525 uint32_t twoD_destination
;
526 uint32_t twoD_dimension
;
527 uint32_t twoD_control
;
529 uint32_t twoD_foreground
;
530 uint32_t twoD_background
;
531 uint32_t twoD_stretch
;
532 uint32_t twoD_color_compare
;
533 uint32_t twoD_color_compare_mask
;
535 uint32_t twoD_clip_tl
;
536 uint32_t twoD_clip_br
;
537 uint32_t twoD_mono_pattern_low
;
538 uint32_t twoD_mono_pattern_high
;
539 uint32_t twoD_window_width
;
540 uint32_t twoD_source_base
;
541 uint32_t twoD_destination_base
;
546 static uint32_t get_local_mem_size_index(uint32_t size
)
548 uint32_t norm_size
= 0;
551 for (i
= 0; i
< ARRAY_SIZE(sm501_mem_local_size
); i
++) {
552 uint32_t new_size
= sm501_mem_local_size
[i
];
553 if (new_size
>= size
) {
554 if (norm_size
== 0 || norm_size
> new_size
) {
555 norm_size
= new_size
;
564 static ram_addr_t
get_fb_addr(SM501State
*s
, int crt
)
566 return (crt
? s
->dc_crt_fb_addr
: s
->dc_panel_fb_addr
) & 0x3FFFFF0;
569 static inline int get_width(SM501State
*s
, int crt
)
571 int width
= crt
? s
->dc_crt_h_total
: s
->dc_panel_h_total
;
572 return (width
& 0x00000FFF) + 1;
575 static inline int get_height(SM501State
*s
, int crt
)
577 int height
= crt
? s
->dc_crt_v_total
: s
->dc_panel_v_total
;
578 return (height
& 0x00000FFF) + 1;
581 static inline int get_bpp(SM501State
*s
, int crt
)
583 int bpp
= crt
? s
->dc_crt_control
: s
->dc_panel_control
;
584 return 1 << (bpp
& 3);
588 * Check the availability of hardware cursor.
589 * @param crt 0 for PANEL, 1 for CRT.
591 static inline int is_hwc_enabled(SM501State
*state
, int crt
)
593 uint32_t addr
= crt
? state
->dc_crt_hwc_addr
: state
->dc_panel_hwc_addr
;
594 return addr
& SM501_HWC_EN
;
598 * Get the address which holds cursor pattern data.
599 * @param crt 0 for PANEL, 1 for CRT.
601 static inline uint8_t *get_hwc_address(SM501State
*state
, int crt
)
603 uint32_t addr
= crt
? state
->dc_crt_hwc_addr
: state
->dc_panel_hwc_addr
;
604 return state
->local_mem
+ (addr
& 0x03FFFFF0);
608 * Get the cursor position in y coordinate.
609 * @param crt 0 for PANEL, 1 for CRT.
611 static inline uint32_t get_hwc_y(SM501State
*state
, int crt
)
613 uint32_t location
= crt
? state
->dc_crt_hwc_location
614 : state
->dc_panel_hwc_location
;
615 return (location
& 0x07FF0000) >> 16;
619 * Get the cursor position in x coordinate.
620 * @param crt 0 for PANEL, 1 for CRT.
622 static inline uint32_t get_hwc_x(SM501State
*state
, int crt
)
624 uint32_t location
= crt
? state
->dc_crt_hwc_location
625 : state
->dc_panel_hwc_location
;
626 return location
& 0x000007FF;
630 * Get the hardware cursor palette.
631 * @param crt 0 for PANEL, 1 for CRT.
632 * @param palette pointer to a [3 * 3] array to store color values in
634 static inline void get_hwc_palette(SM501State
*state
, int crt
, uint8_t *palette
)
640 for (i
= 0; i
< 3; i
++) {
642 color_reg
= crt
? state
->dc_crt_hwc_color_3
643 : state
->dc_panel_hwc_color_3
;
645 color_reg
= crt
? state
->dc_crt_hwc_color_1_2
646 : state
->dc_panel_hwc_color_1_2
;
650 rgb565
= (color_reg
>> 16) & 0xFFFF;
652 rgb565
= color_reg
& 0xFFFF;
654 palette
[i
* 3 + 0] = ((rgb565
>> 11) * 527 + 23) >> 6; /* r */
655 palette
[i
* 3 + 1] = (((rgb565
>> 5) & 0x3f) * 259 + 33) >> 6; /* g */
656 palette
[i
* 3 + 2] = ((rgb565
& 0x1f) * 527 + 23) >> 6; /* b */
660 static inline void hwc_invalidate(SM501State
*s
, int crt
)
662 int w
= get_width(s
, crt
);
663 int h
= get_height(s
, crt
);
664 int bpp
= get_bpp(s
, crt
);
665 int start
= get_hwc_y(s
, crt
);
666 int end
= MIN(h
, start
+ SM501_HWC_HEIGHT
) + 1;
671 memory_region_set_dirty(&s
->local_mem_region
,
672 get_fb_addr(s
, crt
) + start
, end
- start
);
675 static void sm501_2d_operation(SM501State
*s
)
677 int cmd
= (s
->twoD_control
>> 16) & 0x1F;
678 int rtl
= s
->twoD_control
& BIT(27);
679 int format
= (s
->twoD_stretch
>> 20) & 3;
680 int bypp
= 1 << format
; /* bytes per pixel */
681 int rop_mode
= (s
->twoD_control
>> 15) & 1; /* 1 for rop2, else rop3 */
682 /* 1 if rop2 source is the pattern, otherwise the source is the bitmap */
683 int rop2_source_is_pattern
= (s
->twoD_control
>> 14) & 1;
684 int rop
= s
->twoD_control
& 0xFF;
685 unsigned int dst_x
= (s
->twoD_destination
>> 16) & 0x01FFF;
686 unsigned int dst_y
= s
->twoD_destination
& 0xFFFF;
687 unsigned int width
= (s
->twoD_dimension
>> 16) & 0x1FFF;
688 unsigned int height
= s
->twoD_dimension
& 0xFFFF;
689 uint32_t dst_base
= s
->twoD_destination_base
& 0x03FFFFFF;
690 unsigned int dst_pitch
= (s
->twoD_pitch
>> 16) & 0x1FFF;
691 int crt
= (s
->dc_crt_control
& SM501_DC_CRT_CONTROL_SEL
) ? 1 : 0;
692 int fb_len
= get_width(s
, crt
) * get_height(s
, crt
) * get_bpp(s
, crt
);
694 if ((s
->twoD_stretch
>> 16) & 0xF) {
695 qemu_log_mask(LOG_UNIMP
, "sm501: only XY addressing is supported.\n");
699 if (s
->twoD_source_base
& BIT(27) || s
->twoD_destination_base
& BIT(27)) {
700 qemu_log_mask(LOG_UNIMP
, "sm501: only local memory is supported.\n");
705 qemu_log_mask(LOG_GUEST_ERROR
, "sm501: Zero dest pitch.\n");
709 if (!width
|| !height
) {
710 qemu_log_mask(LOG_GUEST_ERROR
, "sm501: Zero size 2D op.\n");
719 if (dst_base
>= get_local_mem_size(s
) ||
720 dst_base
+ (dst_x
+ width
+ (dst_y
+ height
) * dst_pitch
) * bypp
>=
721 get_local_mem_size(s
)) {
722 qemu_log_mask(LOG_GUEST_ERROR
, "sm501: 2D op dest is outside vram.\n");
729 static uint32_t tmp_buf
[16384];
730 unsigned int src_x
= (s
->twoD_source
>> 16) & 0x01FFF;
731 unsigned int src_y
= s
->twoD_source
& 0xFFFF;
732 uint32_t src_base
= s
->twoD_source_base
& 0x03FFFFFF;
733 unsigned int src_pitch
= s
->twoD_pitch
& 0x1FFF;
736 qemu_log_mask(LOG_GUEST_ERROR
, "sm501: Zero src pitch.\n");
745 if (src_base
>= get_local_mem_size(s
) ||
746 src_base
+ (src_x
+ width
+ (src_y
+ height
) * src_pitch
) * bypp
>=
747 get_local_mem_size(s
)) {
748 qemu_log_mask(LOG_GUEST_ERROR
,
749 "sm501: 2D op src is outside vram.\n");
753 if ((rop_mode
&& rop
== 0x5) || (!rop_mode
&& rop
== 0x55)) {
754 /* Invert dest, is there a way to do this with pixman? */
755 unsigned int x
, y
, i
;
756 uint8_t *d
= s
->local_mem
+ dst_base
;
758 for (y
= 0; y
< height
; y
++) {
759 i
= (dst_x
+ (dst_y
+ y
) * dst_pitch
) * bypp
;
760 for (x
= 0; x
< width
; x
++, i
+= bypp
) {
761 stn_he_p(&d
[i
], bypp
, ~ldn_he_p(&d
[i
], bypp
));
765 /* Do copy src for unimplemented ops, better than unpainted area */
766 if ((rop_mode
&& (rop
!= 0xc || rop2_source_is_pattern
)) ||
767 (!rop_mode
&& rop
!= 0xcc)) {
768 qemu_log_mask(LOG_UNIMP
,
769 "sm501: rop%d op %x%s not implemented\n",
770 (rop_mode
? 2 : 3), rop
,
771 (rop2_source_is_pattern
?
772 " with pattern source" : ""));
774 /* Ignore no-op blits, some guests seem to do this */
775 if (src_base
== dst_base
&& src_pitch
== dst_pitch
&&
776 src_x
== dst_x
&& src_y
== dst_y
) {
779 /* Some clients also do 1 pixel blits, avoid overhead for these */
780 if (width
== 1 && height
== 1) {
781 unsigned int si
= (src_x
+ src_y
* src_pitch
) * bypp
;
782 unsigned int di
= (dst_x
+ dst_y
* dst_pitch
) * bypp
;
783 stn_he_p(&s
->local_mem
[dst_base
+ di
], bypp
,
784 ldn_he_p(&s
->local_mem
[src_base
+ si
], bypp
));
787 /* Check for overlaps, this could be made more exact */
788 uint32_t sb
, se
, db
, de
;
789 sb
= src_base
+ src_x
+ src_y
* (width
+ src_pitch
);
790 se
= sb
+ width
+ height
* (width
+ src_pitch
);
791 db
= dst_base
+ dst_x
+ dst_y
* (width
+ dst_pitch
);
792 de
= db
+ width
+ height
* (width
+ dst_pitch
);
793 if (rtl
&& ((db
>= sb
&& db
<= se
) || (de
>= sb
&& de
<= se
))) {
794 /* regions may overlap: copy via temporary */
795 int llb
= width
* bypp
;
796 int tmp_stride
= DIV_ROUND_UP(llb
, sizeof(uint32_t));
797 uint32_t *tmp
= tmp_buf
;
799 if (tmp_stride
* sizeof(uint32_t) * height
> sizeof(tmp_buf
)) {
800 tmp
= g_malloc(tmp_stride
* sizeof(uint32_t) * height
);
802 pixman_blt((uint32_t *)&s
->local_mem
[src_base
], tmp
,
803 src_pitch
* bypp
/ sizeof(uint32_t),
804 tmp_stride
, 8 * bypp
, 8 * bypp
,
805 src_x
, src_y
, 0, 0, width
, height
);
806 pixman_blt(tmp
, (uint32_t *)&s
->local_mem
[dst_base
],
808 dst_pitch
* bypp
/ sizeof(uint32_t),
810 0, 0, dst_x
, dst_y
, width
, height
);
811 if (tmp
!= tmp_buf
) {
815 pixman_blt((uint32_t *)&s
->local_mem
[src_base
],
816 (uint32_t *)&s
->local_mem
[dst_base
],
817 src_pitch
* bypp
/ sizeof(uint32_t),
818 dst_pitch
* bypp
/ sizeof(uint32_t),
820 src_x
, src_y
, dst_x
, dst_y
, width
, height
);
825 case 1: /* Rectangle Fill */
827 uint32_t color
= s
->twoD_foreground
;
830 color
= cpu_to_le32(color
);
831 } else if (format
== 1) {
832 color
= cpu_to_le16(color
);
835 if (width
== 1 && height
== 1) {
836 unsigned int i
= (dst_x
+ dst_y
* dst_pitch
) * bypp
;
837 stn_he_p(&s
->local_mem
[dst_base
+ i
], bypp
, color
);
839 pixman_fill((uint32_t *)&s
->local_mem
[dst_base
],
840 dst_pitch
* bypp
/ sizeof(uint32_t),
841 8 * bypp
, dst_x
, dst_y
, width
, height
, color
);
846 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented 2D operation: %d\n",
851 if (dst_base
>= get_fb_addr(s
, crt
) &&
852 dst_base
<= get_fb_addr(s
, crt
) + fb_len
) {
853 int dst_len
= MIN(fb_len
, ((dst_y
+ height
- 1) * dst_pitch
+
854 dst_x
+ width
) * bypp
);
856 memory_region_set_dirty(&s
->local_mem_region
, dst_base
, dst_len
);
861 static uint64_t sm501_system_config_read(void *opaque
, hwaddr addr
,
864 SM501State
*s
= (SM501State
*)opaque
;
868 case SM501_SYSTEM_CONTROL
:
869 ret
= s
->system_control
;
871 case SM501_MISC_CONTROL
:
872 ret
= s
->misc_control
;
874 case SM501_GPIO31_0_CONTROL
:
875 ret
= s
->gpio_31_0_control
;
877 case SM501_GPIO63_32_CONTROL
:
878 ret
= s
->gpio_63_32_control
;
883 case SM501_DRAM_CONTROL
:
884 ret
= (s
->dram_control
& 0x07F107C0) | s
->local_mem_size_index
<< 13;
886 case SM501_ARBTRTN_CONTROL
:
887 ret
= s
->arbitration_control
;
889 case SM501_COMMAND_LIST_STATUS
:
890 ret
= 0x00180002; /* FIFOs are empty, everything idle */
895 case SM501_MISC_TIMING
:
896 /* TODO : simulate gate control */
897 ret
= s
->misc_timing
;
899 case SM501_CURRENT_GATE
:
900 /* TODO : simulate gate control */
903 case SM501_CURRENT_CLOCK
:
906 case SM501_POWER_MODE_CONTROL
:
907 ret
= s
->power_mode_control
;
909 case SM501_ENDIAN_CONTROL
:
910 ret
= 0; /* Only default little endian mode is supported */
914 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented system config"
915 "register read. addr=%" HWADDR_PRIx
"\n", addr
);
917 trace_sm501_system_config_read(addr
, ret
);
921 static void sm501_system_config_write(void *opaque
, hwaddr addr
,
922 uint64_t value
, unsigned size
)
924 SM501State
*s
= (SM501State
*)opaque
;
926 trace_sm501_system_config_write((uint32_t)addr
, (uint32_t)value
);
928 case SM501_SYSTEM_CONTROL
:
929 s
->system_control
&= 0x10DB0000;
930 s
->system_control
|= value
& 0xEF00B8F7;
932 case SM501_MISC_CONTROL
:
933 s
->misc_control
&= 0xEF;
934 s
->misc_control
|= value
& 0xFF7FFF10;
936 case SM501_GPIO31_0_CONTROL
:
937 s
->gpio_31_0_control
= value
;
939 case SM501_GPIO63_32_CONTROL
:
940 s
->gpio_63_32_control
= value
& 0xFF80FFFF;
942 case SM501_DRAM_CONTROL
:
943 s
->local_mem_size_index
= (value
>> 13) & 0x7;
944 /* TODO : check validity of size change */
945 s
->dram_control
&= 0x80000000;
946 s
->dram_control
|= value
& 0x7FFFFFC3;
948 case SM501_ARBTRTN_CONTROL
:
949 s
->arbitration_control
= value
& 0x37777777;
952 s
->irq_mask
= value
& 0xFFDF3F5F;
954 case SM501_MISC_TIMING
:
955 s
->misc_timing
= value
& 0xF31F1FFF;
957 case SM501_POWER_MODE_0_GATE
:
958 case SM501_POWER_MODE_1_GATE
:
959 case SM501_POWER_MODE_0_CLOCK
:
960 case SM501_POWER_MODE_1_CLOCK
:
961 /* TODO : simulate gate & clock control */
963 case SM501_POWER_MODE_CONTROL
:
964 s
->power_mode_control
= value
& 0x00000003;
966 case SM501_ENDIAN_CONTROL
:
967 if (value
& 0x00000001) {
968 qemu_log_mask(LOG_UNIMP
, "sm501: system config big endian mode not"
974 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented system config"
975 "register write. addr=%" HWADDR_PRIx
976 ", val=%" PRIx64
"\n", addr
, value
);
980 static const MemoryRegionOps sm501_system_config_ops
= {
981 .read
= sm501_system_config_read
,
982 .write
= sm501_system_config_write
,
984 .min_access_size
= 4,
985 .max_access_size
= 4,
987 .endianness
= DEVICE_LITTLE_ENDIAN
,
990 static uint64_t sm501_i2c_read(void *opaque
, hwaddr addr
, unsigned size
)
992 SM501State
*s
= (SM501State
*)opaque
;
996 case SM501_I2C_BYTE_COUNT
:
997 ret
= s
->i2c_byte_count
;
999 case SM501_I2C_STATUS
:
1000 ret
= s
->i2c_status
;
1002 case SM501_I2C_SLAVE_ADDRESS
:
1005 case SM501_I2C_DATA
... SM501_I2C_DATA
+ 15:
1006 ret
= s
->i2c_data
[addr
- SM501_I2C_DATA
];
1009 qemu_log_mask(LOG_UNIMP
, "sm501 i2c : not implemented register read."
1010 " addr=0x%" HWADDR_PRIx
"\n", addr
);
1012 trace_sm501_i2c_read((uint32_t)addr
, ret
);
1016 static void sm501_i2c_write(void *opaque
, hwaddr addr
, uint64_t value
,
1019 SM501State
*s
= (SM501State
*)opaque
;
1021 trace_sm501_i2c_write((uint32_t)addr
, (uint32_t)value
);
1023 case SM501_I2C_BYTE_COUNT
:
1024 s
->i2c_byte_count
= value
& 0xf;
1026 case SM501_I2C_CONTROL
:
1027 if (value
& SM501_I2C_CONTROL_ENABLE
) {
1028 if (value
& SM501_I2C_CONTROL_START
) {
1029 int res
= i2c_start_transfer(s
->i2c_bus
,
1032 s
->i2c_status
|= (res
? SM501_I2C_STATUS_ERROR
: 0);
1035 for (i
= 0; i
<= s
->i2c_byte_count
; i
++) {
1036 res
= i2c_send_recv(s
->i2c_bus
, &s
->i2c_data
[i
],
1037 !(s
->i2c_addr
& 1));
1039 s
->i2c_status
|= SM501_I2C_STATUS_ERROR
;
1044 s
->i2c_status
= SM501_I2C_STATUS_COMPLETE
;
1048 i2c_end_transfer(s
->i2c_bus
);
1049 s
->i2c_status
&= ~SM501_I2C_STATUS_ERROR
;
1053 case SM501_I2C_RESET
:
1054 if ((value
& SM501_I2C_RESET_ERROR
) == 0) {
1055 s
->i2c_status
&= ~SM501_I2C_STATUS_ERROR
;
1058 case SM501_I2C_SLAVE_ADDRESS
:
1059 s
->i2c_addr
= value
& 0xff;
1061 case SM501_I2C_DATA
... SM501_I2C_DATA
+ 15:
1062 s
->i2c_data
[addr
- SM501_I2C_DATA
] = value
& 0xff;
1065 qemu_log_mask(LOG_UNIMP
, "sm501 i2c : not implemented register write. "
1066 "addr=0x%" HWADDR_PRIx
" val=%" PRIx64
"\n", addr
, value
);
1070 static const MemoryRegionOps sm501_i2c_ops
= {
1071 .read
= sm501_i2c_read
,
1072 .write
= sm501_i2c_write
,
1074 .min_access_size
= 1,
1075 .max_access_size
= 1,
1078 .min_access_size
= 1,
1079 .max_access_size
= 1,
1081 .endianness
= DEVICE_LITTLE_ENDIAN
,
1084 static uint32_t sm501_palette_read(void *opaque
, hwaddr addr
)
1086 SM501State
*s
= (SM501State
*)opaque
;
1088 trace_sm501_palette_read((uint32_t)addr
);
1090 /* TODO : consider BYTE/WORD access */
1091 /* TODO : consider endian */
1093 assert(range_covers_byte(0, 0x400 * 3, addr
));
1094 return *(uint32_t *)&s
->dc_palette
[addr
];
1097 static void sm501_palette_write(void *opaque
, hwaddr addr
,
1100 SM501State
*s
= (SM501State
*)opaque
;
1102 trace_sm501_palette_write((uint32_t)addr
, value
);
1104 /* TODO : consider BYTE/WORD access */
1105 /* TODO : consider endian */
1107 assert(range_covers_byte(0, 0x400 * 3, addr
));
1108 *(uint32_t *)&s
->dc_palette
[addr
] = value
;
1109 s
->do_full_update
= true;
1112 static uint64_t sm501_disp_ctrl_read(void *opaque
, hwaddr addr
,
1115 SM501State
*s
= (SM501State
*)opaque
;
1120 case SM501_DC_PANEL_CONTROL
:
1121 ret
= s
->dc_panel_control
;
1123 case SM501_DC_PANEL_PANNING_CONTROL
:
1124 ret
= s
->dc_panel_panning_control
;
1126 case SM501_DC_PANEL_COLOR_KEY
:
1127 /* Not implemented yet */
1129 case SM501_DC_PANEL_FB_ADDR
:
1130 ret
= s
->dc_panel_fb_addr
;
1132 case SM501_DC_PANEL_FB_OFFSET
:
1133 ret
= s
->dc_panel_fb_offset
;
1135 case SM501_DC_PANEL_FB_WIDTH
:
1136 ret
= s
->dc_panel_fb_width
;
1138 case SM501_DC_PANEL_FB_HEIGHT
:
1139 ret
= s
->dc_panel_fb_height
;
1141 case SM501_DC_PANEL_TL_LOC
:
1142 ret
= s
->dc_panel_tl_location
;
1144 case SM501_DC_PANEL_BR_LOC
:
1145 ret
= s
->dc_panel_br_location
;
1148 case SM501_DC_PANEL_H_TOT
:
1149 ret
= s
->dc_panel_h_total
;
1151 case SM501_DC_PANEL_H_SYNC
:
1152 ret
= s
->dc_panel_h_sync
;
1154 case SM501_DC_PANEL_V_TOT
:
1155 ret
= s
->dc_panel_v_total
;
1157 case SM501_DC_PANEL_V_SYNC
:
1158 ret
= s
->dc_panel_v_sync
;
1161 case SM501_DC_PANEL_HWC_ADDR
:
1162 ret
= s
->dc_panel_hwc_addr
;
1164 case SM501_DC_PANEL_HWC_LOC
:
1165 ret
= s
->dc_panel_hwc_location
;
1167 case SM501_DC_PANEL_HWC_COLOR_1_2
:
1168 ret
= s
->dc_panel_hwc_color_1_2
;
1170 case SM501_DC_PANEL_HWC_COLOR_3
:
1171 ret
= s
->dc_panel_hwc_color_3
;
1174 case SM501_DC_VIDEO_CONTROL
:
1175 ret
= s
->dc_video_control
;
1178 case SM501_DC_CRT_CONTROL
:
1179 ret
= s
->dc_crt_control
;
1181 case SM501_DC_CRT_FB_ADDR
:
1182 ret
= s
->dc_crt_fb_addr
;
1184 case SM501_DC_CRT_FB_OFFSET
:
1185 ret
= s
->dc_crt_fb_offset
;
1187 case SM501_DC_CRT_H_TOT
:
1188 ret
= s
->dc_crt_h_total
;
1190 case SM501_DC_CRT_H_SYNC
:
1191 ret
= s
->dc_crt_h_sync
;
1193 case SM501_DC_CRT_V_TOT
:
1194 ret
= s
->dc_crt_v_total
;
1196 case SM501_DC_CRT_V_SYNC
:
1197 ret
= s
->dc_crt_v_sync
;
1200 case SM501_DC_CRT_HWC_ADDR
:
1201 ret
= s
->dc_crt_hwc_addr
;
1203 case SM501_DC_CRT_HWC_LOC
:
1204 ret
= s
->dc_crt_hwc_location
;
1206 case SM501_DC_CRT_HWC_COLOR_1_2
:
1207 ret
= s
->dc_crt_hwc_color_1_2
;
1209 case SM501_DC_CRT_HWC_COLOR_3
:
1210 ret
= s
->dc_crt_hwc_color_3
;
1213 case SM501_DC_PANEL_PALETTE
... SM501_DC_PANEL_PALETTE
+ 0x400 * 3 - 4:
1214 ret
= sm501_palette_read(opaque
, addr
- SM501_DC_PANEL_PALETTE
);
1218 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented disp ctrl register "
1219 "read. addr=%" HWADDR_PRIx
"\n", addr
);
1221 trace_sm501_disp_ctrl_read((uint32_t)addr
, ret
);
1225 static void sm501_disp_ctrl_write(void *opaque
, hwaddr addr
,
1226 uint64_t value
, unsigned size
)
1228 SM501State
*s
= (SM501State
*)opaque
;
1230 trace_sm501_disp_ctrl_write((uint32_t)addr
, (uint32_t)value
);
1232 case SM501_DC_PANEL_CONTROL
:
1233 s
->dc_panel_control
= value
& 0x0FFF73FF;
1235 case SM501_DC_PANEL_PANNING_CONTROL
:
1236 s
->dc_panel_panning_control
= value
& 0xFF3FFF3F;
1238 case SM501_DC_PANEL_COLOR_KEY
:
1239 /* Not implemented yet */
1241 case SM501_DC_PANEL_FB_ADDR
:
1242 s
->dc_panel_fb_addr
= value
& 0x8FFFFFF0;
1243 if (value
& 0x8000000) {
1244 qemu_log_mask(LOG_UNIMP
, "Panel external memory not supported\n");
1246 s
->do_full_update
= true;
1248 case SM501_DC_PANEL_FB_OFFSET
:
1249 s
->dc_panel_fb_offset
= value
& 0x3FF03FF0;
1251 case SM501_DC_PANEL_FB_WIDTH
:
1252 s
->dc_panel_fb_width
= value
& 0x0FFF0FFF;
1254 case SM501_DC_PANEL_FB_HEIGHT
:
1255 s
->dc_panel_fb_height
= value
& 0x0FFF0FFF;
1257 case SM501_DC_PANEL_TL_LOC
:
1258 s
->dc_panel_tl_location
= value
& 0x07FF07FF;
1260 case SM501_DC_PANEL_BR_LOC
:
1261 s
->dc_panel_br_location
= value
& 0x07FF07FF;
1264 case SM501_DC_PANEL_H_TOT
:
1265 s
->dc_panel_h_total
= value
& 0x0FFF0FFF;
1267 case SM501_DC_PANEL_H_SYNC
:
1268 s
->dc_panel_h_sync
= value
& 0x00FF0FFF;
1270 case SM501_DC_PANEL_V_TOT
:
1271 s
->dc_panel_v_total
= value
& 0x0FFF0FFF;
1273 case SM501_DC_PANEL_V_SYNC
:
1274 s
->dc_panel_v_sync
= value
& 0x003F0FFF;
1277 case SM501_DC_PANEL_HWC_ADDR
:
1278 value
&= 0x8FFFFFF0;
1279 if (value
!= s
->dc_panel_hwc_addr
) {
1280 hwc_invalidate(s
, 0);
1281 s
->dc_panel_hwc_addr
= value
;
1284 case SM501_DC_PANEL_HWC_LOC
:
1285 value
&= 0x0FFF0FFF;
1286 if (value
!= s
->dc_panel_hwc_location
) {
1287 hwc_invalidate(s
, 0);
1288 s
->dc_panel_hwc_location
= value
;
1291 case SM501_DC_PANEL_HWC_COLOR_1_2
:
1292 s
->dc_panel_hwc_color_1_2
= value
;
1294 case SM501_DC_PANEL_HWC_COLOR_3
:
1295 s
->dc_panel_hwc_color_3
= value
& 0x0000FFFF;
1298 case SM501_DC_VIDEO_CONTROL
:
1299 s
->dc_video_control
= value
& 0x00037FFF;
1302 case SM501_DC_CRT_CONTROL
:
1303 s
->dc_crt_control
= value
& 0x0003FFFF;
1305 case SM501_DC_CRT_FB_ADDR
:
1306 s
->dc_crt_fb_addr
= value
& 0x8FFFFFF0;
1307 if (value
& 0x8000000) {
1308 qemu_log_mask(LOG_UNIMP
, "CRT external memory not supported\n");
1310 s
->do_full_update
= true;
1312 case SM501_DC_CRT_FB_OFFSET
:
1313 s
->dc_crt_fb_offset
= value
& 0x3FF03FF0;
1315 case SM501_DC_CRT_H_TOT
:
1316 s
->dc_crt_h_total
= value
& 0x0FFF0FFF;
1318 case SM501_DC_CRT_H_SYNC
:
1319 s
->dc_crt_h_sync
= value
& 0x00FF0FFF;
1321 case SM501_DC_CRT_V_TOT
:
1322 s
->dc_crt_v_total
= value
& 0x0FFF0FFF;
1324 case SM501_DC_CRT_V_SYNC
:
1325 s
->dc_crt_v_sync
= value
& 0x003F0FFF;
1328 case SM501_DC_CRT_HWC_ADDR
:
1329 value
&= 0x8FFFFFF0;
1330 if (value
!= s
->dc_crt_hwc_addr
) {
1331 hwc_invalidate(s
, 1);
1332 s
->dc_crt_hwc_addr
= value
;
1335 case SM501_DC_CRT_HWC_LOC
:
1336 value
&= 0x0FFF0FFF;
1337 if (value
!= s
->dc_crt_hwc_location
) {
1338 hwc_invalidate(s
, 1);
1339 s
->dc_crt_hwc_location
= value
;
1342 case SM501_DC_CRT_HWC_COLOR_1_2
:
1343 s
->dc_crt_hwc_color_1_2
= value
;
1345 case SM501_DC_CRT_HWC_COLOR_3
:
1346 s
->dc_crt_hwc_color_3
= value
& 0x0000FFFF;
1349 case SM501_DC_PANEL_PALETTE
... SM501_DC_PANEL_PALETTE
+ 0x400 * 3 - 4:
1350 sm501_palette_write(opaque
, addr
- SM501_DC_PANEL_PALETTE
, value
);
1354 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented disp ctrl register "
1355 "write. addr=%" HWADDR_PRIx
1356 ", val=%" PRIx64
"\n", addr
, value
);
1360 static const MemoryRegionOps sm501_disp_ctrl_ops
= {
1361 .read
= sm501_disp_ctrl_read
,
1362 .write
= sm501_disp_ctrl_write
,
1364 .min_access_size
= 4,
1365 .max_access_size
= 4,
1367 .endianness
= DEVICE_LITTLE_ENDIAN
,
1370 static uint64_t sm501_2d_engine_read(void *opaque
, hwaddr addr
,
1373 SM501State
*s
= (SM501State
*)opaque
;
1377 case SM501_2D_SOURCE
:
1378 ret
= s
->twoD_source
;
1380 case SM501_2D_DESTINATION
:
1381 ret
= s
->twoD_destination
;
1383 case SM501_2D_DIMENSION
:
1384 ret
= s
->twoD_dimension
;
1386 case SM501_2D_CONTROL
:
1387 ret
= s
->twoD_control
;
1389 case SM501_2D_PITCH
:
1390 ret
= s
->twoD_pitch
;
1392 case SM501_2D_FOREGROUND
:
1393 ret
= s
->twoD_foreground
;
1395 case SM501_2D_BACKGROUND
:
1396 ret
= s
->twoD_background
;
1398 case SM501_2D_STRETCH
:
1399 ret
= s
->twoD_stretch
;
1401 case SM501_2D_COLOR_COMPARE
:
1402 ret
= s
->twoD_color_compare
;
1404 case SM501_2D_COLOR_COMPARE_MASK
:
1405 ret
= s
->twoD_color_compare_mask
;
1410 case SM501_2D_CLIP_TL
:
1411 ret
= s
->twoD_clip_tl
;
1413 case SM501_2D_CLIP_BR
:
1414 ret
= s
->twoD_clip_br
;
1416 case SM501_2D_MONO_PATTERN_LOW
:
1417 ret
= s
->twoD_mono_pattern_low
;
1419 case SM501_2D_MONO_PATTERN_HIGH
:
1420 ret
= s
->twoD_mono_pattern_high
;
1422 case SM501_2D_WINDOW_WIDTH
:
1423 ret
= s
->twoD_window_width
;
1425 case SM501_2D_SOURCE_BASE
:
1426 ret
= s
->twoD_source_base
;
1428 case SM501_2D_DESTINATION_BASE
:
1429 ret
= s
->twoD_destination_base
;
1431 case SM501_2D_ALPHA
:
1432 ret
= s
->twoD_alpha
;
1437 case SM501_2D_STATUS
:
1438 ret
= 0; /* Should return interrupt status */
1441 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented disp ctrl register "
1442 "read. addr=%" HWADDR_PRIx
"\n", addr
);
1444 trace_sm501_2d_engine_read((uint32_t)addr
, ret
);
1448 static void sm501_2d_engine_write(void *opaque
, hwaddr addr
,
1449 uint64_t value
, unsigned size
)
1451 SM501State
*s
= (SM501State
*)opaque
;
1453 trace_sm501_2d_engine_write((uint32_t)addr
, (uint32_t)value
);
1455 case SM501_2D_SOURCE
:
1456 s
->twoD_source
= value
;
1458 case SM501_2D_DESTINATION
:
1459 s
->twoD_destination
= value
;
1461 case SM501_2D_DIMENSION
:
1462 s
->twoD_dimension
= value
;
1464 case SM501_2D_CONTROL
:
1465 s
->twoD_control
= value
;
1467 /* do 2d operation if start flag is set. */
1468 if (value
& 0x80000000) {
1469 sm501_2d_operation(s
);
1470 s
->twoD_control
&= ~0x80000000; /* start flag down */
1474 case SM501_2D_PITCH
:
1475 s
->twoD_pitch
= value
;
1477 case SM501_2D_FOREGROUND
:
1478 s
->twoD_foreground
= value
;
1480 case SM501_2D_BACKGROUND
:
1481 s
->twoD_background
= value
;
1483 case SM501_2D_STRETCH
:
1484 if (((value
>> 20) & 3) == 3) {
1487 s
->twoD_stretch
= value
;
1489 case SM501_2D_COLOR_COMPARE
:
1490 s
->twoD_color_compare
= value
;
1492 case SM501_2D_COLOR_COMPARE_MASK
:
1493 s
->twoD_color_compare_mask
= value
;
1496 s
->twoD_mask
= value
;
1498 case SM501_2D_CLIP_TL
:
1499 s
->twoD_clip_tl
= value
;
1501 case SM501_2D_CLIP_BR
:
1502 s
->twoD_clip_br
= value
;
1504 case SM501_2D_MONO_PATTERN_LOW
:
1505 s
->twoD_mono_pattern_low
= value
;
1507 case SM501_2D_MONO_PATTERN_HIGH
:
1508 s
->twoD_mono_pattern_high
= value
;
1510 case SM501_2D_WINDOW_WIDTH
:
1511 s
->twoD_window_width
= value
;
1513 case SM501_2D_SOURCE_BASE
:
1514 s
->twoD_source_base
= value
;
1516 case SM501_2D_DESTINATION_BASE
:
1517 s
->twoD_destination_base
= value
;
1519 case SM501_2D_ALPHA
:
1520 s
->twoD_alpha
= value
;
1523 s
->twoD_wrap
= value
;
1525 case SM501_2D_STATUS
:
1526 /* ignored, writing 0 should clear interrupt status */
1529 qemu_log_mask(LOG_UNIMP
, "sm501: not implemented 2d engine register "
1530 "write. addr=%" HWADDR_PRIx
1531 ", val=%" PRIx64
"\n", addr
, value
);
1535 static const MemoryRegionOps sm501_2d_engine_ops
= {
1536 .read
= sm501_2d_engine_read
,
1537 .write
= sm501_2d_engine_write
,
1539 .min_access_size
= 4,
1540 .max_access_size
= 4,
1542 .endianness
= DEVICE_LITTLE_ENDIAN
,
1545 /* draw line functions for all console modes */
1547 typedef void draw_line_func(uint8_t *d
, const uint8_t *s
,
1548 int width
, const uint32_t *pal
);
1550 typedef void draw_hwc_line_func(uint8_t *d
, const uint8_t *s
,
1551 int width
, const uint8_t *palette
,
1555 #include "sm501_template.h"
1558 #include "sm501_template.h"
1562 #include "sm501_template.h"
1565 #include "sm501_template.h"
1569 #include "sm501_template.h"
1572 #include "sm501_template.h"
1576 #include "sm501_template.h"
1578 static draw_line_func
*draw_line8_funcs
[] = {
1588 static draw_line_func
*draw_line16_funcs
[] = {
1598 static draw_line_func
*draw_line32_funcs
[] = {
1608 static draw_hwc_line_func
*draw_hwc_line_funcs
[] = {
1613 draw_hwc_line_32bgr
,
1614 draw_hwc_line_15bgr
,
1615 draw_hwc_line_16bgr
,
1618 static inline int get_depth_index(DisplaySurface
*surface
)
1620 switch (surface_bits_per_pixel(surface
)) {
1629 if (is_surface_bgr(surface
)) {
1637 static void sm501_update_display(void *opaque
)
1639 SM501State
*s
= (SM501State
*)opaque
;
1640 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1641 DirtyBitmapSnapshot
*snap
;
1642 int y
, c_x
= 0, c_y
= 0;
1643 int crt
= (s
->dc_crt_control
& SM501_DC_CRT_CONTROL_SEL
) ? 1 : 0;
1644 int width
= get_width(s
, crt
);
1645 int height
= get_height(s
, crt
);
1646 int src_bpp
= get_bpp(s
, crt
);
1647 int dst_bpp
= surface_bytes_per_pixel(surface
);
1648 int dst_depth_index
= get_depth_index(surface
);
1649 draw_line_func
*draw_line
= NULL
;
1650 draw_hwc_line_func
*draw_hwc_line
= NULL
;
1651 int full_update
= 0;
1655 uint8_t hwc_palette
[3 * 3];
1656 uint8_t *hwc_src
= NULL
;
1658 if (!((crt
? s
->dc_crt_control
: s
->dc_panel_control
)
1659 & SM501_DC_CRT_CONTROL_ENABLE
)) {
1663 palette
= (uint32_t *)(crt
? &s
->dc_palette
[SM501_DC_CRT_PALETTE
-
1664 SM501_DC_PANEL_PALETTE
]
1665 : &s
->dc_palette
[0]);
1667 /* choose draw_line function */
1670 draw_line
= draw_line8_funcs
[dst_depth_index
];
1673 draw_line
= draw_line16_funcs
[dst_depth_index
];
1676 draw_line
= draw_line32_funcs
[dst_depth_index
];
1679 qemu_log_mask(LOG_GUEST_ERROR
, "sm501: update display"
1680 "invalid control register value.\n");
1684 /* set up to draw hardware cursor */
1685 if (is_hwc_enabled(s
, crt
)) {
1686 /* choose cursor draw line function */
1687 draw_hwc_line
= draw_hwc_line_funcs
[dst_depth_index
];
1688 hwc_src
= get_hwc_address(s
, crt
);
1689 c_x
= get_hwc_x(s
, crt
);
1690 c_y
= get_hwc_y(s
, crt
);
1691 get_hwc_palette(s
, crt
, hwc_palette
);
1694 /* adjust console size */
1695 if (s
->last_width
!= width
|| s
->last_height
!= height
) {
1696 qemu_console_resize(s
->con
, width
, height
);
1697 surface
= qemu_console_surface(s
->con
);
1698 s
->last_width
= width
;
1699 s
->last_height
= height
;
1703 /* someone else requested a full update */
1704 if (s
->do_full_update
) {
1705 s
->do_full_update
= false;
1709 /* draw each line according to conditions */
1710 offset
= get_fb_addr(s
, crt
);
1711 snap
= memory_region_snapshot_and_clear_dirty(&s
->local_mem_region
,
1712 offset
, width
* height
* src_bpp
, DIRTY_MEMORY_VGA
);
1713 for (y
= 0; y
< height
; y
++, offset
+= width
* src_bpp
) {
1714 int update
, update_hwc
;
1716 /* check if hardware cursor is enabled and we're within its range */
1717 update_hwc
= draw_hwc_line
&& c_y
<= y
&& y
< c_y
+ SM501_HWC_HEIGHT
;
1718 update
= full_update
|| update_hwc
;
1719 /* check dirty flags for each line */
1720 update
|= memory_region_snapshot_get_dirty(&s
->local_mem_region
, snap
,
1721 offset
, width
* src_bpp
);
1723 /* draw line and change status */
1725 uint8_t *d
= surface_data(surface
);
1726 d
+= y
* width
* dst_bpp
;
1728 /* draw graphics layer */
1729 draw_line(d
, s
->local_mem
+ offset
, width
, palette
);
1731 /* draw hardware cursor */
1733 draw_hwc_line(d
, hwc_src
, width
, hwc_palette
, c_x
, y
- c_y
);
1741 /* flush to display */
1742 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
1749 /* complete flush to display */
1751 dpy_gfx_update(s
->con
, 0, y_start
, width
, y
- y_start
);
1755 static const GraphicHwOps sm501_ops
= {
1756 .gfx_update
= sm501_update_display
,
1759 static void sm501_reset(SM501State
*s
)
1761 s
->system_control
= 0x00100000; /* 2D engine FIFO empty */
1762 /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1763 * to be determined at reset by GPIO lines which set config bits.
1765 * SH = 0 : Hitachi Ready Polarity == Active Low
1766 * CDR = 0 : do not reset clock divider
1767 * TEST = 0 : Normal mode (not testing the silicon)
1768 * BUS = 0 : Hitachi SH3/SH4
1770 s
->misc_control
= SM501_MISC_DAC_POWER
;
1771 s
->gpio_31_0_control
= 0;
1772 s
->gpio_63_32_control
= 0;
1773 s
->dram_control
= 0;
1774 s
->arbitration_control
= 0x05146732;
1777 s
->power_mode_control
= 0;
1778 s
->i2c_byte_count
= 0;
1781 memset(s
->i2c_data
, 0, 16);
1782 s
->dc_panel_control
= 0x00010000; /* FIFO level 3 */
1783 s
->dc_video_control
= 0;
1784 s
->dc_crt_control
= 0x00010000;
1786 s
->twoD_destination
= 0;
1787 s
->twoD_dimension
= 0;
1788 s
->twoD_control
= 0;
1790 s
->twoD_foreground
= 0;
1791 s
->twoD_background
= 0;
1792 s
->twoD_stretch
= 0;
1793 s
->twoD_color_compare
= 0;
1794 s
->twoD_color_compare_mask
= 0;
1796 s
->twoD_clip_tl
= 0;
1797 s
->twoD_clip_br
= 0;
1798 s
->twoD_mono_pattern_low
= 0;
1799 s
->twoD_mono_pattern_high
= 0;
1800 s
->twoD_window_width
= 0;
1801 s
->twoD_source_base
= 0;
1802 s
->twoD_destination_base
= 0;
1807 static void sm501_init(SM501State
*s
, DeviceState
*dev
,
1808 uint32_t local_mem_bytes
)
1810 s
->local_mem_size_index
= get_local_mem_size_index(local_mem_bytes
);
1813 memory_region_init_ram(&s
->local_mem_region
, OBJECT(dev
), "sm501.local",
1814 get_local_mem_size(s
), &error_fatal
);
1815 memory_region_set_log(&s
->local_mem_region
, true, DIRTY_MEMORY_VGA
);
1816 s
->local_mem
= memory_region_get_ram_ptr(&s
->local_mem_region
);
1819 s
->i2c_bus
= i2c_init_bus(dev
, "sm501.i2c");
1821 I2CDDCState
*ddc
= I2CDDC(qdev_new(TYPE_I2CDDC
));
1822 i2c_set_slave_address(I2C_SLAVE(ddc
), 0x50);
1823 qdev_realize_and_unref(DEVICE(ddc
), BUS(s
->i2c_bus
), &error_abort
);
1826 memory_region_init(&s
->mmio_region
, OBJECT(dev
), "sm501.mmio", MMIO_SIZE
);
1827 memory_region_init_io(&s
->system_config_region
, OBJECT(dev
),
1828 &sm501_system_config_ops
, s
,
1829 "sm501-system-config", 0x6c);
1830 memory_region_add_subregion(&s
->mmio_region
, SM501_SYS_CONFIG
,
1831 &s
->system_config_region
);
1832 memory_region_init_io(&s
->i2c_region
, OBJECT(dev
), &sm501_i2c_ops
, s
,
1834 memory_region_add_subregion(&s
->mmio_region
, SM501_I2C
, &s
->i2c_region
);
1835 memory_region_init_io(&s
->disp_ctrl_region
, OBJECT(dev
),
1836 &sm501_disp_ctrl_ops
, s
,
1837 "sm501-disp-ctrl", 0x1000);
1838 memory_region_add_subregion(&s
->mmio_region
, SM501_DC
,
1839 &s
->disp_ctrl_region
);
1840 memory_region_init_io(&s
->twoD_engine_region
, OBJECT(dev
),
1841 &sm501_2d_engine_ops
, s
,
1842 "sm501-2d-engine", 0x54);
1843 memory_region_add_subregion(&s
->mmio_region
, SM501_2D_ENGINE
,
1844 &s
->twoD_engine_region
);
1846 /* create qemu graphic console */
1847 s
->con
= graphic_console_init(dev
, 0, &sm501_ops
, s
);
1850 static const VMStateDescription vmstate_sm501_state
= {
1851 .name
= "sm501-state",
1853 .minimum_version_id
= 1,
1854 .fields
= (VMStateField
[]) {
1855 VMSTATE_UINT32(local_mem_size_index
, SM501State
),
1856 VMSTATE_UINT32(system_control
, SM501State
),
1857 VMSTATE_UINT32(misc_control
, SM501State
),
1858 VMSTATE_UINT32(gpio_31_0_control
, SM501State
),
1859 VMSTATE_UINT32(gpio_63_32_control
, SM501State
),
1860 VMSTATE_UINT32(dram_control
, SM501State
),
1861 VMSTATE_UINT32(arbitration_control
, SM501State
),
1862 VMSTATE_UINT32(irq_mask
, SM501State
),
1863 VMSTATE_UINT32(misc_timing
, SM501State
),
1864 VMSTATE_UINT32(power_mode_control
, SM501State
),
1865 VMSTATE_UINT32(uart0_ier
, SM501State
),
1866 VMSTATE_UINT32(uart0_lcr
, SM501State
),
1867 VMSTATE_UINT32(uart0_mcr
, SM501State
),
1868 VMSTATE_UINT32(uart0_scr
, SM501State
),
1869 VMSTATE_UINT8_ARRAY(dc_palette
, SM501State
, DC_PALETTE_ENTRIES
),
1870 VMSTATE_UINT32(dc_panel_control
, SM501State
),
1871 VMSTATE_UINT32(dc_panel_panning_control
, SM501State
),
1872 VMSTATE_UINT32(dc_panel_fb_addr
, SM501State
),
1873 VMSTATE_UINT32(dc_panel_fb_offset
, SM501State
),
1874 VMSTATE_UINT32(dc_panel_fb_width
, SM501State
),
1875 VMSTATE_UINT32(dc_panel_fb_height
, SM501State
),
1876 VMSTATE_UINT32(dc_panel_tl_location
, SM501State
),
1877 VMSTATE_UINT32(dc_panel_br_location
, SM501State
),
1878 VMSTATE_UINT32(dc_panel_h_total
, SM501State
),
1879 VMSTATE_UINT32(dc_panel_h_sync
, SM501State
),
1880 VMSTATE_UINT32(dc_panel_v_total
, SM501State
),
1881 VMSTATE_UINT32(dc_panel_v_sync
, SM501State
),
1882 VMSTATE_UINT32(dc_panel_hwc_addr
, SM501State
),
1883 VMSTATE_UINT32(dc_panel_hwc_location
, SM501State
),
1884 VMSTATE_UINT32(dc_panel_hwc_color_1_2
, SM501State
),
1885 VMSTATE_UINT32(dc_panel_hwc_color_3
, SM501State
),
1886 VMSTATE_UINT32(dc_video_control
, SM501State
),
1887 VMSTATE_UINT32(dc_crt_control
, SM501State
),
1888 VMSTATE_UINT32(dc_crt_fb_addr
, SM501State
),
1889 VMSTATE_UINT32(dc_crt_fb_offset
, SM501State
),
1890 VMSTATE_UINT32(dc_crt_h_total
, SM501State
),
1891 VMSTATE_UINT32(dc_crt_h_sync
, SM501State
),
1892 VMSTATE_UINT32(dc_crt_v_total
, SM501State
),
1893 VMSTATE_UINT32(dc_crt_v_sync
, SM501State
),
1894 VMSTATE_UINT32(dc_crt_hwc_addr
, SM501State
),
1895 VMSTATE_UINT32(dc_crt_hwc_location
, SM501State
),
1896 VMSTATE_UINT32(dc_crt_hwc_color_1_2
, SM501State
),
1897 VMSTATE_UINT32(dc_crt_hwc_color_3
, SM501State
),
1898 VMSTATE_UINT32(twoD_source
, SM501State
),
1899 VMSTATE_UINT32(twoD_destination
, SM501State
),
1900 VMSTATE_UINT32(twoD_dimension
, SM501State
),
1901 VMSTATE_UINT32(twoD_control
, SM501State
),
1902 VMSTATE_UINT32(twoD_pitch
, SM501State
),
1903 VMSTATE_UINT32(twoD_foreground
, SM501State
),
1904 VMSTATE_UINT32(twoD_background
, SM501State
),
1905 VMSTATE_UINT32(twoD_stretch
, SM501State
),
1906 VMSTATE_UINT32(twoD_color_compare
, SM501State
),
1907 VMSTATE_UINT32(twoD_color_compare_mask
, SM501State
),
1908 VMSTATE_UINT32(twoD_mask
, SM501State
),
1909 VMSTATE_UINT32(twoD_clip_tl
, SM501State
),
1910 VMSTATE_UINT32(twoD_clip_br
, SM501State
),
1911 VMSTATE_UINT32(twoD_mono_pattern_low
, SM501State
),
1912 VMSTATE_UINT32(twoD_mono_pattern_high
, SM501State
),
1913 VMSTATE_UINT32(twoD_window_width
, SM501State
),
1914 VMSTATE_UINT32(twoD_source_base
, SM501State
),
1915 VMSTATE_UINT32(twoD_destination_base
, SM501State
),
1916 VMSTATE_UINT32(twoD_alpha
, SM501State
),
1917 VMSTATE_UINT32(twoD_wrap
, SM501State
),
1918 /* Added in version 2 */
1919 VMSTATE_UINT8(i2c_byte_count
, SM501State
),
1920 VMSTATE_UINT8(i2c_status
, SM501State
),
1921 VMSTATE_UINT8(i2c_addr
, SM501State
),
1922 VMSTATE_UINT8_ARRAY(i2c_data
, SM501State
, 16),
1923 VMSTATE_END_OF_LIST()
1927 #define TYPE_SYSBUS_SM501 "sysbus-sm501"
1928 #define SYSBUS_SM501(obj) \
1929 OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
1933 SysBusDevice parent_obj
;
1941 static void sm501_realize_sysbus(DeviceState
*dev
, Error
**errp
)
1943 SM501SysBusState
*s
= SYSBUS_SM501(dev
);
1944 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1945 DeviceState
*usb_dev
;
1948 sm501_init(&s
->state
, dev
, s
->vram_size
);
1949 if (get_local_mem_size(&s
->state
) != s
->vram_size
) {
1950 error_setg(errp
, "Invalid VRAM size, nearest valid size is %" PRIu32
,
1951 get_local_mem_size(&s
->state
));
1954 sysbus_init_mmio(sbd
, &s
->state
.local_mem_region
);
1955 sysbus_init_mmio(sbd
, &s
->state
.mmio_region
);
1957 /* bridge to usb host emulation module */
1958 usb_dev
= qdev_new("sysbus-ohci");
1959 qdev_prop_set_uint32(usb_dev
, "num-ports", 2);
1960 qdev_prop_set_uint64(usb_dev
, "dma-offset", s
->base
);
1961 sysbus_realize_and_unref(SYS_BUS_DEVICE(usb_dev
), &error_fatal
);
1962 memory_region_add_subregion(&s
->state
.mmio_region
, SM501_USB_HOST
,
1963 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev
), 0));
1964 sysbus_pass_irq(sbd
, SYS_BUS_DEVICE(usb_dev
));
1966 /* bridge to serial emulation module */
1967 sysbus_realize(SYS_BUS_DEVICE(&s
->serial
), &error_fatal
);
1968 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->serial
), 0);
1969 memory_region_add_subregion(&s
->state
.mmio_region
, SM501_UART0
, mr
);
1970 /* TODO : chain irq to IRL */
1973 static Property sm501_sysbus_properties
[] = {
1974 DEFINE_PROP_UINT32("vram-size", SM501SysBusState
, vram_size
, 0),
1975 DEFINE_PROP_UINT32("base", SM501SysBusState
, base
, 0),
1976 DEFINE_PROP_END_OF_LIST(),
1979 static void sm501_reset_sysbus(DeviceState
*dev
)
1981 SM501SysBusState
*s
= SYSBUS_SM501(dev
);
1982 sm501_reset(&s
->state
);
1985 static const VMStateDescription vmstate_sm501_sysbus
= {
1986 .name
= TYPE_SYSBUS_SM501
,
1988 .minimum_version_id
= 2,
1989 .fields
= (VMStateField
[]) {
1990 VMSTATE_STRUCT(state
, SM501SysBusState
, 1,
1991 vmstate_sm501_state
, SM501State
),
1992 VMSTATE_END_OF_LIST()
1996 static void sm501_sysbus_class_init(ObjectClass
*klass
, void *data
)
1998 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2000 dc
->realize
= sm501_realize_sysbus
;
2001 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
2002 dc
->desc
= "SM501 Multimedia Companion";
2003 device_class_set_props(dc
, sm501_sysbus_properties
);
2004 dc
->reset
= sm501_reset_sysbus
;
2005 dc
->vmsd
= &vmstate_sm501_sysbus
;
2008 static void sm501_sysbus_init(Object
*o
)
2010 SM501SysBusState
*sm501
= SYSBUS_SM501(o
);
2011 SerialMM
*smm
= &sm501
->serial
;
2013 object_initialize_child(o
, "serial", smm
, TYPE_SERIAL_MM
);
2014 qdev_set_legacy_instance_id(DEVICE(smm
), SM501_UART0
, 2);
2015 qdev_prop_set_uint8(DEVICE(smm
), "regshift", 2);
2016 qdev_prop_set_uint8(DEVICE(smm
), "endianness", DEVICE_LITTLE_ENDIAN
);
2018 object_property_add_alias(o
, "chardev",
2019 OBJECT(smm
), "chardev");
2022 static const TypeInfo sm501_sysbus_info
= {
2023 .name
= TYPE_SYSBUS_SM501
,
2024 .parent
= TYPE_SYS_BUS_DEVICE
,
2025 .instance_size
= sizeof(SM501SysBusState
),
2026 .class_init
= sm501_sysbus_class_init
,
2027 .instance_init
= sm501_sysbus_init
,
2030 #define TYPE_PCI_SM501 "sm501"
2031 #define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501)
2035 PCIDevice parent_obj
;
2041 static void sm501_realize_pci(PCIDevice
*dev
, Error
**errp
)
2043 SM501PCIState
*s
= PCI_SM501(dev
);
2045 sm501_init(&s
->state
, DEVICE(dev
), s
->vram_size
);
2046 if (get_local_mem_size(&s
->state
) != s
->vram_size
) {
2047 error_setg(errp
, "Invalid VRAM size, nearest valid size is %" PRIu32
,
2048 get_local_mem_size(&s
->state
));
2051 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
,
2052 &s
->state
.local_mem_region
);
2053 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_SPACE_MEMORY
,
2054 &s
->state
.mmio_region
);
2057 static Property sm501_pci_properties
[] = {
2058 DEFINE_PROP_UINT32("vram-size", SM501PCIState
, vram_size
, 64 * MiB
),
2059 DEFINE_PROP_END_OF_LIST(),
2062 static void sm501_reset_pci(DeviceState
*dev
)
2064 SM501PCIState
*s
= PCI_SM501(dev
);
2065 sm501_reset(&s
->state
);
2066 /* Bits 2:0 of misc_control register is 001 for PCI */
2067 s
->state
.misc_control
|= 1;
2070 static const VMStateDescription vmstate_sm501_pci
= {
2071 .name
= TYPE_PCI_SM501
,
2073 .minimum_version_id
= 2,
2074 .fields
= (VMStateField
[]) {
2075 VMSTATE_PCI_DEVICE(parent_obj
, SM501PCIState
),
2076 VMSTATE_STRUCT(state
, SM501PCIState
, 1,
2077 vmstate_sm501_state
, SM501State
),
2078 VMSTATE_END_OF_LIST()
2082 static void sm501_pci_class_init(ObjectClass
*klass
, void *data
)
2084 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2085 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2087 k
->realize
= sm501_realize_pci
;
2088 k
->vendor_id
= PCI_VENDOR_ID_SILICON_MOTION
;
2089 k
->device_id
= PCI_DEVICE_ID_SM501
;
2090 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2091 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
2092 dc
->desc
= "SM501 Display Controller";
2093 device_class_set_props(dc
, sm501_pci_properties
);
2094 dc
->reset
= sm501_reset_pci
;
2095 dc
->hotpluggable
= false;
2096 dc
->vmsd
= &vmstate_sm501_pci
;
2099 static const TypeInfo sm501_pci_info
= {
2100 .name
= TYPE_PCI_SM501
,
2101 .parent
= TYPE_PCI_DEVICE
,
2102 .instance_size
= sizeof(SM501PCIState
),
2103 .class_init
= sm501_pci_class_init
,
2104 .interfaces
= (InterfaceInfo
[]) {
2105 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
2110 static void sm501_register_types(void)
2112 type_register_static(&sm501_sysbus_info
);
2113 type_register_static(&sm501_pci_info
);
2116 type_init(sm501_register_types
)