2 * Intel XScale PXA255/270 OS Timers.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
12 #include "qemu/timer.h"
13 #include "sysemu/sysemu.h"
14 #include "hw/arm/pxa.h"
15 #include "hw/sysbus.h"
29 #define OSCR 0x10 /* OS Timer Count */
38 #define OSSR 0x14 /* Timer status register */
40 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
41 #define OMCR4 0xc0 /* OS Match Control registers */
51 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
52 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
54 static int pxa2xx_timer4_freq
[8] = {
60 /* [5] is the "Externally supplied clock". Assign if necessary. */
64 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
65 #define PXA2XX_TIMER(obj) \
66 OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
68 typedef struct PXA2xxTimerInfo PXA2xxTimerInfo
;
75 PXA2xxTimerInfo
*info
;
87 struct PXA2xxTimerInfo
{
88 SysBusDevice parent_obj
;
97 PXA2xxTimer0 timer
[4];
107 #define PXA2XX_TIMER_HAVE_TM4 0
109 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo
*s
)
111 return s
->flags
& (1 << PXA2XX_TIMER_HAVE_TM4
);
114 static void pxa2xx_timer_update(void *opaque
, uint64_t now_qemu
)
116 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
122 muldiv64(now_qemu
- s
->lastload
, s
->freq
, get_ticks_per_sec());
124 for (i
= 0; i
< 4; i
++) {
125 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->timer
[i
].value
- now_vm
),
126 get_ticks_per_sec(), s
->freq
);
127 timer_mod(s
->timer
[i
].qtimer
, new_qemu
);
131 static void pxa2xx_timer_update4(void *opaque
, uint64_t now_qemu
, int n
)
133 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
136 static const int counters
[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
139 if (s
->tm4
[n
].control
& (1 << 7))
142 counter
= counters
[n
];
144 if (!s
->tm4
[counter
].freq
) {
145 timer_del(s
->tm4
[n
].tm
.qtimer
);
149 now_vm
= s
->tm4
[counter
].clock
+ muldiv64(now_qemu
-
150 s
->tm4
[counter
].lastload
,
151 s
->tm4
[counter
].freq
, get_ticks_per_sec());
153 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->tm4
[n
].tm
.value
- now_vm
),
154 get_ticks_per_sec(), s
->tm4
[counter
].freq
);
155 timer_mod(s
->tm4
[n
].tm
.qtimer
, new_qemu
);
158 static uint64_t pxa2xx_timer_read(void *opaque
, hwaddr offset
,
161 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
172 return s
->timer
[tm
].value
;
188 if (!pxa2xx_timer_has_tm4(s
))
190 return s
->tm4
[tm
].tm
.value
;
192 return s
->clock
+ muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
193 s
->lastload
, s
->freq
, get_ticks_per_sec());
209 if (!pxa2xx_timer_has_tm4(s
))
212 if ((tm
== 9 - 4 || tm
== 11 - 4) && (s
->tm4
[tm
].control
& (1 << 9))) {
213 if (s
->tm4
[tm
- 1].freq
)
214 s
->snapshot
= s
->tm4
[tm
- 1].clock
+ muldiv64(
215 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
216 s
->tm4
[tm
- 1].lastload
,
217 s
->tm4
[tm
- 1].freq
, get_ticks_per_sec());
219 s
->snapshot
= s
->tm4
[tm
- 1].clock
;
222 if (!s
->tm4
[tm
].freq
)
223 return s
->tm4
[tm
].clock
;
224 return s
->tm4
[tm
].clock
+ muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
225 s
->tm4
[tm
].lastload
, s
->tm4
[tm
].freq
, get_ticks_per_sec());
227 return s
->irq_enabled
;
228 case OSSR
: /* Status register */
247 if (!pxa2xx_timer_has_tm4(s
))
249 return s
->tm4
[tm
].control
;
254 hw_error("pxa2xx_timer_read: Bad offset " REG_FMT
"\n", offset
);
260 static void pxa2xx_timer_write(void *opaque
, hwaddr offset
,
261 uint64_t value
, unsigned size
)
264 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
274 s
->timer
[tm
].value
= value
;
275 pxa2xx_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
292 if (!pxa2xx_timer_has_tm4(s
))
294 s
->tm4
[tm
].tm
.value
= value
;
295 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
298 s
->oldclock
= s
->clock
;
299 s
->lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
301 pxa2xx_timer_update(s
, s
->lastload
);
318 if (!pxa2xx_timer_has_tm4(s
))
320 s
->tm4
[tm
].oldclock
= s
->tm4
[tm
].clock
;
321 s
->tm4
[tm
].lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
322 s
->tm4
[tm
].clock
= value
;
323 pxa2xx_timer_update4(s
, s
->tm4
[tm
].lastload
, tm
);
326 s
->irq_enabled
= value
& 0xfff;
328 case OSSR
: /* Status register */
331 for (i
= 0; i
< 4; i
++, value
>>= 1)
333 qemu_irq_lower(s
->timer
[i
].irq
);
334 if (pxa2xx_timer_has_tm4(s
) && !(s
->events
& 0xff0) && value
)
335 qemu_irq_lower(s
->irq4
);
337 case OWER
: /* XXX: Reset on OSMR3 match? */
347 if (!pxa2xx_timer_has_tm4(s
))
349 s
->tm4
[tm
].control
= value
& 0x0ff;
350 /* XXX Stop if running (shouldn't happen) */
351 if ((value
& (1 << 7)) || tm
== 0)
352 s
->tm4
[tm
].freq
= pxa2xx_timer4_freq
[value
& 7];
355 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
365 if (!pxa2xx_timer_has_tm4(s
))
367 s
->tm4
[tm
].control
= value
& 0x3ff;
368 /* XXX Stop if running (shouldn't happen) */
369 if ((value
& (1 << 7)) || !(tm
& 1))
371 pxa2xx_timer4_freq
[(value
& (1 << 8)) ? 0 : (value
& 7)];
374 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
379 hw_error("pxa2xx_timer_write: Bad offset " REG_FMT
"\n", offset
);
383 static const MemoryRegionOps pxa2xx_timer_ops
= {
384 .read
= pxa2xx_timer_read
,
385 .write
= pxa2xx_timer_write
,
386 .endianness
= DEVICE_NATIVE_ENDIAN
,
389 static void pxa2xx_timer_tick(void *opaque
)
391 PXA2xxTimer0
*t
= (PXA2xxTimer0
*) opaque
;
392 PXA2xxTimerInfo
*i
= t
->info
;
394 if (i
->irq_enabled
& (1 << t
->num
)) {
395 i
->events
|= 1 << t
->num
;
396 qemu_irq_raise(t
->irq
);
402 qemu_system_reset_request();
406 static void pxa2xx_timer_tick4(void *opaque
)
408 PXA2xxTimer4
*t
= (PXA2xxTimer4
*) opaque
;
409 PXA2xxTimerInfo
*i
= (PXA2xxTimerInfo
*) t
->tm
.info
;
411 pxa2xx_timer_tick(&t
->tm
);
412 if (t
->control
& (1 << 3))
414 if (t
->control
& (1 << 6))
415 pxa2xx_timer_update4(i
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), t
->tm
.num
- 4);
416 if (i
->events
& 0xff0)
417 qemu_irq_raise(i
->irq4
);
420 static int pxa25x_timer_post_load(void *opaque
, int version_id
)
422 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
426 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
427 pxa2xx_timer_update(s
, now
);
429 if (pxa2xx_timer_has_tm4(s
))
430 for (i
= 0; i
< 8; i
++)
431 pxa2xx_timer_update4(s
, now
, i
);
436 static int pxa2xx_timer_init(SysBusDevice
*dev
)
438 PXA2xxTimerInfo
*s
= PXA2XX_TIMER(dev
);
444 s
->lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
447 for (i
= 0; i
< 4; i
++) {
448 s
->timer
[i
].value
= 0;
449 sysbus_init_irq(dev
, &s
->timer
[i
].irq
);
450 s
->timer
[i
].info
= s
;
452 s
->timer
[i
].qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
453 pxa2xx_timer_tick
, &s
->timer
[i
]);
455 if (s
->flags
& (1 << PXA2XX_TIMER_HAVE_TM4
)) {
456 sysbus_init_irq(dev
, &s
->irq4
);
458 for (i
= 0; i
< 8; i
++) {
459 s
->tm4
[i
].tm
.value
= 0;
460 s
->tm4
[i
].tm
.info
= s
;
461 s
->tm4
[i
].tm
.num
= i
+ 4;
463 s
->tm4
[i
].control
= 0x0;
464 s
->tm4
[i
].tm
.qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
465 pxa2xx_timer_tick4
, &s
->tm4
[i
]);
469 memory_region_init_io(&s
->iomem
, OBJECT(s
), &pxa2xx_timer_ops
, s
,
470 "pxa2xx-timer", 0x00001000);
471 sysbus_init_mmio(dev
, &s
->iomem
);
476 static const VMStateDescription vmstate_pxa2xx_timer0_regs
= {
477 .name
= "pxa2xx_timer0",
479 .minimum_version_id
= 2,
480 .fields
= (VMStateField
[]) {
481 VMSTATE_UINT32(value
, PXA2xxTimer0
),
482 VMSTATE_END_OF_LIST(),
486 static const VMStateDescription vmstate_pxa2xx_timer4_regs
= {
487 .name
= "pxa2xx_timer4",
489 .minimum_version_id
= 1,
490 .fields
= (VMStateField
[]) {
491 VMSTATE_STRUCT(tm
, PXA2xxTimer4
, 1,
492 vmstate_pxa2xx_timer0_regs
, PXA2xxTimer0
),
493 VMSTATE_INT32(oldclock
, PXA2xxTimer4
),
494 VMSTATE_INT32(clock
, PXA2xxTimer4
),
495 VMSTATE_UINT64(lastload
, PXA2xxTimer4
),
496 VMSTATE_UINT32(freq
, PXA2xxTimer4
),
497 VMSTATE_UINT32(control
, PXA2xxTimer4
),
498 VMSTATE_END_OF_LIST(),
502 static bool pxa2xx_timer_has_tm4_test(void *opaque
, int version_id
)
504 return pxa2xx_timer_has_tm4(opaque
);
507 static const VMStateDescription vmstate_pxa2xx_timer_regs
= {
508 .name
= "pxa2xx_timer",
510 .minimum_version_id
= 1,
511 .post_load
= pxa25x_timer_post_load
,
512 .fields
= (VMStateField
[]) {
513 VMSTATE_INT32(clock
, PXA2xxTimerInfo
),
514 VMSTATE_INT32(oldclock
, PXA2xxTimerInfo
),
515 VMSTATE_UINT64(lastload
, PXA2xxTimerInfo
),
516 VMSTATE_STRUCT_ARRAY(timer
, PXA2xxTimerInfo
, 4, 1,
517 vmstate_pxa2xx_timer0_regs
, PXA2xxTimer0
),
518 VMSTATE_UINT32(events
, PXA2xxTimerInfo
),
519 VMSTATE_UINT32(irq_enabled
, PXA2xxTimerInfo
),
520 VMSTATE_UINT32(reset3
, PXA2xxTimerInfo
),
521 VMSTATE_UINT32(snapshot
, PXA2xxTimerInfo
),
522 VMSTATE_STRUCT_ARRAY_TEST(tm4
, PXA2xxTimerInfo
, 8,
523 pxa2xx_timer_has_tm4_test
, 0,
524 vmstate_pxa2xx_timer4_regs
, PXA2xxTimer4
),
525 VMSTATE_END_OF_LIST(),
529 static Property pxa25x_timer_dev_properties
[] = {
530 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo
, freq
, PXA25X_FREQ
),
531 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo
, flags
,
532 PXA2XX_TIMER_HAVE_TM4
, false),
533 DEFINE_PROP_END_OF_LIST(),
536 static void pxa25x_timer_dev_class_init(ObjectClass
*klass
, void *data
)
538 DeviceClass
*dc
= DEVICE_CLASS(klass
);
540 dc
->desc
= "PXA25x timer";
541 dc
->props
= pxa25x_timer_dev_properties
;
544 static const TypeInfo pxa25x_timer_dev_info
= {
545 .name
= "pxa25x-timer",
546 .parent
= TYPE_PXA2XX_TIMER
,
547 .instance_size
= sizeof(PXA2xxTimerInfo
),
548 .class_init
= pxa25x_timer_dev_class_init
,
551 static Property pxa27x_timer_dev_properties
[] = {
552 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo
, freq
, PXA27X_FREQ
),
553 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo
, flags
,
554 PXA2XX_TIMER_HAVE_TM4
, true),
555 DEFINE_PROP_END_OF_LIST(),
558 static void pxa27x_timer_dev_class_init(ObjectClass
*klass
, void *data
)
560 DeviceClass
*dc
= DEVICE_CLASS(klass
);
562 dc
->desc
= "PXA27x timer";
563 dc
->props
= pxa27x_timer_dev_properties
;
566 static const TypeInfo pxa27x_timer_dev_info
= {
567 .name
= "pxa27x-timer",
568 .parent
= TYPE_PXA2XX_TIMER
,
569 .instance_size
= sizeof(PXA2xxTimerInfo
),
570 .class_init
= pxa27x_timer_dev_class_init
,
573 static void pxa2xx_timer_class_init(ObjectClass
*oc
, void *data
)
575 DeviceClass
*dc
= DEVICE_CLASS(oc
);
576 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(oc
);
578 sdc
->init
= pxa2xx_timer_init
;
579 dc
->vmsd
= &vmstate_pxa2xx_timer_regs
;
582 static const TypeInfo pxa2xx_timer_type_info
= {
583 .name
= TYPE_PXA2XX_TIMER
,
584 .parent
= TYPE_SYS_BUS_DEVICE
,
585 .instance_size
= sizeof(PXA2xxTimerInfo
),
587 .class_init
= pxa2xx_timer_class_init
,
590 static void pxa2xx_timer_register_types(void)
592 type_register_static(&pxa2xx_timer_type_info
);
593 type_register_static(&pxa25x_timer_dev_info
);
594 type_register_static(&pxa27x_timer_dev_info
);
597 type_init(pxa2xx_timer_register_types
)