hw/timer/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Contributions after 2012-01-13 are licensed under the terms of the
  11  * GNU GPL, version 2 or (at your option) any later version.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/sysbus.h"
  16 #include "qemu/timer.h"
  17 #include "sysemu/sysemu.h"
  18
  19 //#define DEBUG_PL031
  20
  21 #ifdef DEBUG_PL031
  22 #define DPRINTF(fmt, ...) \
  23 do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
  24 #else
  25 #define DPRINTF(fmt, ...) do {} while(0)
  26 #endif
  27
  28 #define RTC_DR      0x00    /* Data read register */
  29 #define RTC_MR      0x04    /* Match register */
  30 #define RTC_LR      0x08    /* Data load register */
  31 #define RTC_CR      0x0c    /* Control register */
  32 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  33 #define RTC_RIS     0x14    /* Raw interrupt status register */
  34 #define RTC_MIS     0x18    /* Masked interrupt status register */
  35 #define RTC_ICR     0x1c    /* Interrupt clear register */
  36
  37 #define TYPE_PL031 "pl031"
  38 #define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
  39
  40 typedef struct PL031State {
  41     SysBusDevice parent_obj;
  42
  43     MemoryRegion iomem;
  44     QEMUTimer *timer;
  45     qemu_irq irq;
  46
  47     /* Needed to preserve the tick_count across migration, even if the
  48      * absolute value of the rtc_clock is different on the source and
  49      * destination.
  50      */
  51     uint32_t tick_offset_vmstate;
  52     uint32_t tick_offset;
  53
  54     uint32_t mr;
  55     uint32_t lr;
  56     uint32_t cr;
  57     uint32_t im;
  58     uint32_t is;
  59 } PL031State;
  60
  61 static const unsigned char pl031_id[] = {
  62     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  63     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  64 };
  65
  66 static void pl031_update(PL031State *s)
  67 {
  68     qemu_set_irq(s->irq, s->is & s->im);
  69 }
  70
  71 static void pl031_interrupt(void * opaque)
  72 {
  73     PL031State *s = (PL031State *)opaque;
  74
  75     s->is = 1;
  76     DPRINTF("Alarm raised\n");
  77     pl031_update(s);
  78 }
  79
  80 static uint32_t pl031_get_count(PL031State *s)
  81 {
  82     int64_t now = qemu_clock_get_ns(rtc_clock);
  83     return s->tick_offset + now / get_ticks_per_sec();
  84 }
  85
  86 static void pl031_set_alarm(PL031State *s)
  87 {
  88     uint32_t ticks;
  89
  90     /* The timer wraps around.  This subtraction also wraps in the same way,
  91        and gives correct results when alarm < now_ticks.  */
  92     ticks = s->mr - pl031_get_count(s);
  93     DPRINTF("Alarm set in %ud ticks\n", ticks);
  94     if (ticks == 0) {
  95         timer_del(s->timer);
  96         pl031_interrupt(s);
  97     } else {
  98         int64_t now = qemu_clock_get_ns(rtc_clock);
  99         timer_mod(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
 100     }
 101 }
 102
 103 static uint64_t pl031_read(void *opaque, hwaddr offset,
 104                            unsigned size)
 105 {
 106     PL031State *s = (PL031State *)opaque;
 107
 108     if (offset >= 0xfe0  &&  offset < 0x1000)
 109         return pl031_id[(offset - 0xfe0) >> 2];
 110
 111     switch (offset) {
 112     case RTC_DR:
 113         return pl031_get_count(s);
 114     case RTC_MR:
 115         return s->mr;
 116     case RTC_IMSC:
 117         return s->im;
 118     case RTC_RIS:
 119         return s->is;
 120     case RTC_LR:
 121         return s->lr;
 122     case RTC_CR:
 123         /* RTC is permanently enabled.  */
 124         return 1;
 125     case RTC_MIS:
 126         return s->is & s->im;
 127     case RTC_ICR:
 128         qemu_log_mask(LOG_GUEST_ERROR,
 129                       "pl031: read of write-only register at offset 0x%x\n",
 130                       (int)offset);
 131         break;
 132     default:
 133         qemu_log_mask(LOG_GUEST_ERROR,
 134                       "pl031_read: Bad offset 0x%x\n", (int)offset);
 135         break;
 136     }
 137
 138     return 0;
 139 }
 140
 141 static void pl031_write(void * opaque, hwaddr offset,
 142                         uint64_t value, unsigned size)
 143 {
 144     PL031State *s = (PL031State *)opaque;
 145
 146
 147     switch (offset) {
 148     case RTC_LR:
 149         s->tick_offset += value - pl031_get_count(s);
 150         pl031_set_alarm(s);
 151         break;
 152     case RTC_MR:
 153         s->mr = value;
 154         pl031_set_alarm(s);
 155         break;
 156     case RTC_IMSC:
 157         s->im = value & 1;
 158         DPRINTF("Interrupt mask %d\n", s->im);
 159         pl031_update(s);
 160         break;
 161     case RTC_ICR:
 162         /* The PL031 documentation (DDI0224B) states that the interrupt is
 163            cleared when bit 0 of the written value is set.  However the
 164            arm926e documentation (DDI0287B) states that the interrupt is
 165            cleared when any value is written.  */
 166         DPRINTF("Interrupt cleared");
 167         s->is = 0;
 168         pl031_update(s);
 169         break;
 170     case RTC_CR:
 171         /* Written value is ignored.  */
 172         break;
 173
 174     case RTC_DR:
 175     case RTC_MIS:
 176     case RTC_RIS:
 177         qemu_log_mask(LOG_GUEST_ERROR,
 178                       "pl031: write to read-only register at offset 0x%x\n",
 179                       (int)offset);
 180         break;
 181
 182     default:
 183         qemu_log_mask(LOG_GUEST_ERROR,
 184                       "pl031_write: Bad offset 0x%x\n", (int)offset);
 185         break;
 186     }
 187 }
 188
 189 static const MemoryRegionOps pl031_ops = {
 190     .read = pl031_read,
 191     .write = pl031_write,
 192     .endianness = DEVICE_NATIVE_ENDIAN,
 193 };
 194
 195 static int pl031_init(SysBusDevice *dev)
 196 {
 197     PL031State *s = PL031(dev);
 198     struct tm tm;
 199
 200     memory_region_init_io(&s->iomem, OBJECT(s), &pl031_ops, s, "pl031", 0x1000);
 201     sysbus_init_mmio(dev, &s->iomem);
 202
 203     sysbus_init_irq(dev, &s->irq);
 204     qemu_get_timedate(&tm, 0);
 205     s->tick_offset = mktimegm(&tm) -
 206         qemu_clock_get_ns(rtc_clock) / get_ticks_per_sec();
 207
 208     s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
 209     return 0;
 210 }
 211
 212 static void pl031_pre_save(void *opaque)
 213 {
 214     PL031State *s = opaque;
 215
 216     /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
 217      * store the base time relative to the QEMU_CLOCK_VIRTUAL for backwards-compatibility.  */
 218     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 219     s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
 220 }
 221
 222 static int pl031_post_load(void *opaque, int version_id)
 223 {
 224     PL031State *s = opaque;
 225
 226     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 227     s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
 228     pl031_set_alarm(s);
 229     return 0;
 230 }
 231
 232 static const VMStateDescription vmstate_pl031 = {
 233     .name = "pl031",
 234     .version_id = 1,
 235     .minimum_version_id = 1,
 236     .pre_save = pl031_pre_save,
 237     .post_load = pl031_post_load,
 238     .fields = (VMStateField[]) {
 239         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
 240         VMSTATE_UINT32(mr, PL031State),
 241         VMSTATE_UINT32(lr, PL031State),
 242         VMSTATE_UINT32(cr, PL031State),
 243         VMSTATE_UINT32(im, PL031State),
 244         VMSTATE_UINT32(is, PL031State),
 245         VMSTATE_END_OF_LIST()
 246     }
 247 };
 248
 249 static void pl031_class_init(ObjectClass *klass, void *data)
 250 {
 251     DeviceClass *dc = DEVICE_CLASS(klass);
 252     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 253
 254     k->init = pl031_init;
 255     dc->vmsd = &vmstate_pl031;
 256 }
 257
 258 static const TypeInfo pl031_info = {
 259     .name          = TYPE_PL031,
 260     .parent        = TYPE_SYS_BUS_DEVICE,
 261     .instance_size = sizeof(PL031State),
 262     .class_init    = pl031_class_init,
 263 };
 264
 265 static void pl031_register_types(void)
 266 {
 267     type_register_static(&pl031_info);
 268 }
 269
 270 type_init(pl031_register_types)