2 * i.MX I2C Bus Serial Interface Emulation
4 * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/i2c/imx_i2c.h"
23 #include "hw/i2c/i2c.h"
25 #include "qemu/module.h"
28 #define DEBUG_IMX_I2C 0
31 #define DPRINTF(fmt, args...) \
33 if (DEBUG_IMX_I2C) { \
34 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_I2C, \
39 static const char *imx_i2c_get_regname(unsigned offset
)
57 static inline bool imx_i2c_is_enabled(IMXI2CState
*s
)
59 return s
->i2cr
& I2CR_IEN
;
62 static inline bool imx_i2c_interrupt_is_enabled(IMXI2CState
*s
)
64 return s
->i2cr
& I2CR_IIEN
;
67 static inline bool imx_i2c_is_master(IMXI2CState
*s
)
69 return s
->i2cr
& I2CR_MSTA
;
72 static void imx_i2c_reset(DeviceState
*dev
)
74 IMXI2CState
*s
= IMX_I2C(dev
);
76 if (s
->address
!= ADDR_RESET
) {
77 i2c_end_transfer(s
->bus
);
80 s
->address
= ADDR_RESET
;
85 s
->i2dr_read
= I2DR_RESET
;
86 s
->i2dr_write
= I2DR_RESET
;
89 static inline void imx_i2c_raise_interrupt(IMXI2CState
*s
)
92 * raise an interrupt if the device is enabled and it is configured
93 * to generate some interrupts.
95 if (imx_i2c_is_enabled(s
) && imx_i2c_interrupt_is_enabled(s
)) {
97 qemu_irq_raise(s
->irq
);
101 static uint64_t imx_i2c_read(void *opaque
, hwaddr offset
,
105 IMXI2CState
*s
= IMX_I2C(opaque
);
121 value
= s
->i2dr_read
;
123 if (imx_i2c_is_master(s
)) {
126 if (s
->address
== ADDR_RESET
) {
127 /* something is wrong as the address is not set */
128 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Trying to read "
129 "without specifying the slave address\n",
130 TYPE_IMX_I2C
, __func__
);
131 } else if (s
->i2cr
& I2CR_MTX
) {
132 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Trying to read "
133 "but MTX is set\n", TYPE_IMX_I2C
, __func__
);
135 /* get the next byte */
136 ret
= i2c_recv(s
->bus
);
137 imx_i2c_raise_interrupt(s
);
142 qemu_log_mask(LOG_UNIMP
, "[%s]%s: slave mode not implemented\n",
143 TYPE_IMX_I2C
, __func__
);
147 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad address at offset 0x%"
148 HWADDR_PRIx
"\n", TYPE_IMX_I2C
, __func__
, offset
);
153 DPRINTF("read %s [0x%" HWADDR_PRIx
"] -> 0x%02x\n",
154 imx_i2c_get_regname(offset
), offset
, value
);
156 return (uint64_t)value
;
159 static void imx_i2c_write(void *opaque
, hwaddr offset
,
160 uint64_t value
, unsigned size
)
162 IMXI2CState
*s
= IMX_I2C(opaque
);
164 DPRINTF("write %s [0x%" HWADDR_PRIx
"] <- 0x%02x\n",
165 imx_i2c_get_regname(offset
), offset
, (int)value
);
171 s
->iadr
= value
& IADR_MASK
;
172 /* i2c_set_slave_address(s->bus, (uint8_t)s->iadr); */
175 s
->ifdr
= value
& IFDR_MASK
;
178 if (imx_i2c_is_enabled(s
) && ((value
& I2CR_IEN
) == 0)) {
179 /* This is a soft reset. IADR is preserved during soft resets */
180 uint16_t iadr
= s
->iadr
;
181 imx_i2c_reset(DEVICE(s
));
183 } else { /* normal write */
184 s
->i2cr
= value
& I2CR_MASK
;
186 if (imx_i2c_is_master(s
)) {
187 /* set the bus to busy */
189 } else { /* slave mode */
190 /* bus is not busy anymore */
191 s
->i2sr
&= ~I2SR_IBB
;
194 * if we unset the master mode then it ends the ongoing
197 if (s
->address
!= ADDR_RESET
) {
198 i2c_end_transfer(s
->bus
);
199 s
->address
= ADDR_RESET
;
203 if (s
->i2cr
& I2CR_RSTA
) { /* Restart */
204 /* if this is a restart then it ends the ongoing transfer */
205 if (s
->address
!= ADDR_RESET
) {
206 i2c_end_transfer(s
->bus
);
207 s
->address
= ADDR_RESET
;
208 s
->i2cr
&= ~I2CR_RSTA
;
215 * if the user writes 0 to IIF then lower the interrupt and
218 if ((s
->i2sr
& I2SR_IIF
) && !(value
& I2SR_IIF
)) {
219 s
->i2sr
&= ~I2SR_IIF
;
220 qemu_irq_lower(s
->irq
);
224 * if the user writes 0 to IAL, reset the bit
226 if ((s
->i2sr
& I2SR_IAL
) && !(value
& I2SR_IAL
)) {
227 s
->i2sr
&= ~I2SR_IAL
;
232 /* if the device is not enabled, nothing to do */
233 if (!imx_i2c_is_enabled(s
)) {
237 s
->i2dr_write
= value
& I2DR_MASK
;
239 if (imx_i2c_is_master(s
)) {
240 /* If this is the first write cycle then it is the slave addr */
241 if (s
->address
== ADDR_RESET
) {
242 if (i2c_start_transfer(s
->bus
, extract32(s
->i2dr_write
, 1, 7),
243 extract32(s
->i2dr_write
, 0, 1))) {
244 /* if non zero is returned, the address is not valid */
245 s
->i2sr
|= I2SR_RXAK
;
247 s
->address
= s
->i2dr_write
;
248 s
->i2sr
&= ~I2SR_RXAK
;
249 imx_i2c_raise_interrupt(s
);
251 } else { /* This is a normal data write */
252 if (i2c_send(s
->bus
, s
->i2dr_write
)) {
253 /* if the target return non zero then end the transfer */
254 s
->i2sr
|= I2SR_RXAK
;
255 s
->address
= ADDR_RESET
;
256 i2c_end_transfer(s
->bus
);
258 s
->i2sr
&= ~I2SR_RXAK
;
259 imx_i2c_raise_interrupt(s
);
263 qemu_log_mask(LOG_UNIMP
, "[%s]%s: slave mode not implemented\n",
264 TYPE_IMX_I2C
, __func__
);
268 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad address at offset 0x%"
269 HWADDR_PRIx
"\n", TYPE_IMX_I2C
, __func__
, offset
);
274 static const MemoryRegionOps imx_i2c_ops
= {
275 .read
= imx_i2c_read
,
276 .write
= imx_i2c_write
,
277 .valid
.min_access_size
= 1,
278 .valid
.max_access_size
= 2,
279 .endianness
= DEVICE_NATIVE_ENDIAN
,
282 static const VMStateDescription imx_i2c_vmstate
= {
283 .name
= TYPE_IMX_I2C
,
285 .minimum_version_id
= 1,
286 .fields
= (VMStateField
[]) {
287 VMSTATE_UINT16(address
, IMXI2CState
),
288 VMSTATE_UINT16(iadr
, IMXI2CState
),
289 VMSTATE_UINT16(ifdr
, IMXI2CState
),
290 VMSTATE_UINT16(i2cr
, IMXI2CState
),
291 VMSTATE_UINT16(i2sr
, IMXI2CState
),
292 VMSTATE_UINT16(i2dr_read
, IMXI2CState
),
293 VMSTATE_UINT16(i2dr_write
, IMXI2CState
),
294 VMSTATE_END_OF_LIST()
298 static void imx_i2c_realize(DeviceState
*dev
, Error
**errp
)
300 IMXI2CState
*s
= IMX_I2C(dev
);
302 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_i2c_ops
, s
, TYPE_IMX_I2C
,
304 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->iomem
);
305 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &s
->irq
);
306 s
->bus
= i2c_init_bus(DEVICE(dev
), NULL
);
309 static void imx_i2c_class_init(ObjectClass
*klass
, void *data
)
311 DeviceClass
*dc
= DEVICE_CLASS(klass
);
313 dc
->vmsd
= &imx_i2c_vmstate
;
314 dc
->reset
= imx_i2c_reset
;
315 dc
->realize
= imx_i2c_realize
;
316 dc
->desc
= "i.MX I2C Controller";
319 static const TypeInfo imx_i2c_type_info
= {
320 .name
= TYPE_IMX_I2C
,
321 .parent
= TYPE_SYS_BUS_DEVICE
,
322 .instance_size
= sizeof(IMXI2CState
),
323 .class_init
= imx_i2c_class_init
,
326 static void imx_i2c_register_types(void)
328 type_register_static(&imx_i2c_type_info
);
331 type_init(imx_i2c_register_types
)