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hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS
[qemu/ar7.git] / target / mips / msa_helper.c
blobf167a42655f5fcda5443b63fe584beadd172eb24
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
28
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
31
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
34
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
37
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
41
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
44
45 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
46 {
47 uint32_t i;
48
49 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
50 pwd->d[i] = pws->d[i];
51 }
52 }
53
54 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
55 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
56 uint32_t i8) \
57 { \
58 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
59 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
60 uint32_t i; \
61 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
62 DEST = OPERATION; \
63 } \
64 }
65
66 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
67 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
68 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
69 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
70
71 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
72 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
73 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
74 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
75
76 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
77 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
78 MSA_FN_IMM8(bmzi_b, pwd->b[i],
79 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
80
81 #define BIT_SELECT(dest, arg1, arg2, df) \
82 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
83 MSA_FN_IMM8(bseli_b, pwd->b[i],
84 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
85
86 #undef MSA_FN_IMM8
87
88 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
89
90 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
91 uint32_t ws, uint32_t imm)
92 {
93 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
94 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
95 wr_t wx, *pwx = &wx;
96 uint32_t i;
97
98 switch (df) {
99 case DF_BYTE:
100 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
101 pwx->b[i] = pws->b[SHF_POS(i, imm)];
102 }
103 break;
104 case DF_HALF:
105 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
106 pwx->h[i] = pws->h[SHF_POS(i, imm)];
107 }
108 break;
109 case DF_WORD:
110 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
111 pwx->w[i] = pws->w[SHF_POS(i, imm)];
112 }
113 break;
114 default:
115 assert(0);
116 }
117 msa_move_v(pwd, pwx);
118 }
119
120 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
121 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
122 uint32_t wt) \
123 { \
124 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
125 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
126 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
127 uint32_t i; \
128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
129 DEST = OPERATION; \
130 } \
131 }
132
133 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
134 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
135 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
136 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
137 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
138 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
139 MSA_FN_VECTOR(bmz_v, pwd->d[i],
140 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
141 MSA_FN_VECTOR(bsel_v, pwd->d[i],
142 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
143 #undef BIT_MOVE_IF_NOT_ZERO
144 #undef BIT_MOVE_IF_ZERO
145 #undef BIT_SELECT
146 #undef MSA_FN_VECTOR
147
148 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
149 {
150 return arg1 + arg2;
151 }
152
153 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
154 {
155 return arg1 - arg2;
156 }
157
158 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
159 {
160 return arg1 == arg2 ? -1 : 0;
161 }
162
163 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
164 {
165 return arg1 <= arg2 ? -1 : 0;
166 }
167
168 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
169 {
170 uint64_t u_arg1 = UNSIGNED(arg1, df);
171 uint64_t u_arg2 = UNSIGNED(arg2, df);
172 return u_arg1 <= u_arg2 ? -1 : 0;
173 }
174
175 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
176 {
177 return arg1 < arg2 ? -1 : 0;
178 }
179
180 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
181 {
182 uint64_t u_arg1 = UNSIGNED(arg1, df);
183 uint64_t u_arg2 = UNSIGNED(arg2, df);
184 return u_arg1 < u_arg2 ? -1 : 0;
185 }
186
187 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
188 {
189 return arg1 > arg2 ? arg1 : arg2;
190 }
191
192 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
193 {
194 uint64_t u_arg1 = UNSIGNED(arg1, df);
195 uint64_t u_arg2 = UNSIGNED(arg2, df);
196 return u_arg1 > u_arg2 ? arg1 : arg2;
197 }
198
199 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
200 {
201 return arg1 < arg2 ? arg1 : arg2;
202 }
203
204 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
205 {
206 uint64_t u_arg1 = UNSIGNED(arg1, df);
207 uint64_t u_arg2 = UNSIGNED(arg2, df);
208 return u_arg1 < u_arg2 ? arg1 : arg2;
209 }
210
211 #define MSA_BINOP_IMM_DF(helper, func) \
212 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
213 uint32_t wd, uint32_t ws, int32_t u5) \
214 { \
215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
216 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
217 uint32_t i; \
218 \
219 switch (df) { \
220 case DF_BYTE: \
221 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
222 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
223 } \
224 break; \
225 case DF_HALF: \
226 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
227 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
228 } \
229 break; \
230 case DF_WORD: \
231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
232 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
233 } \
234 break; \
235 case DF_DOUBLE: \
236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
237 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
238 } \
239 break; \
240 default: \
241 assert(0); \
242 } \
243 }
244
245 MSA_BINOP_IMM_DF(addvi, addv)
246 MSA_BINOP_IMM_DF(subvi, subv)
247 MSA_BINOP_IMM_DF(ceqi, ceq)
248 MSA_BINOP_IMM_DF(clei_s, cle_s)
249 MSA_BINOP_IMM_DF(clei_u, cle_u)
250 MSA_BINOP_IMM_DF(clti_s, clt_s)
251 MSA_BINOP_IMM_DF(clti_u, clt_u)
252 MSA_BINOP_IMM_DF(maxi_s, max_s)
253 MSA_BINOP_IMM_DF(maxi_u, max_u)
254 MSA_BINOP_IMM_DF(mini_s, min_s)
255 MSA_BINOP_IMM_DF(mini_u, min_u)
256 #undef MSA_BINOP_IMM_DF
257
258 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
259 int32_t s10)
260 {
261 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
262 uint32_t i;
263
264 switch (df) {
265 case DF_BYTE:
266 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
267 pwd->b[i] = (int8_t)s10;
268 }
269 break;
270 case DF_HALF:
271 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
272 pwd->h[i] = (int16_t)s10;
273 }
274 break;
275 case DF_WORD:
276 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
277 pwd->w[i] = (int32_t)s10;
278 }
279 break;
280 case DF_DOUBLE:
281 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
282 pwd->d[i] = (int64_t)s10;
283 }
284 break;
285 default:
286 assert(0);
287 }
288 }
289
290 /* Data format bit position and unsigned values */
291 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
292
293 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
294 {
295 int32_t b_arg2 = BIT_POSITION(arg2, df);
296 return arg1 << b_arg2;
297 }
298
299 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
300 {
301 int32_t b_arg2 = BIT_POSITION(arg2, df);
302 return arg1 >> b_arg2;
303 }
304
305 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
306 {
307 uint64_t u_arg1 = UNSIGNED(arg1, df);
308 int32_t b_arg2 = BIT_POSITION(arg2, df);
309 return u_arg1 >> b_arg2;
310 }
311
312 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
313 {
314 int32_t b_arg2 = BIT_POSITION(arg2, df);
315 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
316 }
317
318 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
319 int64_t arg2)
320 {
321 int32_t b_arg2 = BIT_POSITION(arg2, df);
322 return UNSIGNED(arg1 | (1LL << b_arg2), df);
323 }
324
325 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
326 {
327 int32_t b_arg2 = BIT_POSITION(arg2, df);
328 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
329 }
330
331 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
332 int64_t arg2)
333 {
334 uint64_t u_arg1 = UNSIGNED(arg1, df);
335 uint64_t u_dest = UNSIGNED(dest, df);
336 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
337 int32_t sh_a = DF_BITS(df) - sh_d;
338 if (sh_d == DF_BITS(df)) {
339 return u_arg1;
340 } else {
341 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
342 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
343 }
344 }
345
346 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
347 int64_t arg2)
348 {
349 uint64_t u_arg1 = UNSIGNED(arg1, df);
350 uint64_t u_dest = UNSIGNED(dest, df);
351 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
352 int32_t sh_a = DF_BITS(df) - sh_d;
353 if (sh_d == DF_BITS(df)) {
354 return u_arg1;
355 } else {
356 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
357 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
358 }
359 }
360
361 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
362 {
363 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
364 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
365 arg;
366 }
367
368 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
369 {
370 uint64_t u_arg = UNSIGNED(arg, df);
371 return u_arg < M_MAX_UINT(m+1) ? u_arg :
372 M_MAX_UINT(m+1);
373 }
374
375 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
376 {
377 int32_t b_arg2 = BIT_POSITION(arg2, df);
378 if (b_arg2 == 0) {
379 return arg1;
380 } else {
381 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
382 return (arg1 >> b_arg2) + r_bit;
383 }
384 }
385
386 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
387 {
388 uint64_t u_arg1 = UNSIGNED(arg1, df);
389 int32_t b_arg2 = BIT_POSITION(arg2, df);
390 if (b_arg2 == 0) {
391 return u_arg1;
392 } else {
393 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
394 return (u_arg1 >> b_arg2) + r_bit;
395 }
396 }
397
398 #define MSA_BINOP_IMMU_DF(helper, func) \
399 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
400 uint32_t ws, uint32_t u5) \
401 { \
402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
403 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
404 uint32_t i; \
405 \
406 switch (df) { \
407 case DF_BYTE: \
408 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
409 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
410 } \
411 break; \
412 case DF_HALF: \
413 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
414 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
415 } \
416 break; \
417 case DF_WORD: \
418 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
419 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
420 } \
421 break; \
422 case DF_DOUBLE: \
423 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
424 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
425 } \
426 break; \
427 default: \
428 assert(0); \
429 } \
430 }
431
432 MSA_BINOP_IMMU_DF(slli, sll)
433 MSA_BINOP_IMMU_DF(srai, sra)
434 MSA_BINOP_IMMU_DF(srli, srl)
435 MSA_BINOP_IMMU_DF(bclri, bclr)
436 MSA_BINOP_IMMU_DF(bseti, bset)
437 MSA_BINOP_IMMU_DF(bnegi, bneg)
438 MSA_BINOP_IMMU_DF(sat_s, sat_s)
439 MSA_BINOP_IMMU_DF(sat_u, sat_u)
440 MSA_BINOP_IMMU_DF(srari, srar)
441 MSA_BINOP_IMMU_DF(srlri, srlr)
442 #undef MSA_BINOP_IMMU_DF
443
444 #define MSA_TEROP_IMMU_DF(helper, func) \
445 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
446 uint32_t wd, uint32_t ws, uint32_t u5) \
447 { \
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
450 uint32_t i; \
451 \
452 switch (df) { \
453 case DF_BYTE: \
454 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
455 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
456 u5); \
457 } \
458 break; \
459 case DF_HALF: \
460 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
461 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
462 u5); \
463 } \
464 break; \
465 case DF_WORD: \
466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
467 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
468 u5); \
469 } \
470 break; \
471 case DF_DOUBLE: \
472 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
473 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
474 u5); \
475 } \
476 break; \
477 default: \
478 assert(0); \
479 } \
480 }
481
482 MSA_TEROP_IMMU_DF(binsli, binsl)
483 MSA_TEROP_IMMU_DF(binsri, binsr)
484 #undef MSA_TEROP_IMMU_DF
485
486 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
487 {
488 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
489 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
490 return abs_arg1 > abs_arg2 ? arg1 : arg2;
491 }
492
493 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
494 {
495 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
496 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
497 return abs_arg1 < abs_arg2 ? arg1 : arg2;
498 }
499
500 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
501 {
502 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
503 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
504 return abs_arg1 + abs_arg2;
505 }
506
507 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
508 {
509 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
510 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
511 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
512 if (abs_arg1 > max_int || abs_arg2 > max_int) {
513 return (int64_t)max_int;
514 } else {
515 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
516 }
517 }
518
519 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
520 {
521 int64_t max_int = DF_MAX_INT(df);
522 int64_t min_int = DF_MIN_INT(df);
523 if (arg1 < 0) {
524 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
525 } else {
526 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
527 }
528 }
529
530 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
531 {
532 uint64_t max_uint = DF_MAX_UINT(df);
533 uint64_t u_arg1 = UNSIGNED(arg1, df);
534 uint64_t u_arg2 = UNSIGNED(arg2, df);
535 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
536 }
537
538 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
539 {
540 /* signed shift */
541 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
542 }
543
544 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
545 {
546 uint64_t u_arg1 = UNSIGNED(arg1, df);
547 uint64_t u_arg2 = UNSIGNED(arg2, df);
548 /* unsigned shift */
549 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
550 }
551
552 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
553 {
554 /* signed shift */
555 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
556 }
557
558 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
559 {
560 uint64_t u_arg1 = UNSIGNED(arg1, df);
561 uint64_t u_arg2 = UNSIGNED(arg2, df);
562 /* unsigned shift */
563 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
564 }
565
566 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
567 {
568 int64_t max_int = DF_MAX_INT(df);
569 int64_t min_int = DF_MIN_INT(df);
570 if (arg2 > 0) {
571 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
572 } else {
573 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
574 }
575 }
576
577 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
578 {
579 uint64_t u_arg1 = UNSIGNED(arg1, df);
580 uint64_t u_arg2 = UNSIGNED(arg2, df);
581 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
582 }
583
584 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
585 {
586 uint64_t u_arg1 = UNSIGNED(arg1, df);
587 uint64_t max_uint = DF_MAX_UINT(df);
588 if (arg2 >= 0) {
589 uint64_t u_arg2 = (uint64_t)arg2;
590 return (u_arg1 > u_arg2) ?
591 (int64_t)(u_arg1 - u_arg2) :
592 0;
593 } else {
594 uint64_t u_arg2 = (uint64_t)(-arg2);
595 return (u_arg1 < max_uint - u_arg2) ?
596 (int64_t)(u_arg1 + u_arg2) :
597 (int64_t)max_uint;
598 }
599 }
600
601 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
602 {
603 uint64_t u_arg1 = UNSIGNED(arg1, df);
604 uint64_t u_arg2 = UNSIGNED(arg2, df);
605 int64_t max_int = DF_MAX_INT(df);
606 int64_t min_int = DF_MIN_INT(df);
607 if (u_arg1 > u_arg2) {
608 return u_arg1 - u_arg2 < (uint64_t)max_int ?
609 (int64_t)(u_arg1 - u_arg2) :
610 max_int;
611 } else {
612 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
613 (int64_t)(u_arg1 - u_arg2) :
614 min_int;
615 }
616 }
617
618 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
619 {
620 /* signed compare */
621 return (arg1 < arg2) ?
622 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
623 }
624
625 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
626 {
627 uint64_t u_arg1 = UNSIGNED(arg1, df);
628 uint64_t u_arg2 = UNSIGNED(arg2, df);
629 /* unsigned compare */
630 return (u_arg1 < u_arg2) ?
631 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
632 }
633
634 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
635 {
636 return arg1 * arg2;
637 }
638
639 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
640 {
641 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
642 return DF_MIN_INT(df);
643 }
644 return arg2 ? arg1 / arg2 : 0;
645 }
646
647 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
648 {
649 uint64_t u_arg1 = UNSIGNED(arg1, df);
650 uint64_t u_arg2 = UNSIGNED(arg2, df);
651 return u_arg2 ? u_arg1 / u_arg2 : 0;
652 }
653
654 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
655 {
656 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
657 return 0;
658 }
659 return arg2 ? arg1 % arg2 : 0;
660 }
661
662 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
663 {
664 uint64_t u_arg1 = UNSIGNED(arg1, df);
665 uint64_t u_arg2 = UNSIGNED(arg2, df);
666 return u_arg2 ? u_arg1 % u_arg2 : 0;
667 }
668
669 #define SIGNED_EVEN(a, df) \
670 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
671
672 #define UNSIGNED_EVEN(a, df) \
673 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
674
675 #define SIGNED_ODD(a, df) \
676 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
677
678 #define UNSIGNED_ODD(a, df) \
679 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
680
681 #define SIGNED_EXTRACT(e, o, a, df) \
682 do { \
683 e = SIGNED_EVEN(a, df); \
684 o = SIGNED_ODD(a, df); \
685 } while (0);
686
687 #define UNSIGNED_EXTRACT(e, o, a, df) \
688 do { \
689 e = UNSIGNED_EVEN(a, df); \
690 o = UNSIGNED_ODD(a, df); \
691 } while (0);
692
693 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
694 {
695 int64_t even_arg1;
696 int64_t even_arg2;
697 int64_t odd_arg1;
698 int64_t odd_arg2;
699 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
700 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
701 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
702 }
703
704 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
705 {
706 int64_t even_arg1;
707 int64_t even_arg2;
708 int64_t odd_arg1;
709 int64_t odd_arg2;
710 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
711 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
712 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
713 }
714
715 #define CONCATENATE_AND_SLIDE(s, k) \
716 do { \
717 for (i = 0; i < s; i++) { \
718 v[i] = pws->b[s * k + i]; \
719 v[i + s] = pwd->b[s * k + i]; \
720 } \
721 for (i = 0; i < s; i++) { \
722 pwd->b[s * k + i] = v[i + n]; \
723 } \
724 } while (0)
725
726 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
727 wr_t *pws, target_ulong rt)
728 {
729 uint32_t n = rt % DF_ELEMENTS(df);
730 uint8_t v[64];
731 uint32_t i, k;
732
733 switch (df) {
734 case DF_BYTE:
735 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
736 break;
737 case DF_HALF:
738 for (k = 0; k < 2; k++) {
739 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
740 }
741 break;
742 case DF_WORD:
743 for (k = 0; k < 4; k++) {
744 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
745 }
746 break;
747 case DF_DOUBLE:
748 for (k = 0; k < 8; k++) {
749 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
750 }
751 break;
752 default:
753 assert(0);
754 }
755 }
756
757 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
758 {
759 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
760 }
761
762 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
763 {
764 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
765 }
766
767 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
768 {
769 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
770 }
771
772 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
773 {
774 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
775 }
776
777 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
778 {
779 int64_t q_min = DF_MIN_INT(df);
780 int64_t q_max = DF_MAX_INT(df);
781
782 if (arg1 == q_min && arg2 == q_min) {
783 return q_max;
784 }
785 return (arg1 * arg2) >> (DF_BITS(df) - 1);
786 }
787
788 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
789 {
790 int64_t q_min = DF_MIN_INT(df);
791 int64_t q_max = DF_MAX_INT(df);
792 int64_t r_bit = 1 << (DF_BITS(df) - 2);
793
794 if (arg1 == q_min && arg2 == q_min) {
795 return q_max;
796 }
797 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
798 }
799
800 #define MSA_BINOP_DF(func) \
801 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
802 uint32_t wd, uint32_t ws, uint32_t wt) \
803 { \
804 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
805 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
806 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
807 uint32_t i; \
808 \
809 switch (df) { \
810 case DF_BYTE: \
811 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
812 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
813 } \
814 break; \
815 case DF_HALF: \
816 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
817 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
818 } \
819 break; \
820 case DF_WORD: \
821 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
822 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
823 } \
824 break; \
825 case DF_DOUBLE: \
826 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
827 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
828 } \
829 break; \
830 default: \
831 assert(0); \
832 } \
833 }
834
835 MSA_BINOP_DF(sll)
836 MSA_BINOP_DF(sra)
837 MSA_BINOP_DF(srl)
838 MSA_BINOP_DF(bclr)
839 MSA_BINOP_DF(bset)
840 MSA_BINOP_DF(bneg)
841 MSA_BINOP_DF(addv)
842 MSA_BINOP_DF(subv)
843 MSA_BINOP_DF(max_s)
844 MSA_BINOP_DF(max_u)
845 MSA_BINOP_DF(min_s)
846 MSA_BINOP_DF(min_u)
847 MSA_BINOP_DF(max_a)
848 MSA_BINOP_DF(min_a)
849 MSA_BINOP_DF(ceq)
850 MSA_BINOP_DF(clt_s)
851 MSA_BINOP_DF(clt_u)
852 MSA_BINOP_DF(cle_s)
853 MSA_BINOP_DF(cle_u)
854 MSA_BINOP_DF(add_a)
855 MSA_BINOP_DF(adds_a)
856 MSA_BINOP_DF(adds_s)
857 MSA_BINOP_DF(adds_u)
858 MSA_BINOP_DF(ave_s)
859 MSA_BINOP_DF(ave_u)
860 MSA_BINOP_DF(aver_s)
861 MSA_BINOP_DF(aver_u)
862 MSA_BINOP_DF(subs_s)
863 MSA_BINOP_DF(subs_u)
864 MSA_BINOP_DF(subsus_u)
865 MSA_BINOP_DF(subsuu_s)
866 MSA_BINOP_DF(asub_s)
867 MSA_BINOP_DF(asub_u)
868 MSA_BINOP_DF(mulv)
869 MSA_BINOP_DF(div_s)
870 MSA_BINOP_DF(div_u)
871 MSA_BINOP_DF(mod_s)
872 MSA_BINOP_DF(mod_u)
873 MSA_BINOP_DF(dotp_s)
874 MSA_BINOP_DF(dotp_u)
875 MSA_BINOP_DF(srar)
876 MSA_BINOP_DF(srlr)
877 MSA_BINOP_DF(hadd_s)
878 MSA_BINOP_DF(hadd_u)
879 MSA_BINOP_DF(hsub_s)
880 MSA_BINOP_DF(hsub_u)
881
882 MSA_BINOP_DF(mul_q)
883 MSA_BINOP_DF(mulr_q)
884 #undef MSA_BINOP_DF
885
886 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
887 uint32_t ws, uint32_t rt)
888 {
889 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
890 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
891
892 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
893 }
894
895 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
896 int64_t arg2)
897 {
898 return dest + arg1 * arg2;
899 }
900
901 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
902 int64_t arg2)
903 {
904 return dest - arg1 * arg2;
905 }
906
907 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
908 int64_t arg2)
909 {
910 int64_t even_arg1;
911 int64_t even_arg2;
912 int64_t odd_arg1;
913 int64_t odd_arg2;
914 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
915 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
916 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
917 }
918
919 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
920 int64_t arg2)
921 {
922 int64_t even_arg1;
923 int64_t even_arg2;
924 int64_t odd_arg1;
925 int64_t odd_arg2;
926 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
927 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
928 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
929 }
930
931 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
932 int64_t arg2)
933 {
934 int64_t even_arg1;
935 int64_t even_arg2;
936 int64_t odd_arg1;
937 int64_t odd_arg2;
938 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
939 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
940 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
941 }
942
943 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
944 int64_t arg2)
945 {
946 int64_t even_arg1;
947 int64_t even_arg2;
948 int64_t odd_arg1;
949 int64_t odd_arg2;
950 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
951 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
952 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
953 }
954
955 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
956 int64_t arg2)
957 {
958 int64_t q_prod, q_ret;
959
960 int64_t q_max = DF_MAX_INT(df);
961 int64_t q_min = DF_MIN_INT(df);
962
963 q_prod = arg1 * arg2;
964 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
965
966 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
967 }
968
969 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
970 int64_t arg2)
971 {
972 int64_t q_prod, q_ret;
973
974 int64_t q_max = DF_MAX_INT(df);
975 int64_t q_min = DF_MIN_INT(df);
976
977 q_prod = arg1 * arg2;
978 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
979
980 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
981 }
982
983 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
984 int64_t arg2)
985 {
986 int64_t q_prod, q_ret;
987
988 int64_t q_max = DF_MAX_INT(df);
989 int64_t q_min = DF_MIN_INT(df);
990 int64_t r_bit = 1 << (DF_BITS(df) - 2);
991
992 q_prod = arg1 * arg2;
993 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
994
995 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
996 }
997
998 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
999 int64_t arg2)
1000 {
1001 int64_t q_prod, q_ret;
1002
1003 int64_t q_max = DF_MAX_INT(df);
1004 int64_t q_min = DF_MIN_INT(df);
1005 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1006
1007 q_prod = arg1 * arg2;
1008 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1009
1010 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1011 }
1012
1013 #define MSA_TEROP_DF(func) \
1014 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1015 uint32_t ws, uint32_t wt) \
1016 { \
1017 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1018 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1019 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1020 uint32_t i; \
1021 \
1022 switch (df) { \
1023 case DF_BYTE: \
1024 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1025 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1026 pwt->b[i]); \
1027 } \
1028 break; \
1029 case DF_HALF: \
1030 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1031 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1032 pwt->h[i]); \
1033 } \
1034 break; \
1035 case DF_WORD: \
1036 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1037 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1038 pwt->w[i]); \
1039 } \
1040 break; \
1041 case DF_DOUBLE: \
1042 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1043 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1044 pwt->d[i]); \
1045 } \
1046 break; \
1047 default: \
1048 assert(0); \
1049 } \
1050 }
1051
1052 MSA_TEROP_DF(maddv)
1053 MSA_TEROP_DF(msubv)
1054 MSA_TEROP_DF(dpadd_s)
1055 MSA_TEROP_DF(dpadd_u)
1056 MSA_TEROP_DF(dpsub_s)
1057 MSA_TEROP_DF(dpsub_u)
1058 MSA_TEROP_DF(binsl)
1059 MSA_TEROP_DF(binsr)
1060 MSA_TEROP_DF(madd_q)
1061 MSA_TEROP_DF(msub_q)
1062 MSA_TEROP_DF(maddr_q)
1063 MSA_TEROP_DF(msubr_q)
1064 #undef MSA_TEROP_DF
1065
1066 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1067 wr_t *pws, target_ulong rt)
1068 {
1069 uint32_t n = rt % DF_ELEMENTS(df);
1070 uint32_t i;
1071
1072 switch (df) {
1073 case DF_BYTE:
1074 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1075 pwd->b[i] = pws->b[n];
1076 }
1077 break;
1078 case DF_HALF:
1079 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1080 pwd->h[i] = pws->h[n];
1081 }
1082 break;
1083 case DF_WORD:
1084 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1085 pwd->w[i] = pws->w[n];
1086 }
1087 break;
1088 case DF_DOUBLE:
1089 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1090 pwd->d[i] = pws->d[n];
1091 }
1092 break;
1093 default:
1094 assert(0);
1095 }
1096 }
1097
1098 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1099 uint32_t ws, uint32_t rt)
1100 {
1101 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1102 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1103
1104 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1105 }
1106
1107 #define MSA_DO_B MSA_DO(b)
1108 #define MSA_DO_H MSA_DO(h)
1109 #define MSA_DO_W MSA_DO(w)
1110 #define MSA_DO_D MSA_DO(d)
1111
1112 #define MSA_LOOP_B MSA_LOOP(B)
1113 #define MSA_LOOP_H MSA_LOOP(H)
1114 #define MSA_LOOP_W MSA_LOOP(W)
1115 #define MSA_LOOP_D MSA_LOOP(D)
1116
1117 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1118 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1119 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1120 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1121
1122 #define MSA_LOOP(DF) \
1123 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1124 MSA_DO_ ## DF \
1125 }
1126
1127 #define MSA_FN_DF(FUNC) \
1128 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1129 uint32_t ws, uint32_t wt) \
1130 { \
1131 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1132 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1133 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1134 wr_t wx, *pwx = &wx; \
1135 uint32_t i; \
1136 switch (df) { \
1137 case DF_BYTE: \
1138 MSA_LOOP_B \
1139 break; \
1140 case DF_HALF: \
1141 MSA_LOOP_H \
1142 break; \
1143 case DF_WORD: \
1144 MSA_LOOP_W \
1145 break; \
1146 case DF_DOUBLE: \
1147 MSA_LOOP_D \
1148 break; \
1149 default: \
1150 assert(0); \
1151 } \
1152 msa_move_v(pwd, pwx); \
1153 }
1154
1155 #define MSA_LOOP_COND(DF) \
1156 (DF_ELEMENTS(DF) / 2)
1157
1158 #define Rb(pwr, i) (pwr->b[i])
1159 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1160 #define Rh(pwr, i) (pwr->h[i])
1161 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1162 #define Rw(pwr, i) (pwr->w[i])
1163 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1164 #define Rd(pwr, i) (pwr->d[i])
1165 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1166
1167 #define MSA_DO(DF) \
1168 do { \
1169 R##DF(pwx, i) = pwt->DF[2*i]; \
1170 L##DF(pwx, i) = pws->DF[2*i]; \
1171 } while (0);
1172 MSA_FN_DF(pckev_df)
1173 #undef MSA_DO
1174
1175 #define MSA_DO(DF) \
1176 do { \
1177 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1178 L##DF(pwx, i) = pws->DF[2*i+1]; \
1179 } while (0);
1180 MSA_FN_DF(pckod_df)
1181 #undef MSA_DO
1182
1183 #define MSA_DO(DF) \
1184 do { \
1185 pwx->DF[2*i] = L##DF(pwt, i); \
1186 pwx->DF[2*i+1] = L##DF(pws, i); \
1187 } while (0);
1188 MSA_FN_DF(ilvl_df)
1189 #undef MSA_DO
1190
1191 #define MSA_DO(DF) \
1192 do { \
1193 pwx->DF[2*i] = R##DF(pwt, i); \
1194 pwx->DF[2*i+1] = R##DF(pws, i); \
1195 } while (0);
1196 MSA_FN_DF(ilvr_df)
1197 #undef MSA_DO
1198
1199 #define MSA_DO(DF) \
1200 do { \
1201 pwx->DF[2*i] = pwt->DF[2*i]; \
1202 pwx->DF[2*i+1] = pws->DF[2*i]; \
1203 } while (0);
1204 MSA_FN_DF(ilvev_df)
1205 #undef MSA_DO
1206
1207 #define MSA_DO(DF) \
1208 do { \
1209 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1210 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1211 } while (0);
1212 MSA_FN_DF(ilvod_df)
1213 #undef MSA_DO
1214 #undef MSA_LOOP_COND
1215
1216 #define MSA_LOOP_COND(DF) \
1217 (DF_ELEMENTS(DF))
1218
1219 #define MSA_DO(DF) \
1220 do { \
1221 uint32_t n = DF_ELEMENTS(df); \
1222 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1223 pwx->DF[i] = \
1224 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1225 } while (0);
1226 MSA_FN_DF(vshf_df)
1227 #undef MSA_DO
1228 #undef MSA_LOOP_COND
1229 #undef MSA_FN_DF
1230
1231 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1232 uint32_t ws, uint32_t n)
1233 {
1234 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1235 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1236
1237 msa_sld_df(df, pwd, pws, n);
1238 }
1239
1240 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1241 uint32_t ws, uint32_t n)
1242 {
1243 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1244 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1245
1246 msa_splat_df(df, pwd, pws, n);
1247 }
1248
1249 void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1250 uint32_t ws, uint32_t n)
1251 {
1252 n %= DF_ELEMENTS(df);
1253
1254 switch (df) {
1255 case DF_BYTE:
1256 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1257 break;
1258 case DF_HALF:
1259 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1260 break;
1261 case DF_WORD:
1262 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1263 break;
1264 #ifdef TARGET_MIPS64
1265 case DF_DOUBLE:
1266 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1267 break;
1268 #endif
1269 default:
1270 assert(0);
1271 }
1272 }
1273
1274 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1275 uint32_t ws, uint32_t n)
1276 {
1277 n %= DF_ELEMENTS(df);
1278
1279 switch (df) {
1280 case DF_BYTE:
1281 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1282 break;
1283 case DF_HALF:
1284 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1285 break;
1286 case DF_WORD:
1287 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1288 break;
1289 #ifdef TARGET_MIPS64
1290 case DF_DOUBLE:
1291 env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
1292 break;
1293 #endif
1294 default:
1295 assert(0);
1296 }
1297 }
1298
1299 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1300 uint32_t rs_num, uint32_t n)
1301 {
1302 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1303 target_ulong rs = env->active_tc.gpr[rs_num];
1304
1305 switch (df) {
1306 case DF_BYTE:
1307 pwd->b[n] = (int8_t)rs;
1308 break;
1309 case DF_HALF:
1310 pwd->h[n] = (int16_t)rs;
1311 break;
1312 case DF_WORD:
1313 pwd->w[n] = (int32_t)rs;
1314 break;
1315 case DF_DOUBLE:
1316 pwd->d[n] = (int64_t)rs;
1317 break;
1318 default:
1319 assert(0);
1320 }
1321 }
1322
1323 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1324 uint32_t ws, uint32_t n)
1325 {
1326 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1327 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1328
1329 switch (df) {
1330 case DF_BYTE:
1331 pwd->b[n] = (int8_t)pws->b[0];
1332 break;
1333 case DF_HALF:
1334 pwd->h[n] = (int16_t)pws->h[0];
1335 break;
1336 case DF_WORD:
1337 pwd->w[n] = (int32_t)pws->w[0];
1338 break;
1339 case DF_DOUBLE:
1340 pwd->d[n] = (int64_t)pws->d[0];
1341 break;
1342 default:
1343 assert(0);
1344 }
1345 }
1346
1347 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1348 {
1349 switch (cd) {
1350 case 0:
1351 break;
1352 case 1:
1353 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1354 restore_msa_fp_status(env);
1355 /* check exception */
1356 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1357 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1358 do_raise_exception(env, EXCP_MSAFPE, GETPC());
1359 }
1360 break;
1361 }
1362 }
1363
1364 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1365 {
1366 switch (cs) {
1367 case 0:
1368 return env->msair;
1369 case 1:
1370 return env->active_tc.msacsr & MSACSR_MASK;
1371 }
1372 return 0;
1373 }
1374
1375 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1376 {
1377 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1378 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1379
1380 msa_move_v(pwd, pws);
1381 }
1382
1383 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1384 {
1385 uint64_t x;
1386
1387 x = UNSIGNED(arg, df);
1388
1389 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1390 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1391 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1392 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1393 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1394 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1395
1396 return x;
1397 }
1398
1399 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1400 {
1401 uint64_t x, y;
1402 int n, c;
1403
1404 x = UNSIGNED(arg, df);
1405 n = DF_BITS(df);
1406 c = DF_BITS(df) / 2;
1407
1408 do {
1409 y = x >> c;
1410 if (y != 0) {
1411 n = n - c;
1412 x = y;
1413 }
1414 c = c >> 1;
1415 } while (c != 0);
1416
1417 return n - x;
1418 }
1419
1420 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1421 {
1422 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1423 }
1424
1425 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1426 uint32_t rs)
1427 {
1428 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1429 uint32_t i;
1430
1431 switch (df) {
1432 case DF_BYTE:
1433 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1434 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1435 }
1436 break;
1437 case DF_HALF:
1438 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1439 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1440 }
1441 break;
1442 case DF_WORD:
1443 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1444 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1445 }
1446 break;
1447 case DF_DOUBLE:
1448 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1449 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1450 }
1451 break;
1452 default:
1453 assert(0);
1454 }
1455 }
1456
1457 #define MSA_UNOP_DF(func) \
1458 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1459 uint32_t wd, uint32_t ws) \
1460 { \
1461 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1462 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1463 uint32_t i; \
1464 \
1465 switch (df) { \
1466 case DF_BYTE: \
1467 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1468 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1469 } \
1470 break; \
1471 case DF_HALF: \
1472 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1473 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1474 } \
1475 break; \
1476 case DF_WORD: \
1477 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1478 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1479 } \
1480 break; \
1481 case DF_DOUBLE: \
1482 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1483 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1484 } \
1485 break; \
1486 default: \
1487 assert(0); \
1488 } \
1489 }
1490
1491 MSA_UNOP_DF(nlzc)
1492 MSA_UNOP_DF(nloc)
1493 MSA_UNOP_DF(pcnt)
1494 #undef MSA_UNOP_DF
1495
1496 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1497 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1498
1499 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
1500 /* 0x7c20 */
1501 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
1502 /* 0x7f800020 */
1503 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
1504 /* 0x7ff0000000000020 */
1505
1506 static inline void clear_msacsr_cause(CPUMIPSState *env)
1507 {
1508 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1509 }
1510
1511 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
1512 {
1513 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1514 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1515 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1516 GET_FP_CAUSE(env->active_tc.msacsr));
1517 } else {
1518 do_raise_exception(env, EXCP_MSAFPE, retaddr);
1519 }
1520 }
1521
1522 /* Flush-to-zero use cases for update_msacsr() */
1523 #define CLEAR_FS_UNDERFLOW 1
1524 #define CLEAR_IS_INEXACT 2
1525 #define RECIPROCAL_INEXACT 4
1526
1527 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1528 {
1529 int ieee_ex;
1530
1531 int c;
1532 int cause;
1533 int enable;
1534
1535 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1536
1537 /* QEMU softfloat does not signal all underflow cases */
1538 if (denormal) {
1539 ieee_ex |= float_flag_underflow;
1540 }
1541
1542 c = ieee_ex_to_mips(ieee_ex);
1543 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1544
1545 /* Set Inexact (I) when flushing inputs to zero */
1546 if ((ieee_ex & float_flag_input_denormal) &&
1547 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1548 if (action & CLEAR_IS_INEXACT) {
1549 c &= ~FP_INEXACT;
1550 } else {
1551 c |= FP_INEXACT;
1552 }
1553 }
1554
1555 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1556 if ((ieee_ex & float_flag_output_denormal) &&
1557 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1558 c |= FP_INEXACT;
1559 if (action & CLEAR_FS_UNDERFLOW) {
1560 c &= ~FP_UNDERFLOW;
1561 } else {
1562 c |= FP_UNDERFLOW;
1563 }
1564 }
1565
1566 /* Set Inexact (I) when Overflow (O) is not enabled */
1567 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1568 c |= FP_INEXACT;
1569 }
1570
1571 /* Clear Exact Underflow when Underflow (U) is not enabled */
1572 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1573 (c & FP_INEXACT) == 0) {
1574 c &= ~FP_UNDERFLOW;
1575 }
1576
1577 /* Reciprocal operations set only Inexact when valid and not
1578 divide by zero */
1579 if ((action & RECIPROCAL_INEXACT) &&
1580 (c & (FP_INVALID | FP_DIV0)) == 0) {
1581 c = FP_INEXACT;
1582 }
1583
1584 cause = c & enable; /* all current enabled exceptions */
1585
1586 if (cause == 0) {
1587 /* No enabled exception, update the MSACSR Cause
1588 with all current exceptions */
1589 SET_FP_CAUSE(env->active_tc.msacsr,
1590 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1591 } else {
1592 /* Current exceptions are enabled */
1593 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1594 /* Exception(s) will trap, update MSACSR Cause
1595 with all enabled exceptions */
1596 SET_FP_CAUSE(env->active_tc.msacsr,
1597 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1598 }
1599 }
1600
1601 return c;
1602 }
1603
1604 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1605 {
1606 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1607 return c & enable;
1608 }
1609
1610 static inline float16 float16_from_float32(int32_t a, flag ieee,
1611 float_status *status)
1612 {
1613 float16 f_val;
1614
1615 f_val = float32_to_float16((float32)a, ieee, status);
1616 f_val = float16_maybe_silence_nan(f_val, status);
1617
1618 return a < 0 ? (f_val | (1 << 15)) : f_val;
1619 }
1620
1621 static inline float32 float32_from_float64(int64_t a, float_status *status)
1622 {
1623 float32 f_val;
1624
1625 f_val = float64_to_float32((float64)a, status);
1626 f_val = float32_maybe_silence_nan(f_val, status);
1627
1628 return a < 0 ? (f_val | (1 << 31)) : f_val;
1629 }
1630
1631 static inline float32 float32_from_float16(int16_t a, flag ieee,
1632 float_status *status)
1633 {
1634 float32 f_val;
1635
1636 f_val = float16_to_float32((float16)a, ieee, status);
1637 f_val = float32_maybe_silence_nan(f_val, status);
1638
1639 return a < 0 ? (f_val | (1 << 31)) : f_val;
1640 }
1641
1642 static inline float64 float64_from_float32(int32_t a, float_status *status)
1643 {
1644 float64 f_val;
1645
1646 f_val = float32_to_float64((float64)a, status);
1647 f_val = float64_maybe_silence_nan(f_val, status);
1648
1649 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1650 }
1651
1652 static inline float32 float32_from_q16(int16_t a, float_status *status)
1653 {
1654 float32 f_val;
1655
1656 /* conversion as integer and scaling */
1657 f_val = int32_to_float32(a, status);
1658 f_val = float32_scalbn(f_val, -15, status);
1659
1660 return f_val;
1661 }
1662
1663 static inline float64 float64_from_q32(int32_t a, float_status *status)
1664 {
1665 float64 f_val;
1666
1667 /* conversion as integer and scaling */
1668 f_val = int32_to_float64(a, status);
1669 f_val = float64_scalbn(f_val, -31, status);
1670
1671 return f_val;
1672 }
1673
1674 static inline int16_t float32_to_q16(float32 a, float_status *status)
1675 {
1676 int32_t q_val;
1677 int32_t q_min = 0xffff8000;
1678 int32_t q_max = 0x00007fff;
1679
1680 int ieee_ex;
1681
1682 if (float32_is_any_nan(a)) {
1683 float_raise(float_flag_invalid, status);
1684 return 0;
1685 }
1686
1687 /* scaling */
1688 a = float32_scalbn(a, 15, status);
1689
1690 ieee_ex = get_float_exception_flags(status);
1691 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1692 , status);
1693
1694 if (ieee_ex & float_flag_overflow) {
1695 float_raise(float_flag_inexact, status);
1696 return (int32_t)a < 0 ? q_min : q_max;
1697 }
1698
1699 /* conversion to int */
1700 q_val = float32_to_int32(a, status);
1701
1702 ieee_ex = get_float_exception_flags(status);
1703 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1704 , status);
1705
1706 if (ieee_ex & float_flag_invalid) {
1707 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1708 , status);
1709 float_raise(float_flag_overflow | float_flag_inexact, status);
1710 return (int32_t)a < 0 ? q_min : q_max;
1711 }
1712
1713 if (q_val < q_min) {
1714 float_raise(float_flag_overflow | float_flag_inexact, status);
1715 return (int16_t)q_min;
1716 }
1717
1718 if (q_max < q_val) {
1719 float_raise(float_flag_overflow | float_flag_inexact, status);
1720 return (int16_t)q_max;
1721 }
1722
1723 return (int16_t)q_val;
1724 }
1725
1726 static inline int32_t float64_to_q32(float64 a, float_status *status)
1727 {
1728 int64_t q_val;
1729 int64_t q_min = 0xffffffff80000000LL;
1730 int64_t q_max = 0x000000007fffffffLL;
1731
1732 int ieee_ex;
1733
1734 if (float64_is_any_nan(a)) {
1735 float_raise(float_flag_invalid, status);
1736 return 0;
1737 }
1738
1739 /* scaling */
1740 a = float64_scalbn(a, 31, status);
1741
1742 ieee_ex = get_float_exception_flags(status);
1743 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1744 , status);
1745
1746 if (ieee_ex & float_flag_overflow) {
1747 float_raise(float_flag_inexact, status);
1748 return (int64_t)a < 0 ? q_min : q_max;
1749 }
1750
1751 /* conversion to integer */
1752 q_val = float64_to_int64(a, status);
1753
1754 ieee_ex = get_float_exception_flags(status);
1755 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1756 , status);
1757
1758 if (ieee_ex & float_flag_invalid) {
1759 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1760 , status);
1761 float_raise(float_flag_overflow | float_flag_inexact, status);
1762 return (int64_t)a < 0 ? q_min : q_max;
1763 }
1764
1765 if (q_val < q_min) {
1766 float_raise(float_flag_overflow | float_flag_inexact, status);
1767 return (int32_t)q_min;
1768 }
1769
1770 if (q_max < q_val) {
1771 float_raise(float_flag_overflow | float_flag_inexact, status);
1772 return (int32_t)q_max;
1773 }
1774
1775 return (int32_t)q_val;
1776 }
1777
1778 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1779 do { \
1780 float_status *status = &env->active_tc.msa_fp_status; \
1781 int c; \
1782 int64_t cond; \
1783 set_float_exception_flags(0, status); \
1784 if (!QUIET) { \
1785 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1786 } else { \
1787 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1788 } \
1789 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1790 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1791 \
1792 if (get_enabled_exceptions(env, c)) { \
1793 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
1794 } \
1795 } while (0)
1796
1797 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1798 do { \
1799 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1800 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1801 DEST = 0; \
1802 } \
1803 } while (0)
1804
1805 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1806 do { \
1807 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1808 if (DEST == 0) { \
1809 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1810 } \
1811 } while (0)
1812
1813 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1814 do { \
1815 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1816 if (DEST == 0) { \
1817 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1818 } \
1819 } while (0)
1820
1821 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1822 do { \
1823 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1824 if (DEST == 0) { \
1825 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1826 if (DEST == 0) { \
1827 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1828 } \
1829 } \
1830 } while (0)
1831
1832 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1833 do { \
1834 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1835 if (DEST == 0) { \
1836 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1837 } \
1838 } while (0)
1839
1840 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1841 do { \
1842 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1843 if (DEST == 0) { \
1844 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1845 } \
1846 } while (0)
1847
1848 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1849 do { \
1850 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1851 if (DEST == 0) { \
1852 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1853 } \
1854 } while (0)
1855
1856 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1857 wr_t *pwt, uint32_t df, int quiet,
1858 uintptr_t retaddr)
1859 {
1860 wr_t wx, *pwx = &wx;
1861 uint32_t i;
1862
1863 clear_msacsr_cause(env);
1864
1865 switch (df) {
1866 case DF_WORD:
1867 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1868 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1869 }
1870 break;
1871 case DF_DOUBLE:
1872 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1873 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1874 }
1875 break;
1876 default:
1877 assert(0);
1878 }
1879
1880 check_msacsr_cause(env, retaddr);
1881
1882 msa_move_v(pwd, pwx);
1883 }
1884
1885 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1886 wr_t *pwt, uint32_t df, int quiet,
1887 uintptr_t retaddr)
1888 {
1889 wr_t wx, *pwx = &wx;
1890 uint32_t i;
1891
1892 clear_msacsr_cause(env);
1893
1894 switch (df) {
1895 case DF_WORD:
1896 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1897 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1898 quiet);
1899 }
1900 break;
1901 case DF_DOUBLE:
1902 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1903 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1904 quiet);
1905 }
1906 break;
1907 default:
1908 assert(0);
1909 }
1910
1911 check_msacsr_cause(env, retaddr);
1912
1913 msa_move_v(pwd, pwx);
1914 }
1915
1916 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1917 wr_t *pwt, uint32_t df, int quiet,
1918 uintptr_t retaddr)
1919 {
1920 wr_t wx, *pwx = &wx;
1921 uint32_t i;
1922
1923 clear_msacsr_cause(env);
1924
1925 switch (df) {
1926 case DF_WORD:
1927 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1928 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1929 }
1930 break;
1931 case DF_DOUBLE:
1932 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1933 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1934 }
1935 break;
1936 default:
1937 assert(0);
1938 }
1939
1940 check_msacsr_cause(env, retaddr);
1941
1942 msa_move_v(pwd, pwx);
1943 }
1944
1945 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1946 wr_t *pwt, uint32_t df, int quiet,
1947 uintptr_t retaddr)
1948 {
1949 wr_t wx, *pwx = &wx;
1950 uint32_t i;
1951
1952 clear_msacsr_cause(env);
1953
1954 switch (df) {
1955 case DF_WORD:
1956 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1957 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1958 }
1959 break;
1960 case DF_DOUBLE:
1961 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1962 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1963 }
1964 break;
1965 default:
1966 assert(0);
1967 }
1968
1969 check_msacsr_cause(env, retaddr);
1970
1971 msa_move_v(pwd, pwx);
1972 }
1973
1974 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1975 wr_t *pwt, uint32_t df, int quiet,
1976 uintptr_t retaddr)
1977 {
1978 wr_t wx, *pwx = &wx;
1979 uint32_t i;
1980
1981 clear_msacsr_cause(env);
1982
1983 switch (df) {
1984 case DF_WORD:
1985 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1986 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
1987 }
1988 break;
1989 case DF_DOUBLE:
1990 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1991 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
1992 }
1993 break;
1994 default:
1995 assert(0);
1996 }
1997
1998 check_msacsr_cause(env, retaddr);
1999
2000 msa_move_v(pwd, pwx);
2001 }
2002
2003 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2004 wr_t *pwt, uint32_t df, int quiet,
2005 uintptr_t retaddr)
2006 {
2007 wr_t wx, *pwx = &wx;
2008 uint32_t i;
2009
2010 clear_msacsr_cause(env);
2011
2012 switch (df) {
2013 case DF_WORD:
2014 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2015 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2016 }
2017 break;
2018 case DF_DOUBLE:
2019 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2020 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2021 }
2022 break;
2023 default:
2024 assert(0);
2025 }
2026
2027 check_msacsr_cause(env, retaddr);
2028
2029 msa_move_v(pwd, pwx);
2030 }
2031
2032 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2033 wr_t *pwt, uint32_t df, int quiet,
2034 uintptr_t retaddr)
2035 {
2036 wr_t wx, *pwx = &wx;
2037 uint32_t i;
2038
2039 clear_msacsr_cause(env);
2040
2041 switch (df) {
2042 case DF_WORD:
2043 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2044 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2045 }
2046 break;
2047 case DF_DOUBLE:
2048 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2049 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2050 }
2051 break;
2052 default:
2053 assert(0);
2054 }
2055
2056 check_msacsr_cause(env, retaddr);
2057
2058 msa_move_v(pwd, pwx);
2059 }
2060
2061 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2062 wr_t *pwt, uint32_t df, int quiet,
2063 uintptr_t retaddr)
2064 {
2065 wr_t wx, *pwx = &wx;
2066 uint32_t i;
2067
2068 clear_msacsr_cause(env);
2069
2070 switch (df) {
2071 case DF_WORD:
2072 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2073 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2074 }
2075 break;
2076 case DF_DOUBLE:
2077 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2078 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2079 }
2080 break;
2081 default:
2082 assert(0);
2083 }
2084
2085 check_msacsr_cause(env, retaddr);
2086
2087 msa_move_v(pwd, pwx);
2088 }
2089
2090 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2091 wr_t *pwt, uint32_t df, int quiet,
2092 uintptr_t retaddr)
2093 {
2094 wr_t wx, *pwx = &wx;
2095 uint32_t i;
2096
2097 clear_msacsr_cause(env);
2098
2099 switch (df) {
2100 case DF_WORD:
2101 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2102 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2103 }
2104 break;
2105 case DF_DOUBLE:
2106 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2107 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2108 }
2109 break;
2110 default:
2111 assert(0);
2112 }
2113
2114 check_msacsr_cause(env, retaddr);
2115
2116 msa_move_v(pwd, pwx);
2117 }
2118
2119 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2120 wr_t *pwt, uint32_t df, int quiet,
2121 uintptr_t retaddr)
2122 {
2123 wr_t wx, *pwx = &wx;
2124 uint32_t i;
2125
2126 clear_msacsr_cause(env);
2127
2128 switch (df) {
2129 case DF_WORD:
2130 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2131 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2132 }
2133 break;
2134 case DF_DOUBLE:
2135 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2136 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2137 }
2138 break;
2139 default:
2140 assert(0);
2141 }
2142
2143 check_msacsr_cause(env, retaddr);
2144
2145 msa_move_v(pwd, pwx);
2146 }
2147
2148 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2149 wr_t *pwt, uint32_t df, int quiet,
2150 uintptr_t retaddr)
2151 {
2152 wr_t wx, *pwx = &wx;
2153 uint32_t i;
2154
2155 clear_msacsr_cause(env);
2156
2157 switch (df) {
2158 case DF_WORD:
2159 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2160 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2161 }
2162 break;
2163 case DF_DOUBLE:
2164 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2165 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2166 }
2167 break;
2168 default:
2169 assert(0);
2170 }
2171
2172 check_msacsr_cause(env, retaddr);
2173
2174 msa_move_v(pwd, pwx);
2175 }
2176
2177 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2178 uint32_t ws, uint32_t wt)
2179 {
2180 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2181 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2182 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2183 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
2184 }
2185
2186 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2187 uint32_t ws, uint32_t wt)
2188 {
2189 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2190 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2191 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2192 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
2193 }
2194
2195 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2196 uint32_t ws, uint32_t wt)
2197 {
2198 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2199 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2200 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2201 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
2202 }
2203
2204 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2205 uint32_t ws, uint32_t wt)
2206 {
2207 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2208 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2209 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2210 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
2211 }
2212
2213 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2214 uint32_t ws, uint32_t wt)
2215 {
2216 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2217 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2218 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2219 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
2220 }
2221
2222 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2223 uint32_t ws, uint32_t wt)
2224 {
2225 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2226 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2227 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2228 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
2229 }
2230
2231 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2232 uint32_t ws, uint32_t wt)
2233 {
2234 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2235 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2236 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2237 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
2238 }
2239
2240 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2241 uint32_t ws, uint32_t wt)
2242 {
2243 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2244 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2245 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2246 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
2247 }
2248
2249 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2250 uint32_t ws, uint32_t wt)
2251 {
2252 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2253 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2254 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2255 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
2256 }
2257
2258 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2259 uint32_t ws, uint32_t wt)
2260 {
2261 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2262 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2263 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2264 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
2265 }
2266
2267 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2268 uint32_t ws, uint32_t wt)
2269 {
2270 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2271 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2272 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2273 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
2274 }
2275
2276 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2277 uint32_t ws, uint32_t wt)
2278 {
2279 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2280 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2281 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2282 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
2283 }
2284
2285 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2286 uint32_t ws, uint32_t wt)
2287 {
2288 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2289 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2290 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2291 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
2292 }
2293
2294 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2295 uint32_t ws, uint32_t wt)
2296 {
2297 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2298 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2299 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2300 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
2301 }
2302
2303 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2304 uint32_t ws, uint32_t wt)
2305 {
2306 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2307 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2308 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2309 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
2310 }
2311
2312 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2313 uint32_t ws, uint32_t wt)
2314 {
2315 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2316 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2317 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2318 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
2319 }
2320
2321 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2322 uint32_t ws, uint32_t wt)
2323 {
2324 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2325 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2326 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2327 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
2328 }
2329
2330 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2331 uint32_t ws, uint32_t wt)
2332 {
2333 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2334 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2335 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2336 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
2337 }
2338
2339 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2340 uint32_t ws, uint32_t wt)
2341 {
2342 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2343 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2344 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2345 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
2346 }
2347
2348 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2349 uint32_t ws, uint32_t wt)
2350 {
2351 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2352 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2353 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2354 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
2355 }
2356
2357 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2358 uint32_t ws, uint32_t wt)
2359 {
2360 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2361 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2362 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2363 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
2364 }
2365
2366 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2367 uint32_t ws, uint32_t wt)
2368 {
2369 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2370 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2371 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2372 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
2373 }
2374
2375 #define float16_is_zero(ARG) 0
2376 #define float16_is_zero_or_denormal(ARG) 0
2377
2378 #define IS_DENORMAL(ARG, BITS) \
2379 (!float ## BITS ## _is_zero(ARG) \
2380 && float ## BITS ## _is_zero_or_denormal(ARG))
2381
2382 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2383 do { \
2384 float_status *status = &env->active_tc.msa_fp_status; \
2385 int c; \
2386 \
2387 set_float_exception_flags(0, status); \
2388 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2389 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2390 \
2391 if (get_enabled_exceptions(env, c)) { \
2392 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2393 } \
2394 } while (0)
2395
2396 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2397 uint32_t ws, uint32_t wt)
2398 {
2399 wr_t wx, *pwx = &wx;
2400 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2401 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2402 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2403 uint32_t i;
2404
2405 clear_msacsr_cause(env);
2406
2407 switch (df) {
2408 case DF_WORD:
2409 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2410 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2411 }
2412 break;
2413 case DF_DOUBLE:
2414 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2415 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2416 }
2417 break;
2418 default:
2419 assert(0);
2420 }
2421
2422 check_msacsr_cause(env, GETPC());
2423 msa_move_v(pwd, pwx);
2424 }
2425
2426 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2427 uint32_t ws, uint32_t wt)
2428 {
2429 wr_t wx, *pwx = &wx;
2430 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2431 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2432 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2433 uint32_t i;
2434
2435 clear_msacsr_cause(env);
2436
2437 switch (df) {
2438 case DF_WORD:
2439 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2440 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2441 }
2442 break;
2443 case DF_DOUBLE:
2444 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2445 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2446 }
2447 break;
2448 default:
2449 assert(0);
2450 }
2451
2452 check_msacsr_cause(env, GETPC());
2453 msa_move_v(pwd, pwx);
2454 }
2455
2456 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2457 uint32_t ws, uint32_t wt)
2458 {
2459 wr_t wx, *pwx = &wx;
2460 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2461 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2462 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2463 uint32_t i;
2464
2465 clear_msacsr_cause(env);
2466
2467 switch (df) {
2468 case DF_WORD:
2469 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2470 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2471 }
2472 break;
2473 case DF_DOUBLE:
2474 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2475 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2476 }
2477 break;
2478 default:
2479 assert(0);
2480 }
2481
2482 check_msacsr_cause(env, GETPC());
2483
2484 msa_move_v(pwd, pwx);
2485 }
2486
2487 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2488 uint32_t ws, uint32_t wt)
2489 {
2490 wr_t wx, *pwx = &wx;
2491 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2492 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2493 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2494 uint32_t i;
2495
2496 clear_msacsr_cause(env);
2497
2498 switch (df) {
2499 case DF_WORD:
2500 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2501 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2502 }
2503 break;
2504 case DF_DOUBLE:
2505 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2506 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2507 }
2508 break;
2509 default:
2510 assert(0);
2511 }
2512
2513 check_msacsr_cause(env, GETPC());
2514
2515 msa_move_v(pwd, pwx);
2516 }
2517
2518 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2519 do { \
2520 float_status *status = &env->active_tc.msa_fp_status; \
2521 int c; \
2522 \
2523 set_float_exception_flags(0, status); \
2524 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2525 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2526 \
2527 if (get_enabled_exceptions(env, c)) { \
2528 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2529 } \
2530 } while (0)
2531
2532 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2533 uint32_t ws, uint32_t wt)
2534 {
2535 wr_t wx, *pwx = &wx;
2536 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2537 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2538 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2539 uint32_t i;
2540
2541 clear_msacsr_cause(env);
2542
2543 switch (df) {
2544 case DF_WORD:
2545 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2546 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2547 pws->w[i], pwt->w[i], 0, 32);
2548 }
2549 break;
2550 case DF_DOUBLE:
2551 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2552 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2553 pws->d[i], pwt->d[i], 0, 64);
2554 }
2555 break;
2556 default:
2557 assert(0);
2558 }
2559
2560 check_msacsr_cause(env, GETPC());
2561
2562 msa_move_v(pwd, pwx);
2563 }
2564
2565 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2566 uint32_t ws, uint32_t wt)
2567 {
2568 wr_t wx, *pwx = &wx;
2569 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2570 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2571 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2572 uint32_t i;
2573
2574 clear_msacsr_cause(env);
2575
2576 switch (df) {
2577 case DF_WORD:
2578 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2579 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2580 pws->w[i], pwt->w[i],
2581 float_muladd_negate_product, 32);
2582 }
2583 break;
2584 case DF_DOUBLE:
2585 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2586 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2587 pws->d[i], pwt->d[i],
2588 float_muladd_negate_product, 64);
2589 }
2590 break;
2591 default:
2592 assert(0);
2593 }
2594
2595 check_msacsr_cause(env, GETPC());
2596
2597 msa_move_v(pwd, pwx);
2598 }
2599
2600 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2601 uint32_t ws, uint32_t wt)
2602 {
2603 wr_t wx, *pwx = &wx;
2604 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2605 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2606 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2607 uint32_t i;
2608
2609 clear_msacsr_cause(env);
2610
2611 switch (df) {
2612 case DF_WORD:
2613 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2614 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2615 pwt->w[i] > 0x200 ? 0x200 :
2616 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2617 32);
2618 }
2619 break;
2620 case DF_DOUBLE:
2621 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2622 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2623 pwt->d[i] > 0x1000 ? 0x1000 :
2624 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2625 64);
2626 }
2627 break;
2628 default:
2629 assert(0);
2630 }
2631
2632 check_msacsr_cause(env, GETPC());
2633
2634 msa_move_v(pwd, pwx);
2635 }
2636
2637 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2638 do { \
2639 float_status *status = &env->active_tc.msa_fp_status; \
2640 int c; \
2641 \
2642 set_float_exception_flags(0, status); \
2643 DEST = float ## BITS ## _ ## OP(ARG, status); \
2644 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2645 \
2646 if (get_enabled_exceptions(env, c)) { \
2647 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2648 } \
2649 } while (0)
2650
2651 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2652 uint32_t ws, uint32_t wt)
2653 {
2654 wr_t wx, *pwx = &wx;
2655 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2656 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2657 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2658 uint32_t i;
2659
2660 clear_msacsr_cause(env);
2661
2662 switch (df) {
2663 case DF_WORD:
2664 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2665 /* Half precision floats come in two formats: standard
2666 IEEE and "ARM" format. The latter gains extra exponent
2667 range by omitting the NaN/Inf encodings. */
2668 flag ieee = 1;
2669
2670 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2671 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2672 }
2673 break;
2674 case DF_DOUBLE:
2675 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2676 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2677 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2678 }
2679 break;
2680 default:
2681 assert(0);
2682 }
2683
2684 check_msacsr_cause(env, GETPC());
2685 msa_move_v(pwd, pwx);
2686 }
2687
2688 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2689 do { \
2690 float_status *status = &env->active_tc.msa_fp_status; \
2691 int c; \
2692 \
2693 set_float_exception_flags(0, status); \
2694 DEST = float ## BITS ## _ ## OP(ARG, status); \
2695 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2696 \
2697 if (get_enabled_exceptions(env, c)) { \
2698 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
2699 } \
2700 } while (0)
2701
2702 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2703 uint32_t ws, uint32_t wt)
2704 {
2705 wr_t wx, *pwx = &wx;
2706 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2707 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2708 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2709 uint32_t i;
2710
2711 clear_msacsr_cause(env);
2712
2713 switch (df) {
2714 case DF_WORD:
2715 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2716 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2717 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2718 }
2719 break;
2720 case DF_DOUBLE:
2721 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2722 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2723 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2724 }
2725 break;
2726 default:
2727 assert(0);
2728 }
2729
2730 check_msacsr_cause(env, GETPC());
2731
2732 msa_move_v(pwd, pwx);
2733 }
2734
2735 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
2736 !float ## BITS ## _is_any_nan(ARG1) \
2737 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
2738
2739 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2740 do { \
2741 float_status *status = &env->active_tc.msa_fp_status; \
2742 int c; \
2743 \
2744 set_float_exception_flags(0, status); \
2745 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2746 c = update_msacsr(env, 0, 0); \
2747 \
2748 if (get_enabled_exceptions(env, c)) { \
2749 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2750 } \
2751 } while (0)
2752
2753 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
2754 do { \
2755 uint## BITS ##_t S = _S, T = _T; \
2756 uint## BITS ##_t as, at, xs, xt, xd; \
2757 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
2758 T = S; \
2759 } \
2760 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
2761 S = T; \
2762 } \
2763 as = float## BITS ##_abs(S); \
2764 at = float## BITS ##_abs(T); \
2765 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2766 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2767 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2768 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2769 } while (0)
2770
2771 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2772 uint32_t ws, uint32_t wt)
2773 {
2774 float_status *status = &env->active_tc.msa_fp_status;
2775 wr_t wx, *pwx = &wx;
2776 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2777 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2778 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2779 uint32_t i;
2780
2781 clear_msacsr_cause(env);
2782
2783 switch (df) {
2784 case DF_WORD:
2785 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2786 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
2787 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2788 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
2789 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2790 } else {
2791 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2792 }
2793 }
2794 break;
2795 case DF_DOUBLE:
2796 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2797 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
2798 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2799 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
2800 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2801 } else {
2802 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2803 }
2804 }
2805 break;
2806 default:
2807 assert(0);
2808 }
2809
2810 check_msacsr_cause(env, GETPC());
2811
2812 msa_move_v(pwd, pwx);
2813 }
2814
2815 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2816 uint32_t ws, uint32_t wt)
2817 {
2818 float_status *status = &env->active_tc.msa_fp_status;
2819 wr_t wx, *pwx = &wx;
2820 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2821 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2822 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2823 uint32_t i;
2824
2825 clear_msacsr_cause(env);
2826
2827 switch (df) {
2828 case DF_WORD:
2829 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2830 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
2831 }
2832 break;
2833 case DF_DOUBLE:
2834 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2835 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
2836 }
2837 break;
2838 default:
2839 assert(0);
2840 }
2841
2842 check_msacsr_cause(env, GETPC());
2843
2844 msa_move_v(pwd, pwx);
2845 }
2846
2847 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2848 uint32_t ws, uint32_t wt)
2849 {
2850 float_status *status = &env->active_tc.msa_fp_status;
2851 wr_t wx, *pwx = &wx;
2852 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2853 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2854 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2855 uint32_t i;
2856
2857 clear_msacsr_cause(env);
2858
2859 switch (df) {
2860 case DF_WORD:
2861 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2862 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
2863 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2864 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
2865 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2866 } else {
2867 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2868 }
2869 }
2870 break;
2871 case DF_DOUBLE:
2872 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2873 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
2874 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2875 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
2876 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2877 } else {
2878 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2879 }
2880 }
2881 break;
2882 default:
2883 assert(0);
2884 }
2885
2886 check_msacsr_cause(env, GETPC());
2887
2888 msa_move_v(pwd, pwx);
2889 }
2890
2891 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2892 uint32_t ws, uint32_t wt)
2893 {
2894 float_status *status = &env->active_tc.msa_fp_status;
2895 wr_t wx, *pwx = &wx;
2896 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2897 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2898 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2899 uint32_t i;
2900
2901 clear_msacsr_cause(env);
2902
2903 switch (df) {
2904 case DF_WORD:
2905 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2906 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
2907 }
2908 break;
2909 case DF_DOUBLE:
2910 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2911 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
2912 }
2913 break;
2914 default:
2915 assert(0);
2916 }
2917
2918 check_msacsr_cause(env, GETPC());
2919
2920 msa_move_v(pwd, pwx);
2921 }
2922
2923 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2924 uint32_t wd, uint32_t ws)
2925 {
2926 float_status* status = &env->active_tc.msa_fp_status;
2927
2928 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2929 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2930 if (df == DF_WORD) {
2931 pwd->w[0] = float_class_s(pws->w[0], status);
2932 pwd->w[1] = float_class_s(pws->w[1], status);
2933 pwd->w[2] = float_class_s(pws->w[2], status);
2934 pwd->w[3] = float_class_s(pws->w[3], status);
2935 } else {
2936 pwd->d[0] = float_class_d(pws->d[0], status);
2937 pwd->d[1] = float_class_d(pws->d[1], status);
2938 }
2939 }
2940
2941 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2942 do { \
2943 float_status *status = &env->active_tc.msa_fp_status; \
2944 int c; \
2945 \
2946 set_float_exception_flags(0, status); \
2947 DEST = float ## BITS ## _ ## OP(ARG, status); \
2948 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2949 \
2950 if (get_enabled_exceptions(env, c)) { \
2951 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2952 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2953 DEST = 0; \
2954 } \
2955 } while (0)
2956
2957 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2958 uint32_t ws)
2959 {
2960 wr_t wx, *pwx = &wx;
2961 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2962 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2963 uint32_t i;
2964
2965 clear_msacsr_cause(env);
2966
2967 switch (df) {
2968 case DF_WORD:
2969 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2970 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
2971 }
2972 break;
2973 case DF_DOUBLE:
2974 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2975 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
2976 }
2977 break;
2978 default:
2979 assert(0);
2980 }
2981
2982 check_msacsr_cause(env, GETPC());
2983
2984 msa_move_v(pwd, pwx);
2985 }
2986
2987 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2988 uint32_t ws)
2989 {
2990 wr_t wx, *pwx = &wx;
2991 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2992 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2993 uint32_t i;
2994
2995 clear_msacsr_cause(env);
2996
2997 switch (df) {
2998 case DF_WORD:
2999 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3000 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
3001 }
3002 break;
3003 case DF_DOUBLE:
3004 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3005 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
3006 }
3007 break;
3008 default:
3009 assert(0);
3010 }
3011
3012 check_msacsr_cause(env, GETPC());
3013
3014 msa_move_v(pwd, pwx);
3015 }
3016
3017 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3018 uint32_t ws)
3019 {
3020 wr_t wx, *pwx = &wx;
3021 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3022 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3023 uint32_t i;
3024
3025 clear_msacsr_cause(env);
3026
3027 switch (df) {
3028 case DF_WORD:
3029 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3030 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3031 }
3032 break;
3033 case DF_DOUBLE:
3034 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3035 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3036 }
3037 break;
3038 default:
3039 assert(0);
3040 }
3041
3042 check_msacsr_cause(env, GETPC());
3043
3044 msa_move_v(pwd, pwx);
3045 }
3046
3047 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3048 do { \
3049 float_status *status = &env->active_tc.msa_fp_status; \
3050 int c; \
3051 \
3052 set_float_exception_flags(0, status); \
3053 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3054 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3055 float ## BITS ## _is_quiet_nan(DEST, status) ? \
3056 0 : RECIPROCAL_INEXACT, \
3057 IS_DENORMAL(DEST, BITS)); \
3058 \
3059 if (get_enabled_exceptions(env, c)) { \
3060 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3061 } \
3062 } while (0)
3063
3064 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3065 uint32_t ws)
3066 {
3067 wr_t wx, *pwx = &wx;
3068 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3069 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3070 uint32_t i;
3071
3072 clear_msacsr_cause(env);
3073
3074 switch (df) {
3075 case DF_WORD:
3076 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3077 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3078 &env->active_tc.msa_fp_status), 32);
3079 }
3080 break;
3081 case DF_DOUBLE:
3082 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3083 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3084 &env->active_tc.msa_fp_status), 64);
3085 }
3086 break;
3087 default:
3088 assert(0);
3089 }
3090
3091 check_msacsr_cause(env, GETPC());
3092
3093 msa_move_v(pwd, pwx);
3094 }
3095
3096 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3097 uint32_t ws)
3098 {
3099 wr_t wx, *pwx = &wx;
3100 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3101 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3102 uint32_t i;
3103
3104 clear_msacsr_cause(env);
3105
3106 switch (df) {
3107 case DF_WORD:
3108 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3109 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3110 }
3111 break;
3112 case DF_DOUBLE:
3113 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3114 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3115 }
3116 break;
3117 default:
3118 assert(0);
3119 }
3120
3121 check_msacsr_cause(env, GETPC());
3122
3123 msa_move_v(pwd, pwx);
3124 }
3125
3126 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3127 uint32_t ws)
3128 {
3129 wr_t wx, *pwx = &wx;
3130 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3131 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3132 uint32_t i;
3133
3134 clear_msacsr_cause(env);
3135
3136 switch (df) {
3137 case DF_WORD:
3138 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3139 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3140 }
3141 break;
3142 case DF_DOUBLE:
3143 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3144 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3145 }
3146 break;
3147 default:
3148 assert(0);
3149 }
3150
3151 check_msacsr_cause(env, GETPC());
3152
3153 msa_move_v(pwd, pwx);
3154 }
3155
3156 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3157 do { \
3158 float_status *status = &env->active_tc.msa_fp_status; \
3159 int c; \
3160 \
3161 set_float_exception_flags(0, status); \
3162 set_float_rounding_mode(float_round_down, status); \
3163 DEST = float ## BITS ## _ ## log2(ARG, status); \
3164 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3165 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3166 MSACSR_RM_MASK) >> MSACSR_RM], \
3167 status); \
3168 \
3169 set_float_exception_flags(get_float_exception_flags(status) & \
3170 (~float_flag_inexact), \
3171 status); \
3172 \
3173 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3174 \
3175 if (get_enabled_exceptions(env, c)) { \
3176 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3177 } \
3178 } while (0)
3179
3180 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3181 uint32_t ws)
3182 {
3183 wr_t wx, *pwx = &wx;
3184 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3185 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3186 uint32_t i;
3187
3188 clear_msacsr_cause(env);
3189
3190 switch (df) {
3191 case DF_WORD:
3192 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3193 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3194 }
3195 break;
3196 case DF_DOUBLE:
3197 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3198 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3199 }
3200 break;
3201 default:
3202 assert(0);
3203 }
3204
3205 check_msacsr_cause(env, GETPC());
3206
3207 msa_move_v(pwd, pwx);
3208 }
3209
3210 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3211 uint32_t ws)
3212 {
3213 wr_t wx, *pwx = &wx;
3214 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3215 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3216 uint32_t i;
3217
3218 clear_msacsr_cause(env);
3219
3220 switch (df) {
3221 case DF_WORD:
3222 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3223 /* Half precision floats come in two formats: standard
3224 IEEE and "ARM" format. The latter gains extra exponent
3225 range by omitting the NaN/Inf encodings. */
3226 flag ieee = 1;
3227
3228 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3229 }
3230 break;
3231 case DF_DOUBLE:
3232 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3233 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3234 }
3235 break;
3236 default:
3237 assert(0);
3238 }
3239
3240 check_msacsr_cause(env, GETPC());
3241 msa_move_v(pwd, pwx);
3242 }
3243
3244 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3245 uint32_t ws)
3246 {
3247 wr_t wx, *pwx = &wx;
3248 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3249 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3250 uint32_t i;
3251
3252 clear_msacsr_cause(env);
3253
3254 switch (df) {
3255 case DF_WORD:
3256 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3257 /* Half precision floats come in two formats: standard
3258 IEEE and "ARM" format. The latter gains extra exponent
3259 range by omitting the NaN/Inf encodings. */
3260 flag ieee = 1;
3261
3262 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3263 }
3264 break;
3265 case DF_DOUBLE:
3266 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3267 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3268 }
3269 break;
3270 default:
3271 assert(0);
3272 }
3273
3274 check_msacsr_cause(env, GETPC());
3275 msa_move_v(pwd, pwx);
3276 }
3277
3278 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3279 uint32_t ws)
3280 {
3281 wr_t wx, *pwx = &wx;
3282 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3283 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3284 uint32_t i;
3285
3286 switch (df) {
3287 case DF_WORD:
3288 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3289 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3290 }
3291 break;
3292 case DF_DOUBLE:
3293 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3294 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3295 }
3296 break;
3297 default:
3298 assert(0);
3299 }
3300
3301 msa_move_v(pwd, pwx);
3302 }
3303
3304 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3305 uint32_t ws)
3306 {
3307 wr_t wx, *pwx = &wx;
3308 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3309 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3310 uint32_t i;
3311
3312 switch (df) {
3313 case DF_WORD:
3314 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3315 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3316 }
3317 break;
3318 case DF_DOUBLE:
3319 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3320 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3321 }
3322 break;
3323 default:
3324 assert(0);
3325 }
3326
3327 msa_move_v(pwd, pwx);
3328 }
3329
3330 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3331 uint32_t ws)
3332 {
3333 wr_t wx, *pwx = &wx;
3334 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3335 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3336 uint32_t i;
3337
3338 clear_msacsr_cause(env);
3339
3340 switch (df) {
3341 case DF_WORD:
3342 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3343 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3344 }
3345 break;
3346 case DF_DOUBLE:
3347 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3348 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3349 }
3350 break;
3351 default:
3352 assert(0);
3353 }
3354
3355 check_msacsr_cause(env, GETPC());
3356
3357 msa_move_v(pwd, pwx);
3358 }
3359
3360 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3361 uint32_t ws)
3362 {
3363 wr_t wx, *pwx = &wx;
3364 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3365 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3366 uint32_t i;
3367
3368 clear_msacsr_cause(env);
3369
3370 switch (df) {
3371 case DF_WORD:
3372 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3373 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3374 }
3375 break;
3376 case DF_DOUBLE:
3377 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3378 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3379 }
3380 break;
3381 default:
3382 assert(0);
3383 }
3384
3385 check_msacsr_cause(env, GETPC());
3386
3387 msa_move_v(pwd, pwx);
3388 }
3389
3390 #define float32_from_int32 int32_to_float32
3391 #define float32_from_uint32 uint32_to_float32
3392
3393 #define float64_from_int64 int64_to_float64
3394 #define float64_from_uint64 uint64_to_float64
3395
3396 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3397 uint32_t ws)
3398 {
3399 wr_t wx, *pwx = &wx;
3400 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3401 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3402 uint32_t i;
3403
3404 clear_msacsr_cause(env);
3405
3406 switch (df) {
3407 case DF_WORD:
3408 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3409 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3410 }
3411 break;
3412 case DF_DOUBLE:
3413 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3414 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3415 }
3416 break;
3417 default:
3418 assert(0);
3419 }
3420
3421 check_msacsr_cause(env, GETPC());
3422
3423 msa_move_v(pwd, pwx);
3424 }
3425
3426 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3427 uint32_t ws)
3428 {
3429 wr_t wx, *pwx = &wx;
3430 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3431 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3432 uint32_t i;
3433
3434 clear_msacsr_cause(env);
3435
3436 switch (df) {
3437 case DF_WORD:
3438 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3439 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3440 }
3441 break;
3442 case DF_DOUBLE:
3443 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3444 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3445 }
3446 break;
3447 default:
3448 assert(0);
3449 }
3450
3451 check_msacsr_cause(env, GETPC());
3452
3453 msa_move_v(pwd, pwx);
3454 }
AR7 emulation for QEMU