hw/acpi/ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   8  *
   9  * This is based on acpi.c.
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License version 2 as published by the Free Software Foundation.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  22  *
  23  * Contributions after 2012-01-13 are licensed under the terms of the
  24  * GNU GPL, version 2 or (at your option) any later version.
  25  */
  26 #include "hw/hw.h"
  27 #include "qapi/visitor.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/pci/pci.h"
  30 #include "qemu/timer.h"
  31 #include "sysemu/sysemu.h"
  32 #include "hw/acpi/acpi.h"
  33 #include "sysemu/kvm.h"
  34 #include "exec/address-spaces.h"
  35
  36 #include "hw/i386/ich9.h"
  37
  38 //#define DEBUG
  39
  40 #ifdef DEBUG
  41 #define ICH9_DEBUG(fmt, ...) \
  42 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
  43 #else
  44 #define ICH9_DEBUG(fmt, ...)    do { } while (0)
  45 #endif
  46
  47 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
  48 {
  49     ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
  50     acpi_update_sci(&pm->acpi_regs, pm->irq);
  51 }
  52
  53 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
  54 {
  55     ICH9LPCPMRegs *pm = opaque;
  56     return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
  57 }
  58
  59 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
  60                             unsigned width)
  61 {
  62     ICH9LPCPMRegs *pm = opaque;
  63     acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
  64     acpi_update_sci(&pm->acpi_regs, pm->irq);
  65 }
  66
  67 static const MemoryRegionOps ich9_gpe_ops = {
  68     .read = ich9_gpe_readb,
  69     .write = ich9_gpe_writeb,
  70     .valid.min_access_size = 1,
  71     .valid.max_access_size = 4,
  72     .impl.min_access_size = 1,
  73     .impl.max_access_size = 1,
  74     .endianness = DEVICE_LITTLE_ENDIAN,
  75 };
  76
  77 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
  78 {
  79     ICH9LPCPMRegs *pm = opaque;
  80     switch (addr) {
  81     case 0:
  82         return pm->smi_en;
  83     case 4:
  84         return pm->smi_sts;
  85     default:
  86         return 0;
  87     }
  88 }
  89
  90 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
  91                             unsigned width)
  92 {
  93     ICH9LPCPMRegs *pm = opaque;
  94     switch (addr) {
  95     case 0:
  96         pm->smi_en = val;
  97         break;
  98     }
  99 }
 100
 101 static const MemoryRegionOps ich9_smi_ops = {
 102     .read = ich9_smi_readl,
 103     .write = ich9_smi_writel,
 104     .valid.min_access_size = 4,
 105     .valid.max_access_size = 4,
 106     .endianness = DEVICE_LITTLE_ENDIAN,
 107 };
 108
 109 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
 110 {
 111     ICH9_DEBUG("to 0x%x\n", pm_io_base);
 112
 113     assert((pm_io_base & ICH9_PMIO_MASK) == 0);
 114
 115     pm->pm_io_base = pm_io_base;
 116     memory_region_transaction_begin();
 117     memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
 118     memory_region_set_address(&pm->io, pm->pm_io_base);
 119     memory_region_transaction_commit();
 120 }
 121
 122 static int ich9_pm_post_load(void *opaque, int version_id)
 123 {
 124     ICH9LPCPMRegs *pm = opaque;
 125     uint32_t pm_io_base = pm->pm_io_base;
 126     pm->pm_io_base = 0;
 127     ich9_pm_iospace_update(pm, pm_io_base);
 128     return 0;
 129 }
 130
 131 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 132  {                                                                   \
 133      .name       = (stringify(_field)),                              \
 134      .version_id = 0,                                                \
 135      .num        = ICH9_PMIO_GPE0_LEN,                               \
 136      .info       = &vmstate_info_uint8,                              \
 137      .size       = sizeof(uint8_t),                                  \
 138      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 139      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 140  }
 141
 142 const VMStateDescription vmstate_ich9_pm = {
 143     .name = "ich9_pm",
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .minimum_version_id_old = 1,
 147     .post_load = ich9_pm_post_load,
 148     .fields = (VMStateField[]) {
 149         VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
 150         VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
 151         VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
 152         VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
 153         VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
 154         VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
 155         VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
 156         VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
 157         VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
 158         VMSTATE_END_OF_LIST()
 159     }
 160 };
 161
 162 static void pm_reset(void *opaque)
 163 {
 164     ICH9LPCPMRegs *pm = opaque;
 165     ich9_pm_iospace_update(pm, 0);
 166
 167     acpi_pm1_evt_reset(&pm->acpi_regs);
 168     acpi_pm1_cnt_reset(&pm->acpi_regs);
 169     acpi_pm_tmr_reset(&pm->acpi_regs);
 170     acpi_gpe_reset(&pm->acpi_regs);
 171
 172     if (kvm_enabled()) {
 173         /* Mark SMM as already inited to prevent SMM from running. KVM does not
 174          * support SMM mode. */
 175         pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
 176     }
 177
 178     acpi_update_sci(&pm->acpi_regs, pm->irq);
 179 }
 180
 181 static void pm_powerdown_req(Notifier *n, void *opaque)
 182 {
 183     ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
 184
 185     acpi_pm1_evt_power_down(&pm->acpi_regs);
 186 }
 187
 188 static void ich9_cpu_added_req(Notifier *n, void *opaque)
 189 {
 190     ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, cpu_added_notifier);
 191
 192     assert(pm != NULL);
 193     AcpiCpuHotplug_add(&pm->acpi_regs.gpe, &pm->gpe_cpu, CPU(opaque));
 194     acpi_update_sci(&pm->acpi_regs, pm->irq);
 195 }
 196
 197 void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
 198                   qemu_irq sci_irq)
 199 {
 200     memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
 201     memory_region_set_enabled(&pm->io, false);
 202     memory_region_add_subregion(pci_address_space_io(lpc_pci),
 203                                 0, &pm->io);
 204
 205     acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 206     acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 207     acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2);
 208
 209     acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
 210     memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
 211                           "apci-gpe0", ICH9_PMIO_GPE0_LEN);
 212     memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
 213
 214     memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
 215                           "apci-smi", 8);
 216     memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
 217
 218     pm->irq = sci_irq;
 219     qemu_register_reset(pm_reset, pm);
 220     pm->powerdown_notifier.notify = pm_powerdown_req;
 221     qemu_register_powerdown_notifier(&pm->powerdown_notifier);
 222
 223     AcpiCpuHotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci),
 224                         &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
 225     pm->cpu_added_notifier.notify = ich9_cpu_added_req;
 226     qemu_register_cpu_added_notifier(&pm->cpu_added_notifier);
 227 }
 228
 229 static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
 230                                  void *opaque, const char *name,
 231                                  Error **errp)
 232 {
 233     ICH9LPCPMRegs *pm = opaque;
 234     uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
 235
 236     visit_type_uint32(v, &value, name, errp);
 237 }
 238
 239 void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
 240 {
 241     static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
 242
 243     object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
 244                                    &pm->pm_io_base, errp);
 245     object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
 246                         ich9_pm_get_gpe0_blk,
 247                         NULL, NULL, pm, NULL);
 248     object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
 249                                    &gpe0_len, errp);
 250 }