2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
19 #include "hw/pci/pci.h"
22 #include "net/checksum.h"
23 #include "sysemu/sysemu.h"
24 #include "qemu-common.h"
25 #include "qemu/bswap.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
30 #include "vmxnet_debug.h"
31 #include "vmware_utils.h"
32 #include "vmxnet_tx_pkt.h"
33 #include "vmxnet_rx_pkt.h"
35 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
36 #define VMXNET3_MSIX_BAR_SIZE 0x2000
37 #define MIN_BUF_SIZE 60
39 #define VMXNET3_BAR0_IDX (0)
40 #define VMXNET3_BAR1_IDX (1)
41 #define VMXNET3_MSIX_BAR_IDX (2)
43 #define VMXNET3_OFF_MSIX_TABLE (0x000)
44 #define VMXNET3_OFF_MSIX_PBA (0x800)
46 /* Link speed in Mbps should be shifted by 16 */
47 #define VMXNET3_LINK_SPEED (1000 << 16)
49 /* Link status: 1 - up, 0 - down. */
50 #define VMXNET3_LINK_STATUS_UP 0x1
52 /* Least significant bit should be set for revision and version */
53 #define VMXNET3_DEVICE_VERSION 0x1
54 #define VMXNET3_DEVICE_REVISION 0x1
56 /* Number of interrupt vectors for non-MSIx modes */
57 #define VMXNET3_MAX_NMSIX_INTRS (1)
59 /* Macros for rings descriptors access */
60 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
61 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
63 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
64 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
66 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
67 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
69 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
70 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
72 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
73 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
75 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
76 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
78 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
79 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
81 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
82 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
84 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
85 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
87 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
88 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
90 /* Macros for guest driver shared area access */
91 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
92 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
94 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
95 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
97 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
98 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
100 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
101 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
103 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
104 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
106 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
107 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
109 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
111 #define TYPE_VMXNET3 "vmxnet3"
112 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
114 /* Cyclic ring abstraction */
123 static inline void vmxnet3_ring_init(Vmxnet3Ring
*ring
,
131 ring
->cell_size
= cell_size
;
132 ring
->gen
= VMXNET3_INIT_GEN
;
136 vmw_shmem_set(pa
, 0, size
* cell_size
);
140 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
141 macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \
142 (ring_name), (ridx), \
143 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
145 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
147 if (++ring
->next
>= ring
->size
) {
153 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
155 if (ring
->next
-- == 0) {
156 ring
->next
= ring
->size
- 1;
161 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
163 return ring
->pa
+ ring
->next
* ring
->cell_size
;
166 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
168 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
171 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
173 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
176 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
181 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
186 /* Debug trace-related functions */
188 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
190 VMW_PKPRN("TX DESCR: "
191 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
192 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
193 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
194 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
, descr
->rsvd
,
195 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
196 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
200 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
202 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
203 "csum_start: %d, csum_offset: %d",
204 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
205 vhdr
->csum_start
, vhdr
->csum_offset
);
209 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
211 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
212 "dtype: %d, ext1: %d, btype: %d",
213 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
,
214 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
217 /* Device state and helper functions */
218 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
222 Vmxnet3Ring comp_ring
;
226 struct UPT1_TxStats txq_stats
;
230 Vmxnet3Ring rx_ring
[VMXNET3_RX_RINGS_PER_QUEUE
];
231 Vmxnet3Ring comp_ring
;
234 struct UPT1_RxStats rxq_stats
;
244 PCIDevice parent_obj
;
249 MemoryRegion msix_bar
;
251 Vmxnet3RxqDescr rxq_descr
[VMXNET3_DEVICE_MAX_RX_QUEUES
];
252 Vmxnet3TxqDescr txq_descr
[VMXNET3_DEVICE_MAX_TX_QUEUES
];
254 /* Whether MSI-X support was installed successfully */
256 /* Whether MSI support was installed successfully */
259 hwaddr temp_shared_guest_driver_memory
;
263 /* This boolean tells whether RX packet being indicated has to */
264 /* be split into head and body chunks from different RX rings */
265 bool rx_packets_compound
;
267 bool rx_vlan_stripping
;
275 /* Maximum number of fragments for indicated TX packets */
276 uint32_t max_tx_frags
;
278 /* Maximum number of fragments for indicated RX packets */
279 uint16_t max_rx_frags
;
281 /* Index for events interrupt */
282 uint8_t event_int_idx
;
284 /* Whether automatic interrupts masking enabled */
285 bool auto_int_masking
;
289 /* TX packets to QEMU interface */
290 struct VmxnetTxPkt
*tx_pkt
;
291 uint32_t offload_mode
;
292 uint32_t cso_or_gso_size
;
296 struct VmxnetRxPkt
*rx_pkt
;
299 bool skip_current_tx_pkt
;
301 uint32_t device_active
;
302 uint32_t last_command
;
304 uint32_t link_status_and_speed
;
306 Vmxnet3IntState interrupt_states
[VMXNET3_MAX_INTRS
];
308 uint32_t temp_mac
; /* To store the low part first */
311 uint32_t vlan_table
[VMXNET3_VFT_SIZE
];
314 uint32_t mcast_list_len
;
315 uint32_t mcast_list_buff_size
; /* needed for live migration. */
318 /* Interrupt management */
321 *This function returns sign whether interrupt line is in asserted state
322 * This depends on the type of interrupt used. For INTX interrupt line will
323 * be asserted until explicit deassertion, for MSI(X) interrupt line will
324 * be deasserted automatically due to notification semantics of the MSI(X)
327 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
329 PCIDevice
*d
= PCI_DEVICE(s
);
331 if (s
->msix_used
&& msix_enabled(d
)) {
332 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
333 msix_notify(d
, int_idx
);
336 if (s
->msi_used
&& msi_enabled(d
)) {
337 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
338 msi_notify(d
, int_idx
);
342 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
347 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
349 PCIDevice
*d
= PCI_DEVICE(s
);
352 * This function should never be called for MSI(X) interrupts
353 * because deassertion never required for message interrupts
355 assert(!s
->msix_used
|| !msix_enabled(d
));
357 * This function should never be called for MSI(X) interrupts
358 * because deassertion never required for message interrupts
360 assert(!s
->msi_used
|| !msi_enabled(d
));
362 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
366 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
368 if (!s
->interrupt_states
[lidx
].is_pending
&&
369 s
->interrupt_states
[lidx
].is_asserted
) {
370 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
371 _vmxnet3_deassert_interrupt_line(s
, lidx
);
372 s
->interrupt_states
[lidx
].is_asserted
= false;
376 if (s
->interrupt_states
[lidx
].is_pending
&&
377 !s
->interrupt_states
[lidx
].is_masked
&&
378 !s
->interrupt_states
[lidx
].is_asserted
) {
379 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
380 s
->interrupt_states
[lidx
].is_asserted
=
381 _vmxnet3_assert_interrupt_line(s
, lidx
);
382 s
->interrupt_states
[lidx
].is_pending
= false;
387 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
389 PCIDevice
*d
= PCI_DEVICE(s
);
390 s
->interrupt_states
[lidx
].is_pending
= true;
391 vmxnet3_update_interrupt_line_state(s
, lidx
);
393 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
397 if (s
->msi_used
&& msi_enabled(d
) && s
->auto_int_masking
) {
404 s
->interrupt_states
[lidx
].is_masked
= true;
405 vmxnet3_update_interrupt_line_state(s
, lidx
);
408 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
410 return s
->interrupt_states
[lidx
].is_asserted
;
413 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
415 s
->interrupt_states
[int_idx
].is_pending
= false;
416 if (s
->auto_int_masking
) {
417 s
->interrupt_states
[int_idx
].is_masked
= true;
419 vmxnet3_update_interrupt_line_state(s
, int_idx
);
423 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
425 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
426 vmxnet3_update_interrupt_line_state(s
, lidx
);
429 static bool vmxnet3_verify_driver_magic(hwaddr dshmem
)
431 return (VMXNET3_READ_DRV_SHARED32(dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
434 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
435 #define VMXNET3_MAKE_BYTE(byte_num, val) \
436 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
438 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
440 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
441 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
442 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
443 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
444 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
445 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
447 VMW_CFPRN("Variable MAC: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
449 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
452 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
454 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
455 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
456 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
457 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
460 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
462 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
463 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
467 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
469 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
473 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
475 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
479 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
481 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
485 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
487 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
491 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
493 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
496 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32 tx_ridx
)
498 struct Vmxnet3_TxCompDesc txcq_descr
;
500 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
502 txcq_descr
.txdIdx
= tx_ridx
;
503 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
505 vmxnet3_ring_write_curr_cell(&s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
507 /* Flush changes in TX descriptor before changing the counter value */
510 vmxnet3_inc_tx_completion_counter(s
, qidx
);
511 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
515 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
517 switch (s
->offload_mode
) {
518 case VMXNET3_OM_NONE
:
519 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
522 case VMXNET3_OM_CSUM
:
523 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
524 VMW_PKPRN("L4 CSO requested\n");
528 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
530 vmxnet_tx_pkt_update_ip_checksums(s
->tx_pkt
);
531 VMW_PKPRN("GSO offload requested.");
535 g_assert_not_reached();
543 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
544 const struct Vmxnet3_TxDesc
*txd
)
546 s
->offload_mode
= txd
->om
;
547 s
->cso_or_gso_size
= txd
->msscof
;
549 s
->needs_vlan
= txd
->ti
;
553 VMXNET3_PKT_STATUS_OK
,
554 VMXNET3_PKT_STATUS_ERROR
,
555 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
556 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
560 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
561 Vmxnet3PktStatus status
)
563 size_t tot_len
= vmxnet_tx_pkt_get_total_len(s
->tx_pkt
);
564 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
567 case VMXNET3_PKT_STATUS_OK
:
568 switch (vmxnet_tx_pkt_get_packet_type(s
->tx_pkt
)) {
570 stats
->bcastPktsTxOK
++;
571 stats
->bcastBytesTxOK
+= tot_len
;
574 stats
->mcastPktsTxOK
++;
575 stats
->mcastBytesTxOK
+= tot_len
;
578 stats
->ucastPktsTxOK
++;
579 stats
->ucastBytesTxOK
+= tot_len
;
582 g_assert_not_reached();
585 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
587 * According to VMWARE headers this statistic is a number
588 * of packets after segmentation but since we don't have
589 * this information in QEMU model, the best we can do is to
590 * provide number of non-segmented packets
592 stats
->TSOPktsTxOK
++;
593 stats
->TSOBytesTxOK
+= tot_len
;
597 case VMXNET3_PKT_STATUS_DISCARD
:
598 stats
->pktsTxDiscard
++;
601 case VMXNET3_PKT_STATUS_ERROR
:
602 stats
->pktsTxError
++;
606 g_assert_not_reached();
611 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
613 Vmxnet3PktStatus status
)
615 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
616 size_t tot_len
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
619 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
620 stats
->pktsRxOutOfBuf
++;
623 case VMXNET3_PKT_STATUS_ERROR
:
624 stats
->pktsRxError
++;
626 case VMXNET3_PKT_STATUS_OK
:
627 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
629 stats
->bcastPktsRxOK
++;
630 stats
->bcastBytesRxOK
+= tot_len
;
633 stats
->mcastPktsRxOK
++;
634 stats
->mcastBytesRxOK
+= tot_len
;
637 stats
->ucastPktsRxOK
++;
638 stats
->ucastBytesRxOK
+= tot_len
;
641 g_assert_not_reached();
644 if (tot_len
> s
->mtu
) {
645 stats
->LROPktsRxOK
++;
646 stats
->LROBytesRxOK
+= tot_len
;
650 g_assert_not_reached();
655 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
657 struct Vmxnet3_TxDesc
*txd
,
660 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
662 vmxnet3_ring_read_curr_cell(ring
, txd
);
663 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
664 /* Only read after generation field verification */
666 /* Re-read to be sure we got the latest version */
667 vmxnet3_ring_read_curr_cell(ring
, txd
);
668 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
669 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
670 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
678 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
680 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
682 if (!vmxnet3_setup_tx_offloads(s
)) {
683 status
= VMXNET3_PKT_STATUS_ERROR
;
688 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s
->tx_pkt
));
689 vmxnet_tx_pkt_dump(s
->tx_pkt
);
691 if (!vmxnet_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
692 status
= VMXNET3_PKT_STATUS_DISCARD
;
697 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
698 return (status
== VMXNET3_PKT_STATUS_OK
);
701 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
703 struct Vmxnet3_TxDesc txd
;
709 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
713 vmxnet3_dump_tx_descr(&txd
);
715 if (!s
->skip_current_tx_pkt
) {
716 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
717 data_pa
= le64_to_cpu(txd
.addr
);
719 if (!vmxnet_tx_pkt_add_raw_fragment(s
->tx_pkt
,
722 s
->skip_current_tx_pkt
= true;
727 vmxnet3_tx_retrieve_metadata(s
, &txd
);
732 if (!s
->skip_current_tx_pkt
&& vmxnet_tx_pkt_parse(s
->tx_pkt
)) {
734 vmxnet_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
737 vmxnet3_send_packet(s
, qidx
);
739 vmxnet3_on_tx_done_update_stats(s
, qidx
,
740 VMXNET3_PKT_STATUS_ERROR
);
743 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
745 s
->skip_current_tx_pkt
= false;
746 vmxnet_tx_pkt_reset(s
->tx_pkt
);
752 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
753 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
755 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
756 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
757 vmxnet3_ring_read_curr_cell(ring
, dbuf
);
760 static inline uint8_t
761 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
763 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
767 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
770 struct Vmxnet3_RxCompDesc rxcd
;
773 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
775 cpu_physical_memory_read(daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
776 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
778 if (rxcd
.gen
!= ring_gen
) {
779 *descr_gen
= ring_gen
;
780 vmxnet3_inc_rx_completion_counter(s
, qidx
);
788 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
790 vmxnet3_dec_rx_completion_counter(s
, qidx
);
794 #define RX_HEAD_BODY_RING (0)
795 #define RX_BODY_ONLY_RING (1)
798 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
799 struct Vmxnet3_RxDesc
*descr_buf
,
805 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
806 descr_buf
, descr_idx
);
808 /* If no more free descriptors - return */
809 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
810 if (descr_buf
->gen
!= ring_gen
) {
814 /* Only read after generation field verification */
816 /* Re-read to be sure we got the latest version */
817 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
818 descr_buf
, descr_idx
);
820 /* Mark current descriptor as used/skipped */
821 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
823 /* If this is what we are looking for - return */
824 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
825 *ridx
= RX_HEAD_BODY_RING
;
832 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
833 struct Vmxnet3_RxDesc
*d
,
837 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
839 /* Try to find corresponding descriptor in head/body ring */
840 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
841 /* Only read after generation field verification */
843 /* Re-read to be sure we got the latest version */
844 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
845 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
846 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
847 *ridx
= RX_HEAD_BODY_RING
;
853 * If there is no free descriptors on head/body ring or next free
854 * descriptor is a head descriptor switch to body only ring
856 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
858 /* If no more free descriptors - return */
859 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
860 /* Only read after generation field verification */
862 /* Re-read to be sure we got the latest version */
863 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
864 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
865 *ridx
= RX_BODY_ONLY_RING
;
866 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
874 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
875 struct Vmxnet3_RxDesc
*descr_buf
,
879 if (is_head
|| !s
->rx_packets_compound
) {
880 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
882 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
886 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
887 * the implementation always passes an RxCompDesc with a "Checksum
888 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
889 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
891 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
892 * and place a fully computed checksum into the tcp/udp header.
893 * Otherwise, the OS driver will receive a checksum-correct indication
894 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
895 * having just the pseudo header csum value.
897 * While this is not a problem if packet is destined for local delivery,
898 * in the case the host OS performs forwarding, it will forward an
899 * incorrectly checksummed packet.
901 static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt
*pkt
,
902 const void *pkt_data
,
905 struct virtio_net_hdr
*vhdr
;
906 bool isip4
, isip6
, istcp
, isudp
;
910 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
914 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
915 if (!VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
919 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
920 if (!(isip4
|| isip6
) || !(istcp
|| isudp
)) {
924 vmxnet3_dump_virt_hdr(vhdr
);
926 /* Validate packet len: csum_start + scum_offset + length of csum field */
927 if (pkt_len
< (vhdr
->csum_start
+ vhdr
->csum_offset
+ 2)) {
928 VMW_PKPRN("packet len:%lu < csum_start(%d) + csum_offset(%d) + 2, "
929 "cannot calculate checksum",
930 pkt_len
, vhdr
->csum_start
, vhdr
->csum_offset
);
934 data
= (uint8_t *)pkt_data
+ vhdr
->csum_start
;
935 len
= pkt_len
- vhdr
->csum_start
;
936 /* Put the checksum obtained into the packet */
937 stw_be_p(data
+ vhdr
->csum_offset
, net_raw_checksum(data
, len
));
939 vhdr
->flags
&= ~VIRTIO_NET_HDR_F_NEEDS_CSUM
;
940 vhdr
->flags
|= VIRTIO_NET_HDR_F_DATA_VALID
;
943 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt
*pkt
,
944 struct Vmxnet3_RxCompDesc
*rxcd
)
947 bool isip4
, isip6
, istcp
, isudp
;
948 struct virtio_net_hdr
*vhdr
;
949 uint8_t offload_type
;
951 if (vmxnet_rx_pkt_is_vlan_stripped(pkt
)) {
953 rxcd
->tci
= vmxnet_rx_pkt_get_vlan_tag(pkt
);
956 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
960 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
962 * Checksum is valid when lower level tell so or when lower level
963 * requires checksum offload telling that packet produced/bridged
964 * locally and did travel over network after last checksum calculation
967 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
968 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
970 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
971 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
973 if (!csum_ok
&& !is_gso
) {
977 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
978 if ((!istcp
&& !isudp
) || (!isip4
&& !isip6
)) {
983 rxcd
->v4
= isip4
? 1 : 0;
984 rxcd
->v6
= isip6
? 1 : 0;
985 rxcd
->tcp
= istcp
? 1 : 0;
986 rxcd
->udp
= isudp
? 1 : 0;
987 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
996 vmxnet3_physical_memory_writev(const struct iovec
*iov
,
997 size_t start_iov_off
,
999 size_t bytes_to_copy
)
1001 size_t curr_off
= 0;
1004 while (bytes_to_copy
) {
1005 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
1007 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
1009 cpu_physical_memory_write(target_addr
+ copied
,
1010 iov
->iov_base
+ start_iov_off
- curr_off
,
1013 copied
+= chunk_len
;
1014 start_iov_off
+= chunk_len
;
1015 curr_off
= start_iov_off
;
1016 bytes_to_copy
-= chunk_len
;
1018 curr_off
+= iov
->iov_len
;
1025 vmxnet3_indicate_packet(VMXNET3State
*s
)
1027 struct Vmxnet3_RxDesc rxd
;
1028 bool is_head
= true;
1030 uint32_t rx_ridx
= 0;
1032 struct Vmxnet3_RxCompDesc rxcd
;
1033 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
1034 hwaddr new_rxcd_pa
= 0;
1035 hwaddr ready_rxcd_pa
= 0;
1036 struct iovec
*data
= vmxnet_rx_pkt_get_iovec(s
->rx_pkt
);
1037 size_t bytes_copied
= 0;
1038 size_t bytes_left
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
1039 uint16_t num_frags
= 0;
1042 vmxnet_rx_pkt_dump(s
->rx_pkt
);
1044 while (bytes_left
> 0) {
1046 /* cannot add more frags to packet */
1047 if (num_frags
== s
->max_rx_frags
) {
1051 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
1056 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1060 chunk_size
= MIN(bytes_left
, rxd
.len
);
1061 vmxnet3_physical_memory_writev(data
, bytes_copied
,
1062 le64_to_cpu(rxd
.addr
), chunk_size
);
1063 bytes_copied
+= chunk_size
;
1064 bytes_left
-= chunk_size
;
1066 vmxnet3_dump_rx_descr(&rxd
);
1068 if (ready_rxcd_pa
!= 0) {
1069 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1072 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1073 rxcd
.rxdIdx
= rxd_idx
;
1074 rxcd
.len
= chunk_size
;
1076 rxcd
.gen
= new_rxcd_gen
;
1077 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1079 if (bytes_left
== 0) {
1080 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1083 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1084 "sop %d csum_correct %lu",
1085 (unsigned long) rx_ridx
,
1086 (unsigned long) rxcd
.rxdIdx
,
1087 (unsigned long) rxcd
.len
,
1089 (unsigned long) rxcd
.tuc
);
1092 ready_rxcd_pa
= new_rxcd_pa
;
1097 if (ready_rxcd_pa
!= 0) {
1099 rxcd
.err
= (bytes_left
!= 0);
1100 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1102 /* Flush RX descriptor changes */
1106 if (new_rxcd_pa
!= 0) {
1107 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1110 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1112 if (bytes_left
== 0) {
1113 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1115 } else if (num_frags
== s
->max_rx_frags
) {
1116 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1119 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1120 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1126 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1127 uint64_t val
, unsigned size
)
1129 VMXNET3State
*s
= opaque
;
1131 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1132 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1134 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1136 assert(tx_queue_idx
<= s
->txq_num
);
1137 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1141 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1142 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1143 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1146 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1148 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1152 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1153 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1154 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1155 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1159 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1160 (uint64_t) addr
, val
, size
);
1164 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1166 VMXNET3State
*s
= opaque
;
1168 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1169 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1170 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1172 return s
->interrupt_states
[l
].is_masked
;
1175 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1179 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1182 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1183 s
->interrupt_states
[i
].is_asserted
= false;
1184 s
->interrupt_states
[i
].is_pending
= false;
1185 s
->interrupt_states
[i
].is_masked
= true;
1189 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1191 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1192 VMW_CFPRN("MAC address set to: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
1195 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1197 VMW_CBPRN("Deactivating vmxnet3...");
1198 s
->device_active
= false;
1201 static void vmxnet3_reset(VMXNET3State
*s
)
1203 VMW_CBPRN("Resetting vmxnet3...");
1205 vmxnet3_deactivate_device(s
);
1206 vmxnet3_reset_interrupt_states(s
);
1207 vmxnet_tx_pkt_reset(s
->tx_pkt
);
1210 s
->skip_current_tx_pkt
= false;
1213 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1215 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1216 devRead
.rxFilterConf
.rxMode
);
1217 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1220 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1224 /* Copy configuration from shared memory */
1225 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
,
1226 devRead
.rxFilterConf
.vfTable
,
1228 sizeof(s
->vlan_table
));
1230 /* Invert byte order when needed */
1231 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1232 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1235 /* Dump configuration for debugging purposes */
1236 VMW_CFPRN("Configured VLANs:");
1237 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1238 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1239 VMW_CFPRN("\tVLAN %d is present", i
);
1244 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1246 uint16_t list_bytes
=
1247 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
,
1248 devRead
.rxFilterConf
.mfTableLen
);
1250 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1252 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1253 if (!s
->mcast_list
) {
1254 if (s
->mcast_list_len
== 0) {
1255 VMW_CFPRN("Current multicast list is empty");
1257 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1260 s
->mcast_list_len
= 0;
1263 hwaddr mcast_list_pa
=
1264 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
,
1265 devRead
.rxFilterConf
.mfTablePA
);
1267 cpu_physical_memory_read(mcast_list_pa
, s
->mcast_list
, list_bytes
);
1268 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1269 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1270 VMW_CFPRN("\t" VMXNET_MF
, VMXNET_MA(s
->mcast_list
[i
].a
));
1275 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1277 vmxnet3_update_rx_mode(s
);
1278 vmxnet3_update_vlan_filters(s
);
1279 vmxnet3_update_mcast_filters(s
);
1282 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1284 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1285 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1286 return interrupt_mode
;
1289 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1292 for (i
= 0; i
< s
->txq_num
; i
++) {
1293 cpu_physical_memory_write(s
->txq_descr
[i
].tx_stats_pa
,
1294 &s
->txq_descr
[i
].txq_stats
,
1295 sizeof(s
->txq_descr
[i
].txq_stats
));
1298 for (i
= 0; i
< s
->rxq_num
; i
++) {
1299 cpu_physical_memory_write(s
->rxq_descr
[i
].rx_stats_pa
,
1300 &s
->rxq_descr
[i
].rxq_stats
,
1301 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1305 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1307 struct Vmxnet3_GOSInfo gos
;
1309 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1311 s
->rx_packets_compound
=
1312 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1314 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1318 vmxnet3_dump_conf_descr(const char *name
,
1319 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1321 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1322 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1326 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1328 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1331 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1333 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1335 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1337 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1340 static void vmxnet3_update_features(VMXNET3State
*s
)
1342 uint32_t guest_features
;
1343 int rxcso_supported
;
1345 guest_features
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1346 devRead
.misc
.uptFeatures
);
1348 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1349 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1350 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1352 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1353 s
->lro_supported
, rxcso_supported
,
1354 s
->rx_vlan_stripping
);
1355 if (s
->peer_has_vhdr
) {
1356 qemu_set_offload(qemu_get_queue(s
->nic
)->peer
,
1365 static bool vmxnet3_verify_intx(VMXNET3State
*s
, int intx
)
1367 return s
->msix_used
|| s
->msi_used
|| (intx
==
1368 (pci_get_byte(s
->parent_obj
.config
+ PCI_INTERRUPT_PIN
) - 1));
1371 static void vmxnet3_validate_interrupt_idx(bool is_msix
, int idx
)
1373 int max_ints
= is_msix
? VMXNET3_MAX_INTRS
: VMXNET3_MAX_NMSIX_INTRS
;
1374 if (idx
>= max_ints
) {
1375 hw_error("Bad interrupt index: %d\n", idx
);
1379 static void vmxnet3_validate_interrupts(VMXNET3State
*s
)
1383 VMW_CFPRN("Verifying event interrupt index (%d)", s
->event_int_idx
);
1384 vmxnet3_validate_interrupt_idx(s
->msix_used
, s
->event_int_idx
);
1386 for (i
= 0; i
< s
->txq_num
; i
++) {
1387 int idx
= s
->txq_descr
[i
].intr_idx
;
1388 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i
, idx
);
1389 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1392 for (i
= 0; i
< s
->rxq_num
; i
++) {
1393 int idx
= s
->rxq_descr
[i
].intr_idx
;
1394 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i
, idx
);
1395 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1399 static void vmxnet3_validate_queues(VMXNET3State
*s
)
1402 * txq_num and rxq_num are total number of queues
1403 * configured by guest. These numbers must not
1404 * exceed corresponding maximal values.
1407 if (s
->txq_num
> VMXNET3_DEVICE_MAX_TX_QUEUES
) {
1408 hw_error("Bad TX queues number: %d\n", s
->txq_num
);
1411 if (s
->rxq_num
> VMXNET3_DEVICE_MAX_RX_QUEUES
) {
1412 hw_error("Bad RX queues number: %d\n", s
->rxq_num
);
1416 static void vmxnet3_activate_device(VMXNET3State
*s
)
1419 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1420 hwaddr qdescr_table_pa
;
1424 /* Verify configuration consistency */
1425 if (!vmxnet3_verify_driver_magic(s
->drv_shmem
)) {
1426 VMW_ERPRN("Device configuration received from driver is invalid");
1430 vmxnet3_adjust_by_guest_type(s
);
1431 vmxnet3_update_features(s
);
1432 vmxnet3_update_pm_state(s
);
1433 vmxnet3_setup_rx_filtering(s
);
1434 /* Cache fields from shared memory */
1435 s
->mtu
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.misc
.mtu
);
1436 VMW_CFPRN("MTU is %u", s
->mtu
);
1439 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1441 if (s
->max_rx_frags
== 0) {
1442 s
->max_rx_frags
= 1;
1445 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1448 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1449 assert(vmxnet3_verify_intx(s
, s
->event_int_idx
));
1450 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1452 s
->auto_int_masking
=
1453 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1454 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1457 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1459 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1461 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1462 vmxnet3_validate_queues(s
);
1465 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1466 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1469 * Worst-case scenario is a packet that holds all TX rings space so
1470 * we calculate total size of all TX rings for max TX fragments number
1472 s
->max_tx_frags
= 0;
1475 for (i
= 0; i
< s
->txq_num
; i
++) {
1477 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1479 /* Read interrupt number for this TX queue */
1480 s
->txq_descr
[i
].intr_idx
=
1481 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa
, conf
.intrIdx
);
1482 assert(vmxnet3_verify_intx(s
, s
->txq_descr
[i
].intr_idx
));
1484 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1486 /* Read rings memory locations for TX queues */
1487 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.txRingBasePA
);
1488 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.txRingSize
);
1490 vmxnet3_ring_init(&s
->txq_descr
[i
].tx_ring
, pa
, size
,
1491 sizeof(struct Vmxnet3_TxDesc
), false);
1492 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1494 s
->max_tx_frags
+= size
;
1497 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.compRingBasePA
);
1498 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.compRingSize
);
1499 vmxnet3_ring_init(&s
->txq_descr
[i
].comp_ring
, pa
, size
,
1500 sizeof(struct Vmxnet3_TxCompDesc
), true);
1501 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1503 s
->txq_descr
[i
].tx_stats_pa
=
1504 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1506 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1507 sizeof(s
->txq_descr
[i
].txq_stats
));
1509 /* Fill device-managed parameters for queues */
1510 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa
,
1512 VMXNET3_DEF_TX_THRESHOLD
);
1515 /* Preallocate TX packet wrapper */
1516 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1517 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
1518 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
1520 /* Read rings memory locations for RX queues */
1521 for (i
= 0; i
< s
->rxq_num
; i
++) {
1524 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1525 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1527 /* Read interrupt number for this RX queue */
1528 s
->rxq_descr
[i
].intr_idx
=
1529 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa
, conf
.intrIdx
);
1530 assert(vmxnet3_verify_intx(s
, s
->rxq_descr
[i
].intr_idx
));
1532 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1534 /* Read rings memory locations */
1535 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1537 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.rxRingBasePA
[j
]);
1538 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.rxRingSize
[j
]);
1539 vmxnet3_ring_init(&s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1540 sizeof(struct Vmxnet3_RxDesc
), false);
1541 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1546 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.compRingBasePA
);
1547 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.compRingSize
);
1548 vmxnet3_ring_init(&s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1549 sizeof(struct Vmxnet3_RxCompDesc
), true);
1550 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1552 s
->rxq_descr
[i
].rx_stats_pa
=
1553 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1554 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1555 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1558 vmxnet3_validate_interrupts(s
);
1560 /* Make sure everything is in place before device activation */
1563 vmxnet3_reset_mac(s
);
1565 s
->device_active
= true;
1568 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1570 s
->last_command
= cmd
;
1573 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1574 VMW_CBPRN("Set: Get upper part of permanent MAC");
1577 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1578 VMW_CBPRN("Set: Get lower part of permanent MAC");
1581 case VMXNET3_CMD_GET_STATS
:
1582 VMW_CBPRN("Set: Get device statistics");
1583 vmxnet3_fill_stats(s
);
1586 case VMXNET3_CMD_ACTIVATE_DEV
:
1587 VMW_CBPRN("Set: Activating vmxnet3 device");
1588 vmxnet3_activate_device(s
);
1591 case VMXNET3_CMD_UPDATE_RX_MODE
:
1592 VMW_CBPRN("Set: Update rx mode");
1593 vmxnet3_update_rx_mode(s
);
1596 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1597 VMW_CBPRN("Set: Update VLAN filters");
1598 vmxnet3_update_vlan_filters(s
);
1601 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1602 VMW_CBPRN("Set: Update MAC filters");
1603 vmxnet3_update_mcast_filters(s
);
1606 case VMXNET3_CMD_UPDATE_FEATURE
:
1607 VMW_CBPRN("Set: Update features");
1608 vmxnet3_update_features(s
);
1611 case VMXNET3_CMD_UPDATE_PMCFG
:
1612 VMW_CBPRN("Set: Update power management config");
1613 vmxnet3_update_pm_state(s
);
1616 case VMXNET3_CMD_GET_LINK
:
1617 VMW_CBPRN("Set: Get link");
1620 case VMXNET3_CMD_RESET_DEV
:
1621 VMW_CBPRN("Set: Reset device");
1625 case VMXNET3_CMD_QUIESCE_DEV
:
1626 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
1627 vmxnet3_deactivate_device(s
);
1630 case VMXNET3_CMD_GET_CONF_INTR
:
1631 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1634 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1635 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1636 "adaptive ring info flags");
1640 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1645 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1649 switch (s
->last_command
) {
1650 case VMXNET3_CMD_ACTIVATE_DEV
:
1651 ret
= (s
->device_active
) ? 0 : -1;
1652 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1655 case VMXNET3_CMD_RESET_DEV
:
1656 case VMXNET3_CMD_QUIESCE_DEV
:
1657 case VMXNET3_CMD_GET_QUEUE_STATUS
:
1661 case VMXNET3_CMD_GET_LINK
:
1662 ret
= s
->link_status_and_speed
;
1663 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1666 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1667 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1670 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1671 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1674 case VMXNET3_CMD_GET_CONF_INTR
:
1675 ret
= vmxnet3_get_interrupt_config(s
);
1678 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1679 ret
= VMXNET3_DISABLE_ADAPTIVE_RING
;
1683 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1691 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1695 VMW_CBPRN("Setting events: 0x%x", val
);
1696 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) | val
;
1697 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1700 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1704 VMW_CBPRN("Clearing events: 0x%x", val
);
1705 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) & ~val
;
1706 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1710 vmxnet3_io_bar1_write(void *opaque
,
1715 VMXNET3State
*s
= opaque
;
1718 /* Vmxnet3 Revision Report Selection */
1719 case VMXNET3_REG_VRRS
:
1720 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1724 /* UPT Version Report Selection */
1725 case VMXNET3_REG_UVRS
:
1726 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1730 /* Driver Shared Address Low */
1731 case VMXNET3_REG_DSAL
:
1732 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1735 * Guest driver will first write the low part of the shared
1736 * memory address. We save it to temp variable and set the
1737 * shared address only after we get the high part
1740 s
->device_active
= false;
1742 s
->temp_shared_guest_driver_memory
= val
;
1746 /* Driver Shared Address High */
1747 case VMXNET3_REG_DSAH
:
1748 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1751 * Set the shared memory between guest driver and device.
1752 * We already should have low address part.
1754 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1758 case VMXNET3_REG_CMD
:
1759 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1761 vmxnet3_handle_command(s
, val
);
1764 /* MAC Address Low */
1765 case VMXNET3_REG_MACL
:
1766 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1771 /* MAC Address High */
1772 case VMXNET3_REG_MACH
:
1773 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1775 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1778 /* Interrupt Cause Register */
1779 case VMXNET3_REG_ICR
:
1780 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1782 g_assert_not_reached();
1785 /* Event Cause Register */
1786 case VMXNET3_REG_ECR
:
1787 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1789 vmxnet3_ack_events(s
, val
);
1793 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1800 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1802 VMXNET3State
*s
= opaque
;
1806 /* Vmxnet3 Revision Report Selection */
1807 case VMXNET3_REG_VRRS
:
1808 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1809 ret
= VMXNET3_DEVICE_REVISION
;
1812 /* UPT Version Report Selection */
1813 case VMXNET3_REG_UVRS
:
1814 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1815 ret
= VMXNET3_DEVICE_VERSION
;
1819 case VMXNET3_REG_CMD
:
1820 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1821 ret
= vmxnet3_get_command_status(s
);
1824 /* MAC Address Low */
1825 case VMXNET3_REG_MACL
:
1826 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1827 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1830 /* MAC Address High */
1831 case VMXNET3_REG_MACH
:
1832 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1833 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1837 * Interrupt Cause Register
1838 * Used for legacy interrupts only so interrupt index always 0
1840 case VMXNET3_REG_ICR
:
1841 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1842 if (vmxnet3_interrupt_asserted(s
, 0)) {
1843 vmxnet3_clear_interrupt(s
, 0);
1851 VMW_CBPRN("Unknow read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1859 vmxnet3_can_receive(NetClientState
*nc
)
1861 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1862 return s
->device_active
&&
1863 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1867 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1869 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1870 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1874 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1878 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1881 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1882 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1890 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1893 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1895 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1899 if (!vmxnet3_is_registered_vlan(s
, data
)) {
1903 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
1905 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
1908 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
1914 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
1920 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
1923 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
1926 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
1932 g_assert_not_reached();
1939 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
1941 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1942 size_t bytes_indicated
;
1943 uint8_t min_buf
[MIN_BUF_SIZE
];
1945 if (!vmxnet3_can_receive(nc
)) {
1946 VMW_PKPRN("Cannot receive now");
1950 if (s
->peer_has_vhdr
) {
1951 vmxnet_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
1952 buf
+= sizeof(struct virtio_net_hdr
);
1953 size
-= sizeof(struct virtio_net_hdr
);
1956 /* Pad to minimum Ethernet frame length */
1957 if (size
< sizeof(min_buf
)) {
1958 memcpy(min_buf
, buf
, size
);
1959 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
1961 size
= sizeof(min_buf
);
1964 vmxnet_rx_pkt_set_packet_type(s
->rx_pkt
,
1965 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
1967 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
1968 vmxnet_rx_pkt_set_protocols(s
->rx_pkt
, buf
, size
);
1969 vmxnet3_rx_need_csum_calculate(s
->rx_pkt
, buf
, size
);
1970 vmxnet_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
1971 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
1972 if (bytes_indicated
< size
) {
1973 VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated
, size
);
1976 VMW_PKPRN("Packet dropped by RX filter");
1977 bytes_indicated
= size
;
1981 assert(bytes_indicated
!= 0);
1982 return bytes_indicated
;
1985 static void vmxnet3_set_link_status(NetClientState
*nc
)
1987 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1989 if (nc
->link_down
) {
1990 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
1992 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
1995 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
1996 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
1999 static NetClientInfo net_vmxnet3_info
= {
2000 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
2001 .size
= sizeof(NICState
),
2002 .receive
= vmxnet3_receive
,
2003 .link_status_changed
= vmxnet3_set_link_status
,
2006 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
2008 NetClientState
*nc
= qemu_get_queue(s
->nic
);
2010 if (qemu_has_vnet_hdr(nc
->peer
)) {
2014 VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
2018 static void vmxnet3_net_uninit(VMXNET3State
*s
)
2020 g_free(s
->mcast_list
);
2021 vmxnet_tx_pkt_reset(s
->tx_pkt
);
2022 vmxnet_tx_pkt_uninit(s
->tx_pkt
);
2023 vmxnet_rx_pkt_uninit(s
->rx_pkt
);
2024 qemu_del_nic(s
->nic
);
2027 static void vmxnet3_net_init(VMXNET3State
*s
)
2029 DeviceState
*d
= DEVICE(s
);
2031 VMW_CBPRN("vmxnet3_net_init called...");
2033 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
2035 /* Windows guest will query the address that was set on init */
2036 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
2038 s
->mcast_list
= NULL
;
2039 s
->mcast_list_len
= 0;
2041 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
2043 VMW_CFPRN("Permanent MAC: " MAC_FMT
, MAC_ARG(s
->perm_mac
.a
));
2045 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
2046 object_get_typename(OBJECT(s
)),
2049 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
2051 s
->skip_current_tx_pkt
= false;
2054 s
->rx_vlan_stripping
= false;
2055 s
->lro_supported
= false;
2057 if (s
->peer_has_vhdr
) {
2058 qemu_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
2059 sizeof(struct virtio_net_hdr
));
2061 qemu_using_vnet_hdr(qemu_get_queue(s
->nic
)->peer
, 1);
2064 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
2068 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2070 PCIDevice
*d
= PCI_DEVICE(s
);
2072 for (i
= 0; i
< num_vectors
; i
++) {
2073 msix_vector_unuse(d
, i
);
2078 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2080 PCIDevice
*d
= PCI_DEVICE(s
);
2082 for (i
= 0; i
< num_vectors
; i
++) {
2083 int res
= msix_vector_use(d
, i
);
2085 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i
, res
);
2086 vmxnet3_unuse_msix_vectors(s
, i
);
2094 vmxnet3_init_msix(VMXNET3State
*s
)
2096 PCIDevice
*d
= PCI_DEVICE(s
);
2097 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
2099 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
2101 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA
,
2105 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
2106 s
->msix_used
= false;
2108 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2109 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res
);
2110 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2111 s
->msix_used
= false;
2113 s
->msix_used
= true;
2116 return s
->msix_used
;
2120 vmxnet3_cleanup_msix(VMXNET3State
*s
)
2122 PCIDevice
*d
= PCI_DEVICE(s
);
2125 vmxnet3_unuse_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2126 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2130 #define VMXNET3_MSI_OFFSET (0x50)
2131 #define VMXNET3_USE_64BIT (true)
2132 #define VMXNET3_PER_VECTOR_MASK (false)
2135 vmxnet3_init_msi(VMXNET3State
*s
)
2137 PCIDevice
*d
= PCI_DEVICE(s
);
2140 res
= msi_init(d
, VMXNET3_MSI_OFFSET
, VMXNET3_MAX_NMSIX_INTRS
,
2141 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
);
2143 VMW_WRPRN("Failed to initialize MSI, error %d", res
);
2144 s
->msi_used
= false;
2153 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2155 PCIDevice
*d
= PCI_DEVICE(s
);
2163 vmxnet3_msix_save(QEMUFile
*f
, void *opaque
)
2165 PCIDevice
*d
= PCI_DEVICE(opaque
);
2170 vmxnet3_msix_load(QEMUFile
*f
, void *opaque
, int version_id
)
2172 PCIDevice
*d
= PCI_DEVICE(opaque
);
2177 static const MemoryRegionOps b0_ops
= {
2178 .read
= vmxnet3_io_bar0_read
,
2179 .write
= vmxnet3_io_bar0_write
,
2180 .endianness
= DEVICE_LITTLE_ENDIAN
,
2182 .min_access_size
= 4,
2183 .max_access_size
= 4,
2187 static const MemoryRegionOps b1_ops
= {
2188 .read
= vmxnet3_io_bar1_read
,
2189 .write
= vmxnet3_io_bar1_write
,
2190 .endianness
= DEVICE_LITTLE_ENDIAN
,
2192 .min_access_size
= 4,
2193 .max_access_size
= 4,
2197 static void vmxnet3_pci_realize(PCIDevice
*pci_dev
, Error
**errp
)
2199 DeviceState
*dev
= DEVICE(pci_dev
);
2200 VMXNET3State
*s
= VMXNET3(pci_dev
);
2202 VMW_CBPRN("Starting init...");
2204 memory_region_init_io(&s
->bar0
, OBJECT(s
), &b0_ops
, s
,
2205 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2206 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2207 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2209 memory_region_init_io(&s
->bar1
, OBJECT(s
), &b1_ops
, s
,
2210 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2211 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2212 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2214 memory_region_init(&s
->msix_bar
, OBJECT(s
), "vmxnet3-msix-bar",
2215 VMXNET3_MSIX_BAR_SIZE
);
2216 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2217 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2219 vmxnet3_reset_interrupt_states(s
);
2221 /* Interrupt pin A */
2222 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2224 if (!vmxnet3_init_msix(s
)) {
2225 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2228 if (!vmxnet3_init_msi(s
)) {
2229 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2232 vmxnet3_net_init(s
);
2234 register_savevm(dev
, "vmxnet3-msix", -1, 1,
2235 vmxnet3_msix_save
, vmxnet3_msix_load
, s
);
2238 static void vmxnet3_instance_init(Object
*obj
)
2240 VMXNET3State
*s
= VMXNET3(obj
);
2241 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
2242 "bootindex", "/ethernet-phy@0",
2246 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2248 DeviceState
*dev
= DEVICE(pci_dev
);
2249 VMXNET3State
*s
= VMXNET3(pci_dev
);
2251 VMW_CBPRN("Starting uninit...");
2253 unregister_savevm(dev
, "vmxnet3-msix", s
);
2255 vmxnet3_net_uninit(s
);
2257 vmxnet3_cleanup_msix(s
);
2259 vmxnet3_cleanup_msi(s
);
2262 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2264 PCIDevice
*d
= PCI_DEVICE(dev
);
2265 VMXNET3State
*s
= VMXNET3(d
);
2267 VMW_CBPRN("Starting QDEV reset...");
2271 static bool vmxnet3_mc_list_needed(void *opaque
)
2276 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2278 VMXNET3State
*s
= opaque
;
2280 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2286 static void vmxnet3_pre_save(void *opaque
)
2288 VMXNET3State
*s
= opaque
;
2290 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2293 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2294 .name
= "vmxnet3/mcast_list",
2296 .minimum_version_id
= 1,
2297 .pre_load
= vmxnet3_mcast_list_pre_load
,
2298 .needed
= vmxnet3_mc_list_needed
,
2299 .fields
= (VMStateField
[]) {
2300 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
, 0,
2301 mcast_list_buff_size
),
2302 VMSTATE_END_OF_LIST()
2306 static void vmxnet3_get_ring_from_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2308 r
->pa
= qemu_get_be64(f
);
2309 r
->size
= qemu_get_be32(f
);
2310 r
->cell_size
= qemu_get_be32(f
);
2311 r
->next
= qemu_get_be32(f
);
2312 r
->gen
= qemu_get_byte(f
);
2315 static void vmxnet3_put_ring_to_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2317 qemu_put_be64(f
, r
->pa
);
2318 qemu_put_be32(f
, r
->size
);
2319 qemu_put_be32(f
, r
->cell_size
);
2320 qemu_put_be32(f
, r
->next
);
2321 qemu_put_byte(f
, r
->gen
);
2324 static void vmxnet3_get_tx_stats_from_file(QEMUFile
*f
,
2325 struct UPT1_TxStats
*tx_stat
)
2327 tx_stat
->TSOPktsTxOK
= qemu_get_be64(f
);
2328 tx_stat
->TSOBytesTxOK
= qemu_get_be64(f
);
2329 tx_stat
->ucastPktsTxOK
= qemu_get_be64(f
);
2330 tx_stat
->ucastBytesTxOK
= qemu_get_be64(f
);
2331 tx_stat
->mcastPktsTxOK
= qemu_get_be64(f
);
2332 tx_stat
->mcastBytesTxOK
= qemu_get_be64(f
);
2333 tx_stat
->bcastPktsTxOK
= qemu_get_be64(f
);
2334 tx_stat
->bcastBytesTxOK
= qemu_get_be64(f
);
2335 tx_stat
->pktsTxError
= qemu_get_be64(f
);
2336 tx_stat
->pktsTxDiscard
= qemu_get_be64(f
);
2339 static void vmxnet3_put_tx_stats_to_file(QEMUFile
*f
,
2340 struct UPT1_TxStats
*tx_stat
)
2342 qemu_put_be64(f
, tx_stat
->TSOPktsTxOK
);
2343 qemu_put_be64(f
, tx_stat
->TSOBytesTxOK
);
2344 qemu_put_be64(f
, tx_stat
->ucastPktsTxOK
);
2345 qemu_put_be64(f
, tx_stat
->ucastBytesTxOK
);
2346 qemu_put_be64(f
, tx_stat
->mcastPktsTxOK
);
2347 qemu_put_be64(f
, tx_stat
->mcastBytesTxOK
);
2348 qemu_put_be64(f
, tx_stat
->bcastPktsTxOK
);
2349 qemu_put_be64(f
, tx_stat
->bcastBytesTxOK
);
2350 qemu_put_be64(f
, tx_stat
->pktsTxError
);
2351 qemu_put_be64(f
, tx_stat
->pktsTxDiscard
);
2354 static int vmxnet3_get_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2356 Vmxnet3TxqDescr
*r
= pv
;
2358 vmxnet3_get_ring_from_file(f
, &r
->tx_ring
);
2359 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2360 r
->intr_idx
= qemu_get_byte(f
);
2361 r
->tx_stats_pa
= qemu_get_be64(f
);
2363 vmxnet3_get_tx_stats_from_file(f
, &r
->txq_stats
);
2368 static void vmxnet3_put_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2370 Vmxnet3TxqDescr
*r
= pv
;
2372 vmxnet3_put_ring_to_file(f
, &r
->tx_ring
);
2373 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2374 qemu_put_byte(f
, r
->intr_idx
);
2375 qemu_put_be64(f
, r
->tx_stats_pa
);
2376 vmxnet3_put_tx_stats_to_file(f
, &r
->txq_stats
);
2379 static const VMStateInfo txq_descr_info
= {
2380 .name
= "txq_descr",
2381 .get
= vmxnet3_get_txq_descr
,
2382 .put
= vmxnet3_put_txq_descr
2385 static void vmxnet3_get_rx_stats_from_file(QEMUFile
*f
,
2386 struct UPT1_RxStats
*rx_stat
)
2388 rx_stat
->LROPktsRxOK
= qemu_get_be64(f
);
2389 rx_stat
->LROBytesRxOK
= qemu_get_be64(f
);
2390 rx_stat
->ucastPktsRxOK
= qemu_get_be64(f
);
2391 rx_stat
->ucastBytesRxOK
= qemu_get_be64(f
);
2392 rx_stat
->mcastPktsRxOK
= qemu_get_be64(f
);
2393 rx_stat
->mcastBytesRxOK
= qemu_get_be64(f
);
2394 rx_stat
->bcastPktsRxOK
= qemu_get_be64(f
);
2395 rx_stat
->bcastBytesRxOK
= qemu_get_be64(f
);
2396 rx_stat
->pktsRxOutOfBuf
= qemu_get_be64(f
);
2397 rx_stat
->pktsRxError
= qemu_get_be64(f
);
2400 static void vmxnet3_put_rx_stats_to_file(QEMUFile
*f
,
2401 struct UPT1_RxStats
*rx_stat
)
2403 qemu_put_be64(f
, rx_stat
->LROPktsRxOK
);
2404 qemu_put_be64(f
, rx_stat
->LROBytesRxOK
);
2405 qemu_put_be64(f
, rx_stat
->ucastPktsRxOK
);
2406 qemu_put_be64(f
, rx_stat
->ucastBytesRxOK
);
2407 qemu_put_be64(f
, rx_stat
->mcastPktsRxOK
);
2408 qemu_put_be64(f
, rx_stat
->mcastBytesRxOK
);
2409 qemu_put_be64(f
, rx_stat
->bcastPktsRxOK
);
2410 qemu_put_be64(f
, rx_stat
->bcastBytesRxOK
);
2411 qemu_put_be64(f
, rx_stat
->pktsRxOutOfBuf
);
2412 qemu_put_be64(f
, rx_stat
->pktsRxError
);
2415 static int vmxnet3_get_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2417 Vmxnet3RxqDescr
*r
= pv
;
2420 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2421 vmxnet3_get_ring_from_file(f
, &r
->rx_ring
[i
]);
2424 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2425 r
->intr_idx
= qemu_get_byte(f
);
2426 r
->rx_stats_pa
= qemu_get_be64(f
);
2428 vmxnet3_get_rx_stats_from_file(f
, &r
->rxq_stats
);
2433 static void vmxnet3_put_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2435 Vmxnet3RxqDescr
*r
= pv
;
2438 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2439 vmxnet3_put_ring_to_file(f
, &r
->rx_ring
[i
]);
2442 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2443 qemu_put_byte(f
, r
->intr_idx
);
2444 qemu_put_be64(f
, r
->rx_stats_pa
);
2445 vmxnet3_put_rx_stats_to_file(f
, &r
->rxq_stats
);
2448 static int vmxnet3_post_load(void *opaque
, int version_id
)
2450 VMXNET3State
*s
= opaque
;
2451 PCIDevice
*d
= PCI_DEVICE(s
);
2453 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
2454 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
2457 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2458 VMW_WRPRN("Failed to re-use MSI-X vectors");
2459 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2460 s
->msix_used
= false;
2465 vmxnet3_validate_queues(s
);
2466 vmxnet3_validate_interrupts(s
);
2471 static const VMStateInfo rxq_descr_info
= {
2472 .name
= "rxq_descr",
2473 .get
= vmxnet3_get_rxq_descr
,
2474 .put
= vmxnet3_put_rxq_descr
2477 static int vmxnet3_get_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2479 Vmxnet3IntState
*r
= pv
;
2481 r
->is_masked
= qemu_get_byte(f
);
2482 r
->is_pending
= qemu_get_byte(f
);
2483 r
->is_asserted
= qemu_get_byte(f
);
2488 static void vmxnet3_put_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2490 Vmxnet3IntState
*r
= pv
;
2492 qemu_put_byte(f
, r
->is_masked
);
2493 qemu_put_byte(f
, r
->is_pending
);
2494 qemu_put_byte(f
, r
->is_asserted
);
2497 static const VMStateInfo int_state_info
= {
2498 .name
= "int_state",
2499 .get
= vmxnet3_get_int_state
,
2500 .put
= vmxnet3_put_int_state
2503 static const VMStateDescription vmstate_vmxnet3
= {
2506 .minimum_version_id
= 1,
2507 .pre_save
= vmxnet3_pre_save
,
2508 .post_load
= vmxnet3_post_load
,
2509 .fields
= (VMStateField
[]) {
2510 VMSTATE_PCI_DEVICE(parent_obj
, VMXNET3State
),
2511 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2512 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2513 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2514 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2515 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2516 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2517 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2518 VMSTATE_UINT32(mtu
, VMXNET3State
),
2519 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2520 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2521 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2522 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2523 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2524 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2525 VMSTATE_UINT32(device_active
, VMXNET3State
),
2526 VMSTATE_UINT32(last_command
, VMXNET3State
),
2527 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2528 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2529 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2530 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2532 VMSTATE_ARRAY(txq_descr
, VMXNET3State
,
2533 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, txq_descr_info
,
2535 VMSTATE_ARRAY(rxq_descr
, VMXNET3State
,
2536 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, rxq_descr_info
,
2538 VMSTATE_ARRAY(interrupt_states
, VMXNET3State
, VMXNET3_MAX_INTRS
,
2539 0, int_state_info
, Vmxnet3IntState
),
2541 VMSTATE_END_OF_LIST()
2543 .subsections
= (const VMStateDescription
*[]) {
2544 &vmxstate_vmxnet3_mcast_list
,
2549 static Property vmxnet3_properties
[] = {
2550 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2551 DEFINE_PROP_END_OF_LIST(),
2554 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2556 DeviceClass
*dc
= DEVICE_CLASS(class);
2557 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2559 c
->realize
= vmxnet3_pci_realize
;
2560 c
->exit
= vmxnet3_pci_uninit
;
2561 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2562 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2563 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2564 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2565 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2566 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2567 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2568 dc
->reset
= vmxnet3_qdev_reset
;
2569 dc
->vmsd
= &vmstate_vmxnet3
;
2570 dc
->props
= vmxnet3_properties
;
2571 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2574 static const TypeInfo vmxnet3_info
= {
2575 .name
= TYPE_VMXNET3
,
2576 .parent
= TYPE_PCI_DEVICE
,
2577 .instance_size
= sizeof(VMXNET3State
),
2578 .class_init
= vmxnet3_class_init
,
2579 .instance_init
= vmxnet3_instance_init
,
2582 static void vmxnet3_register_types(void)
2584 VMW_CBPRN("vmxnet3_register_types called...");
2585 type_register_static(&vmxnet3_info
);
2588 type_init(vmxnet3_register_types
)