hw/ppc/pnv_lpc.c

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "sysemu/sysemu.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qapi/error.h"
  24 #include "qemu/log.h"
  25
  26 #include "hw/ppc/pnv.h"
  27 #include "hw/ppc/pnv_lpc.h"
  28 #include "hw/ppc/pnv_xscom.h"
  29 #include "hw/ppc/fdt.h"
  30
  31 #include <libfdt.h>
  32
  33 enum {
  34     ECCB_CTL    = 0,
  35     ECCB_RESET  = 1,
  36     ECCB_STAT   = 2,
  37     ECCB_DATA   = 3,
  38 };
  39
  40 /* OPB Master LS registers */
  41 #define OPB_MASTER_LS_IRQ_STAT  0x50
  42 #define   OPB_MASTER_IRQ_LPC            0x00000800
  43 #define OPB_MASTER_LS_IRQ_MASK  0x54
  44 #define OPB_MASTER_LS_IRQ_POL   0x58
  45 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
  46
  47 /* LPC HC registers */
  48 #define LPC_HC_FW_SEG_IDSEL     0x24
  49 #define LPC_HC_FW_RD_ACC_SIZE   0x28
  50 #define   LPC_HC_FW_RD_1B               0x00000000
  51 #define   LPC_HC_FW_RD_2B               0x01000000
  52 #define   LPC_HC_FW_RD_4B               0x02000000
  53 #define   LPC_HC_FW_RD_16B              0x04000000
  54 #define   LPC_HC_FW_RD_128B             0x07000000
  55 #define LPC_HC_IRQSER_CTRL      0x30
  56 #define   LPC_HC_IRQSER_EN              0x80000000
  57 #define   LPC_HC_IRQSER_QMODE           0x40000000
  58 #define   LPC_HC_IRQSER_START_MASK      0x03000000
  59 #define   LPC_HC_IRQSER_START_4CLK      0x00000000
  60 #define   LPC_HC_IRQSER_START_6CLK      0x01000000
  61 #define   LPC_HC_IRQSER_START_8CLK      0x02000000
  62 #define LPC_HC_IRQMASK          0x34    /* same bit defs as LPC_HC_IRQSTAT */
  63 #define LPC_HC_IRQSTAT          0x38
  64 #define   LPC_HC_IRQ_SERIRQ0            0x80000000 /* all bits down to ... */
  65 #define   LPC_HC_IRQ_SERIRQ16           0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
  66 #define   LPC_HC_IRQ_SERIRQ_ALL         0xffff8000
  67 #define   LPC_HC_IRQ_LRESET             0x00000400
  68 #define   LPC_HC_IRQ_SYNC_ABNORM_ERR    0x00000080
  69 #define   LPC_HC_IRQ_SYNC_NORESP_ERR    0x00000040
  70 #define   LPC_HC_IRQ_SYNC_NORM_ERR      0x00000020
  71 #define   LPC_HC_IRQ_SYNC_TIMEOUT_ERR   0x00000010
  72 #define   LPC_HC_IRQ_SYNC_TARG_TAR_ERR  0x00000008
  73 #define   LPC_HC_IRQ_SYNC_BM_TAR_ERR    0x00000004
  74 #define   LPC_HC_IRQ_SYNC_BM0_REQ       0x00000002
  75 #define   LPC_HC_IRQ_SYNC_BM1_REQ       0x00000001
  76 #define LPC_HC_ERROR_ADDRESS    0x40
  77
  78 #define LPC_OPB_SIZE            0x100000000ull
  79
  80 #define ISA_IO_SIZE             0x00010000
  81 #define ISA_MEM_SIZE            0x10000000
  82 #define ISA_FW_SIZE             0x10000000
  83 #define LPC_IO_OPB_ADDR         0xd0010000
  84 #define LPC_IO_OPB_SIZE         0x00010000
  85 #define LPC_MEM_OPB_ADDR        0xe0010000
  86 #define LPC_MEM_OPB_SIZE        0x10000000
  87 #define LPC_FW_OPB_ADDR         0xf0000000
  88 #define LPC_FW_OPB_SIZE         0x10000000
  89
  90 #define LPC_OPB_REGS_OPB_ADDR   0xc0010000
  91 #define LPC_OPB_REGS_OPB_SIZE   0x00002000
  92 #define LPC_HC_REGS_OPB_ADDR    0xc0012000
  93 #define LPC_HC_REGS_OPB_SIZE    0x00001000
  94
  95
  96 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
  97 {
  98     const char compat[] = "ibm,power8-lpc\0ibm,lpc";
  99     char *name;
 100     int offset;
 101     uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
 102     uint32_t reg[] = {
 103         cpu_to_be32(lpc_pcba),
 104         cpu_to_be32(PNV_XSCOM_LPC_SIZE)
 105     };
 106
 107     name = g_strdup_printf("isa@%x", lpc_pcba);
 108     offset = fdt_add_subnode(fdt, xscom_offset, name);
 109     _FDT(offset);
 110     g_free(name);
 111
 112     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 113     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 114     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 115     _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
 116     return 0;
 117 }
 118
 119 /*
 120  * These read/write handlers of the OPB address space should be common
 121  * with the P9 LPC Controller which uses direct MMIOs.
 122  *
 123  * TODO: rework to use address_space_stq() and address_space_ldq()
 124  * instead.
 125  */
 126 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 127                      int sz)
 128 {
 129     /* XXX Handle access size limits and FW read caching here */
 130     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 131                              data, sz, false);
 132 }
 133
 134 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 135                       int sz)
 136 {
 137     /* XXX Handle access size limits here */
 138     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 139                              data, sz, true);
 140 }
 141
 142 #define ECCB_CTL_READ           PPC_BIT(15)
 143 #define ECCB_CTL_SZ_LSH         (63 - 7)
 144 #define ECCB_CTL_SZ_MASK        PPC_BITMASK(4, 7)
 145 #define ECCB_CTL_ADDR_MASK      PPC_BITMASK(32, 63)
 146
 147 #define ECCB_STAT_OP_DONE       PPC_BIT(52)
 148 #define ECCB_STAT_OP_ERR        PPC_BIT(52)
 149 #define ECCB_STAT_RD_DATA_LSH   (63 - 37)
 150 #define ECCB_STAT_RD_DATA_MASK  (0xffffffff << ECCB_STAT_RD_DATA_LSH)
 151
 152 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
 153 {
 154     /* XXX Check for magic bits at the top, addr size etc... */
 155     unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
 156     uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
 157     uint8_t data[4];
 158     bool success;
 159
 160     if (cmd & ECCB_CTL_READ) {
 161         success = opb_read(lpc, opb_addr, data, sz);
 162         if (success) {
 163             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 164                     (((uint64_t)data[0]) << 24 |
 165                      ((uint64_t)data[1]) << 16 |
 166                      ((uint64_t)data[2]) <<  8 |
 167                      ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
 168         } else {
 169             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 170                     (0xffffffffull << ECCB_STAT_RD_DATA_LSH);
 171         }
 172     } else {
 173         data[0] = lpc->eccb_data_reg >> 24;
 174         data[1] = lpc->eccb_data_reg >> 16;
 175         data[2] = lpc->eccb_data_reg >>  8;
 176         data[3] = lpc->eccb_data_reg;
 177
 178         success = opb_write(lpc, opb_addr, data, sz);
 179         lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
 180     }
 181     /* XXX Which error bit (if any) to signal OPB error ? */
 182 }
 183
 184 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
 185 {
 186     PnvLpcController *lpc = PNV_LPC(opaque);
 187     uint32_t offset = addr >> 3;
 188     uint64_t val = 0;
 189
 190     switch (offset & 3) {
 191     case ECCB_CTL:
 192     case ECCB_RESET:
 193         val = 0;
 194         break;
 195     case ECCB_STAT:
 196         val = lpc->eccb_stat_reg;
 197         lpc->eccb_stat_reg = 0;
 198         break;
 199     case ECCB_DATA:
 200         val = ((uint64_t)lpc->eccb_data_reg) << 32;
 201         break;
 202     }
 203     return val;
 204 }
 205
 206 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
 207                                 uint64_t val, unsigned size)
 208 {
 209     PnvLpcController *lpc = PNV_LPC(opaque);
 210     uint32_t offset = addr >> 3;
 211
 212     switch (offset & 3) {
 213     case ECCB_CTL:
 214         pnv_lpc_do_eccb(lpc, val);
 215         break;
 216     case ECCB_RESET:
 217         /*  XXXX  */
 218         break;
 219     case ECCB_STAT:
 220         break;
 221     case ECCB_DATA:
 222         lpc->eccb_data_reg = val >> 32;
 223         break;
 224     }
 225 }
 226
 227 static const MemoryRegionOps pnv_lpc_xscom_ops = {
 228     .read = pnv_lpc_xscom_read,
 229     .write = pnv_lpc_xscom_write,
 230     .valid.min_access_size = 8,
 231     .valid.max_access_size = 8,
 232     .impl.min_access_size = 8,
 233     .impl.max_access_size = 8,
 234     .endianness = DEVICE_BIG_ENDIAN,
 235 };
 236
 237 static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
 238 {
 239     bool lpc_to_opb_irq = false;
 240
 241     /* Update LPC controller to OPB line */
 242     if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
 243         uint32_t irqs;
 244
 245         irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
 246         lpc_to_opb_irq = (irqs != 0);
 247     }
 248
 249     /* We don't honor the polarity register, it's pointless and unused
 250      * anyway
 251      */
 252     if (lpc_to_opb_irq) {
 253         lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
 254     } else {
 255         lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
 256     }
 257
 258     /* Update OPB internal latch */
 259     lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
 260
 261     /* Reflect the interrupt */
 262     pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0);
 263 }
 264
 265 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
 266 {
 267     PnvLpcController *lpc = opaque;
 268     uint64_t val = 0xfffffffffffffffful;
 269
 270     switch (addr) {
 271     case LPC_HC_FW_SEG_IDSEL:
 272         val =  lpc->lpc_hc_fw_seg_idsel;
 273         break;
 274     case LPC_HC_FW_RD_ACC_SIZE:
 275         val =  lpc->lpc_hc_fw_rd_acc_size;
 276         break;
 277     case LPC_HC_IRQSER_CTRL:
 278         val =  lpc->lpc_hc_irqser_ctrl;
 279         break;
 280     case LPC_HC_IRQMASK:
 281         val =  lpc->lpc_hc_irqmask;
 282         break;
 283     case LPC_HC_IRQSTAT:
 284         val =  lpc->lpc_hc_irqstat;
 285         break;
 286     case LPC_HC_ERROR_ADDRESS:
 287         val =  lpc->lpc_hc_error_addr;
 288         break;
 289     default:
 290         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
 291                       HWADDR_PRIx "\n", addr);
 292     }
 293     return val;
 294 }
 295
 296 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
 297                          unsigned size)
 298 {
 299     PnvLpcController *lpc = opaque;
 300
 301     /* XXX Filter out reserved bits */
 302
 303     switch (addr) {
 304     case LPC_HC_FW_SEG_IDSEL:
 305         /* XXX Actually figure out how that works as this impact
 306          * memory regions/aliases
 307          */
 308         lpc->lpc_hc_fw_seg_idsel = val;
 309         break;
 310     case LPC_HC_FW_RD_ACC_SIZE:
 311         lpc->lpc_hc_fw_rd_acc_size = val;
 312         break;
 313     case LPC_HC_IRQSER_CTRL:
 314         lpc->lpc_hc_irqser_ctrl = val;
 315         pnv_lpc_eval_irqs(lpc);
 316         break;
 317     case LPC_HC_IRQMASK:
 318         lpc->lpc_hc_irqmask = val;
 319         pnv_lpc_eval_irqs(lpc);
 320         break;
 321     case LPC_HC_IRQSTAT:
 322         lpc->lpc_hc_irqstat &= ~val;
 323         pnv_lpc_eval_irqs(lpc);
 324         break;
 325     case LPC_HC_ERROR_ADDRESS:
 326         break;
 327     default:
 328         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
 329                       HWADDR_PRIx "\n", addr);
 330     }
 331 }
 332
 333 static const MemoryRegionOps lpc_hc_ops = {
 334     .read = lpc_hc_read,
 335     .write = lpc_hc_write,
 336     .endianness = DEVICE_BIG_ENDIAN,
 337     .valid = {
 338         .min_access_size = 4,
 339         .max_access_size = 4,
 340     },
 341     .impl = {
 342         .min_access_size = 4,
 343         .max_access_size = 4,
 344     },
 345 };
 346
 347 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
 348 {
 349     PnvLpcController *lpc = opaque;
 350     uint64_t val = 0xfffffffffffffffful;
 351
 352     switch (addr) {
 353     case OPB_MASTER_LS_IRQ_STAT:
 354         val = lpc->opb_irq_stat;
 355         break;
 356     case OPB_MASTER_LS_IRQ_MASK:
 357         val = lpc->opb_irq_mask;
 358         break;
 359     case OPB_MASTER_LS_IRQ_POL:
 360         val = lpc->opb_irq_pol;
 361         break;
 362     case OPB_MASTER_LS_IRQ_INPUT:
 363         val = lpc->opb_irq_input;
 364         break;
 365     default:
 366         qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
 367                       HWADDR_PRIx "\n", addr);
 368     }
 369
 370     return val;
 371 }
 372
 373 static void opb_master_write(void *opaque, hwaddr addr,
 374                              uint64_t val, unsigned size)
 375 {
 376     PnvLpcController *lpc = opaque;
 377
 378     switch (addr) {
 379     case OPB_MASTER_LS_IRQ_STAT:
 380         lpc->opb_irq_stat &= ~val;
 381         pnv_lpc_eval_irqs(lpc);
 382         break;
 383     case OPB_MASTER_LS_IRQ_MASK:
 384         lpc->opb_irq_mask = val;
 385         pnv_lpc_eval_irqs(lpc);
 386         break;
 387     case OPB_MASTER_LS_IRQ_POL:
 388         lpc->opb_irq_pol = val;
 389         pnv_lpc_eval_irqs(lpc);
 390         break;
 391     case OPB_MASTER_LS_IRQ_INPUT:
 392         /* Read only */
 393         break;
 394     default:
 395         qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
 396                       HWADDR_PRIx "\n", addr);
 397     }
 398 }
 399
 400 static const MemoryRegionOps opb_master_ops = {
 401     .read = opb_master_read,
 402     .write = opb_master_write,
 403     .endianness = DEVICE_BIG_ENDIAN,
 404     .valid = {
 405         .min_access_size = 4,
 406         .max_access_size = 4,
 407     },
 408     .impl = {
 409         .min_access_size = 4,
 410         .max_access_size = 4,
 411     },
 412 };
 413
 414 static void pnv_lpc_realize(DeviceState *dev, Error **errp)
 415 {
 416     PnvLpcController *lpc = PNV_LPC(dev);
 417     Object *obj;
 418     Error *error = NULL;
 419
 420     /* Reg inits */
 421     lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
 422
 423     /* Create address space and backing MR for the OPB bus */
 424     memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
 425     address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
 426
 427     /* Create ISA IO and Mem space regions which are the root of
 428      * the ISA bus (ie, ISA address spaces). We don't create a
 429      * separate one for FW which we alias to memory.
 430      */
 431     memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
 432     memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
 433     memory_region_init(&lpc->isa_fw, OBJECT(dev),  "isa-fw", ISA_FW_SIZE);
 434
 435     /* Create windows from the OPB space to the ISA space */
 436     memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
 437                              &lpc->isa_io, 0, LPC_IO_OPB_SIZE);
 438     memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
 439                                 &lpc->opb_isa_io);
 440     memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
 441                              &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
 442     memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
 443                                 &lpc->opb_isa_mem);
 444     memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
 445                              &lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
 446     memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
 447                                 &lpc->opb_isa_fw);
 448
 449     /* Create MMIO regions for LPC HC and OPB registers */
 450     memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
 451                           lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
 452     memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
 453                                 &lpc->opb_master_regs);
 454     memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
 455                           "lpc-hc", LPC_HC_REGS_OPB_SIZE);
 456     memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
 457                                 &lpc->lpc_hc_regs);
 458
 459     /* XScom region for LPC registers */
 460     pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev),
 461                           &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
 462                           PNV_XSCOM_LPC_SIZE);
 463
 464     /* get PSI object from chip */
 465     obj = object_property_get_link(OBJECT(dev), "psi", &error);
 466     if (!obj) {
 467         error_setg(errp, "%s: required link 'psi' not found: %s",
 468                    __func__, error_get_pretty(error));
 469         return;
 470     }
 471     lpc->psi = PNV_PSI(obj);
 472 }
 473
 474 static void pnv_lpc_class_init(ObjectClass *klass, void *data)
 475 {
 476     DeviceClass *dc = DEVICE_CLASS(klass);
 477     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 478
 479     xdc->dt_xscom = pnv_lpc_dt_xscom;
 480
 481     dc->realize = pnv_lpc_realize;
 482 }
 483
 484 static const TypeInfo pnv_lpc_info = {
 485     .name          = TYPE_PNV_LPC,
 486     .parent        = TYPE_DEVICE,
 487     .instance_size = sizeof(PnvLpcController),
 488     .class_init    = pnv_lpc_class_init,
 489     .interfaces = (InterfaceInfo[]) {
 490         { TYPE_PNV_XSCOM_INTERFACE },
 491         { }
 492     }
 493 };
 494
 495 static void pnv_lpc_register_types(void)
 496 {
 497     type_register_static(&pnv_lpc_info);
 498 }
 499
 500 type_init(pnv_lpc_register_types)
 501
 502 /* If we don't use the built-in LPC interrupt deserializer, we need
 503  * to provide a set of qirqs for the ISA bus or things will go bad.
 504  *
 505  * Most machines using pre-Naples chips (without said deserializer)
 506  * have a CPLD that will collect the SerIRQ and shoot them as a
 507  * single level interrupt to the P8 chip. So let's setup a hook
 508  * for doing just that.
 509  */
 510 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 511 {
 512     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
 513     uint32_t old_state = pnv->cpld_irqstate;
 514     PnvLpcController *lpc = PNV_LPC(opaque);
 515
 516     if (level) {
 517         pnv->cpld_irqstate |= 1u << n;
 518     } else {
 519         pnv->cpld_irqstate &= ~(1u << n);
 520     }
 521
 522     if (pnv->cpld_irqstate != old_state) {
 523         pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
 524     }
 525 }
 526
 527 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 528 {
 529     PnvLpcController *lpc = PNV_LPC(opaque);
 530
 531     /* The Naples HW latches the 1 levels, clearing is done by SW */
 532     if (level) {
 533         lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
 534         pnv_lpc_eval_irqs(lpc);
 535     }
 536 }
 537
 538 qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type,
 539                                  int nirqs)
 540 {
 541     /* Not all variants have a working serial irq decoder. If not,
 542      * handling of LPC interrupts becomes a platform issue (some
 543      * platforms have a CPLD to do it).
 544      */
 545     if (chip_type == PNV_CHIP_POWER8NVL) {
 546         return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs);
 547     } else {
 548         return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs);
 549     }
 550 }