target/xtensa/cpu.c

   1 /*
   2  * QEMU Xtensa CPU
   3  *
   4  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in the
  14  *       documentation and/or other materials provided with the distribution.
  15  *     * Neither the name of the Open Source and Linux Lab nor the
  16  *       names of its contributors may be used to endorse or promote products
  17  *       derived from this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qapi/error.h"
  33 #include "cpu.h"
  34 #include "qemu/module.h"
  35 #include "migration/vmstate.h"
  36
  37
  38 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
  39 {
  40     XtensaCPU *cpu = XTENSA_CPU(cs);
  41
  42     cpu->env.pc = value;
  43 }
  44
  45 static bool xtensa_cpu_has_work(CPUState *cs)
  46 {
  47 #ifndef CONFIG_USER_ONLY
  48     XtensaCPU *cpu = XTENSA_CPU(cs);
  49
  50     return !cpu->env.runstall && cpu->env.pending_irq_level;
  51 #else
  52     return true;
  53 #endif
  54 }
  55
  56 /* CPUClass::reset() */
  57 static void xtensa_cpu_reset(CPUState *s)
  58 {
  59     XtensaCPU *cpu = XTENSA_CPU(s);
  60     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
  61     CPUXtensaState *env = &cpu->env;
  62
  63     xcc->parent_reset(s);
  64
  65     env->exception_taken = 0;
  66     env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
  67     env->sregs[LITBASE] &= ~1;
  68 #ifndef CONFIG_USER_ONLY
  69     env->sregs[PS] = xtensa_option_enabled(env->config,
  70             XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
  71     env->pending_irq_level = 0;
  72 #else
  73     env->sregs[PS] =
  74         (xtensa_option_enabled(env->config,
  75                                XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) |
  76         PS_UM | (3 << PS_RING_SHIFT);
  77 #endif
  78     env->sregs[VECBASE] = env->config->vecbase;
  79     env->sregs[IBREAKENABLE] = 0;
  80     env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
  81     env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
  82             XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
  83     env->sregs[CONFIGID0] = env->config->configid[0];
  84     env->sregs[CONFIGID1] = env->config->configid[1];
  85     env->exclusive_addr = -1;
  86
  87 #ifndef CONFIG_USER_ONLY
  88     reset_mmu(env);
  89     s->halted = env->runstall;
  90 #endif
  91 }
  92
  93 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
  94 {
  95     ObjectClass *oc;
  96     char *typename;
  97
  98     typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
  99     oc = object_class_by_name(typename);
 100     g_free(typename);
 101     if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
 102         object_class_is_abstract(oc)) {
 103         return NULL;
 104     }
 105     return oc;
 106 }
 107
 108 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
 109 {
 110     XtensaCPU *cpu = XTENSA_CPU(cs);
 111
 112     info->private_data = cpu->env.config->isa;
 113     info->print_insn = print_insn_xtensa;
 114 }
 115
 116 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
 117 {
 118     CPUState *cs = CPU(dev);
 119     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
 120     Error *local_err = NULL;
 121
 122 #ifndef CONFIG_USER_ONLY
 123     xtensa_irq_init(&XTENSA_CPU(dev)->env);
 124 #endif
 125
 126     cpu_exec_realizefn(cs, &local_err);
 127     if (local_err != NULL) {
 128         error_propagate(errp, local_err);
 129         return;
 130     }
 131
 132     cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
 133
 134     qemu_init_vcpu(cs);
 135
 136     xcc->parent_realize(dev, errp);
 137 }
 138
 139 static void xtensa_cpu_initfn(Object *obj)
 140 {
 141     XtensaCPU *cpu = XTENSA_CPU(obj);
 142     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
 143     CPUXtensaState *env = &cpu->env;
 144
 145     cpu_set_cpustate_pointers(cpu);
 146     env->config = xcc->config;
 147
 148 #ifndef CONFIG_USER_ONLY
 149     env->address_space_er = g_malloc(sizeof(*env->address_space_er));
 150     env->system_er = g_malloc(sizeof(*env->system_er));
 151     memory_region_init_io(env->system_er, obj, NULL, env, "er",
 152                           UINT64_C(0x100000000));
 153     address_space_init(env->address_space_er, env->system_er, "ER");
 154 #endif
 155 }
 156
 157 static const VMStateDescription vmstate_xtensa_cpu = {
 158     .name = "cpu",
 159     .unmigratable = 1,
 160 };
 161
 162 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 163 {
 164     DeviceClass *dc = DEVICE_CLASS(oc);
 165     CPUClass *cc = CPU_CLASS(oc);
 166     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
 167
 168     device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
 169                                     &xcc->parent_realize);
 170
 171     xcc->parent_reset = cc->reset;
 172     cc->reset = xtensa_cpu_reset;
 173
 174     cc->class_by_name = xtensa_cpu_class_by_name;
 175     cc->has_work = xtensa_cpu_has_work;
 176     cc->do_interrupt = xtensa_cpu_do_interrupt;
 177     cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
 178     cc->dump_state = xtensa_cpu_dump_state;
 179     cc->set_pc = xtensa_cpu_set_pc;
 180     cc->gdb_read_register = xtensa_cpu_gdb_read_register;
 181     cc->gdb_write_register = xtensa_cpu_gdb_write_register;
 182     cc->gdb_stop_before_watchpoint = true;
 183     cc->tlb_fill = xtensa_cpu_tlb_fill;
 184 #ifndef CONFIG_USER_ONLY
 185     cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
 186     cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
 187     cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
 188 #endif
 189     cc->debug_excp_handler = xtensa_breakpoint_handler;
 190     cc->disas_set_info = xtensa_cpu_disas_set_info;
 191     cc->tcg_initialize = xtensa_translate_init;
 192     dc->vmsd = &vmstate_xtensa_cpu;
 193 }
 194
 195 static const TypeInfo xtensa_cpu_type_info = {
 196     .name = TYPE_XTENSA_CPU,
 197     .parent = TYPE_CPU,
 198     .instance_size = sizeof(XtensaCPU),
 199     .instance_init = xtensa_cpu_initfn,
 200     .abstract = true,
 201     .class_size = sizeof(XtensaCPUClass),
 202     .class_init = xtensa_cpu_class_init,
 203 };
 204
 205 static void xtensa_cpu_register_types(void)
 206 {
 207     type_register_static(&xtensa_cpu_type_info);
 208 }
 209
 210 type_init(xtensa_cpu_register_types)