target/alpha/cpu.c

   1 /*
   2  * QEMU Alpha CPU
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "exec/exec-all.h"
  27
  28
  29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     AlphaCPU *cpu = ALPHA_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static vaddr alpha_cpu_get_pc(CPUState *cs)
  37 {
  38     AlphaCPU *cpu = ALPHA_CPU(cs);
  39
  40     return cpu->env.pc;
  41 }
  42
  43 static void alpha_restore_state_to_opc(CPUState *cs,
  44                                        const TranslationBlock *tb,
  45                                        const uint64_t *data)
  46 {
  47     AlphaCPU *cpu = ALPHA_CPU(cs);
  48
  49     cpu->env.pc = data[0];
  50 }
  51
  52 static bool alpha_cpu_has_work(CPUState *cs)
  53 {
  54     /* Here we are checking to see if the CPU should wake up from HALT.
  55        We will have gotten into this state only for WTINT from PALmode.  */
  56     /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
  57        asleep even if (some) interrupts have been asserted.  For now,
  58        assume that if a CPU really wants to stay asleep, it will mask
  59        interrupts at the chipset level, which will prevent these bits
  60        from being set in the first place.  */
  61     return cs->interrupt_request & (CPU_INTERRUPT_HARD
  62                                     | CPU_INTERRUPT_TIMER
  63                                     | CPU_INTERRUPT_SMP
  64                                     | CPU_INTERRUPT_MCHK);
  65 }
  66
  67 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  68 {
  69     info->mach = bfd_mach_alpha_ev6;
  70     info->print_insn = print_insn_alpha;
  71 }
  72
  73 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
  74 {
  75     CPUState *cs = CPU(dev);
  76     AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
  77     Error *local_err = NULL;
  78
  79     cpu_exec_realizefn(cs, &local_err);
  80     if (local_err != NULL) {
  81         error_propagate(errp, local_err);
  82         return;
  83     }
  84
  85     qemu_init_vcpu(cs);
  86
  87     acc->parent_realize(dev, errp);
  88 }
  89
  90 static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
  91 {
  92     ObjectClass *oc = data;
  93
  94     qemu_printf("  %s\n", object_class_get_name(oc));
  95 }
  96
  97 void alpha_cpu_list(void)
  98 {
  99     GSList *list;
 100
 101     list = object_class_get_list_sorted(TYPE_ALPHA_CPU, false);
 102     qemu_printf("Available CPUs:\n");
 103     g_slist_foreach(list, alpha_cpu_list_entry, NULL);
 104     g_slist_free(list);
 105 }
 106
 107 /* Models */
 108 typedef struct AlphaCPUAlias {
 109     const char *alias;
 110     const char *typename;
 111 } AlphaCPUAlias;
 112
 113 static const AlphaCPUAlias alpha_cpu_aliases[] = {
 114     { "21064",   ALPHA_CPU_TYPE_NAME("ev4") },
 115     { "21164",   ALPHA_CPU_TYPE_NAME("ev5") },
 116     { "21164a",  ALPHA_CPU_TYPE_NAME("ev56") },
 117     { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
 118     { "21264",   ALPHA_CPU_TYPE_NAME("ev6") },
 119     { "21264a",  ALPHA_CPU_TYPE_NAME("ev67") },
 120 };
 121
 122 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
 123 {
 124     ObjectClass *oc;
 125     char *typename;
 126     int i;
 127
 128     oc = object_class_by_name(cpu_model);
 129     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) {
 130         return oc;
 131     }
 132
 133     for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
 134         if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
 135             oc = object_class_by_name(alpha_cpu_aliases[i].typename);
 136             assert(oc != NULL && !object_class_is_abstract(oc));
 137             return oc;
 138         }
 139     }
 140
 141     typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
 142     oc = object_class_by_name(typename);
 143     g_free(typename);
 144
 145     return oc;
 146 }
 147
 148 static void ev4_cpu_initfn(Object *obj)
 149 {
 150     AlphaCPU *cpu = ALPHA_CPU(obj);
 151     CPUAlphaState *env = &cpu->env;
 152
 153     env->implver = IMPLVER_2106x;
 154 }
 155
 156 static void ev5_cpu_initfn(Object *obj)
 157 {
 158     AlphaCPU *cpu = ALPHA_CPU(obj);
 159     CPUAlphaState *env = &cpu->env;
 160
 161     env->implver = IMPLVER_21164;
 162 }
 163
 164 static void ev56_cpu_initfn(Object *obj)
 165 {
 166     AlphaCPU *cpu = ALPHA_CPU(obj);
 167     CPUAlphaState *env = &cpu->env;
 168
 169     env->amask |= AMASK_BWX;
 170 }
 171
 172 static void pca56_cpu_initfn(Object *obj)
 173 {
 174     AlphaCPU *cpu = ALPHA_CPU(obj);
 175     CPUAlphaState *env = &cpu->env;
 176
 177     env->amask |= AMASK_MVI;
 178 }
 179
 180 static void ev6_cpu_initfn(Object *obj)
 181 {
 182     AlphaCPU *cpu = ALPHA_CPU(obj);
 183     CPUAlphaState *env = &cpu->env;
 184
 185     env->implver = IMPLVER_21264;
 186     env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
 187 }
 188
 189 static void ev67_cpu_initfn(Object *obj)
 190 {
 191     AlphaCPU *cpu = ALPHA_CPU(obj);
 192     CPUAlphaState *env = &cpu->env;
 193
 194     env->amask |= AMASK_CIX | AMASK_PREFETCH;
 195 }
 196
 197 static void alpha_cpu_initfn(Object *obj)
 198 {
 199     AlphaCPU *cpu = ALPHA_CPU(obj);
 200     CPUAlphaState *env = &cpu->env;
 201
 202     env->lock_addr = -1;
 203 #if defined(CONFIG_USER_ONLY)
 204     env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
 205     cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
 206                                          | FPCR_UNFD | FPCR_INED | FPCR_DNOD
 207                                          | FPCR_DYN_NORMAL) << 32);
 208 #else
 209     env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;
 210 #endif
 211 }
 212
 213 #ifndef CONFIG_USER_ONLY
 214 #include "hw/core/sysemu-cpu-ops.h"
 215
 216 static const struct SysemuCPUOps alpha_sysemu_ops = {
 217     .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
 218 };
 219 #endif
 220
 221 #include "hw/core/tcg-cpu-ops.h"
 222
 223 static const struct TCGCPUOps alpha_tcg_ops = {
 224     .initialize = alpha_translate_init,
 225     .restore_state_to_opc = alpha_restore_state_to_opc,
 226
 227 #ifdef CONFIG_USER_ONLY
 228     .record_sigsegv = alpha_cpu_record_sigsegv,
 229     .record_sigbus = alpha_cpu_record_sigbus,
 230 #else
 231     .tlb_fill = alpha_cpu_tlb_fill,
 232     .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
 233     .do_interrupt = alpha_cpu_do_interrupt,
 234     .do_transaction_failed = alpha_cpu_do_transaction_failed,
 235     .do_unaligned_access = alpha_cpu_do_unaligned_access,
 236 #endif /* !CONFIG_USER_ONLY */
 237 };
 238
 239 static void alpha_cpu_class_init(ObjectClass *oc, void *data)
 240 {
 241     DeviceClass *dc = DEVICE_CLASS(oc);
 242     CPUClass *cc = CPU_CLASS(oc);
 243     AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
 244
 245     device_class_set_parent_realize(dc, alpha_cpu_realizefn,
 246                                     &acc->parent_realize);
 247
 248     cc->class_by_name = alpha_cpu_class_by_name;
 249     cc->has_work = alpha_cpu_has_work;
 250     cc->dump_state = alpha_cpu_dump_state;
 251     cc->set_pc = alpha_cpu_set_pc;
 252     cc->get_pc = alpha_cpu_get_pc;
 253     cc->gdb_read_register = alpha_cpu_gdb_read_register;
 254     cc->gdb_write_register = alpha_cpu_gdb_write_register;
 255 #ifndef CONFIG_USER_ONLY
 256     dc->vmsd = &vmstate_alpha_cpu;
 257     cc->sysemu_ops = &alpha_sysemu_ops;
 258 #endif
 259     cc->disas_set_info = alpha_cpu_disas_set_info;
 260
 261     cc->tcg_ops = &alpha_tcg_ops;
 262     cc->gdb_num_core_regs = 67;
 263 }
 264
 265 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
 266      {                                                      \
 267          .parent = base_type,                               \
 268          .instance_init = initfn,                           \
 269          .name = ALPHA_CPU_TYPE_NAME(cpu_model),            \
 270      }
 271
 272 static const TypeInfo alpha_cpu_type_infos[] = {
 273     {
 274         .name = TYPE_ALPHA_CPU,
 275         .parent = TYPE_CPU,
 276         .instance_size = sizeof(AlphaCPU),
 277         .instance_align = __alignof(AlphaCPU),
 278         .instance_init = alpha_cpu_initfn,
 279         .abstract = true,
 280         .class_size = sizeof(AlphaCPUClass),
 281         .class_init = alpha_cpu_class_init,
 282     },
 283     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn),
 284     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn),
 285     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn),
 286     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
 287                           pca56_cpu_initfn),
 288     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn),
 289     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn),
 290     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL),
 291 };
 292
 293 DEFINE_TYPES(alpha_cpu_type_infos)