hw/net/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/pci/pci.h"
  26 #include "net/eth.h"
  27 #include "ne2000.h"
  28 #include "sysemu/sysemu.h"
  29 #include "trace.h"
  30
  31 /* debug NE2000 card */
  32 //#define DEBUG_NE2000
  33
  34 #define MAX_ETH_FRAME_SIZE 1514
  35
  36 #define E8390_CMD       0x00  /* The command register (for all pages) */
  37 /* Page 0 register offsets. */
  38 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  39 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  40 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  41 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  42 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  43 #define EN0_TSR         0x04    /* Transmit status reg RD */
  44 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  45 #define EN0_NCR         0x05    /* Number of collision reg RD */
  46 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  47 #define EN0_FIFO        0x06    /* FIFO RD */
  48 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  49 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  50 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  51 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  52 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  53 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  54 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  55 #define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
  56 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  57 #define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
  58 #define EN0_RSR         0x0c    /* rx status reg RD */
  59 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  60 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  61 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  62 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  63 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  64 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  65 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  66
  67 #define EN1_PHYS        0x11
  68 #define EN1_CURPAG      0x17
  69 #define EN1_MULT        0x18
  70
  71 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  72 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  73
  74 #define EN3_CONFIG0     0x33
  75 #define EN3_CONFIG1     0x34
  76 #define EN3_CONFIG2     0x35
  77 #define EN3_CONFIG3     0x36
  78
  79 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  80 #define E8390_STOP      0x01    /* Stop and reset the chip */
  81 #define E8390_START     0x02    /* Start the chip, clear reset */
  82 #define E8390_TRANS     0x04    /* Transmit a frame */
  83 #define E8390_RREAD     0x08    /* Remote read */
  84 #define E8390_RWRITE    0x10    /* Remote write  */
  85 #define E8390_NODMA     0x20    /* Remote DMA */
  86 #define E8390_PAGE0     0x00    /* Select page chip registers */
  87 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  88 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  89
  90 /* Bits in EN0_ISR - Interrupt status register */
  91 #define ENISR_RX        0x01    /* Receiver, no error */
  92 #define ENISR_TX        0x02    /* Transmitter, no error */
  93 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  94 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  95 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  96 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  97 #define ENISR_RDC       0x40    /* remote dma complete */
  98 #define ENISR_RESET     0x80    /* Reset completed */
  99 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 100
 101 /* Bits in received packet status byte and EN0_RSR*/
 102 #define ENRSR_RXOK      0x01    /* Received a good packet */
 103 #define ENRSR_CRC       0x02    /* CRC error */
 104 #define ENRSR_FAE       0x04    /* frame alignment error */
 105 #define ENRSR_FO        0x08    /* FIFO overrun */
 106 #define ENRSR_MPA       0x10    /* missed pkt */
 107 #define ENRSR_PHY       0x20    /* physical/multicast address */
 108 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 109 #define ENRSR_DEF       0x80    /* deferring */
 110
 111 /* Transmitted packet status, EN0_TSR. */
 112 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 113 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 114 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 115 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 116 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 117 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 118 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 119 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 120
 121 typedef struct PCINE2000State {
 122     PCIDevice dev;
 123     NE2000State ne2000;
 124 } PCINE2000State;
 125
 126 void ne2000_reset(NE2000State *s)
 127 {
 128     int i;
 129
 130     s->isr = ENISR_RESET;
 131     memcpy(s->mem, &s->c.macaddr, 6);
 132     s->mem[14] = 0x57;
 133     s->mem[15] = 0x57;
 134
 135     /* duplicate prom data */
 136     for(i = 15;i >= 0; i--) {
 137         s->mem[2 * i] = s->mem[i];
 138         s->mem[2 * i + 1] = s->mem[i];
 139     }
 140 }
 141
 142 static void ne2000_update_irq(NE2000State *s)
 143 {
 144     int isr;
 145     isr = (s->isr & s->imr) & 0x7f;
 146 #if defined(DEBUG_NE2000)
 147     printf("NE2000: Set IRQ to %d (%02x %02x)\n",
 148            isr ? 1 : 0, s->isr, s->imr);
 149 #endif
 150     qemu_set_irq(s->irq, (isr != 0));
 151 }
 152
 153 static int ne2000_buffer_full(NE2000State *s)
 154 {
 155     int avail, index, boundary;
 156
 157     if (s->stop <= s->start) {
 158         return 1;
 159     }
 160
 161     index = s->curpag << 8;
 162     boundary = s->boundary << 8;
 163     if (index < boundary)
 164         avail = boundary - index;
 165     else
 166         avail = (s->stop - s->start) - (index - boundary);
 167     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 168         return 1;
 169     return 0;
 170 }
 171
 172 #define MIN_BUF_SIZE 60
 173
 174 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
 175 {
 176     NE2000State *s = qemu_get_nic_opaque(nc);
 177     size_t size = size_;
 178     uint8_t *p;
 179     unsigned int total_len, next, avail, len, index, mcast_idx;
 180     uint8_t buf1[60];
 181     static const uint8_t broadcast_macaddr[6] =
 182         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 183
 184 #if defined(DEBUG_NE2000)
 185     printf("NE2000: received len=%zu\n", size);
 186 #endif
 187
 188     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
 189         return -1;
 190
 191     /* XXX: check this */
 192     if (s->rxcr & 0x10) {
 193         /* promiscuous: receive all */
 194     } else {
 195         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 196             /* broadcast address */
 197             if (!(s->rxcr & 0x04))
 198                 return size;
 199         } else if (buf[0] & 0x01) {
 200             /* multicast */
 201             if (!(s->rxcr & 0x08))
 202                 return size;
 203             mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
 204             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 205                 return size;
 206         } else if (s->mem[0] == buf[0] &&
 207                    s->mem[2] == buf[1] &&
 208                    s->mem[4] == buf[2] &&
 209                    s->mem[6] == buf[3] &&
 210                    s->mem[8] == buf[4] &&
 211                    s->mem[10] == buf[5]) {
 212             /* match */
 213         } else {
 214             return size;
 215         }
 216     }
 217
 218
 219     /* if too small buffer, then expand it */
 220     if (size < MIN_BUF_SIZE) {
 221         memcpy(buf1, buf, size);
 222         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 223         buf = buf1;
 224         size = MIN_BUF_SIZE;
 225     }
 226
 227     index = s->curpag << 8;
 228     if (index >= NE2000_PMEM_END) {
 229         index = s->start;
 230     }
 231     /* 4 bytes for header */
 232     total_len = size + 4;
 233     /* address for next packet (4 bytes for CRC) */
 234     next = index + ((total_len + 4 + 255) & ~0xff);
 235     if (next >= s->stop)
 236         next -= (s->stop - s->start);
 237     /* prepare packet header */
 238     p = s->mem + index;
 239     s->rsr = ENRSR_RXOK; /* receive status */
 240     /* XXX: check this */
 241     if (buf[0] & 0x01)
 242         s->rsr |= ENRSR_PHY;
 243     p[0] = s->rsr;
 244     p[1] = next >> 8;
 245     p[2] = total_len;
 246     p[3] = total_len >> 8;
 247     index += 4;
 248
 249     /* write packet data */
 250     while (size > 0) {
 251         if (index <= s->stop)
 252             avail = s->stop - index;
 253         else
 254             break;
 255         len = size;
 256         if (len > avail)
 257             len = avail;
 258         memcpy(s->mem + index, buf, len);
 259         buf += len;
 260         index += len;
 261         if (index == s->stop)
 262             index = s->start;
 263         size -= len;
 264     }
 265     s->curpag = next >> 8;
 266
 267     /* now we can signal we have received something */
 268     s->isr |= ENISR_RX;
 269     ne2000_update_irq(s);
 270
 271     return size_;
 272 }
 273
 274 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 275 {
 276     NE2000State *s = opaque;
 277     int offset, page, index;
 278
 279     addr &= 0xf;
 280     trace_ne2000_ioport_write(addr, val);
 281     if (addr == E8390_CMD) {
 282         /* control register */
 283         s->cmd = val;
 284         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 285             s->isr &= ~ENISR_RESET;
 286             /* test specific case: zero length transfer */
 287             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 288                 s->rcnt == 0) {
 289                 s->isr |= ENISR_RDC;
 290                 ne2000_update_irq(s);
 291             }
 292             if (val & E8390_TRANS) {
 293                 index = (s->tpsr << 8);
 294                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 295                 if (index >= NE2000_PMEM_END)
 296                     index -= NE2000_PMEM_SIZE;
 297                 /* fail safe: check range on the transmitted length  */
 298                 if (index + s->tcnt <= NE2000_PMEM_END) {
 299                     qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
 300                                      s->tcnt);
 301                 }
 302                 /* signal end of transfer */
 303                 s->tsr = ENTSR_PTX;
 304                 s->isr |= ENISR_TX;
 305                 s->cmd &= ~E8390_TRANS;
 306                 ne2000_update_irq(s);
 307             }
 308         }
 309     } else {
 310         page = s->cmd >> 6;
 311         offset = addr | (page << 4);
 312         switch(offset) {
 313         case EN0_STARTPG:
 314             if (val << 8 <= NE2000_PMEM_END) {
 315                 s->start = val << 8;
 316             }
 317             break;
 318         case EN0_STOPPG:
 319             if (val << 8 <= NE2000_PMEM_END) {
 320                 s->stop = val << 8;
 321             }
 322             break;
 323         case EN0_BOUNDARY:
 324             if (val << 8 < NE2000_PMEM_END) {
 325                 s->boundary = val;
 326             }
 327             break;
 328         case EN0_IMR:
 329             s->imr = val;
 330             ne2000_update_irq(s);
 331             break;
 332         case EN0_TPSR:
 333             s->tpsr = val;
 334             break;
 335         case EN0_TCNTLO:
 336             s->tcnt = (s->tcnt & 0xff00) | val;
 337             break;
 338         case EN0_TCNTHI:
 339             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 340             break;
 341         case EN0_RSARLO:
 342             s->rsar = (s->rsar & 0xff00) | val;
 343             break;
 344         case EN0_RSARHI:
 345             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 346             break;
 347         case EN0_RCNTLO:
 348             s->rcnt = (s->rcnt & 0xff00) | val;
 349             break;
 350         case EN0_RCNTHI:
 351             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 352             break;
 353         case EN0_RXCR:
 354             s->rxcr = val;
 355             break;
 356         case EN0_DCFG:
 357             s->dcfg = val;
 358             break;
 359         case EN0_ISR:
 360             s->isr &= ~(val & 0x7f);
 361             ne2000_update_irq(s);
 362             break;
 363         case EN1_PHYS ... EN1_PHYS + 5:
 364             s->phys[offset - EN1_PHYS] = val;
 365             break;
 366         case EN1_CURPAG:
 367             if (val << 8 < NE2000_PMEM_END) {
 368                 s->curpag = val;
 369             }
 370             break;
 371         case EN1_MULT ... EN1_MULT + 7:
 372             s->mult[offset - EN1_MULT] = val;
 373             break;
 374         }
 375     }
 376 }
 377
 378 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 379 {
 380     NE2000State *s = opaque;
 381     int offset, page, ret;
 382
 383     addr &= 0xf;
 384     if (addr == E8390_CMD) {
 385         ret = s->cmd;
 386     } else {
 387         page = s->cmd >> 6;
 388         offset = addr | (page << 4);
 389         switch(offset) {
 390         case EN0_TSR:
 391             ret = s->tsr;
 392             break;
 393         case EN0_BOUNDARY:
 394             ret = s->boundary;
 395             break;
 396         case EN0_ISR:
 397             ret = s->isr;
 398             break;
 399         case EN0_RSARLO:
 400             ret = s->rsar & 0x00ff;
 401             break;
 402         case EN0_RSARHI:
 403             ret = s->rsar >> 8;
 404             break;
 405         case EN1_PHYS ... EN1_PHYS + 5:
 406             ret = s->phys[offset - EN1_PHYS];
 407             break;
 408         case EN1_CURPAG:
 409             ret = s->curpag;
 410             break;
 411         case EN1_MULT ... EN1_MULT + 7:
 412             ret = s->mult[offset - EN1_MULT];
 413             break;
 414         case EN0_RSR:
 415             ret = s->rsr;
 416             break;
 417         case EN2_STARTPG:
 418             ret = s->start >> 8;
 419             break;
 420         case EN2_STOPPG:
 421             ret = s->stop >> 8;
 422             break;
 423         case EN0_RTL8029ID0:
 424             ret = 0x50;
 425             break;
 426         case EN0_RTL8029ID1:
 427             ret = 0x43;
 428             break;
 429         case EN3_CONFIG0:
 430             ret = 0;            /* 10baseT media */
 431             break;
 432         case EN3_CONFIG2:
 433             ret = 0x40;         /* 10baseT active */
 434             break;
 435         case EN3_CONFIG3:
 436             ret = 0x40;         /* Full duplex */
 437             break;
 438         default:
 439             ret = 0x00;
 440             break;
 441         }
 442     }
 443     trace_ne2000_ioport_read(addr, ret);
 444     return ret;
 445 }
 446
 447 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 448                                      uint32_t val)
 449 {
 450     if (addr < 32 ||
 451         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 452         s->mem[addr] = val;
 453     }
 454 }
 455
 456 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 457                                      uint32_t val)
 458 {
 459     addr &= ~1; /* XXX: check exact behaviour if not even */
 460     if (addr < 32 ||
 461         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 462         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 463     }
 464 }
 465
 466 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 467                                      uint32_t val)
 468 {
 469     addr &= ~1; /* XXX: check exact behaviour if not even */
 470     if (addr < 32
 471         || (addr >= NE2000_PMEM_START
 472             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
 473         stl_le_p(s->mem + addr, val);
 474     }
 475 }
 476
 477 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 478 {
 479     if (addr < 32 ||
 480         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 481         return s->mem[addr];
 482     } else {
 483         return 0xff;
 484     }
 485 }
 486
 487 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 488 {
 489     addr &= ~1; /* XXX: check exact behaviour if not even */
 490     if (addr < 32 ||
 491         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 492         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 493     } else {
 494         return 0xffff;
 495     }
 496 }
 497
 498 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 499 {
 500     addr &= ~1; /* XXX: check exact behaviour if not even */
 501     if (addr < 32
 502         || (addr >= NE2000_PMEM_START
 503             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
 504         return ldl_le_p(s->mem + addr);
 505     } else {
 506         return 0xffffffff;
 507     }
 508 }
 509
 510 static inline void ne2000_dma_update(NE2000State *s, int len)
 511 {
 512     s->rsar += len;
 513     /* wrap */
 514     /* XXX: check what to do if rsar > stop */
 515     if (s->rsar == s->stop)
 516         s->rsar = s->start;
 517
 518     if (s->rcnt <= len) {
 519         s->rcnt = 0;
 520         /* signal end of transfer */
 521         s->isr |= ENISR_RDC;
 522         ne2000_update_irq(s);
 523     } else {
 524         s->rcnt -= len;
 525     }
 526 }
 527
 528 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 529 {
 530     NE2000State *s = opaque;
 531
 532 #ifdef DEBUG_NE2000
 533     printf("NE2000: asic write val=0x%04x\n", val);
 534 #endif
 535     if (s->rcnt == 0)
 536         return;
 537     if (s->dcfg & 0x01) {
 538         /* 16 bit access */
 539         ne2000_mem_writew(s, s->rsar, val);
 540         ne2000_dma_update(s, 2);
 541     } else {
 542         /* 8 bit access */
 543         ne2000_mem_writeb(s, s->rsar, val);
 544         ne2000_dma_update(s, 1);
 545     }
 546 }
 547
 548 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 549 {
 550     NE2000State *s = opaque;
 551     int ret;
 552
 553     if (s->dcfg & 0x01) {
 554         /* 16 bit access */
 555         ret = ne2000_mem_readw(s, s->rsar);
 556         ne2000_dma_update(s, 2);
 557     } else {
 558         /* 8 bit access */
 559         ret = ne2000_mem_readb(s, s->rsar);
 560         ne2000_dma_update(s, 1);
 561     }
 562 #ifdef DEBUG_NE2000
 563     printf("NE2000: asic read val=0x%04x\n", ret);
 564 #endif
 565     return ret;
 566 }
 567
 568 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 569 {
 570     NE2000State *s = opaque;
 571
 572 #ifdef DEBUG_NE2000
 573     printf("NE2000: asic writel val=0x%04x\n", val);
 574 #endif
 575     if (s->rcnt == 0)
 576         return;
 577     /* 32 bit access */
 578     ne2000_mem_writel(s, s->rsar, val);
 579     ne2000_dma_update(s, 4);
 580 }
 581
 582 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 583 {
 584     NE2000State *s = opaque;
 585     int ret;
 586
 587     /* 32 bit access */
 588     ret = ne2000_mem_readl(s, s->rsar);
 589     ne2000_dma_update(s, 4);
 590 #ifdef DEBUG_NE2000
 591     printf("NE2000: asic readl val=0x%04x\n", ret);
 592 #endif
 593     return ret;
 594 }
 595
 596 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 597 {
 598     /* nothing to do (end of reset pulse) */
 599 }
 600
 601 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 602 {
 603     NE2000State *s = opaque;
 604     ne2000_reset(s);
 605     return 0;
 606 }
 607
 608 static int ne2000_post_load(void* opaque, int version_id)
 609 {
 610     NE2000State* s = opaque;
 611
 612     if (version_id < 2) {
 613         s->rxcr = 0x0c;
 614     }
 615     return 0;
 616 }
 617
 618 const VMStateDescription vmstate_ne2000 = {
 619     .name = "ne2000",
 620     .version_id = 2,
 621     .minimum_version_id = 0,
 622     .post_load = ne2000_post_load,
 623     .fields = (VMStateField[]) {
 624         VMSTATE_UINT8_V(rxcr, NE2000State, 2),
 625         VMSTATE_UINT8(cmd, NE2000State),
 626         VMSTATE_UINT32(start, NE2000State),
 627         VMSTATE_UINT32(stop, NE2000State),
 628         VMSTATE_UINT8(boundary, NE2000State),
 629         VMSTATE_UINT8(tsr, NE2000State),
 630         VMSTATE_UINT8(tpsr, NE2000State),
 631         VMSTATE_UINT16(tcnt, NE2000State),
 632         VMSTATE_UINT16(rcnt, NE2000State),
 633         VMSTATE_UINT32(rsar, NE2000State),
 634         VMSTATE_UINT8(rsr, NE2000State),
 635         VMSTATE_UINT8(isr, NE2000State),
 636         VMSTATE_UINT8(dcfg, NE2000State),
 637         VMSTATE_UINT8(imr, NE2000State),
 638         VMSTATE_BUFFER(phys, NE2000State),
 639         VMSTATE_UINT8(curpag, NE2000State),
 640         VMSTATE_BUFFER(mult, NE2000State),
 641         VMSTATE_UNUSED(4), /* was irq */
 642         VMSTATE_BUFFER(mem, NE2000State),
 643         VMSTATE_END_OF_LIST()
 644     }
 645 };
 646
 647 static const VMStateDescription vmstate_pci_ne2000 = {
 648     .name = "ne2000",
 649     .version_id = 3,
 650     .minimum_version_id = 3,
 651     .fields = (VMStateField[]) {
 652         VMSTATE_PCI_DEVICE(dev, PCINE2000State),
 653         VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
 654         VMSTATE_END_OF_LIST()
 655     }
 656 };
 657
 658 static uint64_t ne2000_read(void *opaque, hwaddr addr,
 659                             unsigned size)
 660 {
 661     NE2000State *s = opaque;
 662     uint64_t val;
 663
 664     if (addr < 0x10 && size == 1) {
 665         val = ne2000_ioport_read(s, addr);
 666     } else if (addr == 0x10) {
 667         if (size <= 2) {
 668             val = ne2000_asic_ioport_read(s, addr);
 669         } else {
 670             val = ne2000_asic_ioport_readl(s, addr);
 671         }
 672     } else if (addr == 0x1f && size == 1) {
 673         val = ne2000_reset_ioport_read(s, addr);
 674     } else {
 675         val = ((uint64_t)1 << (size * 8)) - 1;
 676     }
 677     trace_ne2000_read(addr, val);
 678
 679     return val;
 680 }
 681
 682 static void ne2000_write(void *opaque, hwaddr addr,
 683                          uint64_t data, unsigned size)
 684 {
 685     NE2000State *s = opaque;
 686
 687     trace_ne2000_write(addr, data);
 688     if (addr < 0x10 && size == 1) {
 689         ne2000_ioport_write(s, addr, data);
 690     } else if (addr == 0x10) {
 691         if (size <= 2) {
 692             ne2000_asic_ioport_write(s, addr, data);
 693         } else {
 694             ne2000_asic_ioport_writel(s, addr, data);
 695         }
 696     } else if (addr == 0x1f && size == 1) {
 697         ne2000_reset_ioport_write(s, addr, data);
 698     }
 699 }
 700
 701 static const MemoryRegionOps ne2000_ops = {
 702     .read = ne2000_read,
 703     .write = ne2000_write,
 704     .endianness = DEVICE_LITTLE_ENDIAN,
 705 };
 706
 707 /***********************************************************/
 708 /* PCI NE2000 definitions */
 709
 710 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
 711 {
 712     memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
 713 }
 714
 715 static NetClientInfo net_ne2000_info = {
 716     .type = NET_CLIENT_DRIVER_NIC,
 717     .size = sizeof(NICState),
 718     .receive = ne2000_receive,
 719 };
 720
 721 static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
 722 {
 723     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 724     NE2000State *s;
 725     uint8_t *pci_conf;
 726
 727     pci_conf = d->dev.config;
 728     pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
 729
 730     s = &d->ne2000;
 731     ne2000_setup_io(s, DEVICE(pci_dev), 0x100);
 732     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 733     s->irq = pci_allocate_irq(&d->dev);
 734
 735     qemu_macaddr_default_if_unset(&s->c.macaddr);
 736     ne2000_reset(s);
 737
 738     s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
 739                           object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
 740     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
 741 }
 742
 743 static void pci_ne2000_exit(PCIDevice *pci_dev)
 744 {
 745     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 746     NE2000State *s = &d->ne2000;
 747
 748     qemu_del_nic(s->nic);
 749     qemu_free_irq(s->irq);
 750 }
 751
 752 static void ne2000_instance_init(Object *obj)
 753 {
 754     PCIDevice *pci_dev = PCI_DEVICE(obj);
 755     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 756     NE2000State *s = &d->ne2000;
 757
 758     device_add_bootindex_property(obj, &s->c.bootindex,
 759                                   "bootindex", "/ethernet-phy@0",
 760                                   &pci_dev->qdev, NULL);
 761 }
 762
 763 static Property ne2000_properties[] = {
 764     DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
 765     DEFINE_PROP_END_OF_LIST(),
 766 };
 767
 768 static void ne2000_class_init(ObjectClass *klass, void *data)
 769 {
 770     DeviceClass *dc = DEVICE_CLASS(klass);
 771     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 772
 773     k->realize = pci_ne2000_realize;
 774     k->exit = pci_ne2000_exit;
 775     k->romfile = "efi-ne2k_pci.rom",
 776     k->vendor_id = PCI_VENDOR_ID_REALTEK;
 777     k->device_id = PCI_DEVICE_ID_REALTEK_8029;
 778     k->class_id = PCI_CLASS_NETWORK_ETHERNET;
 779     dc->vmsd = &vmstate_pci_ne2000;
 780     dc->props = ne2000_properties;
 781     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 782 }
 783
 784 static const TypeInfo ne2000_info = {
 785     .name          = "ne2k_pci",
 786     .parent        = TYPE_PCI_DEVICE,
 787     .instance_size = sizeof(PCINE2000State),
 788     .class_init    = ne2000_class_init,
 789     .instance_init = ne2000_instance_init,
 790     .interfaces = (InterfaceInfo[]) {
 791         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 792         { },
 793     },
 794 };
 795
 796 static void ne2000_register_types(void)
 797 {
 798     type_register_static(&ne2000_info);
 799 }
 800
 801 type_init(ne2000_register_types)