4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci.h"
29 #include "qemu/error-report.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/dma.h"
33 #include "hw/ide/internal.h"
34 #include "hw/ide/pci.h"
35 #include "ahci_internal.h"
39 static void check_cmd(AHCIState
*s
, int port
);
40 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
);
41 static void ahci_reset_port(AHCIState
*s
, int port
);
42 static bool ahci_write_fis_d2h(AHCIDevice
*ad
);
43 static void ahci_init_d2h(AHCIDevice
*ad
);
44 static int ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
);
45 static bool ahci_map_clb_address(AHCIDevice
*ad
);
46 static bool ahci_map_fis_address(AHCIDevice
*ad
);
47 static void ahci_unmap_clb_address(AHCIDevice
*ad
);
48 static void ahci_unmap_fis_address(AHCIDevice
*ad
);
50 static const char *AHCIHostReg_lookup
[AHCI_HOST_REG__COUNT
] = {
51 [AHCI_HOST_REG_CAP
] = "CAP",
52 [AHCI_HOST_REG_CTL
] = "GHC",
53 [AHCI_HOST_REG_IRQ_STAT
] = "IS",
54 [AHCI_HOST_REG_PORTS_IMPL
] = "PI",
55 [AHCI_HOST_REG_VERSION
] = "VS",
56 [AHCI_HOST_REG_CCC_CTL
] = "CCC_CTL",
57 [AHCI_HOST_REG_CCC_PORTS
] = "CCC_PORTS",
58 [AHCI_HOST_REG_EM_LOC
] = "EM_LOC",
59 [AHCI_HOST_REG_EM_CTL
] = "EM_CTL",
60 [AHCI_HOST_REG_CAP2
] = "CAP2",
61 [AHCI_HOST_REG_BOHC
] = "BOHC",
64 static const char *AHCIPortReg_lookup
[AHCI_PORT_REG__COUNT
] = {
65 [AHCI_PORT_REG_LST_ADDR
] = "PxCLB",
66 [AHCI_PORT_REG_LST_ADDR_HI
] = "PxCLBU",
67 [AHCI_PORT_REG_FIS_ADDR
] = "PxFB",
68 [AHCI_PORT_REG_FIS_ADDR_HI
] = "PxFBU",
69 [AHCI_PORT_REG_IRQ_STAT
] = "PxIS",
70 [AHCI_PORT_REG_IRQ_MASK
] = "PXIE",
71 [AHCI_PORT_REG_CMD
] = "PxCMD",
73 [AHCI_PORT_REG_TFDATA
] = "PxTFD",
74 [AHCI_PORT_REG_SIG
] = "PxSIG",
75 [AHCI_PORT_REG_SCR_STAT
] = "PxSSTS",
76 [AHCI_PORT_REG_SCR_CTL
] = "PxSCTL",
77 [AHCI_PORT_REG_SCR_ERR
] = "PxSERR",
78 [AHCI_PORT_REG_SCR_ACT
] = "PxSACT",
79 [AHCI_PORT_REG_CMD_ISSUE
] = "PxCI",
80 [AHCI_PORT_REG_SCR_NOTIF
] = "PxSNTF",
81 [AHCI_PORT_REG_FIS_CTL
] = "PxFBS",
82 [AHCI_PORT_REG_DEV_SLEEP
] = "PxDEVSLP",
83 [18 ... 27] = "Reserved",
84 [AHCI_PORT_REG_VENDOR_1
...
85 AHCI_PORT_REG_VENDOR_4
] = "PxVS",
88 static const char *AHCIPortIRQ_lookup
[AHCI_PORT_IRQ__COUNT
] = {
89 [AHCI_PORT_IRQ_BIT_DHRS
] = "DHRS",
90 [AHCI_PORT_IRQ_BIT_PSS
] = "PSS",
91 [AHCI_PORT_IRQ_BIT_DSS
] = "DSS",
92 [AHCI_PORT_IRQ_BIT_SDBS
] = "SDBS",
93 [AHCI_PORT_IRQ_BIT_UFS
] = "UFS",
94 [AHCI_PORT_IRQ_BIT_DPS
] = "DPS",
95 [AHCI_PORT_IRQ_BIT_PCS
] = "PCS",
96 [AHCI_PORT_IRQ_BIT_DMPS
] = "DMPS",
97 [8 ... 21] = "RESERVED",
98 [AHCI_PORT_IRQ_BIT_PRCS
] = "PRCS",
99 [AHCI_PORT_IRQ_BIT_IPMS
] = "IPMS",
100 [AHCI_PORT_IRQ_BIT_OFS
] = "OFS",
102 [AHCI_PORT_IRQ_BIT_INFS
] = "INFS",
103 [AHCI_PORT_IRQ_BIT_IFS
] = "IFS",
104 [AHCI_PORT_IRQ_BIT_HBDS
] = "HBDS",
105 [AHCI_PORT_IRQ_BIT_HBFS
] = "HBFS",
106 [AHCI_PORT_IRQ_BIT_TFES
] = "TFES",
107 [AHCI_PORT_IRQ_BIT_CPDS
] = "CPDS"
110 static uint32_t ahci_port_read(AHCIState
*s
, int port
, int offset
)
113 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
114 enum AHCIPortReg regnum
= offset
/ sizeof(uint32_t);
115 assert(regnum
< (AHCI_PORT_ADDR_OFFSET_LEN
/ sizeof(uint32_t)));
118 case AHCI_PORT_REG_LST_ADDR
:
121 case AHCI_PORT_REG_LST_ADDR_HI
:
122 val
= pr
->lst_addr_hi
;
124 case AHCI_PORT_REG_FIS_ADDR
:
127 case AHCI_PORT_REG_FIS_ADDR_HI
:
128 val
= pr
->fis_addr_hi
;
130 case AHCI_PORT_REG_IRQ_STAT
:
133 case AHCI_PORT_REG_IRQ_MASK
:
136 case AHCI_PORT_REG_CMD
:
139 case AHCI_PORT_REG_TFDATA
:
142 case AHCI_PORT_REG_SIG
:
145 case AHCI_PORT_REG_SCR_STAT
:
146 if (s
->dev
[port
].port
.ifs
[0].blk
) {
147 val
= SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP
|
148 SATA_SCR_SSTATUS_SPD_GEN1
| SATA_SCR_SSTATUS_IPM_ACTIVE
;
150 val
= SATA_SCR_SSTATUS_DET_NODEV
;
153 case AHCI_PORT_REG_SCR_CTL
:
156 case AHCI_PORT_REG_SCR_ERR
:
159 case AHCI_PORT_REG_SCR_ACT
:
162 case AHCI_PORT_REG_CMD_ISSUE
:
166 trace_ahci_port_read_default(s
, port
, AHCIPortReg_lookup
[regnum
],
171 trace_ahci_port_read(s
, port
, AHCIPortReg_lookup
[regnum
], offset
, val
);
175 static void ahci_irq_raise(AHCIState
*s
)
177 DeviceState
*dev_state
= s
->container
;
178 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
181 trace_ahci_irq_raise(s
);
183 if (pci_dev
&& msi_enabled(pci_dev
)) {
184 msi_notify(pci_dev
, 0);
186 qemu_irq_raise(s
->irq
);
190 static void ahci_irq_lower(AHCIState
*s
)
192 DeviceState
*dev_state
= s
->container
;
193 PCIDevice
*pci_dev
= (PCIDevice
*) object_dynamic_cast(OBJECT(dev_state
),
196 trace_ahci_irq_lower(s
);
198 if (!pci_dev
|| !msi_enabled(pci_dev
)) {
199 qemu_irq_lower(s
->irq
);
203 static void ahci_check_irq(AHCIState
*s
)
206 uint32_t old_irq
= s
->control_regs
.irqstatus
;
208 s
->control_regs
.irqstatus
= 0;
209 for (i
= 0; i
< s
->ports
; i
++) {
210 AHCIPortRegs
*pr
= &s
->dev
[i
].port_regs
;
211 if (pr
->irq_stat
& pr
->irq_mask
) {
212 s
->control_regs
.irqstatus
|= (1 << i
);
215 trace_ahci_check_irq(s
, old_irq
, s
->control_regs
.irqstatus
);
216 if (s
->control_regs
.irqstatus
&&
217 (s
->control_regs
.ghc
& HOST_CTL_IRQ_EN
)) {
224 static void ahci_trigger_irq(AHCIState
*s
, AHCIDevice
*d
,
225 enum AHCIPortIRQ irqbit
)
227 g_assert((unsigned)irqbit
< 32);
228 uint32_t irq
= 1U << irqbit
;
229 uint32_t irqstat
= d
->port_regs
.irq_stat
| irq
;
231 trace_ahci_trigger_irq(s
, d
->port_no
,
232 AHCIPortIRQ_lookup
[irqbit
], irq
,
233 d
->port_regs
.irq_stat
, irqstat
,
234 irqstat
& d
->port_regs
.irq_mask
);
236 d
->port_regs
.irq_stat
= irqstat
;
240 static void map_page(AddressSpace
*as
, uint8_t **ptr
, uint64_t addr
,
246 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
249 *ptr
= dma_memory_map(as
, addr
, &len
, DMA_DIRECTION_FROM_DEVICE
);
251 dma_memory_unmap(as
, *ptr
, len
, DMA_DIRECTION_FROM_DEVICE
, len
);
257 * Check the cmd register to see if we should start or stop
258 * the DMA or FIS RX engines.
260 * @ad: Device to dis/engage.
262 * @return 0 on success, -1 on error.
264 static int ahci_cond_start_engines(AHCIDevice
*ad
)
266 AHCIPortRegs
*pr
= &ad
->port_regs
;
267 bool cmd_start
= pr
->cmd
& PORT_CMD_START
;
268 bool cmd_on
= pr
->cmd
& PORT_CMD_LIST_ON
;
269 bool fis_start
= pr
->cmd
& PORT_CMD_FIS_RX
;
270 bool fis_on
= pr
->cmd
& PORT_CMD_FIS_ON
;
272 if (cmd_start
&& !cmd_on
) {
273 if (!ahci_map_clb_address(ad
)) {
274 pr
->cmd
&= ~PORT_CMD_START
;
275 error_report("AHCI: Failed to start DMA engine: "
276 "bad command list buffer address");
279 } else if (!cmd_start
&& cmd_on
) {
280 ahci_unmap_clb_address(ad
);
283 if (fis_start
&& !fis_on
) {
284 if (!ahci_map_fis_address(ad
)) {
285 pr
->cmd
&= ~PORT_CMD_FIS_RX
;
286 error_report("AHCI: Failed to start FIS receive engine: "
287 "bad FIS receive buffer address");
290 } else if (!fis_start
&& fis_on
) {
291 ahci_unmap_fis_address(ad
);
297 static void ahci_port_write(AHCIState
*s
, int port
, int offset
, uint32_t val
)
299 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
300 enum AHCIPortReg regnum
= offset
/ sizeof(uint32_t);
301 assert(regnum
< (AHCI_PORT_ADDR_OFFSET_LEN
/ sizeof(uint32_t)));
302 trace_ahci_port_write(s
, port
, AHCIPortReg_lookup
[regnum
], offset
, val
);
305 case AHCI_PORT_REG_LST_ADDR
:
308 case AHCI_PORT_REG_LST_ADDR_HI
:
309 pr
->lst_addr_hi
= val
;
311 case AHCI_PORT_REG_FIS_ADDR
:
314 case AHCI_PORT_REG_FIS_ADDR_HI
:
315 pr
->fis_addr_hi
= val
;
317 case AHCI_PORT_REG_IRQ_STAT
:
318 pr
->irq_stat
&= ~val
;
321 case AHCI_PORT_REG_IRQ_MASK
:
322 pr
->irq_mask
= val
& 0xfdc000ff;
325 case AHCI_PORT_REG_CMD
:
326 /* Block any Read-only fields from being set;
327 * including LIST_ON and FIS_ON.
328 * The spec requires to set ICC bits to zero after the ICC change
329 * is done. We don't support ICC state changes, therefore always
330 * force the ICC bits to zero.
332 pr
->cmd
= (pr
->cmd
& PORT_CMD_RO_MASK
) |
333 (val
& ~(PORT_CMD_RO_MASK
| PORT_CMD_ICC_MASK
));
335 /* Check FIS RX and CLB engines */
336 ahci_cond_start_engines(&s
->dev
[port
]);
338 /* XXX usually the FIS would be pending on the bus here and
339 issuing deferred until the OS enables FIS receival.
340 Instead, we only submit it once - which works in most
341 cases, but is a hack. */
342 if ((pr
->cmd
& PORT_CMD_FIS_ON
) &&
343 !s
->dev
[port
].init_d2h_sent
) {
344 ahci_init_d2h(&s
->dev
[port
]);
349 case AHCI_PORT_REG_TFDATA
:
350 case AHCI_PORT_REG_SIG
:
351 case AHCI_PORT_REG_SCR_STAT
:
354 case AHCI_PORT_REG_SCR_CTL
:
355 if (((pr
->scr_ctl
& AHCI_SCR_SCTL_DET
) == 1) &&
356 ((val
& AHCI_SCR_SCTL_DET
) == 0)) {
357 ahci_reset_port(s
, port
);
361 case AHCI_PORT_REG_SCR_ERR
:
364 case AHCI_PORT_REG_SCR_ACT
:
368 case AHCI_PORT_REG_CMD_ISSUE
:
369 pr
->cmd_issue
|= val
;
373 trace_ahci_port_write_unimpl(s
, port
, AHCIPortReg_lookup
[regnum
],
375 qemu_log_mask(LOG_UNIMP
, "Attempted write to unimplemented register: "
376 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32
,
377 port
, AHCIPortReg_lookup
[regnum
], offset
, val
);
382 static uint64_t ahci_mem_read_32(void *opaque
, hwaddr addr
)
384 AHCIState
*s
= opaque
;
387 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
388 enum AHCIHostReg regnum
= addr
/ 4;
389 assert(regnum
< AHCI_HOST_REG__COUNT
);
392 case AHCI_HOST_REG_CAP
:
393 val
= s
->control_regs
.cap
;
395 case AHCI_HOST_REG_CTL
:
396 val
= s
->control_regs
.ghc
;
398 case AHCI_HOST_REG_IRQ_STAT
:
399 val
= s
->control_regs
.irqstatus
;
401 case AHCI_HOST_REG_PORTS_IMPL
:
402 val
= s
->control_regs
.impl
;
404 case AHCI_HOST_REG_VERSION
:
405 val
= s
->control_regs
.version
;
408 trace_ahci_mem_read_32_host_default(s
, AHCIHostReg_lookup
[regnum
],
411 trace_ahci_mem_read_32_host(s
, AHCIHostReg_lookup
[regnum
], addr
, val
);
412 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
413 (addr
< (AHCI_PORT_REGS_START_ADDR
+
414 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
415 val
= ahci_port_read(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
416 addr
& AHCI_PORT_ADDR_OFFSET_MASK
);
418 trace_ahci_mem_read_32_default(s
, addr
, val
);
421 trace_ahci_mem_read_32(s
, addr
, val
);
427 * AHCI 1.3 section 3 ("HBA Memory Registers")
428 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
429 * Caller is responsible for masking unwanted higher order bytes.
431 static uint64_t ahci_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
433 hwaddr aligned
= addr
& ~0x3;
434 int ofst
= addr
- aligned
;
435 uint64_t lo
= ahci_mem_read_32(opaque
, aligned
);
439 /* if < 8 byte read does not cross 4 byte boundary */
440 if (ofst
+ size
<= 4) {
441 val
= lo
>> (ofst
* 8);
443 g_assert_cmpint(size
, >, 1);
445 /* If the 64bit read is unaligned, we will produce undefined
446 * results. AHCI does not support unaligned 64bit reads. */
447 hi
= ahci_mem_read_32(opaque
, aligned
+ 4);
448 val
= (hi
<< 32 | lo
) >> (ofst
* 8);
451 trace_ahci_mem_read(opaque
, size
, addr
, val
);
456 static void ahci_mem_write(void *opaque
, hwaddr addr
,
457 uint64_t val
, unsigned size
)
459 AHCIState
*s
= opaque
;
461 trace_ahci_mem_write(s
, size
, addr
, val
);
463 /* Only aligned reads are allowed on AHCI */
465 fprintf(stderr
, "ahci: Mis-aligned write to addr 0x"
466 TARGET_FMT_plx
"\n", addr
);
470 if (addr
< AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR
) {
471 enum AHCIHostReg regnum
= addr
/ 4;
472 assert(regnum
< AHCI_HOST_REG__COUNT
);
475 case AHCI_HOST_REG_CAP
: /* R/WO, RO */
476 /* FIXME handle R/WO */
478 case AHCI_HOST_REG_CTL
: /* R/W */
479 if (val
& HOST_CTL_RESET
) {
482 s
->control_regs
.ghc
= (val
& 0x3) | HOST_CTL_AHCI_EN
;
486 case AHCI_HOST_REG_IRQ_STAT
: /* R/WC, RO */
487 s
->control_regs
.irqstatus
&= ~val
;
490 case AHCI_HOST_REG_PORTS_IMPL
: /* R/WO, RO */
491 /* FIXME handle R/WO */
493 case AHCI_HOST_REG_VERSION
: /* RO */
494 /* FIXME report write? */
497 trace_ahci_mem_write_unknown(s
, size
, addr
, val
);
499 } else if ((addr
>= AHCI_PORT_REGS_START_ADDR
) &&
500 (addr
< (AHCI_PORT_REGS_START_ADDR
+
501 (s
->ports
* AHCI_PORT_ADDR_OFFSET_LEN
)))) {
502 ahci_port_write(s
, (addr
- AHCI_PORT_REGS_START_ADDR
) >> 7,
503 addr
& AHCI_PORT_ADDR_OFFSET_MASK
, val
);
507 static const MemoryRegionOps ahci_mem_ops
= {
508 .read
= ahci_mem_read
,
509 .write
= ahci_mem_write
,
510 .endianness
= DEVICE_LITTLE_ENDIAN
,
513 static uint64_t ahci_idp_read(void *opaque
, hwaddr addr
,
516 AHCIState
*s
= opaque
;
518 if (addr
== s
->idp_offset
) {
521 } else if (addr
== s
->idp_offset
+ 4) {
522 /* data register - do memory read at location selected by index */
523 return ahci_mem_read(opaque
, s
->idp_index
, size
);
529 static void ahci_idp_write(void *opaque
, hwaddr addr
,
530 uint64_t val
, unsigned size
)
532 AHCIState
*s
= opaque
;
534 if (addr
== s
->idp_offset
) {
535 /* index register - mask off reserved bits */
536 s
->idp_index
= (uint32_t)val
& ((AHCI_MEM_BAR_SIZE
- 1) & ~3);
537 } else if (addr
== s
->idp_offset
+ 4) {
538 /* data register - do memory write at location selected by index */
539 ahci_mem_write(opaque
, s
->idp_index
, val
, size
);
543 static const MemoryRegionOps ahci_idp_ops
= {
544 .read
= ahci_idp_read
,
545 .write
= ahci_idp_write
,
546 .endianness
= DEVICE_LITTLE_ENDIAN
,
550 static void ahci_reg_init(AHCIState
*s
)
554 s
->control_regs
.cap
= (s
->ports
- 1) |
555 (AHCI_NUM_COMMAND_SLOTS
<< 8) |
556 (AHCI_SUPPORTED_SPEED_GEN1
<< AHCI_SUPPORTED_SPEED
) |
557 HOST_CAP_NCQ
| HOST_CAP_AHCI
| HOST_CAP_64
;
559 s
->control_regs
.impl
= (1 << s
->ports
) - 1;
561 s
->control_regs
.version
= AHCI_VERSION_1_0
;
563 for (i
= 0; i
< s
->ports
; i
++) {
564 s
->dev
[i
].port_state
= STATE_RUN
;
568 static void check_cmd(AHCIState
*s
, int port
)
570 AHCIPortRegs
*pr
= &s
->dev
[port
].port_regs
;
573 if ((pr
->cmd
& PORT_CMD_START
) && pr
->cmd_issue
) {
574 for (slot
= 0; (slot
< 32) && pr
->cmd_issue
; slot
++) {
575 if ((pr
->cmd_issue
& (1U << slot
)) &&
576 !handle_cmd(s
, port
, slot
)) {
577 pr
->cmd_issue
&= ~(1U << slot
);
583 static void ahci_check_cmd_bh(void *opaque
)
585 AHCIDevice
*ad
= opaque
;
587 qemu_bh_delete(ad
->check_bh
);
590 check_cmd(ad
->hba
, ad
->port_no
);
593 static void ahci_init_d2h(AHCIDevice
*ad
)
595 IDEState
*ide_state
= &ad
->port
.ifs
[0];
596 AHCIPortRegs
*pr
= &ad
->port_regs
;
598 if (ad
->init_d2h_sent
) {
602 if (ahci_write_fis_d2h(ad
)) {
603 ad
->init_d2h_sent
= true;
604 /* We're emulating receiving the first Reg H2D Fis from the device;
605 * Update the SIG register, but otherwise proceed as normal. */
606 pr
->sig
= ((uint32_t)ide_state
->hcyl
<< 24) |
607 (ide_state
->lcyl
<< 16) |
608 (ide_state
->sector
<< 8) |
609 (ide_state
->nsector
& 0xFF);
613 static void ahci_set_signature(AHCIDevice
*ad
, uint32_t sig
)
615 IDEState
*s
= &ad
->port
.ifs
[0];
616 s
->hcyl
= sig
>> 24 & 0xFF;
617 s
->lcyl
= sig
>> 16 & 0xFF;
618 s
->sector
= sig
>> 8 & 0xFF;
619 s
->nsector
= sig
& 0xFF;
621 trace_ahci_set_signature(ad
->hba
, ad
->port_no
, s
->nsector
, s
->sector
,
622 s
->lcyl
, s
->hcyl
, sig
);
625 static void ahci_reset_port(AHCIState
*s
, int port
)
627 AHCIDevice
*d
= &s
->dev
[port
];
628 AHCIPortRegs
*pr
= &d
->port_regs
;
629 IDEState
*ide_state
= &d
->port
.ifs
[0];
632 trace_ahci_reset_port(s
, port
);
634 ide_bus_reset(&d
->port
);
635 ide_state
->ncq_queues
= AHCI_MAX_CMDS
;
641 pr
->sig
= 0xFFFFFFFF;
643 d
->init_d2h_sent
= false;
645 ide_state
= &s
->dev
[port
].port
.ifs
[0];
646 if (!ide_state
->blk
) {
650 /* reset ncq queue */
651 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
652 NCQTransferState
*ncq_tfs
= &s
->dev
[port
].ncq_tfs
[i
];
653 ncq_tfs
->halt
= false;
654 if (!ncq_tfs
->used
) {
658 if (ncq_tfs
->aiocb
) {
659 blk_aio_cancel(ncq_tfs
->aiocb
);
660 ncq_tfs
->aiocb
= NULL
;
663 /* Maybe we just finished the request thanks to blk_aio_cancel() */
664 if (!ncq_tfs
->used
) {
668 qemu_sglist_destroy(&ncq_tfs
->sglist
);
672 s
->dev
[port
].port_state
= STATE_RUN
;
673 if (ide_state
->drive_kind
== IDE_CD
) {
674 ahci_set_signature(d
, SATA_SIGNATURE_CDROM
);\
675 ide_state
->status
= SEEK_STAT
| WRERR_STAT
| READY_STAT
;
677 ahci_set_signature(d
, SATA_SIGNATURE_DISK
);
678 ide_state
->status
= SEEK_STAT
| WRERR_STAT
;
681 ide_state
->error
= 1;
685 /* Buffer pretty output based on a raw FIS structure. */
686 static char *ahci_pretty_buffer_fis(uint8_t *fis
, int cmd_len
)
689 GString
*s
= g_string_new("FIS:");
691 for (i
= 0; i
< cmd_len
; i
++) {
692 if ((i
& 0xf) == 0) {
693 g_string_append_printf(s
, "\n0x%02x: ", i
);
695 g_string_append_printf(s
, "%02x ", fis
[i
]);
697 g_string_append_c(s
, '\n');
699 return g_string_free(s
, FALSE
);
702 static bool ahci_map_fis_address(AHCIDevice
*ad
)
704 AHCIPortRegs
*pr
= &ad
->port_regs
;
705 map_page(ad
->hba
->as
, &ad
->res_fis
,
706 ((uint64_t)pr
->fis_addr_hi
<< 32) | pr
->fis_addr
, 256);
707 if (ad
->res_fis
!= NULL
) {
708 pr
->cmd
|= PORT_CMD_FIS_ON
;
712 pr
->cmd
&= ~PORT_CMD_FIS_ON
;
716 static void ahci_unmap_fis_address(AHCIDevice
*ad
)
718 if (ad
->res_fis
== NULL
) {
719 trace_ahci_unmap_fis_address_null(ad
->hba
, ad
->port_no
);
722 ad
->port_regs
.cmd
&= ~PORT_CMD_FIS_ON
;
723 dma_memory_unmap(ad
->hba
->as
, ad
->res_fis
, 256,
724 DMA_DIRECTION_FROM_DEVICE
, 256);
728 static bool ahci_map_clb_address(AHCIDevice
*ad
)
730 AHCIPortRegs
*pr
= &ad
->port_regs
;
732 map_page(ad
->hba
->as
, &ad
->lst
,
733 ((uint64_t)pr
->lst_addr_hi
<< 32) | pr
->lst_addr
, 1024);
734 if (ad
->lst
!= NULL
) {
735 pr
->cmd
|= PORT_CMD_LIST_ON
;
739 pr
->cmd
&= ~PORT_CMD_LIST_ON
;
743 static void ahci_unmap_clb_address(AHCIDevice
*ad
)
745 if (ad
->lst
== NULL
) {
746 trace_ahci_unmap_clb_address_null(ad
->hba
, ad
->port_no
);
749 ad
->port_regs
.cmd
&= ~PORT_CMD_LIST_ON
;
750 dma_memory_unmap(ad
->hba
->as
, ad
->lst
, 1024,
751 DMA_DIRECTION_FROM_DEVICE
, 1024);
755 static void ahci_write_fis_sdb(AHCIState
*s
, NCQTransferState
*ncq_tfs
)
757 AHCIDevice
*ad
= ncq_tfs
->drive
;
758 AHCIPortRegs
*pr
= &ad
->port_regs
;
763 !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
767 sdb_fis
= (SDBFIS
*)&ad
->res_fis
[RES_FIS_SDBFIS
];
768 ide_state
= &ad
->port
.ifs
[0];
770 sdb_fis
->type
= SATA_FIS_TYPE_SDB
;
771 /* Interrupt pending & Notification bit */
772 sdb_fis
->flags
= 0x40; /* Interrupt bit, always 1 for NCQ */
773 sdb_fis
->status
= ide_state
->status
& 0x77;
774 sdb_fis
->error
= ide_state
->error
;
775 /* update SAct field in SDB_FIS */
776 sdb_fis
->payload
= cpu_to_le32(ad
->finished
);
778 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
779 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
780 (ad
->port
.ifs
[0].status
& 0x77) |
782 pr
->scr_act
&= ~ad
->finished
;
785 /* Trigger IRQ if interrupt bit is set (which currently, it always is) */
786 if (sdb_fis
->flags
& 0x40) {
787 ahci_trigger_irq(s
, ad
, AHCI_PORT_IRQ_BIT_SDBS
);
791 static void ahci_write_fis_pio(AHCIDevice
*ad
, uint16_t len
)
793 AHCIPortRegs
*pr
= &ad
->port_regs
;
795 IDEState
*s
= &ad
->port
.ifs
[0];
797 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
801 pio_fis
= &ad
->res_fis
[RES_FIS_PSFIS
];
803 pio_fis
[0] = SATA_FIS_TYPE_PIO_SETUP
;
804 pio_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
805 pio_fis
[2] = s
->status
;
806 pio_fis
[3] = s
->error
;
808 pio_fis
[4] = s
->sector
;
809 pio_fis
[5] = s
->lcyl
;
810 pio_fis
[6] = s
->hcyl
;
811 pio_fis
[7] = s
->select
;
812 pio_fis
[8] = s
->hob_sector
;
813 pio_fis
[9] = s
->hob_lcyl
;
814 pio_fis
[10] = s
->hob_hcyl
;
816 pio_fis
[12] = s
->nsector
& 0xFF;
817 pio_fis
[13] = (s
->nsector
>> 8) & 0xFF;
819 pio_fis
[15] = s
->status
;
820 pio_fis
[16] = len
& 255;
821 pio_fis
[17] = len
>> 8;
825 /* Update shadow registers: */
826 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
827 ad
->port
.ifs
[0].status
;
829 if (pio_fis
[2] & ERR_STAT
) {
830 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_TFES
);
833 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_PSS
);
836 static bool ahci_write_fis_d2h(AHCIDevice
*ad
)
838 AHCIPortRegs
*pr
= &ad
->port_regs
;
841 IDEState
*s
= &ad
->port
.ifs
[0];
843 if (!ad
->res_fis
|| !(pr
->cmd
& PORT_CMD_FIS_RX
)) {
847 d2h_fis
= &ad
->res_fis
[RES_FIS_RFIS
];
849 d2h_fis
[0] = SATA_FIS_TYPE_REGISTER_D2H
;
850 d2h_fis
[1] = (ad
->hba
->control_regs
.irqstatus
? (1 << 6) : 0);
851 d2h_fis
[2] = s
->status
;
852 d2h_fis
[3] = s
->error
;
854 d2h_fis
[4] = s
->sector
;
855 d2h_fis
[5] = s
->lcyl
;
856 d2h_fis
[6] = s
->hcyl
;
857 d2h_fis
[7] = s
->select
;
858 d2h_fis
[8] = s
->hob_sector
;
859 d2h_fis
[9] = s
->hob_lcyl
;
860 d2h_fis
[10] = s
->hob_hcyl
;
862 d2h_fis
[12] = s
->nsector
& 0xFF;
863 d2h_fis
[13] = (s
->nsector
>> 8) & 0xFF;
864 for (i
= 14; i
< 20; i
++) {
868 /* Update shadow registers: */
869 pr
->tfdata
= (ad
->port
.ifs
[0].error
<< 8) |
870 ad
->port
.ifs
[0].status
;
872 if (d2h_fis
[2] & ERR_STAT
) {
873 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_TFES
);
876 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_DHRS
);
880 static int prdt_tbl_entry_size(const AHCI_SG
*tbl
)
882 /* flags_size is zero-based */
883 return (le32_to_cpu(tbl
->flags_size
) & AHCI_PRDT_SIZE_MASK
) + 1;
887 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
888 * @ad: The AHCIDevice for whom we are building the SGList.
889 * @sglist: The SGList target to add PRD entries to.
890 * @cmd: The AHCI Command Header that describes where the PRDT is.
891 * @limit: The remaining size of the S/ATA transaction, in bytes.
892 * @offset: The number of bytes already transferred, in bytes.
894 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
895 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
896 * building the sglist from the PRDT as soon as we hit @limit bytes,
897 * which is <= INT32_MAX/2GiB.
899 static int ahci_populate_sglist(AHCIDevice
*ad
, QEMUSGList
*sglist
,
900 AHCICmdHdr
*cmd
, int64_t limit
, uint64_t offset
)
902 uint16_t opts
= le16_to_cpu(cmd
->opts
);
903 uint16_t prdtl
= le16_to_cpu(cmd
->prdtl
);
904 uint64_t cfis_addr
= le64_to_cpu(cmd
->tbl_addr
);
905 uint64_t prdt_addr
= cfis_addr
+ 0x80;
906 dma_addr_t prdt_len
= (prdtl
* sizeof(AHCI_SG
));
907 dma_addr_t real_prdt_len
= prdt_len
;
913 int64_t off_pos
= -1;
915 IDEBus
*bus
= &ad
->port
;
916 BusState
*qbus
= BUS(bus
);
918 trace_ahci_populate_sglist(ad
->hba
, ad
->port_no
);
921 trace_ahci_populate_sglist_no_prdtl(ad
->hba
, ad
->port_no
, opts
);
926 if (!(prdt
= dma_memory_map(ad
->hba
->as
, prdt_addr
, &prdt_len
,
927 DMA_DIRECTION_TO_DEVICE
))){
928 trace_ahci_populate_sglist_no_map(ad
->hba
, ad
->port_no
);
932 if (prdt_len
< real_prdt_len
) {
933 trace_ahci_populate_sglist_short_map(ad
->hba
, ad
->port_no
);
938 /* Get entries in the PRDT, init a qemu sglist accordingly */
940 AHCI_SG
*tbl
= (AHCI_SG
*)prdt
;
942 for (i
= 0; i
< prdtl
; i
++) {
943 tbl_entry_size
= prdt_tbl_entry_size(&tbl
[i
]);
944 if (offset
< (sum
+ tbl_entry_size
)) {
946 off_pos
= offset
- sum
;
949 sum
+= tbl_entry_size
;
951 if ((off_idx
== -1) || (off_pos
< 0) || (off_pos
> tbl_entry_size
)) {
952 trace_ahci_populate_sglist_bad_offset(ad
->hba
, ad
->port_no
,
958 qemu_sglist_init(sglist
, qbus
->parent
, (prdtl
- off_idx
),
960 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[off_idx
].addr
) + off_pos
,
961 MIN(prdt_tbl_entry_size(&tbl
[off_idx
]) - off_pos
,
964 for (i
= off_idx
+ 1; i
< prdtl
&& sglist
->size
< limit
; i
++) {
965 qemu_sglist_add(sglist
, le64_to_cpu(tbl
[i
].addr
),
966 MIN(prdt_tbl_entry_size(&tbl
[i
]),
967 limit
- sglist
->size
));
972 dma_memory_unmap(ad
->hba
->as
, prdt
, prdt_len
,
973 DMA_DIRECTION_TO_DEVICE
, prdt_len
);
977 static void ncq_err(NCQTransferState
*ncq_tfs
)
979 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
981 ide_state
->error
= ABRT_ERR
;
982 ide_state
->status
= READY_STAT
| ERR_STAT
;
983 ncq_tfs
->drive
->port_regs
.scr_err
|= (1 << ncq_tfs
->tag
);
984 qemu_sglist_destroy(&ncq_tfs
->sglist
);
988 static void ncq_finish(NCQTransferState
*ncq_tfs
)
990 /* If we didn't error out, set our finished bit. Errored commands
991 * do not get a bit set for the SDB FIS ACT register, nor do they
992 * clear the outstanding bit in scr_act (PxSACT). */
993 if (!(ncq_tfs
->drive
->port_regs
.scr_err
& (1 << ncq_tfs
->tag
))) {
994 ncq_tfs
->drive
->finished
|= (1 << ncq_tfs
->tag
);
997 ahci_write_fis_sdb(ncq_tfs
->drive
->hba
, ncq_tfs
);
999 trace_ncq_finish(ncq_tfs
->drive
->hba
, ncq_tfs
->drive
->port_no
,
1002 block_acct_done(blk_get_stats(ncq_tfs
->drive
->port
.ifs
[0].blk
),
1004 qemu_sglist_destroy(&ncq_tfs
->sglist
);
1008 static void ncq_cb(void *opaque
, int ret
)
1010 NCQTransferState
*ncq_tfs
= (NCQTransferState
*)opaque
;
1011 IDEState
*ide_state
= &ncq_tfs
->drive
->port
.ifs
[0];
1013 ncq_tfs
->aiocb
= NULL
;
1014 if (ret
== -ECANCELED
) {
1019 bool is_read
= ncq_tfs
->cmd
== READ_FPDMA_QUEUED
;
1020 BlockErrorAction action
= blk_get_error_action(ide_state
->blk
,
1022 if (action
== BLOCK_ERROR_ACTION_STOP
) {
1023 ncq_tfs
->halt
= true;
1024 ide_state
->bus
->error_status
= IDE_RETRY_HBA
;
1025 } else if (action
== BLOCK_ERROR_ACTION_REPORT
) {
1028 blk_error_action(ide_state
->blk
, action
, is_read
, -ret
);
1030 ide_state
->status
= READY_STAT
| SEEK_STAT
;
1033 if (!ncq_tfs
->halt
) {
1034 ncq_finish(ncq_tfs
);
1038 static int is_ncq(uint8_t ata_cmd
)
1040 /* Based on SATA 3.2 section 13.6.3.2 */
1042 case READ_FPDMA_QUEUED
:
1043 case WRITE_FPDMA_QUEUED
:
1045 case RECEIVE_FPDMA_QUEUED
:
1046 case SEND_FPDMA_QUEUED
:
1053 static void execute_ncq_command(NCQTransferState
*ncq_tfs
)
1055 AHCIDevice
*ad
= ncq_tfs
->drive
;
1056 IDEState
*ide_state
= &ad
->port
.ifs
[0];
1057 int port
= ad
->port_no
;
1059 g_assert(is_ncq(ncq_tfs
->cmd
));
1060 ncq_tfs
->halt
= false;
1062 switch (ncq_tfs
->cmd
) {
1063 case READ_FPDMA_QUEUED
:
1064 trace_execute_ncq_command_read(ad
->hba
, port
, ncq_tfs
->tag
,
1065 ncq_tfs
->sector_count
, ncq_tfs
->lba
);
1066 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1067 &ncq_tfs
->sglist
, BLOCK_ACCT_READ
);
1068 ncq_tfs
->aiocb
= dma_blk_read(ide_state
->blk
, &ncq_tfs
->sglist
,
1069 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1073 case WRITE_FPDMA_QUEUED
:
1074 trace_execute_ncq_command_read(ad
->hba
, port
, ncq_tfs
->tag
,
1075 ncq_tfs
->sector_count
, ncq_tfs
->lba
);
1076 dma_acct_start(ide_state
->blk
, &ncq_tfs
->acct
,
1077 &ncq_tfs
->sglist
, BLOCK_ACCT_WRITE
);
1078 ncq_tfs
->aiocb
= dma_blk_write(ide_state
->blk
, &ncq_tfs
->sglist
,
1079 ncq_tfs
->lba
<< BDRV_SECTOR_BITS
,
1084 trace_execute_ncq_command_unsup(ad
->hba
, port
,
1085 ncq_tfs
->tag
, ncq_tfs
->cmd
);
1091 static void process_ncq_command(AHCIState
*s
, int port
, uint8_t *cmd_fis
,
1094 AHCIDevice
*ad
= &s
->dev
[port
];
1095 NCQFrame
*ncq_fis
= (NCQFrame
*)cmd_fis
;
1096 uint8_t tag
= ncq_fis
->tag
>> 3;
1097 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[tag
];
1100 g_assert(is_ncq(ncq_fis
->command
));
1101 if (ncq_tfs
->used
) {
1102 /* error - already in use */
1103 fprintf(stderr
, "%s: tag %d already used\n", __func__
, tag
);
1108 ncq_tfs
->drive
= ad
;
1109 ncq_tfs
->slot
= slot
;
1110 ncq_tfs
->cmdh
= &((AHCICmdHdr
*)ad
->lst
)[slot
];
1111 ncq_tfs
->cmd
= ncq_fis
->command
;
1112 ncq_tfs
->lba
= ((uint64_t)ncq_fis
->lba5
<< 40) |
1113 ((uint64_t)ncq_fis
->lba4
<< 32) |
1114 ((uint64_t)ncq_fis
->lba3
<< 24) |
1115 ((uint64_t)ncq_fis
->lba2
<< 16) |
1116 ((uint64_t)ncq_fis
->lba1
<< 8) |
1117 (uint64_t)ncq_fis
->lba0
;
1120 /* Sanity-check the NCQ packet */
1122 trace_process_ncq_command_mismatch(s
, port
, tag
, slot
);
1125 if (ncq_fis
->aux0
|| ncq_fis
->aux1
|| ncq_fis
->aux2
|| ncq_fis
->aux3
) {
1126 trace_process_ncq_command_aux(s
, port
, tag
);
1128 if (ncq_fis
->prio
|| ncq_fis
->icc
) {
1129 trace_process_ncq_command_prioicc(s
, port
, tag
);
1131 if (ncq_fis
->fua
& NCQ_FIS_FUA_MASK
) {
1132 trace_process_ncq_command_fua(s
, port
, tag
);
1134 if (ncq_fis
->tag
& NCQ_FIS_RARC_MASK
) {
1135 trace_process_ncq_command_rarc(s
, port
, tag
);
1138 ncq_tfs
->sector_count
= ((ncq_fis
->sector_count_high
<< 8) |
1139 ncq_fis
->sector_count_low
);
1140 if (!ncq_tfs
->sector_count
) {
1141 ncq_tfs
->sector_count
= 0x10000;
1143 size
= ncq_tfs
->sector_count
* 512;
1144 ahci_populate_sglist(ad
, &ncq_tfs
->sglist
, ncq_tfs
->cmdh
, size
, 0);
1146 if (ncq_tfs
->sglist
.size
< size
) {
1147 error_report("ahci: PRDT length for NCQ command (0x%zx) "
1148 "is smaller than the requested size (0x%zx)",
1149 ncq_tfs
->sglist
.size
, size
);
1151 ahci_trigger_irq(ad
->hba
, ad
, AHCI_PORT_IRQ_BIT_OFS
);
1153 } else if (ncq_tfs
->sglist
.size
!= size
) {
1154 trace_process_ncq_command_large(s
, port
, tag
,
1155 ncq_tfs
->sglist
.size
, size
);
1158 trace_process_ncq_command(s
, port
, tag
,
1161 ncq_tfs
->lba
+ ncq_tfs
->sector_count
- 1);
1162 execute_ncq_command(ncq_tfs
);
1165 static AHCICmdHdr
*get_cmd_header(AHCIState
*s
, uint8_t port
, uint8_t slot
)
1167 if (port
>= s
->ports
|| slot
>= AHCI_MAX_CMDS
) {
1171 return s
->dev
[port
].lst
? &((AHCICmdHdr
*)s
->dev
[port
].lst
)[slot
] : NULL
;
1174 static void handle_reg_h2d_fis(AHCIState
*s
, int port
,
1175 uint8_t slot
, uint8_t *cmd_fis
)
1177 IDEState
*ide_state
= &s
->dev
[port
].port
.ifs
[0];
1178 AHCICmdHdr
*cmd
= get_cmd_header(s
, port
, slot
);
1179 uint16_t opts
= le16_to_cpu(cmd
->opts
);
1181 if (cmd_fis
[1] & 0x0F) {
1182 trace_handle_reg_h2d_fis_pmp(s
, port
, cmd_fis
[1],
1183 cmd_fis
[2], cmd_fis
[3]);
1187 if (cmd_fis
[1] & 0x70) {
1188 trace_handle_reg_h2d_fis_res(s
, port
, cmd_fis
[1],
1189 cmd_fis
[2], cmd_fis
[3]);
1193 if (!(cmd_fis
[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER
)) {
1194 switch (s
->dev
[port
].port_state
) {
1196 if (cmd_fis
[15] & ATA_SRST
) {
1197 s
->dev
[port
].port_state
= STATE_RESET
;
1201 if (!(cmd_fis
[15] & ATA_SRST
)) {
1202 ahci_reset_port(s
, port
);
1209 /* Check for NCQ command */
1210 if (is_ncq(cmd_fis
[2])) {
1211 process_ncq_command(s
, port
, cmd_fis
, slot
);
1215 /* Decompose the FIS:
1216 * AHCI does not interpret FIS packets, it only forwards them.
1217 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1218 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1220 * ATA4 describes sector number for LBA28/CHS commands.
1221 * ATA6 describes sector number for LBA48 commands.
1222 * ATA8 deprecates CHS fully, describing only LBA28/48.
1224 * We dutifully convert the FIS into IDE registers, and allow the
1225 * core layer to interpret them as needed. */
1226 ide_state
->feature
= cmd_fis
[3];
1227 ide_state
->sector
= cmd_fis
[4]; /* LBA 7:0 */
1228 ide_state
->lcyl
= cmd_fis
[5]; /* LBA 15:8 */
1229 ide_state
->hcyl
= cmd_fis
[6]; /* LBA 23:16 */
1230 ide_state
->select
= cmd_fis
[7]; /* LBA 27:24 (LBA28) */
1231 ide_state
->hob_sector
= cmd_fis
[8]; /* LBA 31:24 */
1232 ide_state
->hob_lcyl
= cmd_fis
[9]; /* LBA 39:32 */
1233 ide_state
->hob_hcyl
= cmd_fis
[10]; /* LBA 47:40 */
1234 ide_state
->hob_feature
= cmd_fis
[11];
1235 ide_state
->nsector
= (int64_t)((cmd_fis
[13] << 8) | cmd_fis
[12]);
1236 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1237 /* 15: Only valid when UPDATE_COMMAND not set. */
1239 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1240 * table to ide_state->io_buffer */
1241 if (opts
& AHCI_CMD_ATAPI
) {
1242 memcpy(ide_state
->io_buffer
, &cmd_fis
[AHCI_COMMAND_TABLE_ACMD
], 0x10);
1243 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP
)) {
1244 char *pretty_fis
= ahci_pretty_buffer_fis(ide_state
->io_buffer
, 0x10);
1245 trace_handle_reg_h2d_fis_dump(s
, port
, pretty_fis
);
1248 s
->dev
[port
].done_atapi_packet
= false;
1249 /* XXX send PIO setup FIS */
1252 ide_state
->error
= 0;
1254 /* Reset transferred byte counter */
1257 /* We're ready to process the command in FIS byte 2. */
1258 ide_exec_cmd(&s
->dev
[port
].port
, cmd_fis
[2]);
1261 static int handle_cmd(AHCIState
*s
, int port
, uint8_t slot
)
1263 IDEState
*ide_state
;
1269 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1270 /* Engine currently busy, try again later */
1271 trace_handle_cmd_busy(s
, port
);
1275 if (!s
->dev
[port
].lst
) {
1276 trace_handle_cmd_nolist(s
, port
);
1279 cmd
= get_cmd_header(s
, port
, slot
);
1280 /* remember current slot handle for later */
1281 s
->dev
[port
].cur_cmd
= cmd
;
1283 /* The device we are working for */
1284 ide_state
= &s
->dev
[port
].port
.ifs
[0];
1285 if (!ide_state
->blk
) {
1286 trace_handle_cmd_badport(s
, port
);
1290 tbl_addr
= le64_to_cpu(cmd
->tbl_addr
);
1292 cmd_fis
= dma_memory_map(s
->as
, tbl_addr
, &cmd_len
,
1293 DMA_DIRECTION_FROM_DEVICE
);
1295 trace_handle_cmd_badfis(s
, port
);
1297 } else if (cmd_len
!= 0x80) {
1298 ahci_trigger_irq(s
, &s
->dev
[port
], AHCI_PORT_IRQ_BIT_HBFS
);
1299 trace_handle_cmd_badmap(s
, port
, cmd_len
);
1302 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP
)) {
1303 char *pretty_fis
= ahci_pretty_buffer_fis(cmd_fis
, 0x80);
1304 trace_handle_cmd_fis_dump(s
, port
, pretty_fis
);
1307 switch (cmd_fis
[0]) {
1308 case SATA_FIS_TYPE_REGISTER_H2D
:
1309 handle_reg_h2d_fis(s
, port
, slot
, cmd_fis
);
1312 trace_handle_cmd_unhandled_fis(s
, port
,
1313 cmd_fis
[0], cmd_fis
[1], cmd_fis
[2]);
1318 dma_memory_unmap(s
->as
, cmd_fis
, cmd_len
, DMA_DIRECTION_FROM_DEVICE
,
1321 if (s
->dev
[port
].port
.ifs
[0].status
& (BUSY_STAT
|DRQ_STAT
)) {
1322 /* async command, complete later */
1323 s
->dev
[port
].busy_slot
= slot
;
1327 /* done handling the command */
1331 /* DMA dev <-> ram */
1332 static void ahci_start_transfer(IDEDMA
*dma
)
1334 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1335 IDEState
*s
= &ad
->port
.ifs
[0];
1336 uint32_t size
= (uint32_t)(s
->data_end
- s
->data_ptr
);
1337 /* write == ram -> device */
1338 uint16_t opts
= le16_to_cpu(ad
->cur_cmd
->opts
);
1339 int is_write
= opts
& AHCI_CMD_WRITE
;
1340 int is_atapi
= opts
& AHCI_CMD_ATAPI
;
1343 if (is_atapi
&& !ad
->done_atapi_packet
) {
1344 /* already prepopulated iobuffer */
1345 ad
->done_atapi_packet
= true;
1350 if (ahci_dma_prepare_buf(dma
, size
)) {
1354 trace_ahci_start_transfer(ad
->hba
, ad
->port_no
, is_write
? "writ" : "read",
1355 size
, is_atapi
? "atapi" : "ata",
1356 has_sglist
? "" : "o");
1358 if (has_sglist
&& size
) {
1360 dma_buf_write(s
->data_ptr
, size
, &s
->sg
);
1362 dma_buf_read(s
->data_ptr
, size
, &s
->sg
);
1367 /* declare that we processed everything */
1368 s
->data_ptr
= s
->data_end
;
1370 /* Update number of transferred bytes, destroy sglist */
1371 dma_buf_commit(s
, size
);
1373 s
->end_transfer_func(s
);
1375 if (!(s
->status
& DRQ_STAT
)) {
1376 /* done with PIO send/receive */
1377 ahci_write_fis_pio(ad
, le32_to_cpu(ad
->cur_cmd
->status
));
1381 static void ahci_start_dma(IDEDMA
*dma
, IDEState
*s
,
1382 BlockCompletionFunc
*dma_cb
)
1384 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1385 trace_ahci_start_dma(ad
->hba
, ad
->port_no
);
1386 s
->io_buffer_offset
= 0;
1390 static void ahci_restart_dma(IDEDMA
*dma
)
1392 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1396 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1397 * need an extra kick from the AHCI HBA.
1399 static void ahci_restart(IDEDMA
*dma
)
1401 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1404 for (i
= 0; i
< AHCI_MAX_CMDS
; i
++) {
1405 NCQTransferState
*ncq_tfs
= &ad
->ncq_tfs
[i
];
1406 if (ncq_tfs
->halt
) {
1407 execute_ncq_command(ncq_tfs
);
1413 * Called in DMA and PIO R/W chains to read the PRDT.
1414 * Not shared with NCQ pathways.
1416 static int32_t ahci_dma_prepare_buf(IDEDMA
*dma
, int32_t limit
)
1418 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1419 IDEState
*s
= &ad
->port
.ifs
[0];
1421 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
,
1422 limit
, s
->io_buffer_offset
) == -1) {
1423 trace_ahci_dma_prepare_buf_fail(ad
->hba
, ad
->port_no
);
1426 s
->io_buffer_size
= s
->sg
.size
;
1428 trace_ahci_dma_prepare_buf(ad
->hba
, ad
->port_no
, limit
, s
->io_buffer_size
);
1429 return s
->io_buffer_size
;
1433 * Updates the command header with a bytes-read value.
1434 * Called via dma_buf_commit, for both DMA and PIO paths.
1435 * sglist destruction is handled within dma_buf_commit.
1437 static void ahci_commit_buf(IDEDMA
*dma
, uint32_t tx_bytes
)
1439 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1441 tx_bytes
+= le32_to_cpu(ad
->cur_cmd
->status
);
1442 ad
->cur_cmd
->status
= cpu_to_le32(tx_bytes
);
1445 static int ahci_dma_rw_buf(IDEDMA
*dma
, int is_write
)
1447 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1448 IDEState
*s
= &ad
->port
.ifs
[0];
1449 uint8_t *p
= s
->io_buffer
+ s
->io_buffer_index
;
1450 int l
= s
->io_buffer_size
- s
->io_buffer_index
;
1452 if (ahci_populate_sglist(ad
, &s
->sg
, ad
->cur_cmd
, l
, s
->io_buffer_offset
)) {
1457 dma_buf_read(p
, l
, &s
->sg
);
1459 dma_buf_write(p
, l
, &s
->sg
);
1462 /* free sglist, update byte count */
1463 dma_buf_commit(s
, l
);
1464 s
->io_buffer_index
+= l
;
1466 trace_ahci_dma_rw_buf(ad
->hba
, ad
->port_no
, l
);
1470 static void ahci_cmd_done(IDEDMA
*dma
)
1472 AHCIDevice
*ad
= DO_UPCAST(AHCIDevice
, dma
, dma
);
1474 trace_ahci_cmd_done(ad
->hba
, ad
->port_no
);
1476 /* no longer busy */
1477 if (ad
->busy_slot
!= -1) {
1478 ad
->port_regs
.cmd_issue
&= ~(1 << ad
->busy_slot
);
1482 /* update d2h status */
1483 ahci_write_fis_d2h(ad
);
1485 if (ad
->port_regs
.cmd_issue
&& !ad
->check_bh
) {
1486 ad
->check_bh
= qemu_bh_new(ahci_check_cmd_bh
, ad
);
1487 qemu_bh_schedule(ad
->check_bh
);
1491 static void ahci_irq_set(void *opaque
, int n
, int level
)
1495 static const IDEDMAOps ahci_dma_ops
= {
1496 .start_dma
= ahci_start_dma
,
1497 .restart
= ahci_restart
,
1498 .restart_dma
= ahci_restart_dma
,
1499 .start_transfer
= ahci_start_transfer
,
1500 .prepare_buf
= ahci_dma_prepare_buf
,
1501 .commit_buf
= ahci_commit_buf
,
1502 .rw_buf
= ahci_dma_rw_buf
,
1503 .cmd_done
= ahci_cmd_done
,
1506 void ahci_init(AHCIState
*s
, DeviceState
*qdev
)
1508 s
->container
= qdev
;
1509 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1510 memory_region_init_io(&s
->mem
, OBJECT(qdev
), &ahci_mem_ops
, s
,
1511 "ahci", AHCI_MEM_BAR_SIZE
);
1512 memory_region_init_io(&s
->idp
, OBJECT(qdev
), &ahci_idp_ops
, s
,
1516 void ahci_realize(AHCIState
*s
, DeviceState
*qdev
, AddressSpace
*as
, int ports
)
1523 s
->dev
= g_new0(AHCIDevice
, ports
);
1525 irqs
= qemu_allocate_irqs(ahci_irq_set
, s
, s
->ports
);
1526 for (i
= 0; i
< s
->ports
; i
++) {
1527 AHCIDevice
*ad
= &s
->dev
[i
];
1529 ide_bus_new(&ad
->port
, sizeof(ad
->port
), qdev
, i
, 1);
1530 ide_init2(&ad
->port
, irqs
[i
]);
1534 ad
->port
.dma
= &ad
->dma
;
1535 ad
->port
.dma
->ops
= &ahci_dma_ops
;
1536 ide_register_restart_cb(&ad
->port
);
1541 void ahci_uninit(AHCIState
*s
)
1545 for (i
= 0; i
< s
->ports
; i
++) {
1546 AHCIDevice
*ad
= &s
->dev
[i
];
1548 for (j
= 0; j
< 2; j
++) {
1549 IDEState
*s
= &ad
->port
.ifs
[j
];
1553 object_unparent(OBJECT(&ad
->port
));
1559 void ahci_reset(AHCIState
*s
)
1564 trace_ahci_reset(s
);
1566 s
->control_regs
.irqstatus
= 0;
1568 * The implementation of this bit is dependent upon the value of the
1569 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1570 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1571 * read-only and shall have a reset value of '1'.
1573 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1575 s
->control_regs
.ghc
= HOST_CTL_AHCI_EN
;
1577 for (i
= 0; i
< s
->ports
; i
++) {
1578 pr
= &s
->dev
[i
].port_regs
;
1582 pr
->cmd
= PORT_CMD_SPIN_UP
| PORT_CMD_POWER_ON
;
1583 ahci_reset_port(s
, i
);
1587 static const VMStateDescription vmstate_ncq_tfs
= {
1588 .name
= "ncq state",
1590 .fields
= (VMStateField
[]) {
1591 VMSTATE_UINT32(sector_count
, NCQTransferState
),
1592 VMSTATE_UINT64(lba
, NCQTransferState
),
1593 VMSTATE_UINT8(tag
, NCQTransferState
),
1594 VMSTATE_UINT8(cmd
, NCQTransferState
),
1595 VMSTATE_UINT8(slot
, NCQTransferState
),
1596 VMSTATE_BOOL(used
, NCQTransferState
),
1597 VMSTATE_BOOL(halt
, NCQTransferState
),
1598 VMSTATE_END_OF_LIST()
1602 static const VMStateDescription vmstate_ahci_device
= {
1603 .name
= "ahci port",
1605 .fields
= (VMStateField
[]) {
1606 VMSTATE_IDE_BUS(port
, AHCIDevice
),
1607 VMSTATE_IDE_DRIVE(port
.ifs
[0], AHCIDevice
),
1608 VMSTATE_UINT32(port_state
, AHCIDevice
),
1609 VMSTATE_UINT32(finished
, AHCIDevice
),
1610 VMSTATE_UINT32(port_regs
.lst_addr
, AHCIDevice
),
1611 VMSTATE_UINT32(port_regs
.lst_addr_hi
, AHCIDevice
),
1612 VMSTATE_UINT32(port_regs
.fis_addr
, AHCIDevice
),
1613 VMSTATE_UINT32(port_regs
.fis_addr_hi
, AHCIDevice
),
1614 VMSTATE_UINT32(port_regs
.irq_stat
, AHCIDevice
),
1615 VMSTATE_UINT32(port_regs
.irq_mask
, AHCIDevice
),
1616 VMSTATE_UINT32(port_regs
.cmd
, AHCIDevice
),
1617 VMSTATE_UINT32(port_regs
.tfdata
, AHCIDevice
),
1618 VMSTATE_UINT32(port_regs
.sig
, AHCIDevice
),
1619 VMSTATE_UINT32(port_regs
.scr_stat
, AHCIDevice
),
1620 VMSTATE_UINT32(port_regs
.scr_ctl
, AHCIDevice
),
1621 VMSTATE_UINT32(port_regs
.scr_err
, AHCIDevice
),
1622 VMSTATE_UINT32(port_regs
.scr_act
, AHCIDevice
),
1623 VMSTATE_UINT32(port_regs
.cmd_issue
, AHCIDevice
),
1624 VMSTATE_BOOL(done_atapi_packet
, AHCIDevice
),
1625 VMSTATE_INT32(busy_slot
, AHCIDevice
),
1626 VMSTATE_BOOL(init_d2h_sent
, AHCIDevice
),
1627 VMSTATE_STRUCT_ARRAY(ncq_tfs
, AHCIDevice
, AHCI_MAX_CMDS
,
1628 1, vmstate_ncq_tfs
, NCQTransferState
),
1629 VMSTATE_END_OF_LIST()
1633 static int ahci_state_post_load(void *opaque
, int version_id
)
1636 struct AHCIDevice
*ad
;
1637 NCQTransferState
*ncq_tfs
;
1639 AHCIState
*s
= opaque
;
1641 for (i
= 0; i
< s
->ports
; i
++) {
1643 pr
= &ad
->port_regs
;
1645 if (!(pr
->cmd
& PORT_CMD_START
) && (pr
->cmd
& PORT_CMD_LIST_ON
)) {
1646 error_report("AHCI: DMA engine should be off, but status bit "
1647 "indicates it is still running.");
1650 if (!(pr
->cmd
& PORT_CMD_FIS_RX
) && (pr
->cmd
& PORT_CMD_FIS_ON
)) {
1651 error_report("AHCI: FIS RX engine should be off, but status bit "
1652 "indicates it is still running.");
1656 /* After a migrate, the DMA/FIS engines are "off" and
1657 * need to be conditionally restarted */
1658 pr
->cmd
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
);
1659 if (ahci_cond_start_engines(ad
) != 0) {
1663 for (j
= 0; j
< AHCI_MAX_CMDS
; j
++) {
1664 ncq_tfs
= &ad
->ncq_tfs
[j
];
1665 ncq_tfs
->drive
= ad
;
1667 if (ncq_tfs
->used
!= ncq_tfs
->halt
) {
1670 if (!ncq_tfs
->halt
) {
1673 if (!is_ncq(ncq_tfs
->cmd
)) {
1676 if (ncq_tfs
->slot
!= ncq_tfs
->tag
) {
1679 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1680 * and the command list buffer should be mapped. */
1681 ncq_tfs
->cmdh
= get_cmd_header(s
, i
, ncq_tfs
->slot
);
1682 if (!ncq_tfs
->cmdh
) {
1685 ahci_populate_sglist(ncq_tfs
->drive
, &ncq_tfs
->sglist
,
1686 ncq_tfs
->cmdh
, ncq_tfs
->sector_count
* 512,
1688 if (ncq_tfs
->sector_count
!= ncq_tfs
->sglist
.size
>> 9) {
1695 * If an error is present, ad->busy_slot will be valid and not -1.
1696 * In this case, an operation is waiting to resume and will re-check
1697 * for additional AHCI commands to execute upon completion.
1699 * In the case where no error was present, busy_slot will be -1,
1700 * and we should check to see if there are additional commands waiting.
1702 if (ad
->busy_slot
== -1) {
1705 /* We are in the middle of a command, and may need to access
1706 * the command header in guest memory again. */
1707 if (ad
->busy_slot
< 0 || ad
->busy_slot
>= AHCI_MAX_CMDS
) {
1710 ad
->cur_cmd
= get_cmd_header(s
, i
, ad
->busy_slot
);
1717 const VMStateDescription vmstate_ahci
= {
1720 .post_load
= ahci_state_post_load
,
1721 .fields
= (VMStateField
[]) {
1722 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev
, AHCIState
, ports
,
1723 vmstate_ahci_device
, AHCIDevice
),
1724 VMSTATE_UINT32(control_regs
.cap
, AHCIState
),
1725 VMSTATE_UINT32(control_regs
.ghc
, AHCIState
),
1726 VMSTATE_UINT32(control_regs
.irqstatus
, AHCIState
),
1727 VMSTATE_UINT32(control_regs
.impl
, AHCIState
),
1728 VMSTATE_UINT32(control_regs
.version
, AHCIState
),
1729 VMSTATE_UINT32(idp_index
, AHCIState
),
1730 VMSTATE_INT32_EQUAL(ports
, AHCIState
, NULL
),
1731 VMSTATE_END_OF_LIST()
1735 static const VMStateDescription vmstate_sysbus_ahci
= {
1736 .name
= "sysbus-ahci",
1737 .fields
= (VMStateField
[]) {
1738 VMSTATE_AHCI(ahci
, SysbusAHCIState
),
1739 VMSTATE_END_OF_LIST()
1743 static void sysbus_ahci_reset(DeviceState
*dev
)
1745 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1747 ahci_reset(&s
->ahci
);
1750 static void sysbus_ahci_init(Object
*obj
)
1752 SysbusAHCIState
*s
= SYSBUS_AHCI(obj
);
1753 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1755 ahci_init(&s
->ahci
, DEVICE(obj
));
1757 sysbus_init_mmio(sbd
, &s
->ahci
.mem
);
1758 sysbus_init_irq(sbd
, &s
->ahci
.irq
);
1761 static void sysbus_ahci_realize(DeviceState
*dev
, Error
**errp
)
1763 SysbusAHCIState
*s
= SYSBUS_AHCI(dev
);
1765 ahci_realize(&s
->ahci
, dev
, &address_space_memory
, s
->num_ports
);
1768 static Property sysbus_ahci_properties
[] = {
1769 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState
, num_ports
, 1),
1770 DEFINE_PROP_END_OF_LIST(),
1773 static void sysbus_ahci_class_init(ObjectClass
*klass
, void *data
)
1775 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1777 dc
->realize
= sysbus_ahci_realize
;
1778 dc
->vmsd
= &vmstate_sysbus_ahci
;
1779 dc
->props
= sysbus_ahci_properties
;
1780 dc
->reset
= sysbus_ahci_reset
;
1781 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1784 static const TypeInfo sysbus_ahci_info
= {
1785 .name
= TYPE_SYSBUS_AHCI
,
1786 .parent
= TYPE_SYS_BUS_DEVICE
,
1787 .instance_size
= sizeof(SysbusAHCIState
),
1788 .instance_init
= sysbus_ahci_init
,
1789 .class_init
= sysbus_ahci_class_init
,
1792 static void sysbus_ahci_register_types(void)
1794 type_register_static(&sysbus_ahci_info
);
1797 type_init(sysbus_ahci_register_types
)
1799 int32_t ahci_get_num_ports(PCIDevice
*dev
)
1801 AHCIPCIState
*d
= ICH_AHCI(dev
);
1802 AHCIState
*ahci
= &d
->ahci
;
1807 void ahci_ide_create_devs(PCIDevice
*dev
, DriveInfo
**hd
)
1809 AHCIPCIState
*d
= ICH_AHCI(dev
);
1810 AHCIState
*ahci
= &d
->ahci
;
1813 for (i
= 0; i
< ahci
->ports
; i
++) {
1814 if (hd
[i
] == NULL
) {
1817 ide_create_drive(&ahci
->dev
[i
].port
, 0, hd
[i
]);