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[qemu/ar7.git] / target / arm / cpu.c
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1 /*
2 * QEMU ARM CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "target/arm/idau.h"
23 #include "qapi/error.h"
24 #include "qapi/visitor.h"
25 #include "cpu.h"
26 #include "internals.h"
27 #include "qemu-common.h"
28 #include "exec/exec-all.h"
29 #include "hw/qdev-properties.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/loader.h"
32 #endif
33 #include "hw/arm/arm.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/hw_accel.h"
36 #include "kvm_arm.h"
37 #include "disas/capstone.h"
38 #include "fpu/softfloat.h"
40 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
42 ARMCPU *cpu = ARM_CPU(cs);
43 CPUARMState *env = &cpu->env;
45 if (is_a64(env)) {
46 env->pc = value;
47 env->thumb = 0;
48 } else {
49 env->regs[15] = value & ~1;
50 env->thumb = value & 1;
54 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
56 ARMCPU *cpu = ARM_CPU(cs);
57 CPUARMState *env = &cpu->env;
60 * It's OK to look at env for the current mode here, because it's
61 * never possible for an AArch64 TB to chain to an AArch32 TB.
63 if (is_a64(env)) {
64 env->pc = tb->pc;
65 } else {
66 env->regs[15] = tb->pc;
70 static bool arm_cpu_has_work(CPUState *cs)
72 ARMCPU *cpu = ARM_CPU(cs);
74 return (cpu->power_state != PSCI_OFF)
75 && cs->interrupt_request &
76 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
77 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
78 | CPU_INTERRUPT_EXITTB);
81 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
82 void *opaque)
84 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
86 entry->hook = hook;
87 entry->opaque = opaque;
89 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
92 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
93 void *opaque)
95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
97 entry->hook = hook;
98 entry->opaque = opaque;
100 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
103 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
105 /* Reset a single ARMCPRegInfo register */
106 ARMCPRegInfo *ri = value;
107 ARMCPU *cpu = opaque;
109 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
110 return;
113 if (ri->resetfn) {
114 ri->resetfn(&cpu->env, ri);
115 return;
118 /* A zero offset is never possible as it would be regs[0]
119 * so we use it to indicate that reset is being handled elsewhere.
120 * This is basically only used for fields in non-core coprocessors
121 * (like the pxa2xx ones).
123 if (!ri->fieldoffset) {
124 return;
127 if (cpreg_field_is_64bit(ri)) {
128 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
129 } else {
130 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
134 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
136 /* Purely an assertion check: we've already done reset once,
137 * so now check that running the reset for the cpreg doesn't
138 * change its value. This traps bugs where two different cpregs
139 * both try to reset the same state field but to different values.
141 ARMCPRegInfo *ri = value;
142 ARMCPU *cpu = opaque;
143 uint64_t oldvalue, newvalue;
145 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
146 return;
149 oldvalue = read_raw_cp_reg(&cpu->env, ri);
150 cp_reg_reset(key, value, opaque);
151 newvalue = read_raw_cp_reg(&cpu->env, ri);
152 assert(oldvalue == newvalue);
155 /* CPUClass::reset() */
156 static void arm_cpu_reset(CPUState *s)
158 ARMCPU *cpu = ARM_CPU(s);
159 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
160 CPUARMState *env = &cpu->env;
162 acc->parent_reset(s);
164 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
166 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
167 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
169 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
170 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
171 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
172 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
174 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
175 s->halted = cpu->start_powered_off;
177 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
178 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
181 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
182 /* 64 bit CPUs always start in 64 bit mode */
183 env->aarch64 = 1;
184 #if defined(CONFIG_USER_ONLY)
185 env->pstate = PSTATE_MODE_EL0t;
186 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
187 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
188 /* Enable all PAC keys. */
189 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
190 SCTLR_EnDA | SCTLR_EnDB);
191 /* Enable all PAC instructions */
192 env->cp15.hcr_el2 |= HCR_API;
193 env->cp15.scr_el3 |= SCR_API;
194 /* and to the FP/Neon instructions */
195 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
196 /* and to the SVE instructions */
197 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
198 env->cp15.cptr_el[3] |= CPTR_EZ;
199 /* with maximum vector length */
200 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
201 env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
202 env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
204 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
205 * turning on both here will produce smaller code and otherwise
206 * make no difference to the user-level emulation.
208 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
209 #else
210 /* Reset into the highest available EL */
211 if (arm_feature(env, ARM_FEATURE_EL3)) {
212 env->pstate = PSTATE_MODE_EL3h;
213 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
214 env->pstate = PSTATE_MODE_EL2h;
215 } else {
216 env->pstate = PSTATE_MODE_EL1h;
218 env->pc = cpu->rvbar;
219 #endif
220 } else {
221 #if defined(CONFIG_USER_ONLY)
222 /* Userspace expects access to cp10 and cp11 for FP/Neon */
223 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
224 #endif
227 #if defined(CONFIG_USER_ONLY)
228 env->uncached_cpsr = ARM_CPU_MODE_USR;
229 /* For user mode we must enable access to coprocessors */
230 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
231 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
232 env->cp15.c15_cpar = 3;
233 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
234 env->cp15.c15_cpar = 1;
236 #else
239 * If the highest available EL is EL2, AArch32 will start in Hyp
240 * mode; otherwise it starts in SVC. Note that if we start in
241 * AArch64 then these values in the uncached_cpsr will be ignored.
243 if (arm_feature(env, ARM_FEATURE_EL2) &&
244 !arm_feature(env, ARM_FEATURE_EL3)) {
245 env->uncached_cpsr = ARM_CPU_MODE_HYP;
246 } else {
247 env->uncached_cpsr = ARM_CPU_MODE_SVC;
249 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
251 if (arm_feature(env, ARM_FEATURE_M)) {
252 uint32_t initial_msp; /* Loaded from 0x0 */
253 uint32_t initial_pc; /* Loaded from 0x4 */
254 uint8_t *rom;
255 uint32_t vecbase;
257 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
258 env->v7m.secure = true;
259 } else {
260 /* This bit resets to 0 if security is supported, but 1 if
261 * it is not. The bit is not present in v7M, but we set it
262 * here so we can avoid having to make checks on it conditional
263 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
265 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
268 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
269 * that it resets to 1, so QEMU always does that rather than making
270 * it dependent on CPU model. In v8M it is RES1.
272 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
273 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
274 if (arm_feature(env, ARM_FEATURE_V8)) {
275 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
276 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
277 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
279 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
280 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
281 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
284 if (arm_feature(env, ARM_FEATURE_VFP)) {
285 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
286 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
287 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
289 /* Unlike A/R profile, M profile defines the reset LR value */
290 env->regs[14] = 0xffffffff;
292 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
294 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
295 vecbase = env->v7m.vecbase[env->v7m.secure];
296 rom = rom_ptr(vecbase, 8);
297 if (rom) {
298 /* Address zero is covered by ROM which hasn't yet been
299 * copied into physical memory.
301 initial_msp = ldl_p(rom);
302 initial_pc = ldl_p(rom + 4);
303 } else {
304 /* Address zero not covered by a ROM blob, or the ROM blob
305 * is in non-modifiable memory and this is a second reset after
306 * it got copied into memory. In the latter case, rom_ptr
307 * will return a NULL pointer and we should use ldl_phys instead.
309 initial_msp = ldl_phys(s->as, vecbase);
310 initial_pc = ldl_phys(s->as, vecbase + 4);
313 env->regs[13] = initial_msp & 0xFFFFFFFC;
314 env->regs[15] = initial_pc & ~1;
315 env->thumb = initial_pc & 1;
318 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
319 * executing as AArch32 then check if highvecs are enabled and
320 * adjust the PC accordingly.
322 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
323 env->regs[15] = 0xFFFF0000;
326 /* M profile requires that reset clears the exclusive monitor;
327 * A profile does not, but clearing it makes more sense than having it
328 * set with an exclusive access on address zero.
330 arm_clear_exclusive(env);
332 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
333 #endif
335 if (arm_feature(env, ARM_FEATURE_PMSA)) {
336 if (cpu->pmsav7_dregion > 0) {
337 if (arm_feature(env, ARM_FEATURE_V8)) {
338 memset(env->pmsav8.rbar[M_REG_NS], 0,
339 sizeof(*env->pmsav8.rbar[M_REG_NS])
340 * cpu->pmsav7_dregion);
341 memset(env->pmsav8.rlar[M_REG_NS], 0,
342 sizeof(*env->pmsav8.rlar[M_REG_NS])
343 * cpu->pmsav7_dregion);
344 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
345 memset(env->pmsav8.rbar[M_REG_S], 0,
346 sizeof(*env->pmsav8.rbar[M_REG_S])
347 * cpu->pmsav7_dregion);
348 memset(env->pmsav8.rlar[M_REG_S], 0,
349 sizeof(*env->pmsav8.rlar[M_REG_S])
350 * cpu->pmsav7_dregion);
352 } else if (arm_feature(env, ARM_FEATURE_V7)) {
353 memset(env->pmsav7.drbar, 0,
354 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
355 memset(env->pmsav7.drsr, 0,
356 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
357 memset(env->pmsav7.dracr, 0,
358 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
361 env->pmsav7.rnr[M_REG_NS] = 0;
362 env->pmsav7.rnr[M_REG_S] = 0;
363 env->pmsav8.mair0[M_REG_NS] = 0;
364 env->pmsav8.mair0[M_REG_S] = 0;
365 env->pmsav8.mair1[M_REG_NS] = 0;
366 env->pmsav8.mair1[M_REG_S] = 0;
369 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
370 if (cpu->sau_sregion > 0) {
371 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
372 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
374 env->sau.rnr = 0;
375 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
376 * the Cortex-M33 does.
378 env->sau.ctrl = 0;
381 set_flush_to_zero(1, &env->vfp.standard_fp_status);
382 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
383 set_default_nan_mode(1, &env->vfp.standard_fp_status);
384 set_float_detect_tininess(float_tininess_before_rounding,
385 &env->vfp.fp_status);
386 set_float_detect_tininess(float_tininess_before_rounding,
387 &env->vfp.standard_fp_status);
388 set_float_detect_tininess(float_tininess_before_rounding,
389 &env->vfp.fp_status_f16);
390 #ifndef CONFIG_USER_ONLY
391 if (kvm_enabled()) {
392 kvm_arm_reset_vcpu(cpu);
394 #endif
396 hw_breakpoint_update_all(cpu);
397 hw_watchpoint_update_all(cpu);
400 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
402 CPUClass *cc = CPU_GET_CLASS(cs);
403 CPUARMState *env = cs->env_ptr;
404 uint32_t cur_el = arm_current_el(env);
405 bool secure = arm_is_secure(env);
406 uint32_t target_el;
407 uint32_t excp_idx;
408 bool ret = false;
410 if (interrupt_request & CPU_INTERRUPT_FIQ) {
411 excp_idx = EXCP_FIQ;
412 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
413 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
414 cs->exception_index = excp_idx;
415 env->exception.target_el = target_el;
416 cc->do_interrupt(cs);
417 ret = true;
420 if (interrupt_request & CPU_INTERRUPT_HARD) {
421 excp_idx = EXCP_IRQ;
422 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
423 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
424 cs->exception_index = excp_idx;
425 env->exception.target_el = target_el;
426 cc->do_interrupt(cs);
427 ret = true;
430 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
431 excp_idx = EXCP_VIRQ;
432 target_el = 1;
433 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
434 cs->exception_index = excp_idx;
435 env->exception.target_el = target_el;
436 cc->do_interrupt(cs);
437 ret = true;
440 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
441 excp_idx = EXCP_VFIQ;
442 target_el = 1;
443 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
444 cs->exception_index = excp_idx;
445 env->exception.target_el = target_el;
446 cc->do_interrupt(cs);
447 ret = true;
451 return ret;
454 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
455 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
457 CPUClass *cc = CPU_GET_CLASS(cs);
458 ARMCPU *cpu = ARM_CPU(cs);
459 CPUARMState *env = &cpu->env;
460 bool ret = false;
462 /* ARMv7-M interrupt masking works differently than -A or -R.
463 * There is no FIQ/IRQ distinction. Instead of I and F bits
464 * masking FIQ and IRQ interrupts, an exception is taken only
465 * if it is higher priority than the current execution priority
466 * (which depends on state like BASEPRI, FAULTMASK and the
467 * currently active exception).
469 if (interrupt_request & CPU_INTERRUPT_HARD
470 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
471 cs->exception_index = EXCP_IRQ;
472 cc->do_interrupt(cs);
473 ret = true;
475 return ret;
477 #endif
479 void arm_cpu_update_virq(ARMCPU *cpu)
482 * Update the interrupt level for VIRQ, which is the logical OR of
483 * the HCR_EL2.VI bit and the input line level from the GIC.
485 CPUARMState *env = &cpu->env;
486 CPUState *cs = CPU(cpu);
488 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
489 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
491 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
492 if (new_state) {
493 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
494 } else {
495 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
500 void arm_cpu_update_vfiq(ARMCPU *cpu)
503 * Update the interrupt level for VFIQ, which is the logical OR of
504 * the HCR_EL2.VF bit and the input line level from the GIC.
506 CPUARMState *env = &cpu->env;
507 CPUState *cs = CPU(cpu);
509 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
510 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
512 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
513 if (new_state) {
514 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
515 } else {
516 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
521 #ifndef CONFIG_USER_ONLY
522 static void arm_cpu_set_irq(void *opaque, int irq, int level)
524 ARMCPU *cpu = opaque;
525 CPUARMState *env = &cpu->env;
526 CPUState *cs = CPU(cpu);
527 static const int mask[] = {
528 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
529 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
530 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
531 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
534 if (level) {
535 env->irq_line_state |= mask[irq];
536 } else {
537 env->irq_line_state &= ~mask[irq];
540 switch (irq) {
541 case ARM_CPU_VIRQ:
542 assert(arm_feature(env, ARM_FEATURE_EL2));
543 arm_cpu_update_virq(cpu);
544 break;
545 case ARM_CPU_VFIQ:
546 assert(arm_feature(env, ARM_FEATURE_EL2));
547 arm_cpu_update_vfiq(cpu);
548 break;
549 case ARM_CPU_IRQ:
550 case ARM_CPU_FIQ:
551 if (level) {
552 cpu_interrupt(cs, mask[irq]);
553 } else {
554 cpu_reset_interrupt(cs, mask[irq]);
556 break;
557 default:
558 g_assert_not_reached();
562 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
564 #ifdef CONFIG_KVM
565 ARMCPU *cpu = opaque;
566 CPUARMState *env = &cpu->env;
567 CPUState *cs = CPU(cpu);
568 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
569 uint32_t linestate_bit;
571 switch (irq) {
572 case ARM_CPU_IRQ:
573 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
574 linestate_bit = CPU_INTERRUPT_HARD;
575 break;
576 case ARM_CPU_FIQ:
577 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
578 linestate_bit = CPU_INTERRUPT_FIQ;
579 break;
580 default:
581 g_assert_not_reached();
584 if (level) {
585 env->irq_line_state |= linestate_bit;
586 } else {
587 env->irq_line_state &= ~linestate_bit;
590 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
591 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
592 #endif
595 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
597 ARMCPU *cpu = ARM_CPU(cs);
598 CPUARMState *env = &cpu->env;
600 cpu_synchronize_state(cs);
601 return arm_cpu_data_is_big_endian(env);
604 #endif
606 static inline void set_feature(CPUARMState *env, int feature)
608 env->features |= 1ULL << feature;
611 static inline void unset_feature(CPUARMState *env, int feature)
613 env->features &= ~(1ULL << feature);
616 static int
617 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
619 return print_insn_arm(pc | 1, info);
622 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
624 ARMCPU *ac = ARM_CPU(cpu);
625 CPUARMState *env = &ac->env;
626 bool sctlr_b;
628 if (is_a64(env)) {
629 /* We might not be compiled with the A64 disassembler
630 * because it needs a C++ compiler. Leave print_insn
631 * unset in this case to use the caller default behaviour.
633 #if defined(CONFIG_ARM_A64_DIS)
634 info->print_insn = print_insn_arm_a64;
635 #endif
636 info->cap_arch = CS_ARCH_ARM64;
637 info->cap_insn_unit = 4;
638 info->cap_insn_split = 4;
639 } else {
640 int cap_mode;
641 if (env->thumb) {
642 info->print_insn = print_insn_thumb1;
643 info->cap_insn_unit = 2;
644 info->cap_insn_split = 4;
645 cap_mode = CS_MODE_THUMB;
646 } else {
647 info->print_insn = print_insn_arm;
648 info->cap_insn_unit = 4;
649 info->cap_insn_split = 4;
650 cap_mode = CS_MODE_ARM;
652 if (arm_feature(env, ARM_FEATURE_V8)) {
653 cap_mode |= CS_MODE_V8;
655 if (arm_feature(env, ARM_FEATURE_M)) {
656 cap_mode |= CS_MODE_MCLASS;
658 info->cap_arch = CS_ARCH_ARM;
659 info->cap_mode = cap_mode;
662 sctlr_b = arm_sctlr_b(env);
663 if (bswap_code(sctlr_b)) {
664 #ifdef TARGET_WORDS_BIGENDIAN
665 info->endian = BFD_ENDIAN_LITTLE;
666 #else
667 info->endian = BFD_ENDIAN_BIG;
668 #endif
670 info->flags &= ~INSN_ARM_BE32;
671 #ifndef CONFIG_USER_ONLY
672 if (sctlr_b) {
673 info->flags |= INSN_ARM_BE32;
675 #endif
678 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
680 uint32_t Aff1 = idx / clustersz;
681 uint32_t Aff0 = idx % clustersz;
682 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
685 static void cpreg_hashtable_data_destroy(gpointer data)
688 * Destroy function for cpu->cp_regs hashtable data entries.
689 * We must free the name string because it was g_strdup()ed in
690 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
691 * from r->name because we know we definitely allocated it.
693 ARMCPRegInfo *r = data;
695 g_free((void *)r->name);
696 g_free(r);
699 static void arm_cpu_initfn(Object *obj)
701 CPUState *cs = CPU(obj);
702 ARMCPU *cpu = ARM_CPU(obj);
704 cs->env_ptr = &cpu->env;
705 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
706 g_free, cpreg_hashtable_data_destroy);
708 QLIST_INIT(&cpu->pre_el_change_hooks);
709 QLIST_INIT(&cpu->el_change_hooks);
711 #ifndef CONFIG_USER_ONLY
712 /* Our inbound IRQ and FIQ lines */
713 if (kvm_enabled()) {
714 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
715 * the same interface as non-KVM CPUs.
717 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
718 } else {
719 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
722 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
723 ARRAY_SIZE(cpu->gt_timer_outputs));
725 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
726 "gicv3-maintenance-interrupt", 1);
727 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
728 "pmu-interrupt", 1);
729 #endif
731 /* DTB consumers generally don't in fact care what the 'compatible'
732 * string is, so always provide some string and trust that a hypothetical
733 * picky DTB consumer will also provide a helpful error message.
735 cpu->dtb_compatible = "qemu,unknown";
736 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
737 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
739 if (tcg_enabled()) {
740 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
744 static Property arm_cpu_reset_cbar_property =
745 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
747 static Property arm_cpu_reset_hivecs_property =
748 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
750 static Property arm_cpu_rvbar_property =
751 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
753 static Property arm_cpu_has_el2_property =
754 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
756 static Property arm_cpu_has_el3_property =
757 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
759 static Property arm_cpu_cfgend_property =
760 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
762 /* use property name "pmu" to match other archs and virt tools */
763 static Property arm_cpu_has_pmu_property =
764 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
766 static Property arm_cpu_has_mpu_property =
767 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
769 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
770 * because the CPU initfn will have already set cpu->pmsav7_dregion to
771 * the right value for that particular CPU type, and we don't want
772 * to override that with an incorrect constant value.
774 static Property arm_cpu_pmsav7_dregion_property =
775 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
776 pmsav7_dregion,
777 qdev_prop_uint32, uint32_t);
779 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
780 void *opaque, Error **errp)
782 ARMCPU *cpu = ARM_CPU(obj);
784 visit_type_uint32(v, name, &cpu->init_svtor, errp);
787 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
788 void *opaque, Error **errp)
790 ARMCPU *cpu = ARM_CPU(obj);
792 visit_type_uint32(v, name, &cpu->init_svtor, errp);
795 void arm_cpu_post_init(Object *obj)
797 ARMCPU *cpu = ARM_CPU(obj);
799 /* M profile implies PMSA. We have to do this here rather than
800 * in realize with the other feature-implication checks because
801 * we look at the PMSA bit to see if we should add some properties.
803 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
804 set_feature(&cpu->env, ARM_FEATURE_PMSA);
807 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
808 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
809 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
810 &error_abort);
813 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
814 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
815 &error_abort);
818 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
819 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
820 &error_abort);
823 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
824 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
825 * prevent "has_el3" from existing on CPUs which cannot support EL3.
827 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
828 &error_abort);
830 #ifndef CONFIG_USER_ONLY
831 object_property_add_link(obj, "secure-memory",
832 TYPE_MEMORY_REGION,
833 (Object **)&cpu->secure_memory,
834 qdev_prop_allow_set_link_before_realize,
835 OBJ_PROP_LINK_STRONG,
836 &error_abort);
837 #endif
840 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
841 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
842 &error_abort);
845 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
846 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
847 &error_abort);
850 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
851 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
852 &error_abort);
853 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
854 qdev_property_add_static(DEVICE(obj),
855 &arm_cpu_pmsav7_dregion_property,
856 &error_abort);
860 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
861 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
862 qdev_prop_allow_set_link_before_realize,
863 OBJ_PROP_LINK_STRONG,
864 &error_abort);
866 * M profile: initial value of the Secure VTOR. We can't just use
867 * a simple DEFINE_PROP_UINT32 for this because we want to permit
868 * the property to be set after realize.
870 object_property_add(obj, "init-svtor", "uint32",
871 arm_get_init_svtor, arm_set_init_svtor,
872 NULL, NULL, &error_abort);
875 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
876 &error_abort);
879 static void arm_cpu_finalizefn(Object *obj)
881 ARMCPU *cpu = ARM_CPU(obj);
882 ARMELChangeHook *hook, *next;
884 g_hash_table_destroy(cpu->cp_regs);
886 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
887 QLIST_REMOVE(hook, node);
888 g_free(hook);
890 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
891 QLIST_REMOVE(hook, node);
892 g_free(hook);
894 #ifndef CONFIG_USER_ONLY
895 if (cpu->pmu_timer) {
896 timer_del(cpu->pmu_timer);
897 timer_deinit(cpu->pmu_timer);
898 timer_free(cpu->pmu_timer);
900 #endif
903 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
905 CPUState *cs = CPU(dev);
906 ARMCPU *cpu = ARM_CPU(dev);
907 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
908 CPUARMState *env = &cpu->env;
909 int pagebits;
910 Error *local_err = NULL;
911 bool no_aa32 = false;
913 /* If we needed to query the host kernel for the CPU features
914 * then it's possible that might have failed in the initfn, but
915 * this is the first point where we can report it.
917 if (cpu->host_cpu_probe_failed) {
918 if (!kvm_enabled()) {
919 error_setg(errp, "The 'host' CPU type can only be used with KVM");
920 } else {
921 error_setg(errp, "Failed to retrieve host CPU features");
923 return;
926 #ifndef CONFIG_USER_ONLY
927 /* The NVIC and M-profile CPU are two halves of a single piece of
928 * hardware; trying to use one without the other is a command line
929 * error and will result in segfaults if not caught here.
931 if (arm_feature(env, ARM_FEATURE_M)) {
932 if (!env->nvic) {
933 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
934 return;
936 } else {
937 if (env->nvic) {
938 error_setg(errp, "This board can only be used with Cortex-M CPUs");
939 return;
943 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
944 arm_gt_ptimer_cb, cpu);
945 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
946 arm_gt_vtimer_cb, cpu);
947 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
948 arm_gt_htimer_cb, cpu);
949 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
950 arm_gt_stimer_cb, cpu);
951 #endif
953 cpu_exec_realizefn(cs, &local_err);
954 if (local_err != NULL) {
955 error_propagate(errp, local_err);
956 return;
959 /* Some features automatically imply others: */
960 if (arm_feature(env, ARM_FEATURE_V8)) {
961 if (arm_feature(env, ARM_FEATURE_M)) {
962 set_feature(env, ARM_FEATURE_V7);
963 } else {
964 set_feature(env, ARM_FEATURE_V7VE);
969 * There exist AArch64 cpus without AArch32 support. When KVM
970 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
971 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
973 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
974 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
977 if (arm_feature(env, ARM_FEATURE_V7VE)) {
978 /* v7 Virtualization Extensions. In real hardware this implies
979 * EL2 and also the presence of the Security Extensions.
980 * For QEMU, for backwards-compatibility we implement some
981 * CPUs or CPU configs which have no actual EL2 or EL3 but do
982 * include the various other features that V7VE implies.
983 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
984 * Security Extensions is ARM_FEATURE_EL3.
986 assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
987 set_feature(env, ARM_FEATURE_LPAE);
988 set_feature(env, ARM_FEATURE_V7);
990 if (arm_feature(env, ARM_FEATURE_V7)) {
991 set_feature(env, ARM_FEATURE_VAPA);
992 set_feature(env, ARM_FEATURE_THUMB2);
993 set_feature(env, ARM_FEATURE_MPIDR);
994 if (!arm_feature(env, ARM_FEATURE_M)) {
995 set_feature(env, ARM_FEATURE_V6K);
996 } else {
997 set_feature(env, ARM_FEATURE_V6);
1000 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1001 * non-EL3 configs. This is needed by some legacy boards.
1003 set_feature(env, ARM_FEATURE_VBAR);
1005 if (arm_feature(env, ARM_FEATURE_V6K)) {
1006 set_feature(env, ARM_FEATURE_V6);
1007 set_feature(env, ARM_FEATURE_MVFR);
1009 if (arm_feature(env, ARM_FEATURE_V6)) {
1010 set_feature(env, ARM_FEATURE_V5);
1011 if (!arm_feature(env, ARM_FEATURE_M)) {
1012 assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
1013 set_feature(env, ARM_FEATURE_AUXCR);
1016 if (arm_feature(env, ARM_FEATURE_V5)) {
1017 set_feature(env, ARM_FEATURE_V4T);
1019 if (arm_feature(env, ARM_FEATURE_VFP4)) {
1020 set_feature(env, ARM_FEATURE_VFP3);
1022 if (arm_feature(env, ARM_FEATURE_VFP3)) {
1023 set_feature(env, ARM_FEATURE_VFP);
1025 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1026 set_feature(env, ARM_FEATURE_V7MP);
1027 set_feature(env, ARM_FEATURE_PXN);
1029 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1030 set_feature(env, ARM_FEATURE_CBAR);
1032 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1033 !arm_feature(env, ARM_FEATURE_M)) {
1034 set_feature(env, ARM_FEATURE_THUMB_DSP);
1038 * We rely on no XScale CPU having VFP so we can use the same bits in the
1039 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1041 assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
1042 arm_feature(env, ARM_FEATURE_XSCALE)));
1044 if (arm_feature(env, ARM_FEATURE_V7) &&
1045 !arm_feature(env, ARM_FEATURE_M) &&
1046 !arm_feature(env, ARM_FEATURE_PMSA)) {
1047 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1048 * can use 4K pages.
1050 pagebits = 12;
1051 } else {
1052 /* For CPUs which might have tiny 1K pages, or which have an
1053 * MPU and might have small region sizes, stick with 1K pages.
1055 pagebits = 10;
1057 if (!set_preferred_target_page_bits(pagebits)) {
1058 /* This can only ever happen for hotplugging a CPU, or if
1059 * the board code incorrectly creates a CPU which it has
1060 * promised via minimum_page_size that it will not.
1062 error_setg(errp, "This CPU requires a smaller page size than the "
1063 "system is using");
1064 return;
1067 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1068 * We don't support setting cluster ID ([16..23]) (known as Aff2
1069 * in later ARM ARM versions), or any of the higher affinity level fields,
1070 * so these bits always RAZ.
1072 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1073 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1074 ARM_DEFAULT_CPUS_PER_CLUSTER);
1077 if (cpu->reset_hivecs) {
1078 cpu->reset_sctlr |= (1 << 13);
1081 if (cpu->cfgend) {
1082 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1083 cpu->reset_sctlr |= SCTLR_EE;
1084 } else {
1085 cpu->reset_sctlr |= SCTLR_B;
1089 if (!cpu->has_el3) {
1090 /* If the has_el3 CPU property is disabled then we need to disable the
1091 * feature.
1093 unset_feature(env, ARM_FEATURE_EL3);
1095 /* Disable the security extension feature bits in the processor feature
1096 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1098 cpu->id_pfr1 &= ~0xf0;
1099 cpu->isar.id_aa64pfr0 &= ~0xf000;
1102 if (!cpu->has_el2) {
1103 unset_feature(env, ARM_FEATURE_EL2);
1106 if (!cpu->has_pmu) {
1107 unset_feature(env, ARM_FEATURE_PMU);
1109 if (arm_feature(env, ARM_FEATURE_PMU)) {
1110 pmu_init(cpu);
1112 if (!kvm_enabled()) {
1113 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1114 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1117 #ifndef CONFIG_USER_ONLY
1118 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1119 cpu);
1120 #endif
1121 } else {
1122 cpu->id_aa64dfr0 &= ~0xf00;
1123 cpu->id_dfr0 &= ~(0xf << 24);
1124 cpu->pmceid0 = 0;
1125 cpu->pmceid1 = 0;
1128 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1129 /* Disable the hypervisor feature bits in the processor feature
1130 * registers if we don't have EL2. These are id_pfr1[15:12] and
1131 * id_aa64pfr0_el1[11:8].
1133 cpu->isar.id_aa64pfr0 &= ~0xf00;
1134 cpu->id_pfr1 &= ~0xf000;
1137 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1138 * to false or by setting pmsav7-dregion to 0.
1140 if (!cpu->has_mpu) {
1141 cpu->pmsav7_dregion = 0;
1143 if (cpu->pmsav7_dregion == 0) {
1144 cpu->has_mpu = false;
1147 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1148 arm_feature(env, ARM_FEATURE_V7)) {
1149 uint32_t nr = cpu->pmsav7_dregion;
1151 if (nr > 0xff) {
1152 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1153 return;
1156 if (nr) {
1157 if (arm_feature(env, ARM_FEATURE_V8)) {
1158 /* PMSAv8 */
1159 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1160 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1161 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1162 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1163 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1165 } else {
1166 env->pmsav7.drbar = g_new0(uint32_t, nr);
1167 env->pmsav7.drsr = g_new0(uint32_t, nr);
1168 env->pmsav7.dracr = g_new0(uint32_t, nr);
1173 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1174 uint32_t nr = cpu->sau_sregion;
1176 if (nr > 0xff) {
1177 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1178 return;
1181 if (nr) {
1182 env->sau.rbar = g_new0(uint32_t, nr);
1183 env->sau.rlar = g_new0(uint32_t, nr);
1187 if (arm_feature(env, ARM_FEATURE_EL3)) {
1188 set_feature(env, ARM_FEATURE_VBAR);
1191 register_cp_regs_for_features(cpu);
1192 arm_cpu_register_gdb_regs_for_features(cpu);
1194 init_cpreg_list(cpu);
1196 #ifndef CONFIG_USER_ONLY
1197 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1198 cs->num_ases = 2;
1200 if (!cpu->secure_memory) {
1201 cpu->secure_memory = cs->memory;
1203 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1204 cpu->secure_memory);
1205 } else {
1206 cs->num_ases = 1;
1208 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1210 /* No core_count specified, default to smp_cpus. */
1211 if (cpu->core_count == -1) {
1212 cpu->core_count = smp_cpus;
1214 #endif
1216 qemu_init_vcpu(cs);
1217 cpu_reset(cs);
1219 acc->parent_realize(dev, errp);
1222 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1224 ObjectClass *oc;
1225 char *typename;
1226 char **cpuname;
1227 const char *cpunamestr;
1229 cpuname = g_strsplit(cpu_model, ",", 1);
1230 cpunamestr = cpuname[0];
1231 #ifdef CONFIG_USER_ONLY
1232 /* For backwards compatibility usermode emulation allows "-cpu any",
1233 * which has the same semantics as "-cpu max".
1235 if (!strcmp(cpunamestr, "any")) {
1236 cpunamestr = "max";
1238 #endif
1239 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1240 oc = object_class_by_name(typename);
1241 g_strfreev(cpuname);
1242 g_free(typename);
1243 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1244 object_class_is_abstract(oc)) {
1245 return NULL;
1247 return oc;
1250 /* CPU models. These are not needed for the AArch64 linux-user build. */
1251 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1253 static void arm926_initfn(Object *obj)
1255 ARMCPU *cpu = ARM_CPU(obj);
1257 cpu->dtb_compatible = "arm,arm926";
1258 set_feature(&cpu->env, ARM_FEATURE_V5);
1259 set_feature(&cpu->env, ARM_FEATURE_VFP);
1260 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1261 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1262 cpu->midr = 0x41069265;
1263 cpu->reset_fpsid = 0x41011090;
1264 cpu->ctr = 0x1dd20d2;
1265 cpu->reset_sctlr = 0x00090078;
1268 * ARMv5 does not have the ID_ISAR registers, but we can still
1269 * set the field to indicate Jazelle support within QEMU.
1271 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1274 static void arm946_initfn(Object *obj)
1276 ARMCPU *cpu = ARM_CPU(obj);
1278 cpu->dtb_compatible = "arm,arm946";
1279 set_feature(&cpu->env, ARM_FEATURE_V5);
1280 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1281 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1282 cpu->midr = 0x41059461;
1283 cpu->ctr = 0x0f004006;
1284 cpu->reset_sctlr = 0x00000078;
1287 static void arm1026_initfn(Object *obj)
1289 ARMCPU *cpu = ARM_CPU(obj);
1291 cpu->dtb_compatible = "arm,arm1026";
1292 set_feature(&cpu->env, ARM_FEATURE_V5);
1293 set_feature(&cpu->env, ARM_FEATURE_VFP);
1294 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1295 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1296 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1297 cpu->midr = 0x4106a262;
1298 cpu->reset_fpsid = 0x410110a0;
1299 cpu->ctr = 0x1dd20d2;
1300 cpu->reset_sctlr = 0x00090078;
1301 cpu->reset_auxcr = 1;
1304 * ARMv5 does not have the ID_ISAR registers, but we can still
1305 * set the field to indicate Jazelle support within QEMU.
1307 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1310 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1311 ARMCPRegInfo ifar = {
1312 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1313 .access = PL1_RW,
1314 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1315 .resetvalue = 0
1317 define_one_arm_cp_reg(cpu, &ifar);
1321 static void arm1136_r2_initfn(Object *obj)
1323 ARMCPU *cpu = ARM_CPU(obj);
1324 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1325 * older core than plain "arm1136". In particular this does not
1326 * have the v6K features.
1327 * These ID register values are correct for 1136 but may be wrong
1328 * for 1136_r2 (in particular r0p2 does not actually implement most
1329 * of the ID registers).
1332 cpu->dtb_compatible = "arm,arm1136";
1333 set_feature(&cpu->env, ARM_FEATURE_V6);
1334 set_feature(&cpu->env, ARM_FEATURE_VFP);
1335 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1336 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1337 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1338 cpu->midr = 0x4107b362;
1339 cpu->reset_fpsid = 0x410120b4;
1340 cpu->isar.mvfr0 = 0x11111111;
1341 cpu->isar.mvfr1 = 0x00000000;
1342 cpu->ctr = 0x1dd20d2;
1343 cpu->reset_sctlr = 0x00050078;
1344 cpu->id_pfr0 = 0x111;
1345 cpu->id_pfr1 = 0x1;
1346 cpu->id_dfr0 = 0x2;
1347 cpu->id_afr0 = 0x3;
1348 cpu->id_mmfr0 = 0x01130003;
1349 cpu->id_mmfr1 = 0x10030302;
1350 cpu->id_mmfr2 = 0x01222110;
1351 cpu->isar.id_isar0 = 0x00140011;
1352 cpu->isar.id_isar1 = 0x12002111;
1353 cpu->isar.id_isar2 = 0x11231111;
1354 cpu->isar.id_isar3 = 0x01102131;
1355 cpu->isar.id_isar4 = 0x141;
1356 cpu->reset_auxcr = 7;
1359 static void arm1136_initfn(Object *obj)
1361 ARMCPU *cpu = ARM_CPU(obj);
1363 cpu->dtb_compatible = "arm,arm1136";
1364 set_feature(&cpu->env, ARM_FEATURE_V6K);
1365 set_feature(&cpu->env, ARM_FEATURE_V6);
1366 set_feature(&cpu->env, ARM_FEATURE_VFP);
1367 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1368 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1369 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1370 cpu->midr = 0x4117b363;
1371 cpu->reset_fpsid = 0x410120b4;
1372 cpu->isar.mvfr0 = 0x11111111;
1373 cpu->isar.mvfr1 = 0x00000000;
1374 cpu->ctr = 0x1dd20d2;
1375 cpu->reset_sctlr = 0x00050078;
1376 cpu->id_pfr0 = 0x111;
1377 cpu->id_pfr1 = 0x1;
1378 cpu->id_dfr0 = 0x2;
1379 cpu->id_afr0 = 0x3;
1380 cpu->id_mmfr0 = 0x01130003;
1381 cpu->id_mmfr1 = 0x10030302;
1382 cpu->id_mmfr2 = 0x01222110;
1383 cpu->isar.id_isar0 = 0x00140011;
1384 cpu->isar.id_isar1 = 0x12002111;
1385 cpu->isar.id_isar2 = 0x11231111;
1386 cpu->isar.id_isar3 = 0x01102131;
1387 cpu->isar.id_isar4 = 0x141;
1388 cpu->reset_auxcr = 7;
1391 static void arm1176_initfn(Object *obj)
1393 ARMCPU *cpu = ARM_CPU(obj);
1395 cpu->dtb_compatible = "arm,arm1176";
1396 set_feature(&cpu->env, ARM_FEATURE_V6K);
1397 set_feature(&cpu->env, ARM_FEATURE_VFP);
1398 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1399 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1400 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1401 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1402 set_feature(&cpu->env, ARM_FEATURE_EL3);
1403 cpu->midr = 0x410fb767;
1404 cpu->reset_fpsid = 0x410120b5;
1405 cpu->isar.mvfr0 = 0x11111111;
1406 cpu->isar.mvfr1 = 0x00000000;
1407 cpu->ctr = 0x1dd20d2;
1408 cpu->reset_sctlr = 0x00050078;
1409 cpu->id_pfr0 = 0x111;
1410 cpu->id_pfr1 = 0x11;
1411 cpu->id_dfr0 = 0x33;
1412 cpu->id_afr0 = 0;
1413 cpu->id_mmfr0 = 0x01130003;
1414 cpu->id_mmfr1 = 0x10030302;
1415 cpu->id_mmfr2 = 0x01222100;
1416 cpu->isar.id_isar0 = 0x0140011;
1417 cpu->isar.id_isar1 = 0x12002111;
1418 cpu->isar.id_isar2 = 0x11231121;
1419 cpu->isar.id_isar3 = 0x01102131;
1420 cpu->isar.id_isar4 = 0x01141;
1421 cpu->reset_auxcr = 7;
1424 static void arm11mpcore_initfn(Object *obj)
1426 ARMCPU *cpu = ARM_CPU(obj);
1428 cpu->dtb_compatible = "arm,arm11mpcore";
1429 set_feature(&cpu->env, ARM_FEATURE_V6K);
1430 set_feature(&cpu->env, ARM_FEATURE_VFP);
1431 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1432 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1433 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1434 cpu->midr = 0x410fb022;
1435 cpu->reset_fpsid = 0x410120b4;
1436 cpu->isar.mvfr0 = 0x11111111;
1437 cpu->isar.mvfr1 = 0x00000000;
1438 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1439 cpu->id_pfr0 = 0x111;
1440 cpu->id_pfr1 = 0x1;
1441 cpu->id_dfr0 = 0;
1442 cpu->id_afr0 = 0x2;
1443 cpu->id_mmfr0 = 0x01100103;
1444 cpu->id_mmfr1 = 0x10020302;
1445 cpu->id_mmfr2 = 0x01222000;
1446 cpu->isar.id_isar0 = 0x00100011;
1447 cpu->isar.id_isar1 = 0x12002111;
1448 cpu->isar.id_isar2 = 0x11221011;
1449 cpu->isar.id_isar3 = 0x01102131;
1450 cpu->isar.id_isar4 = 0x141;
1451 cpu->reset_auxcr = 1;
1454 static void cortex_m0_initfn(Object *obj)
1456 ARMCPU *cpu = ARM_CPU(obj);
1457 set_feature(&cpu->env, ARM_FEATURE_V6);
1458 set_feature(&cpu->env, ARM_FEATURE_M);
1460 cpu->midr = 0x410cc200;
1463 static void cortex_m3_initfn(Object *obj)
1465 ARMCPU *cpu = ARM_CPU(obj);
1466 set_feature(&cpu->env, ARM_FEATURE_V7);
1467 set_feature(&cpu->env, ARM_FEATURE_M);
1468 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1469 cpu->midr = 0x410fc231;
1470 cpu->pmsav7_dregion = 8;
1471 cpu->id_pfr0 = 0x00000030;
1472 cpu->id_pfr1 = 0x00000200;
1473 cpu->id_dfr0 = 0x00100000;
1474 cpu->id_afr0 = 0x00000000;
1475 cpu->id_mmfr0 = 0x00000030;
1476 cpu->id_mmfr1 = 0x00000000;
1477 cpu->id_mmfr2 = 0x00000000;
1478 cpu->id_mmfr3 = 0x00000000;
1479 cpu->isar.id_isar0 = 0x01141110;
1480 cpu->isar.id_isar1 = 0x02111000;
1481 cpu->isar.id_isar2 = 0x21112231;
1482 cpu->isar.id_isar3 = 0x01111110;
1483 cpu->isar.id_isar4 = 0x01310102;
1484 cpu->isar.id_isar5 = 0x00000000;
1485 cpu->isar.id_isar6 = 0x00000000;
1488 static void cortex_m4_initfn(Object *obj)
1490 ARMCPU *cpu = ARM_CPU(obj);
1492 set_feature(&cpu->env, ARM_FEATURE_V7);
1493 set_feature(&cpu->env, ARM_FEATURE_M);
1494 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1495 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1496 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1497 cpu->midr = 0x410fc240; /* r0p0 */
1498 cpu->pmsav7_dregion = 8;
1499 cpu->isar.mvfr0 = 0x10110021;
1500 cpu->isar.mvfr1 = 0x11000011;
1501 cpu->isar.mvfr2 = 0x00000000;
1502 cpu->id_pfr0 = 0x00000030;
1503 cpu->id_pfr1 = 0x00000200;
1504 cpu->id_dfr0 = 0x00100000;
1505 cpu->id_afr0 = 0x00000000;
1506 cpu->id_mmfr0 = 0x00000030;
1507 cpu->id_mmfr1 = 0x00000000;
1508 cpu->id_mmfr2 = 0x00000000;
1509 cpu->id_mmfr3 = 0x00000000;
1510 cpu->isar.id_isar0 = 0x01141110;
1511 cpu->isar.id_isar1 = 0x02111000;
1512 cpu->isar.id_isar2 = 0x21112231;
1513 cpu->isar.id_isar3 = 0x01111110;
1514 cpu->isar.id_isar4 = 0x01310102;
1515 cpu->isar.id_isar5 = 0x00000000;
1516 cpu->isar.id_isar6 = 0x00000000;
1519 static void cortex_m33_initfn(Object *obj)
1521 ARMCPU *cpu = ARM_CPU(obj);
1523 set_feature(&cpu->env, ARM_FEATURE_V8);
1524 set_feature(&cpu->env, ARM_FEATURE_M);
1525 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1526 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1527 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1528 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1529 cpu->midr = 0x410fd213; /* r0p3 */
1530 cpu->pmsav7_dregion = 16;
1531 cpu->sau_sregion = 8;
1532 cpu->isar.mvfr0 = 0x10110021;
1533 cpu->isar.mvfr1 = 0x11000011;
1534 cpu->isar.mvfr2 = 0x00000040;
1535 cpu->id_pfr0 = 0x00000030;
1536 cpu->id_pfr1 = 0x00000210;
1537 cpu->id_dfr0 = 0x00200000;
1538 cpu->id_afr0 = 0x00000000;
1539 cpu->id_mmfr0 = 0x00101F40;
1540 cpu->id_mmfr1 = 0x00000000;
1541 cpu->id_mmfr2 = 0x01000000;
1542 cpu->id_mmfr3 = 0x00000000;
1543 cpu->isar.id_isar0 = 0x01101110;
1544 cpu->isar.id_isar1 = 0x02212000;
1545 cpu->isar.id_isar2 = 0x20232232;
1546 cpu->isar.id_isar3 = 0x01111131;
1547 cpu->isar.id_isar4 = 0x01310132;
1548 cpu->isar.id_isar5 = 0x00000000;
1549 cpu->isar.id_isar6 = 0x00000000;
1550 cpu->clidr = 0x00000000;
1551 cpu->ctr = 0x8000c000;
1554 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1556 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1557 CPUClass *cc = CPU_CLASS(oc);
1559 acc->info = data;
1560 #ifndef CONFIG_USER_ONLY
1561 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1562 #endif
1564 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1567 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1568 /* Dummy the TCM region regs for the moment */
1569 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1570 .access = PL1_RW, .type = ARM_CP_CONST },
1571 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1572 .access = PL1_RW, .type = ARM_CP_CONST },
1573 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1574 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1575 REGINFO_SENTINEL
1578 static void cortex_r5_initfn(Object *obj)
1580 ARMCPU *cpu = ARM_CPU(obj);
1582 set_feature(&cpu->env, ARM_FEATURE_V7);
1583 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1584 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1585 cpu->midr = 0x411fc153; /* r1p3 */
1586 cpu->id_pfr0 = 0x0131;
1587 cpu->id_pfr1 = 0x001;
1588 cpu->id_dfr0 = 0x010400;
1589 cpu->id_afr0 = 0x0;
1590 cpu->id_mmfr0 = 0x0210030;
1591 cpu->id_mmfr1 = 0x00000000;
1592 cpu->id_mmfr2 = 0x01200000;
1593 cpu->id_mmfr3 = 0x0211;
1594 cpu->isar.id_isar0 = 0x02101111;
1595 cpu->isar.id_isar1 = 0x13112111;
1596 cpu->isar.id_isar2 = 0x21232141;
1597 cpu->isar.id_isar3 = 0x01112131;
1598 cpu->isar.id_isar4 = 0x0010142;
1599 cpu->isar.id_isar5 = 0x0;
1600 cpu->isar.id_isar6 = 0x0;
1601 cpu->mp_is_up = true;
1602 cpu->pmsav7_dregion = 16;
1603 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1606 static void cortex_r5f_initfn(Object *obj)
1608 ARMCPU *cpu = ARM_CPU(obj);
1610 cortex_r5_initfn(obj);
1611 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1614 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1615 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1616 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1617 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1618 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1619 REGINFO_SENTINEL
1622 static void cortex_a8_initfn(Object *obj)
1624 ARMCPU *cpu = ARM_CPU(obj);
1626 cpu->dtb_compatible = "arm,cortex-a8";
1627 set_feature(&cpu->env, ARM_FEATURE_V7);
1628 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1629 set_feature(&cpu->env, ARM_FEATURE_NEON);
1630 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1631 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1632 set_feature(&cpu->env, ARM_FEATURE_EL3);
1633 cpu->midr = 0x410fc080;
1634 cpu->reset_fpsid = 0x410330c0;
1635 cpu->isar.mvfr0 = 0x11110222;
1636 cpu->isar.mvfr1 = 0x00011111;
1637 cpu->ctr = 0x82048004;
1638 cpu->reset_sctlr = 0x00c50078;
1639 cpu->id_pfr0 = 0x1031;
1640 cpu->id_pfr1 = 0x11;
1641 cpu->id_dfr0 = 0x400;
1642 cpu->id_afr0 = 0;
1643 cpu->id_mmfr0 = 0x31100003;
1644 cpu->id_mmfr1 = 0x20000000;
1645 cpu->id_mmfr2 = 0x01202000;
1646 cpu->id_mmfr3 = 0x11;
1647 cpu->isar.id_isar0 = 0x00101111;
1648 cpu->isar.id_isar1 = 0x12112111;
1649 cpu->isar.id_isar2 = 0x21232031;
1650 cpu->isar.id_isar3 = 0x11112131;
1651 cpu->isar.id_isar4 = 0x00111142;
1652 cpu->dbgdidr = 0x15141000;
1653 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1654 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1655 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1656 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1657 cpu->reset_auxcr = 2;
1658 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1661 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1662 /* power_control should be set to maximum latency. Again,
1663 * default to 0 and set by private hook
1665 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1666 .access = PL1_RW, .resetvalue = 0,
1667 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1668 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1669 .access = PL1_RW, .resetvalue = 0,
1670 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1671 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1672 .access = PL1_RW, .resetvalue = 0,
1673 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1674 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1675 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1676 /* TLB lockdown control */
1677 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1678 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1679 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1680 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1681 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1682 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1683 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1684 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1685 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1686 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1687 REGINFO_SENTINEL
1690 static void cortex_a9_initfn(Object *obj)
1692 ARMCPU *cpu = ARM_CPU(obj);
1694 cpu->dtb_compatible = "arm,cortex-a9";
1695 set_feature(&cpu->env, ARM_FEATURE_V7);
1696 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1697 set_feature(&cpu->env, ARM_FEATURE_NEON);
1698 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1699 set_feature(&cpu->env, ARM_FEATURE_EL3);
1700 /* Note that A9 supports the MP extensions even for
1701 * A9UP and single-core A9MP (which are both different
1702 * and valid configurations; we don't model A9UP).
1704 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1705 set_feature(&cpu->env, ARM_FEATURE_CBAR);
1706 cpu->midr = 0x410fc090;
1707 cpu->reset_fpsid = 0x41033090;
1708 cpu->isar.mvfr0 = 0x11110222;
1709 cpu->isar.mvfr1 = 0x01111111;
1710 cpu->ctr = 0x80038003;
1711 cpu->reset_sctlr = 0x00c50078;
1712 cpu->id_pfr0 = 0x1031;
1713 cpu->id_pfr1 = 0x11;
1714 cpu->id_dfr0 = 0x000;
1715 cpu->id_afr0 = 0;
1716 cpu->id_mmfr0 = 0x00100103;
1717 cpu->id_mmfr1 = 0x20000000;
1718 cpu->id_mmfr2 = 0x01230000;
1719 cpu->id_mmfr3 = 0x00002111;
1720 cpu->isar.id_isar0 = 0x00101111;
1721 cpu->isar.id_isar1 = 0x13112111;
1722 cpu->isar.id_isar2 = 0x21232041;
1723 cpu->isar.id_isar3 = 0x11112131;
1724 cpu->isar.id_isar4 = 0x00111142;
1725 cpu->dbgdidr = 0x35141000;
1726 cpu->clidr = (1 << 27) | (1 << 24) | 3;
1727 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1728 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1729 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1732 #ifndef CONFIG_USER_ONLY
1733 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1735 /* Linux wants the number of processors from here.
1736 * Might as well set the interrupt-controller bit too.
1738 return ((smp_cpus - 1) << 24) | (1 << 23);
1740 #endif
1742 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1743 #ifndef CONFIG_USER_ONLY
1744 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1745 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1746 .writefn = arm_cp_write_ignore, },
1747 #endif
1748 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1749 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1750 REGINFO_SENTINEL
1753 static void cortex_a7_initfn(Object *obj)
1755 ARMCPU *cpu = ARM_CPU(obj);
1757 cpu->dtb_compatible = "arm,cortex-a7";
1758 set_feature(&cpu->env, ARM_FEATURE_V7VE);
1759 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1760 set_feature(&cpu->env, ARM_FEATURE_NEON);
1761 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1762 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1763 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1764 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1765 set_feature(&cpu->env, ARM_FEATURE_EL2);
1766 set_feature(&cpu->env, ARM_FEATURE_EL3);
1767 set_feature(&cpu->env, ARM_FEATURE_PMU);
1768 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1769 cpu->midr = 0x410fc075;
1770 cpu->reset_fpsid = 0x41023075;
1771 cpu->isar.mvfr0 = 0x10110222;
1772 cpu->isar.mvfr1 = 0x11111111;
1773 cpu->ctr = 0x84448003;
1774 cpu->reset_sctlr = 0x00c50078;
1775 cpu->id_pfr0 = 0x00001131;
1776 cpu->id_pfr1 = 0x00011011;
1777 cpu->id_dfr0 = 0x02010555;
1778 cpu->id_afr0 = 0x00000000;
1779 cpu->id_mmfr0 = 0x10101105;
1780 cpu->id_mmfr1 = 0x40000000;
1781 cpu->id_mmfr2 = 0x01240000;
1782 cpu->id_mmfr3 = 0x02102211;
1783 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1784 * table 4-41 gives 0x02101110, which includes the arm div insns.
1786 cpu->isar.id_isar0 = 0x02101110;
1787 cpu->isar.id_isar1 = 0x13112111;
1788 cpu->isar.id_isar2 = 0x21232041;
1789 cpu->isar.id_isar3 = 0x11112131;
1790 cpu->isar.id_isar4 = 0x10011142;
1791 cpu->dbgdidr = 0x3515f005;
1792 cpu->clidr = 0x0a200023;
1793 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1794 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1795 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1796 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1799 static void cortex_a15_initfn(Object *obj)
1801 ARMCPU *cpu = ARM_CPU(obj);
1803 cpu->dtb_compatible = "arm,cortex-a15";
1804 set_feature(&cpu->env, ARM_FEATURE_V7VE);
1805 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1806 set_feature(&cpu->env, ARM_FEATURE_NEON);
1807 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1808 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1809 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1810 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1811 set_feature(&cpu->env, ARM_FEATURE_EL2);
1812 set_feature(&cpu->env, ARM_FEATURE_EL3);
1813 set_feature(&cpu->env, ARM_FEATURE_PMU);
1814 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1815 cpu->midr = 0x412fc0f1;
1816 cpu->reset_fpsid = 0x410430f0;
1817 cpu->isar.mvfr0 = 0x10110222;
1818 cpu->isar.mvfr1 = 0x11111111;
1819 cpu->ctr = 0x8444c004;
1820 cpu->reset_sctlr = 0x00c50078;
1821 cpu->id_pfr0 = 0x00001131;
1822 cpu->id_pfr1 = 0x00011011;
1823 cpu->id_dfr0 = 0x02010555;
1824 cpu->id_afr0 = 0x00000000;
1825 cpu->id_mmfr0 = 0x10201105;
1826 cpu->id_mmfr1 = 0x20000000;
1827 cpu->id_mmfr2 = 0x01240000;
1828 cpu->id_mmfr3 = 0x02102211;
1829 cpu->isar.id_isar0 = 0x02101110;
1830 cpu->isar.id_isar1 = 0x13112111;
1831 cpu->isar.id_isar2 = 0x21232041;
1832 cpu->isar.id_isar3 = 0x11112131;
1833 cpu->isar.id_isar4 = 0x10011142;
1834 cpu->dbgdidr = 0x3515f021;
1835 cpu->clidr = 0x0a200023;
1836 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1837 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1838 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1839 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1842 static void ti925t_initfn(Object *obj)
1844 ARMCPU *cpu = ARM_CPU(obj);
1845 set_feature(&cpu->env, ARM_FEATURE_V4T);
1846 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1847 cpu->midr = ARM_CPUID_TI925T;
1848 cpu->ctr = 0x5109149;
1849 cpu->reset_sctlr = 0x00000070;
1852 static void sa1100_initfn(Object *obj)
1854 ARMCPU *cpu = ARM_CPU(obj);
1856 cpu->dtb_compatible = "intel,sa1100";
1857 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1858 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1859 cpu->midr = 0x4401A11B;
1860 cpu->reset_sctlr = 0x00000070;
1863 static void sa1110_initfn(Object *obj)
1865 ARMCPU *cpu = ARM_CPU(obj);
1866 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1867 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1868 cpu->midr = 0x6901B119;
1869 cpu->reset_sctlr = 0x00000070;
1872 static void pxa250_initfn(Object *obj)
1874 ARMCPU *cpu = ARM_CPU(obj);
1876 cpu->dtb_compatible = "marvell,xscale";
1877 set_feature(&cpu->env, ARM_FEATURE_V5);
1878 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1879 cpu->midr = 0x69052100;
1880 cpu->ctr = 0xd172172;
1881 cpu->reset_sctlr = 0x00000078;
1884 static void pxa255_initfn(Object *obj)
1886 ARMCPU *cpu = ARM_CPU(obj);
1888 cpu->dtb_compatible = "marvell,xscale";
1889 set_feature(&cpu->env, ARM_FEATURE_V5);
1890 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1891 cpu->midr = 0x69052d00;
1892 cpu->ctr = 0xd172172;
1893 cpu->reset_sctlr = 0x00000078;
1896 static void pxa260_initfn(Object *obj)
1898 ARMCPU *cpu = ARM_CPU(obj);
1900 cpu->dtb_compatible = "marvell,xscale";
1901 set_feature(&cpu->env, ARM_FEATURE_V5);
1902 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1903 cpu->midr = 0x69052903;
1904 cpu->ctr = 0xd172172;
1905 cpu->reset_sctlr = 0x00000078;
1908 static void pxa261_initfn(Object *obj)
1910 ARMCPU *cpu = ARM_CPU(obj);
1912 cpu->dtb_compatible = "marvell,xscale";
1913 set_feature(&cpu->env, ARM_FEATURE_V5);
1914 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1915 cpu->midr = 0x69052d05;
1916 cpu->ctr = 0xd172172;
1917 cpu->reset_sctlr = 0x00000078;
1920 static void pxa262_initfn(Object *obj)
1922 ARMCPU *cpu = ARM_CPU(obj);
1924 cpu->dtb_compatible = "marvell,xscale";
1925 set_feature(&cpu->env, ARM_FEATURE_V5);
1926 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1927 cpu->midr = 0x69052d06;
1928 cpu->ctr = 0xd172172;
1929 cpu->reset_sctlr = 0x00000078;
1932 static void pxa270a0_initfn(Object *obj)
1934 ARMCPU *cpu = ARM_CPU(obj);
1936 cpu->dtb_compatible = "marvell,xscale";
1937 set_feature(&cpu->env, ARM_FEATURE_V5);
1938 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1939 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1940 cpu->midr = 0x69054110;
1941 cpu->ctr = 0xd172172;
1942 cpu->reset_sctlr = 0x00000078;
1945 static void pxa270a1_initfn(Object *obj)
1947 ARMCPU *cpu = ARM_CPU(obj);
1949 cpu->dtb_compatible = "marvell,xscale";
1950 set_feature(&cpu->env, ARM_FEATURE_V5);
1951 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1952 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1953 cpu->midr = 0x69054111;
1954 cpu->ctr = 0xd172172;
1955 cpu->reset_sctlr = 0x00000078;
1958 static void pxa270b0_initfn(Object *obj)
1960 ARMCPU *cpu = ARM_CPU(obj);
1962 cpu->dtb_compatible = "marvell,xscale";
1963 set_feature(&cpu->env, ARM_FEATURE_V5);
1964 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1965 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1966 cpu->midr = 0x69054112;
1967 cpu->ctr = 0xd172172;
1968 cpu->reset_sctlr = 0x00000078;
1971 static void pxa270b1_initfn(Object *obj)
1973 ARMCPU *cpu = ARM_CPU(obj);
1975 cpu->dtb_compatible = "marvell,xscale";
1976 set_feature(&cpu->env, ARM_FEATURE_V5);
1977 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1978 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1979 cpu->midr = 0x69054113;
1980 cpu->ctr = 0xd172172;
1981 cpu->reset_sctlr = 0x00000078;
1984 static void pxa270c0_initfn(Object *obj)
1986 ARMCPU *cpu = ARM_CPU(obj);
1988 cpu->dtb_compatible = "marvell,xscale";
1989 set_feature(&cpu->env, ARM_FEATURE_V5);
1990 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1991 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1992 cpu->midr = 0x69054114;
1993 cpu->ctr = 0xd172172;
1994 cpu->reset_sctlr = 0x00000078;
1997 static void pxa270c5_initfn(Object *obj)
1999 ARMCPU *cpu = ARM_CPU(obj);
2001 cpu->dtb_compatible = "marvell,xscale";
2002 set_feature(&cpu->env, ARM_FEATURE_V5);
2003 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2004 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2005 cpu->midr = 0x69054117;
2006 cpu->ctr = 0xd172172;
2007 cpu->reset_sctlr = 0x00000078;
2010 #ifndef TARGET_AARCH64
2011 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2012 * otherwise, a CPU with as many features enabled as our emulation supports.
2013 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2014 * this only needs to handle 32 bits.
2016 static void arm_max_initfn(Object *obj)
2018 ARMCPU *cpu = ARM_CPU(obj);
2020 if (kvm_enabled()) {
2021 kvm_arm_set_cpu_features_from_host(cpu);
2022 } else {
2023 cortex_a15_initfn(obj);
2024 #ifdef CONFIG_USER_ONLY
2025 /* We don't set these in system emulation mode for the moment,
2026 * since we don't correctly set (all of) the ID registers to
2027 * advertise them.
2029 set_feature(&cpu->env, ARM_FEATURE_V8);
2031 uint32_t t;
2033 t = cpu->isar.id_isar5;
2034 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2035 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2036 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2037 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2038 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2039 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2040 cpu->isar.id_isar5 = t;
2042 t = cpu->isar.id_isar6;
2043 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
2044 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
2045 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
2046 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
2047 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
2048 cpu->isar.id_isar6 = t;
2050 t = cpu->isar.mvfr2;
2051 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2052 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
2053 cpu->isar.mvfr2 = t;
2055 t = cpu->id_mmfr4;
2056 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2057 cpu->id_mmfr4 = t;
2059 #endif
2062 #endif
2064 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2066 struct ARMCPUInfo {
2067 const char *name;
2068 void (*initfn)(Object *obj);
2069 void (*class_init)(ObjectClass *oc, void *data);
2072 static const ARMCPUInfo arm_cpus[] = {
2073 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2074 { .name = "arm926", .initfn = arm926_initfn },
2075 { .name = "arm946", .initfn = arm946_initfn },
2076 { .name = "arm1026", .initfn = arm1026_initfn },
2077 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2078 * older core than plain "arm1136". In particular this does not
2079 * have the v6K features.
2081 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
2082 { .name = "arm1136", .initfn = arm1136_initfn },
2083 { .name = "arm1176", .initfn = arm1176_initfn },
2084 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
2085 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
2086 .class_init = arm_v7m_class_init },
2087 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
2088 .class_init = arm_v7m_class_init },
2089 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
2090 .class_init = arm_v7m_class_init },
2091 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
2092 .class_init = arm_v7m_class_init },
2093 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
2094 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
2095 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
2096 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
2097 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
2098 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2099 { .name = "ti925t", .initfn = ti925t_initfn },
2100 { .name = "sa1100", .initfn = sa1100_initfn },
2101 { .name = "sa1110", .initfn = sa1110_initfn },
2102 { .name = "pxa250", .initfn = pxa250_initfn },
2103 { .name = "pxa255", .initfn = pxa255_initfn },
2104 { .name = "pxa260", .initfn = pxa260_initfn },
2105 { .name = "pxa261", .initfn = pxa261_initfn },
2106 { .name = "pxa262", .initfn = pxa262_initfn },
2107 /* "pxa270" is an alias for "pxa270-a0" */
2108 { .name = "pxa270", .initfn = pxa270a0_initfn },
2109 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
2110 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
2111 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
2112 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
2113 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
2114 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
2115 #ifndef TARGET_AARCH64
2116 { .name = "max", .initfn = arm_max_initfn },
2117 #endif
2118 #ifdef CONFIG_USER_ONLY
2119 { .name = "any", .initfn = arm_max_initfn },
2120 #endif
2121 #endif
2122 { .name = NULL }
2125 static Property arm_cpu_properties[] = {
2126 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
2127 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2128 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
2129 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2130 mp_affinity, ARM64_AFFINITY_INVALID),
2131 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2132 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2133 DEFINE_PROP_END_OF_LIST()
2136 #ifdef CONFIG_USER_ONLY
2137 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
2138 int rw, int mmu_idx)
2140 ARMCPU *cpu = ARM_CPU(cs);
2141 CPUARMState *env = &cpu->env;
2143 env->exception.vaddress = address;
2144 if (rw == 2) {
2145 cs->exception_index = EXCP_PREFETCH_ABORT;
2146 } else {
2147 cs->exception_index = EXCP_DATA_ABORT;
2149 return 1;
2151 #endif
2153 static gchar *arm_gdb_arch_name(CPUState *cs)
2155 ARMCPU *cpu = ARM_CPU(cs);
2156 CPUARMState *env = &cpu->env;
2158 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2159 return g_strdup("iwmmxt");
2161 return g_strdup("arm");
2164 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2166 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2167 CPUClass *cc = CPU_CLASS(acc);
2168 DeviceClass *dc = DEVICE_CLASS(oc);
2170 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2171 &acc->parent_realize);
2172 dc->props = arm_cpu_properties;
2174 acc->parent_reset = cc->reset;
2175 cc->reset = arm_cpu_reset;
2177 cc->class_by_name = arm_cpu_class_by_name;
2178 cc->has_work = arm_cpu_has_work;
2179 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2180 cc->dump_state = arm_cpu_dump_state;
2181 cc->set_pc = arm_cpu_set_pc;
2182 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
2183 cc->gdb_read_register = arm_cpu_gdb_read_register;
2184 cc->gdb_write_register = arm_cpu_gdb_write_register;
2185 #ifdef CONFIG_USER_ONLY
2186 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
2187 #else
2188 cc->do_interrupt = arm_cpu_do_interrupt;
2189 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2190 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2191 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2192 cc->asidx_from_attrs = arm_asidx_from_attrs;
2193 cc->vmsd = &vmstate_arm_cpu;
2194 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2195 cc->write_elf64_note = arm_cpu_write_elf64_note;
2196 cc->write_elf32_note = arm_cpu_write_elf32_note;
2197 #endif
2198 cc->gdb_num_core_regs = 26;
2199 cc->gdb_core_xml_file = "arm-core.xml";
2200 cc->gdb_arch_name = arm_gdb_arch_name;
2201 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2202 cc->gdb_stop_before_watchpoint = true;
2203 cc->debug_excp_handler = arm_debug_excp_handler;
2204 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2205 #if !defined(CONFIG_USER_ONLY)
2206 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2207 #endif
2209 cc->disas_set_info = arm_disas_set_info;
2210 #ifdef CONFIG_TCG
2211 cc->tcg_initialize = arm_translate_init;
2212 #endif
2215 #ifdef CONFIG_KVM
2216 static void arm_host_initfn(Object *obj)
2218 ARMCPU *cpu = ARM_CPU(obj);
2220 kvm_arm_set_cpu_features_from_host(cpu);
2221 arm_cpu_post_init(obj);
2224 static const TypeInfo host_arm_cpu_type_info = {
2225 .name = TYPE_ARM_HOST_CPU,
2226 #ifdef TARGET_AARCH64
2227 .parent = TYPE_AARCH64_CPU,
2228 #else
2229 .parent = TYPE_ARM_CPU,
2230 #endif
2231 .instance_init = arm_host_initfn,
2234 #endif
2236 static void arm_cpu_instance_init(Object *obj)
2238 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2240 acc->info->initfn(obj);
2241 arm_cpu_post_init(obj);
2244 static void cpu_register_class_init(ObjectClass *oc, void *data)
2246 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2248 acc->info = data;
2251 static void cpu_register(const ARMCPUInfo *info)
2253 TypeInfo type_info = {
2254 .parent = TYPE_ARM_CPU,
2255 .instance_size = sizeof(ARMCPU),
2256 .instance_init = arm_cpu_instance_init,
2257 .class_size = sizeof(ARMCPUClass),
2258 .class_init = info->class_init ?: cpu_register_class_init,
2259 .class_data = (void *)info,
2262 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2263 type_register(&type_info);
2264 g_free((void *)type_info.name);
2267 static const TypeInfo arm_cpu_type_info = {
2268 .name = TYPE_ARM_CPU,
2269 .parent = TYPE_CPU,
2270 .instance_size = sizeof(ARMCPU),
2271 .instance_init = arm_cpu_initfn,
2272 .instance_finalize = arm_cpu_finalizefn,
2273 .abstract = true,
2274 .class_size = sizeof(ARMCPUClass),
2275 .class_init = arm_cpu_class_init,
2278 static const TypeInfo idau_interface_type_info = {
2279 .name = TYPE_IDAU_INTERFACE,
2280 .parent = TYPE_INTERFACE,
2281 .class_size = sizeof(IDAUInterfaceClass),
2284 static void arm_cpu_register_types(void)
2286 const ARMCPUInfo *info = arm_cpus;
2288 type_register_static(&arm_cpu_type_info);
2289 type_register_static(&idau_interface_type_info);
2291 while (info->name) {
2292 cpu_register(info);
2293 info++;
2296 #ifdef CONFIG_KVM
2297 type_register_static(&host_arm_cpu_type_info);
2298 #endif
2301 type_init(arm_cpu_register_types)