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qxl: check release info object
[qemu/ar7.git] / hw / display / qxl.c
blob632923add2395558f2abe1ab4aff30508af41f8b
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include <zlib.h>
24
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "qemu/timer.h"
28 #include "qemu/queue.h"
29 #include "qemu/atomic.h"
30 #include "sysemu/sysemu.h"
31 #include "migration/blocker.h"
32 #include "trace.h"
33
34 #include "qxl.h"
35
36 /*
37 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
38 * such can be changed by the guest, so to avoid a guest trigerrable
39 * abort we just qxl_set_guest_bug and set the return to NULL. Still
40 * it may happen as a result of emulator bug as well.
41 */
42 #undef SPICE_RING_PROD_ITEM
43 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
44 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
45 if (prod >= ARRAY_SIZE((r)->items)) { \
46 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
47 "%u >= %zu", prod, ARRAY_SIZE((r)->items)); \
48 ret = NULL; \
49 } else { \
50 ret = &(r)->items[prod].el; \
51 } \
52 }
53
54 #undef SPICE_RING_CONS_ITEM
55 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
56 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
57 if (cons >= ARRAY_SIZE((r)->items)) { \
58 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
59 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
60 ret = NULL; \
61 } else { \
62 ret = &(r)->items[cons].el; \
63 } \
64 }
65
66 #undef ALIGN
67 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
68
69 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
70
71 #define QXL_MODE(_x, _y, _b, _o) \
72 { .x_res = _x, \
73 .y_res = _y, \
74 .bits = _b, \
75 .stride = (_x) * (_b) / 8, \
76 .x_mili = PIXEL_SIZE * (_x), \
77 .y_mili = PIXEL_SIZE * (_y), \
78 .orientation = _o, \
79 }
80
81 #define QXL_MODE_16_32(x_res, y_res, orientation) \
82 QXL_MODE(x_res, y_res, 16, orientation), \
83 QXL_MODE(x_res, y_res, 32, orientation)
84
85 #define QXL_MODE_EX(x_res, y_res) \
86 QXL_MODE_16_32(x_res, y_res, 0), \
87 QXL_MODE_16_32(x_res, y_res, 1)
88
89 static QXLMode qxl_modes[] = {
90 QXL_MODE_EX(640, 480),
91 QXL_MODE_EX(800, 480),
92 QXL_MODE_EX(800, 600),
93 QXL_MODE_EX(832, 624),
94 QXL_MODE_EX(960, 640),
95 QXL_MODE_EX(1024, 600),
96 QXL_MODE_EX(1024, 768),
97 QXL_MODE_EX(1152, 864),
98 QXL_MODE_EX(1152, 870),
99 QXL_MODE_EX(1280, 720),
100 QXL_MODE_EX(1280, 760),
101 QXL_MODE_EX(1280, 768),
102 QXL_MODE_EX(1280, 800),
103 QXL_MODE_EX(1280, 960),
104 QXL_MODE_EX(1280, 1024),
105 QXL_MODE_EX(1360, 768),
106 QXL_MODE_EX(1366, 768),
107 QXL_MODE_EX(1400, 1050),
108 QXL_MODE_EX(1440, 900),
109 QXL_MODE_EX(1600, 900),
110 QXL_MODE_EX(1600, 1200),
111 QXL_MODE_EX(1680, 1050),
112 QXL_MODE_EX(1920, 1080),
113 /* these modes need more than 8 MB video memory */
114 QXL_MODE_EX(1920, 1200),
115 QXL_MODE_EX(1920, 1440),
116 QXL_MODE_EX(2000, 2000),
117 QXL_MODE_EX(2048, 1536),
118 QXL_MODE_EX(2048, 2048),
119 QXL_MODE_EX(2560, 1440),
120 QXL_MODE_EX(2560, 1600),
121 /* these modes need more than 16 MB video memory */
122 QXL_MODE_EX(2560, 2048),
123 QXL_MODE_EX(2800, 2100),
124 QXL_MODE_EX(3200, 2400),
125 /* these modes need more than 32 MB video memory */
126 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
127 QXL_MODE_EX(4096, 2160), /* 4k */
128 /* these modes need more than 64 MB video memory */
129 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
130 /* these modes need more than 128 MB video memory */
131 QXL_MODE_EX(8192, 4320), /* 8k */
132 };
133
134 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
135 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
136 static void qxl_reset_memslots(PCIQXLDevice *d);
137 static void qxl_reset_surfaces(PCIQXLDevice *d);
138 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
139
140 static void qxl_hw_update(void *opaque);
141
142 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
143 {
144 trace_qxl_set_guest_bug(qxl->id);
145 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
146 qxl->guest_bug = 1;
147 if (qxl->guestdebug) {
148 va_list ap;
149 va_start(ap, msg);
150 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
151 vfprintf(stderr, msg, ap);
152 fprintf(stderr, "\n");
153 va_end(ap);
154 }
155 }
156
157 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
158 {
159 qxl->guest_bug = 0;
160 }
161
162 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
163 struct QXLRect *area, struct QXLRect *dirty_rects,
164 uint32_t num_dirty_rects,
165 uint32_t clear_dirty_region,
166 qxl_async_io async, struct QXLCookie *cookie)
167 {
168 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
169 area->top, area->bottom);
170 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
171 clear_dirty_region);
172 if (async == QXL_SYNC) {
173 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
174 dirty_rects, num_dirty_rects, clear_dirty_region);
175 } else {
176 assert(cookie != NULL);
177 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
178 clear_dirty_region, (uintptr_t)cookie);
179 }
180 }
181
182 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
183 uint32_t id)
184 {
185 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
186 qemu_mutex_lock(&qxl->track_lock);
187 qxl->guest_surfaces.cmds[id] = 0;
188 qxl->guest_surfaces.count--;
189 qemu_mutex_unlock(&qxl->track_lock);
190 }
191
192 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
193 qxl_async_io async)
194 {
195 QXLCookie *cookie;
196
197 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
198 if (async) {
199 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_DESTROY_SURFACE_ASYNC);
201 cookie->u.surface_id = id;
202 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
203 } else {
204 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
205 qxl_spice_destroy_surface_wait_complete(qxl, id);
206 }
207 }
208
209 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
210 {
211 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
212 qxl->num_free_res);
213 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
214 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
215 QXL_IO_FLUSH_SURFACES_ASYNC));
216 }
217
218 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
219 uint32_t count)
220 {
221 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
222 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
223 }
224
225 void qxl_spice_oom(PCIQXLDevice *qxl)
226 {
227 trace_qxl_spice_oom(qxl->id);
228 spice_qxl_oom(&qxl->ssd.qxl);
229 }
230
231 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
232 {
233 trace_qxl_spice_reset_memslots(qxl->id);
234 spice_qxl_reset_memslots(&qxl->ssd.qxl);
235 }
236
237 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
238 {
239 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
240 qemu_mutex_lock(&qxl->track_lock);
241 memset(qxl->guest_surfaces.cmds, 0,
242 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
243 qxl->guest_surfaces.count = 0;
244 qemu_mutex_unlock(&qxl->track_lock);
245 }
246
247 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
248 {
249 trace_qxl_spice_destroy_surfaces(qxl->id, async);
250 if (async) {
251 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
252 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
253 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
254 } else {
255 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
256 qxl_spice_destroy_surfaces_complete(qxl);
257 }
258 }
259
260 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
261 {
262 QXLMonitorsConfig *cfg;
263
264 trace_qxl_spice_monitors_config(qxl->id);
265 if (replay) {
266 /*
267 * don't use QXL_COOKIE_TYPE_IO:
268 * - we are not running yet (post_load), we will assert
269 * in send_events
270 * - this is not a guest io, but a reply, so async_io isn't set.
271 */
272 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
273 qxl->guest_monitors_config,
274 MEMSLOT_GROUP_GUEST,
275 (uintptr_t)qxl_cookie_new(
276 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
277 0));
278 } else {
279 /* >= release 0.12.6, < release 0.14.2 */
280 #if SPICE_SERVER_VERSION >= 0x000c06 && SPICE_SERVER_VERSION < 0x000e02
281 if (qxl->max_outputs) {
282 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
283 }
284 #endif
285 qxl->guest_monitors_config = qxl->ram->monitors_config;
286 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
287 qxl->ram->monitors_config,
288 MEMSLOT_GROUP_GUEST,
289 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
290 QXL_IO_MONITORS_CONFIG_ASYNC));
291 }
292
293 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST);
294 if (cfg != NULL && cfg->count == 1) {
295 qxl->guest_primary.resized = 1;
296 qxl->guest_head0_width = cfg->heads[0].width;
297 qxl->guest_head0_height = cfg->heads[0].height;
298 } else {
299 qxl->guest_head0_width = 0;
300 qxl->guest_head0_height = 0;
301 }
302 }
303
304 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
305 {
306 trace_qxl_spice_reset_image_cache(qxl->id);
307 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
308 }
309
310 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
311 {
312 trace_qxl_spice_reset_cursor(qxl->id);
313 spice_qxl_reset_cursor(&qxl->ssd.qxl);
314 qemu_mutex_lock(&qxl->track_lock);
315 qxl->guest_cursor = 0;
316 qemu_mutex_unlock(&qxl->track_lock);
317 if (qxl->ssd.cursor) {
318 cursor_put(qxl->ssd.cursor);
319 }
320 qxl->ssd.cursor = cursor_builtin_hidden();
321 }
322
323 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
324 {
325 /*
326 * zlib xors the seed with 0xffffffff, and xors the result
327 * again with 0xffffffff; Both are not done with linux's crc32,
328 * which we want to be compatible with, so undo that.
329 */
330 return crc32(0xffffffff, p, len) ^ 0xffffffff;
331 }
332
333 static ram_addr_t qxl_rom_size(void)
334 {
335 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
336 #define QXL_ROM_SZ 8192
337
338 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
339 return QXL_ROM_SZ;
340 }
341
342 static void init_qxl_rom(PCIQXLDevice *d)
343 {
344 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
345 QXLModes *modes = (QXLModes *)(rom + 1);
346 uint32_t ram_header_size;
347 uint32_t surface0_area_size;
348 uint32_t num_pages;
349 uint32_t fb;
350 int i, n;
351
352 memset(rom, 0, d->rom_size);
353
354 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
355 rom->id = cpu_to_le32(d->id);
356 rom->log_level = cpu_to_le32(d->guestdebug);
357 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
358
359 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
360 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
361 rom->slots_start = 1;
362 rom->slots_end = NUM_MEMSLOTS - 1;
363 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
364
365 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
366 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
367 if (fb > d->vgamem_size) {
368 continue;
369 }
370 modes->modes[n].id = cpu_to_le32(i);
371 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
372 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
373 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
374 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
375 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
376 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
377 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
378 n++;
379 }
380 modes->n_modes = cpu_to_le32(n);
381
382 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
383 surface0_area_size = ALIGN(d->vgamem_size, 4096);
384 num_pages = d->vga.vram_size;
385 num_pages -= ram_header_size;
386 num_pages -= surface0_area_size;
387 num_pages = num_pages / QXL_PAGE_SIZE;
388
389 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
390
391 rom->draw_area_offset = cpu_to_le32(0);
392 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
393 rom->pages_offset = cpu_to_le32(surface0_area_size);
394 rom->num_pages = cpu_to_le32(num_pages);
395 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
396
397 if (d->xres && d->yres) {
398 /* needs linux kernel 4.12+ to work */
399 rom->client_monitors_config.count = 1;
400 rom->client_monitors_config.heads[0].left = 0;
401 rom->client_monitors_config.heads[0].top = 0;
402 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
403 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
404 rom->client_monitors_config_crc = qxl_crc32(
405 (const uint8_t *)&rom->client_monitors_config,
406 sizeof(rom->client_monitors_config));
407 }
408
409 d->shadow_rom = *rom;
410 d->rom = rom;
411 d->modes = modes;
412 }
413
414 static void init_qxl_ram(PCIQXLDevice *d)
415 {
416 uint8_t *buf;
417 uint64_t *item;
418
419 buf = d->vga.vram_ptr;
420 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
421 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
422 d->ram->int_pending = cpu_to_le32(0);
423 d->ram->int_mask = cpu_to_le32(0);
424 d->ram->update_surface = 0;
425 d->ram->monitors_config = 0;
426 SPICE_RING_INIT(&d->ram->cmd_ring);
427 SPICE_RING_INIT(&d->ram->cursor_ring);
428 SPICE_RING_INIT(&d->ram->release_ring);
429 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
430 assert(item);
431 *item = 0;
432 qxl_ring_set_dirty(d);
433 }
434
435 /* can be called from spice server thread context */
436 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
437 {
438 memory_region_set_dirty(mr, addr, end - addr);
439 }
440
441 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
442 {
443 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
444 }
445
446 /* called from spice server thread context only */
447 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
448 {
449 void *base = qxl->vga.vram_ptr;
450 intptr_t offset;
451
452 offset = ptr - base;
453 assert(offset < qxl->vga.vram_size);
454 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
455 }
456
457 /* can be called from spice server thread context */
458 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
459 {
460 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
461 ram_addr_t end = qxl->vga.vram_size;
462 qxl_set_dirty(&qxl->vga.vram, addr, end);
463 }
464
465 /*
466 * keep track of some command state, for savevm/loadvm.
467 * called from spice server thread context only
468 */
469 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
470 {
471 switch (le32_to_cpu(ext->cmd.type)) {
472 case QXL_CMD_SURFACE:
473 {
474 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
475
476 if (!cmd) {
477 return 1;
478 }
479 uint32_t id = le32_to_cpu(cmd->surface_id);
480
481 if (id >= qxl->ssd.num_surfaces) {
482 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
483 qxl->ssd.num_surfaces);
484 return 1;
485 }
486 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
487 (cmd->u.surface_create.stride & 0x03) != 0) {
488 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
489 cmd->u.surface_create.stride);
490 return 1;
491 }
492 qemu_mutex_lock(&qxl->track_lock);
493 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
494 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
495 qxl->guest_surfaces.count++;
496 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
497 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
498 }
499 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
500 qxl->guest_surfaces.cmds[id] = 0;
501 qxl->guest_surfaces.count--;
502 }
503 qemu_mutex_unlock(&qxl->track_lock);
504 break;
505 }
506 case QXL_CMD_CURSOR:
507 {
508 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
509
510 if (!cmd) {
511 return 1;
512 }
513 if (cmd->type == QXL_CURSOR_SET) {
514 qemu_mutex_lock(&qxl->track_lock);
515 qxl->guest_cursor = ext->cmd.data;
516 qemu_mutex_unlock(&qxl->track_lock);
517 }
518 if (cmd->type == QXL_CURSOR_HIDE) {
519 qemu_mutex_lock(&qxl->track_lock);
520 qxl->guest_cursor = 0;
521 qemu_mutex_unlock(&qxl->track_lock);
522 }
523 break;
524 }
525 }
526 return 0;
527 }
528
529 /* spice display interface callbacks */
530
531 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
532 {
533 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
534
535 trace_qxl_interface_attach_worker(qxl->id);
536 }
537
538 static void interface_set_compression_level(QXLInstance *sin, int level)
539 {
540 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
541
542 trace_qxl_interface_set_compression_level(qxl->id, level);
543 qxl->shadow_rom.compression_level = cpu_to_le32(level);
544 qxl->rom->compression_level = cpu_to_le32(level);
545 qxl_rom_set_dirty(qxl);
546 }
547
548 #if SPICE_NEEDS_SET_MM_TIME
549 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
550 {
551 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
552
553 if (!qemu_spice_display_is_running(&qxl->ssd)) {
554 return;
555 }
556
557 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
558 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
559 qxl->rom->mm_clock = cpu_to_le32(mm_time);
560 qxl_rom_set_dirty(qxl);
561 }
562 #endif
563
564 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
565 {
566 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
567
568 trace_qxl_interface_get_init_info(qxl->id);
569 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
570 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
571 info->num_memslots = NUM_MEMSLOTS;
572 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
573 info->internal_groupslot_id = 0;
574 info->qxl_ram_size =
575 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
576 info->n_surfaces = qxl->ssd.num_surfaces;
577 }
578
579 static const char *qxl_mode_to_string(int mode)
580 {
581 switch (mode) {
582 case QXL_MODE_COMPAT:
583 return "compat";
584 case QXL_MODE_NATIVE:
585 return "native";
586 case QXL_MODE_UNDEFINED:
587 return "undefined";
588 case QXL_MODE_VGA:
589 return "vga";
590 }
591 return "INVALID";
592 }
593
594 static const char *io_port_to_string(uint32_t io_port)
595 {
596 if (io_port >= QXL_IO_RANGE_SIZE) {
597 return "out of range";
598 }
599 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
600 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
601 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
602 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
603 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
604 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
605 [QXL_IO_RESET] = "QXL_IO_RESET",
606 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
607 [QXL_IO_LOG] = "QXL_IO_LOG",
608 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
609 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
610 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
611 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
612 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
613 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
614 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
615 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
616 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
617 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
618 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
619 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
620 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
621 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
622 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
623 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
624 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
625 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
626 };
627 return io_port_to_string[io_port];
628 }
629
630 /* called from spice server thread context only */
631 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
632 {
633 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
634 SimpleSpiceUpdate *update;
635 QXLCommandRing *ring;
636 QXLCommand *cmd;
637 int notify, ret;
638
639 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
640
641 switch (qxl->mode) {
642 case QXL_MODE_VGA:
643 ret = false;
644 qemu_mutex_lock(&qxl->ssd.lock);
645 update = QTAILQ_FIRST(&qxl->ssd.updates);
646 if (update != NULL) {
647 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
648 *ext = update->ext;
649 ret = true;
650 }
651 qemu_mutex_unlock(&qxl->ssd.lock);
652 if (ret) {
653 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
654 qxl_log_command(qxl, "vga", ext);
655 }
656 return ret;
657 case QXL_MODE_COMPAT:
658 case QXL_MODE_NATIVE:
659 case QXL_MODE_UNDEFINED:
660 ring = &qxl->ram->cmd_ring;
661 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
662 return false;
663 }
664 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
665 if (!cmd) {
666 return false;
667 }
668 ext->cmd = *cmd;
669 ext->group_id = MEMSLOT_GROUP_GUEST;
670 ext->flags = qxl->cmdflags;
671 SPICE_RING_POP(ring, notify);
672 qxl_ring_set_dirty(qxl);
673 if (notify) {
674 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
675 }
676 qxl->guest_primary.commands++;
677 qxl_track_command(qxl, ext);
678 qxl_log_command(qxl, "cmd", ext);
679 {
680 /*
681 * Windows 8 drivers place qxl commands in the vram
682 * (instead of the ram) bar. We can't live migrate such a
683 * guest, so add a migration blocker in case we detect
684 * this, to avoid triggering the assert in pre_save().
685 *
686 * https://cgit.freedesktop.org/spice/win32/qxl-wddm-dod/commit/?id=f6e099db39e7d0787f294d5fd0dce328b5210faa
687 */
688 void *msg = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
689 if (msg != NULL && (
690 msg < (void *)qxl->vga.vram_ptr ||
691 msg > ((void *)qxl->vga.vram_ptr + qxl->vga.vram_size))) {
692 if (!qxl->migration_blocker) {
693 Error *local_err = NULL;
694 error_setg(&qxl->migration_blocker,
695 "qxl: guest bug: command not in ram bar");
696 migrate_add_blocker(qxl->migration_blocker, &local_err);
697 if (local_err) {
698 error_report_err(local_err);
699 }
700 }
701 }
702 }
703 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
704 return true;
705 default:
706 return false;
707 }
708 }
709
710 /* called from spice server thread context only */
711 static int interface_req_cmd_notification(QXLInstance *sin)
712 {
713 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
714 int wait = 1;
715
716 trace_qxl_ring_command_req_notification(qxl->id);
717 switch (qxl->mode) {
718 case QXL_MODE_COMPAT:
719 case QXL_MODE_NATIVE:
720 case QXL_MODE_UNDEFINED:
721 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
722 qxl_ring_set_dirty(qxl);
723 break;
724 default:
725 /* nothing */
726 break;
727 }
728 return wait;
729 }
730
731 /* called from spice server thread context only */
732 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
733 {
734 QXLReleaseRing *ring = &d->ram->release_ring;
735 uint64_t *item;
736 int notify;
737
738 #define QXL_FREE_BUNCH_SIZE 32
739
740 if (ring->prod - ring->cons + 1 == ring->num_items) {
741 /* ring full -- can't push */
742 return;
743 }
744 if (!flush && d->oom_running) {
745 /* collect everything from oom handler before pushing */
746 return;
747 }
748 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
749 /* collect a bit more before pushing */
750 return;
751 }
752
753 SPICE_RING_PUSH(ring, notify);
754 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
755 d->guest_surfaces.count, d->num_free_res,
756 d->last_release, notify ? "yes" : "no");
757 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
758 ring->num_items, ring->prod, ring->cons);
759 if (notify) {
760 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
761 }
762 SPICE_RING_PROD_ITEM(d, ring, item);
763 if (!item) {
764 return;
765 }
766 *item = 0;
767 d->num_free_res = 0;
768 d->last_release = NULL;
769 qxl_ring_set_dirty(d);
770 }
771
772 /* called from spice server thread context only */
773 static void interface_release_resource(QXLInstance *sin,
774 QXLReleaseInfoExt ext)
775 {
776 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
777 QXLReleaseRing *ring;
778 uint64_t *item, id;
779
780 if (!ext.info) {
781 return;
782 }
783 if (ext.group_id == MEMSLOT_GROUP_HOST) {
784 /* host group -> vga mode update request */
785 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
786 SimpleSpiceUpdate *update;
787 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
788 update = container_of(cmdext, SimpleSpiceUpdate, ext);
789 qemu_spice_destroy_update(&qxl->ssd, update);
790 return;
791 }
792
793 /*
794 * ext->info points into guest-visible memory
795 * pci bar 0, $command.release_info
796 */
797 ring = &qxl->ram->release_ring;
798 SPICE_RING_PROD_ITEM(qxl, ring, item);
799 if (!item) {
800 return;
801 }
802 if (*item == 0) {
803 /* stick head into the ring */
804 id = ext.info->id;
805 ext.info->next = 0;
806 qxl_ram_set_dirty(qxl, &ext.info->next);
807 *item = id;
808 qxl_ring_set_dirty(qxl);
809 } else {
810 /* append item to the list */
811 qxl->last_release->next = ext.info->id;
812 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
813 ext.info->next = 0;
814 qxl_ram_set_dirty(qxl, &ext.info->next);
815 }
816 qxl->last_release = ext.info;
817 qxl->num_free_res++;
818 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
819 qxl_push_free_res(qxl, 0);
820 }
821
822 /* called from spice server thread context only */
823 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
824 {
825 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
826 QXLCursorRing *ring;
827 QXLCommand *cmd;
828 int notify;
829
830 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
831
832 switch (qxl->mode) {
833 case QXL_MODE_COMPAT:
834 case QXL_MODE_NATIVE:
835 case QXL_MODE_UNDEFINED:
836 ring = &qxl->ram->cursor_ring;
837 if (SPICE_RING_IS_EMPTY(ring)) {
838 return false;
839 }
840 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
841 if (!cmd) {
842 return false;
843 }
844 ext->cmd = *cmd;
845 ext->group_id = MEMSLOT_GROUP_GUEST;
846 ext->flags = qxl->cmdflags;
847 SPICE_RING_POP(ring, notify);
848 qxl_ring_set_dirty(qxl);
849 if (notify) {
850 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
851 }
852 qxl->guest_primary.commands++;
853 qxl_track_command(qxl, ext);
854 qxl_log_command(qxl, "csr", ext);
855 if (qxl->have_vga) {
856 qxl_render_cursor(qxl, ext);
857 }
858 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
859 return true;
860 default:
861 return false;
862 }
863 }
864
865 /* called from spice server thread context only */
866 static int interface_req_cursor_notification(QXLInstance *sin)
867 {
868 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
869 int wait = 1;
870
871 trace_qxl_ring_cursor_req_notification(qxl->id);
872 switch (qxl->mode) {
873 case QXL_MODE_COMPAT:
874 case QXL_MODE_NATIVE:
875 case QXL_MODE_UNDEFINED:
876 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
877 qxl_ring_set_dirty(qxl);
878 break;
879 default:
880 /* nothing */
881 break;
882 }
883 return wait;
884 }
885
886 /* called from spice server thread context */
887 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
888 {
889 /*
890 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
891 * use by xf86-video-qxl and is defined out in the qxl windows driver.
892 * Probably was at some earlier version that is prior to git start (2009),
893 * and is still guest trigerrable.
894 */
895 fprintf(stderr, "%s: deprecated\n", __func__);
896 }
897
898 /* called from spice server thread context only */
899 static int interface_flush_resources(QXLInstance *sin)
900 {
901 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
902 int ret;
903
904 ret = qxl->num_free_res;
905 if (ret) {
906 qxl_push_free_res(qxl, 1);
907 }
908 return ret;
909 }
910
911 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
912
913 /* called from spice server thread context only */
914 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
915 {
916 uint32_t current_async;
917
918 qemu_mutex_lock(&qxl->async_lock);
919 current_async = qxl->current_async;
920 qxl->current_async = QXL_UNDEFINED_IO;
921 qemu_mutex_unlock(&qxl->async_lock);
922
923 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
924 if (!cookie) {
925 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
926 return;
927 }
928 if (cookie && current_async != cookie->io) {
929 fprintf(stderr,
930 "qxl: %s: error: current_async = %d != %"
931 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
932 }
933 switch (current_async) {
934 case QXL_IO_MEMSLOT_ADD_ASYNC:
935 case QXL_IO_DESTROY_PRIMARY_ASYNC:
936 case QXL_IO_UPDATE_AREA_ASYNC:
937 case QXL_IO_FLUSH_SURFACES_ASYNC:
938 case QXL_IO_MONITORS_CONFIG_ASYNC:
939 break;
940 case QXL_IO_CREATE_PRIMARY_ASYNC:
941 qxl_create_guest_primary_complete(qxl);
942 break;
943 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
944 qxl_spice_destroy_surfaces_complete(qxl);
945 break;
946 case QXL_IO_DESTROY_SURFACE_ASYNC:
947 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
948 break;
949 default:
950 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
951 current_async);
952 }
953 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
954 }
955
956 /* called from spice server thread context only */
957 static void interface_update_area_complete(QXLInstance *sin,
958 uint32_t surface_id,
959 QXLRect *dirty, uint32_t num_updated_rects)
960 {
961 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
962 int i;
963 int qxl_i;
964
965 qemu_mutex_lock(&qxl->ssd.lock);
966 if (surface_id != 0 || !num_updated_rects ||
967 !qxl->render_update_cookie_num) {
968 qemu_mutex_unlock(&qxl->ssd.lock);
969 return;
970 }
971 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
972 dirty->right, dirty->top, dirty->bottom);
973 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
974 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
975 /*
976 * overflow - treat this as a full update. Not expected to be common.
977 */
978 trace_qxl_interface_update_area_complete_overflow(qxl->id,
979 QXL_NUM_DIRTY_RECTS);
980 qxl->guest_primary.resized = 1;
981 }
982 if (qxl->guest_primary.resized) {
983 /*
984 * Don't bother copying or scheduling the bh since we will flip
985 * the whole area anyway on completion of the update_area async call
986 */
987 qemu_mutex_unlock(&qxl->ssd.lock);
988 return;
989 }
990 qxl_i = qxl->num_dirty_rects;
991 for (i = 0; i < num_updated_rects; i++) {
992 qxl->dirty[qxl_i++] = dirty[i];
993 }
994 qxl->num_dirty_rects += num_updated_rects;
995 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
996 qxl->num_dirty_rects);
997 qemu_bh_schedule(qxl->update_area_bh);
998 qemu_mutex_unlock(&qxl->ssd.lock);
999 }
1000
1001 /* called from spice server thread context only */
1002 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
1003 {
1004 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1005 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
1006
1007 switch (cookie->type) {
1008 case QXL_COOKIE_TYPE_IO:
1009 interface_async_complete_io(qxl, cookie);
1010 g_free(cookie);
1011 break;
1012 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
1013 qxl_render_update_area_done(qxl, cookie);
1014 break;
1015 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
1016 break;
1017 default:
1018 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
1019 __func__, cookie->type);
1020 g_free(cookie);
1021 }
1022 }
1023
1024 /* called from spice server thread context only */
1025 static void interface_set_client_capabilities(QXLInstance *sin,
1026 uint8_t client_present,
1027 uint8_t caps[58])
1028 {
1029 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1030
1031 if (qxl->revision < 4) {
1032 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1033 qxl->revision);
1034 return;
1035 }
1036
1037 if (runstate_check(RUN_STATE_INMIGRATE) ||
1038 runstate_check(RUN_STATE_POSTMIGRATE)) {
1039 return;
1040 }
1041
1042 qxl->shadow_rom.client_present = client_present;
1043 memcpy(qxl->shadow_rom.client_capabilities, caps,
1044 sizeof(qxl->shadow_rom.client_capabilities));
1045 qxl->rom->client_present = client_present;
1046 memcpy(qxl->rom->client_capabilities, caps,
1047 sizeof(qxl->rom->client_capabilities));
1048 qxl_rom_set_dirty(qxl);
1049
1050 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1051 }
1052
1053 static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1054 VDAgentMonitorsConfig *monitors_config,
1055 unsigned int max_outputs)
1056 {
1057 int i;
1058 unsigned int monitors_count;
1059
1060 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1061
1062 if (rom->client_monitors_config.count != monitors_count) {
1063 return true;
1064 }
1065
1066 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1067 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1068 QXLURect *rect = &rom->client_monitors_config.heads[i];
1069 /* monitor->depth ignored */
1070 if ((rect->left != monitor->x) ||
1071 (rect->top != monitor->y) ||
1072 (rect->right != monitor->x + monitor->width) ||
1073 (rect->bottom != monitor->y + monitor->height)) {
1074 return true;
1075 }
1076 }
1077
1078 return false;
1079 }
1080
1081 /* called from main context only */
1082 static int interface_client_monitors_config(QXLInstance *sin,
1083 VDAgentMonitorsConfig *monitors_config)
1084 {
1085 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1086 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1087 int i;
1088 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1089 bool config_changed = false;
1090
1091 if (qxl->revision < 4) {
1092 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1093 qxl->revision);
1094 return 0;
1095 }
1096 /*
1097 * Older windows drivers set int_mask to 0 when their ISR is called,
1098 * then later set it to ~0. So it doesn't relate to the actual interrupts
1099 * handled. However, they are old, so clearly they don't support this
1100 * interrupt
1101 */
1102 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1103 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1104 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1105 qxl->ram->int_mask,
1106 monitors_config);
1107 return 0;
1108 }
1109 if (!monitors_config) {
1110 return 1;
1111 }
1112
1113 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
1114 /* limit number of outputs based on setting limit */
1115 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1116 max_outputs = qxl->max_outputs;
1117 }
1118 #endif
1119
1120 config_changed = qxl_rom_monitors_config_changed(rom,
1121 monitors_config,
1122 max_outputs);
1123
1124 memset(&rom->client_monitors_config, 0,
1125 sizeof(rom->client_monitors_config));
1126 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1127 /* monitors_config->flags ignored */
1128 if (rom->client_monitors_config.count >= max_outputs) {
1129 trace_qxl_client_monitors_config_capped(qxl->id,
1130 monitors_config->num_of_monitors,
1131 max_outputs);
1132 rom->client_monitors_config.count = max_outputs;
1133 }
1134 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1135 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1136 QXLURect *rect = &rom->client_monitors_config.heads[i];
1137 /* monitor->depth ignored */
1138 rect->left = monitor->x;
1139 rect->top = monitor->y;
1140 rect->right = monitor->x + monitor->width;
1141 rect->bottom = monitor->y + monitor->height;
1142 }
1143 rom->client_monitors_config_crc = qxl_crc32(
1144 (const uint8_t *)&rom->client_monitors_config,
1145 sizeof(rom->client_monitors_config));
1146 trace_qxl_client_monitors_config_crc(qxl->id,
1147 sizeof(rom->client_monitors_config),
1148 rom->client_monitors_config_crc);
1149
1150 trace_qxl_interrupt_client_monitors_config(qxl->id,
1151 rom->client_monitors_config.count,
1152 rom->client_monitors_config.heads);
1153 if (config_changed) {
1154 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1155 }
1156 return 1;
1157 }
1158
1159 static const QXLInterface qxl_interface = {
1160 .base.type = SPICE_INTERFACE_QXL,
1161 .base.description = "qxl gpu",
1162 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1163 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1164
1165 .attache_worker = interface_attach_worker,
1166 .set_compression_level = interface_set_compression_level,
1167 #if SPICE_NEEDS_SET_MM_TIME
1168 .set_mm_time = interface_set_mm_time,
1169 #endif
1170 .get_init_info = interface_get_init_info,
1171
1172 /* the callbacks below are called from spice server thread context */
1173 .get_command = interface_get_command,
1174 .req_cmd_notification = interface_req_cmd_notification,
1175 .release_resource = interface_release_resource,
1176 .get_cursor_command = interface_get_cursor_command,
1177 .req_cursor_notification = interface_req_cursor_notification,
1178 .notify_update = interface_notify_update,
1179 .flush_resources = interface_flush_resources,
1180 .async_complete = interface_async_complete,
1181 .update_area_complete = interface_update_area_complete,
1182 .set_client_capabilities = interface_set_client_capabilities,
1183 .client_monitors_config = interface_client_monitors_config,
1184 };
1185
1186 static const GraphicHwOps qxl_ops = {
1187 .gfx_update = qxl_hw_update,
1188 };
1189
1190 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1191 {
1192 if (d->mode == QXL_MODE_VGA) {
1193 return;
1194 }
1195 trace_qxl_enter_vga_mode(d->id);
1196 spice_qxl_driver_unload(&d->ssd.qxl);
1197 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1198 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1199 qemu_spice_create_host_primary(&d->ssd);
1200 d->mode = QXL_MODE_VGA;
1201 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1202 vga_dirty_log_start(&d->vga);
1203 graphic_hw_update(d->vga.con);
1204 }
1205
1206 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1207 {
1208 if (d->mode != QXL_MODE_VGA) {
1209 return;
1210 }
1211 trace_qxl_exit_vga_mode(d->id);
1212 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1213 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1214 vga_dirty_log_stop(&d->vga);
1215 qxl_destroy_primary(d, QXL_SYNC);
1216 }
1217
1218 static void qxl_update_irq(PCIQXLDevice *d)
1219 {
1220 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1221 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1222 int level = !!(pending & mask);
1223 pci_set_irq(&d->pci, level);
1224 qxl_ring_set_dirty(d);
1225 }
1226
1227 static void qxl_check_state(PCIQXLDevice *d)
1228 {
1229 QXLRam *ram = d->ram;
1230 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1231
1232 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1233 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1234 }
1235
1236 static void qxl_reset_state(PCIQXLDevice *d)
1237 {
1238 QXLRom *rom = d->rom;
1239
1240 qxl_check_state(d);
1241 d->shadow_rom.update_id = cpu_to_le32(0);
1242 *rom = d->shadow_rom;
1243 qxl_rom_set_dirty(d);
1244 init_qxl_ram(d);
1245 d->num_free_res = 0;
1246 d->last_release = NULL;
1247 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1248 qxl_update_irq(d);
1249 }
1250
1251 static void qxl_soft_reset(PCIQXLDevice *d)
1252 {
1253 trace_qxl_soft_reset(d->id);
1254 qxl_check_state(d);
1255 qxl_clear_guest_bug(d);
1256 qemu_mutex_lock(&d->async_lock);
1257 d->current_async = QXL_UNDEFINED_IO;
1258 qemu_mutex_unlock(&d->async_lock);
1259
1260 if (d->have_vga) {
1261 qxl_enter_vga_mode(d);
1262 } else {
1263 d->mode = QXL_MODE_UNDEFINED;
1264 }
1265 }
1266
1267 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1268 {
1269 bool startstop = qemu_spice_display_is_running(&d->ssd);
1270
1271 trace_qxl_hard_reset(d->id, loadvm);
1272
1273 if (startstop) {
1274 qemu_spice_display_stop();
1275 }
1276
1277 qxl_spice_reset_cursor(d);
1278 qxl_spice_reset_image_cache(d);
1279 qxl_reset_surfaces(d);
1280 qxl_reset_memslots(d);
1281
1282 /* pre loadvm reset must not touch QXLRam. This lives in
1283 * device memory, is migrated together with RAM and thus
1284 * already loaded at this point */
1285 if (!loadvm) {
1286 qxl_reset_state(d);
1287 }
1288 qemu_spice_create_host_memslot(&d->ssd);
1289 qxl_soft_reset(d);
1290
1291 if (d->migration_blocker) {
1292 migrate_del_blocker(d->migration_blocker);
1293 error_free(d->migration_blocker);
1294 d->migration_blocker = NULL;
1295 }
1296
1297 if (startstop) {
1298 qemu_spice_display_start();
1299 }
1300 }
1301
1302 static void qxl_reset_handler(DeviceState *dev)
1303 {
1304 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1305
1306 qxl_hard_reset(d, 0);
1307 }
1308
1309 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1310 {
1311 VGACommonState *vga = opaque;
1312 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1313
1314 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1315 if (qxl->mode != QXL_MODE_VGA) {
1316 qxl_destroy_primary(qxl, QXL_SYNC);
1317 qxl_soft_reset(qxl);
1318 }
1319 vga_ioport_write(opaque, addr, val);
1320 }
1321
1322 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1323 { 0x04, 2, 1, .read = vga_ioport_read,
1324 .write = qxl_vga_ioport_write }, /* 3b4 */
1325 { 0x0a, 1, 1, .read = vga_ioport_read,
1326 .write = qxl_vga_ioport_write }, /* 3ba */
1327 { 0x10, 16, 1, .read = vga_ioport_read,
1328 .write = qxl_vga_ioport_write }, /* 3c0 */
1329 { 0x24, 2, 1, .read = vga_ioport_read,
1330 .write = qxl_vga_ioport_write }, /* 3d4 */
1331 { 0x2a, 1, 1, .read = vga_ioport_read,
1332 .write = qxl_vga_ioport_write }, /* 3da */
1333 PORTIO_END_OF_LIST(),
1334 };
1335
1336 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1337 qxl_async_io async)
1338 {
1339 static const int regions[] = {
1340 QXL_RAM_RANGE_INDEX,
1341 QXL_VRAM_RANGE_INDEX,
1342 QXL_VRAM64_RANGE_INDEX,
1343 };
1344 uint64_t guest_start;
1345 uint64_t guest_end;
1346 int pci_region;
1347 pcibus_t pci_start;
1348 pcibus_t pci_end;
1349 MemoryRegion *mr;
1350 intptr_t virt_start;
1351 QXLDevMemSlot memslot;
1352 int i;
1353
1354 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1355 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1356
1357 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1358
1359 if (slot_id >= NUM_MEMSLOTS) {
1360 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1361 slot_id, NUM_MEMSLOTS);
1362 return 1;
1363 }
1364 if (guest_start > guest_end) {
1365 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1366 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1367 return 1;
1368 }
1369
1370 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1371 pci_region = regions[i];
1372 pci_start = d->pci.io_regions[pci_region].addr;
1373 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1374 /* mapped? */
1375 if (pci_start == -1) {
1376 continue;
1377 }
1378 /* start address in range ? */
1379 if (guest_start < pci_start || guest_start > pci_end) {
1380 continue;
1381 }
1382 /* end address in range ? */
1383 if (guest_end > pci_end) {
1384 continue;
1385 }
1386 /* passed */
1387 break;
1388 }
1389 if (i == ARRAY_SIZE(regions)) {
1390 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1391 return 1;
1392 }
1393
1394 switch (pci_region) {
1395 case QXL_RAM_RANGE_INDEX:
1396 mr = &d->vga.vram;
1397 break;
1398 case QXL_VRAM_RANGE_INDEX:
1399 case 4 /* vram 64bit */:
1400 mr = &d->vram_bar;
1401 break;
1402 default:
1403 /* should not happen */
1404 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1405 return 1;
1406 }
1407
1408 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1409 memslot.slot_id = slot_id;
1410 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1411 memslot.virt_start = virt_start + (guest_start - pci_start);
1412 memslot.virt_end = virt_start + (guest_end - pci_start);
1413 memslot.addr_delta = memslot.virt_start - delta;
1414 memslot.generation = d->rom->slot_generation = 0;
1415 qxl_rom_set_dirty(d);
1416
1417 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1418 d->guest_slots[slot_id].mr = mr;
1419 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1420 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1421 d->guest_slots[slot_id].delta = delta;
1422 d->guest_slots[slot_id].active = 1;
1423 return 0;
1424 }
1425
1426 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1427 {
1428 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1429 d->guest_slots[slot_id].active = 0;
1430 }
1431
1432 static void qxl_reset_memslots(PCIQXLDevice *d)
1433 {
1434 qxl_spice_reset_memslots(d);
1435 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1436 }
1437
1438 static void qxl_reset_surfaces(PCIQXLDevice *d)
1439 {
1440 trace_qxl_reset_surfaces(d->id);
1441 d->mode = QXL_MODE_UNDEFINED;
1442 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1443 }
1444
1445 /* can be also called from spice server thread context */
1446 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1447 uint32_t *s, uint64_t *o)
1448 {
1449 uint64_t phys = le64_to_cpu(pqxl);
1450 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1451 uint64_t offset = phys & 0xffffffffffff;
1452
1453 if (slot >= NUM_MEMSLOTS) {
1454 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1455 NUM_MEMSLOTS);
1456 return false;
1457 }
1458 if (!qxl->guest_slots[slot].active) {
1459 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1460 return false;
1461 }
1462 if (offset < qxl->guest_slots[slot].delta) {
1463 qxl_set_guest_bug(qxl,
1464 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1465 slot, offset, qxl->guest_slots[slot].delta);
1466 return false;
1467 }
1468 offset -= qxl->guest_slots[slot].delta;
1469 if (offset > qxl->guest_slots[slot].size) {
1470 qxl_set_guest_bug(qxl,
1471 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1472 slot, offset, qxl->guest_slots[slot].size);
1473 return false;
1474 }
1475
1476 *s = slot;
1477 *o = offset;
1478 return true;
1479 }
1480
1481 /* can be also called from spice server thread context */
1482 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1483 {
1484 uint64_t offset;
1485 uint32_t slot;
1486 void *ptr;
1487
1488 switch (group_id) {
1489 case MEMSLOT_GROUP_HOST:
1490 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1491 return (void *)(intptr_t)offset;
1492 case MEMSLOT_GROUP_GUEST:
1493 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
1494 return NULL;
1495 }
1496 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1497 ptr += qxl->guest_slots[slot].offset;
1498 ptr += offset;
1499 return ptr;
1500 }
1501 return NULL;
1502 }
1503
1504 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1505 {
1506 /* for local rendering */
1507 qxl_render_resize(qxl);
1508 }
1509
1510 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1511 qxl_async_io async)
1512 {
1513 QXLDevSurfaceCreate surface;
1514 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1515 uint32_t requested_height = le32_to_cpu(sc->height);
1516 int requested_stride = le32_to_cpu(sc->stride);
1517
1518 if (requested_stride == INT32_MIN ||
1519 abs(requested_stride) * (uint64_t)requested_height
1520 > qxl->vgamem_size) {
1521 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1522 " stride %d x height %" PRIu32 " > %" PRIu32,
1523 __func__, requested_stride, requested_height,
1524 qxl->vgamem_size);
1525 return;
1526 }
1527
1528 if (qxl->mode == QXL_MODE_NATIVE) {
1529 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1530 __func__);
1531 }
1532 qxl_exit_vga_mode(qxl);
1533
1534 surface.format = le32_to_cpu(sc->format);
1535 surface.height = le32_to_cpu(sc->height);
1536 surface.mem = le64_to_cpu(sc->mem);
1537 surface.position = le32_to_cpu(sc->position);
1538 surface.stride = le32_to_cpu(sc->stride);
1539 surface.width = le32_to_cpu(sc->width);
1540 surface.type = le32_to_cpu(sc->type);
1541 surface.flags = le32_to_cpu(sc->flags);
1542 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1543 sc->format, sc->position);
1544 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1545 sc->flags);
1546
1547 if ((surface.stride & 0x3) != 0) {
1548 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1549 surface.stride);
1550 return;
1551 }
1552
1553 surface.mouse_mode = true;
1554 surface.group_id = MEMSLOT_GROUP_GUEST;
1555 if (loadvm) {
1556 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1557 }
1558
1559 qxl->mode = QXL_MODE_NATIVE;
1560 qxl->cmdflags = 0;
1561 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1562
1563 if (async == QXL_SYNC) {
1564 qxl_create_guest_primary_complete(qxl);
1565 }
1566 }
1567
1568 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1569 * done (in QXL_SYNC case), 0 otherwise. */
1570 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1571 {
1572 if (d->mode == QXL_MODE_UNDEFINED) {
1573 return 0;
1574 }
1575 trace_qxl_destroy_primary(d->id);
1576 d->mode = QXL_MODE_UNDEFINED;
1577 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1578 qxl_spice_reset_cursor(d);
1579 return 1;
1580 }
1581
1582 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1583 {
1584 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1585 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1586 QXLMode *mode = d->modes->modes + modenr;
1587 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1588 QXLMemSlot slot = {
1589 .mem_start = start,
1590 .mem_end = end
1591 };
1592
1593 if (modenr >= d->modes->n_modes) {
1594 qxl_set_guest_bug(d, "mode number out of range");
1595 return;
1596 }
1597
1598 QXLSurfaceCreate surface = {
1599 .width = mode->x_res,
1600 .height = mode->y_res,
1601 .stride = -mode->x_res * 4,
1602 .format = SPICE_SURFACE_FMT_32_xRGB,
1603 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1604 .mouse_mode = true,
1605 .mem = devmem + d->shadow_rom.draw_area_offset,
1606 };
1607
1608 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1609 devmem);
1610 if (!loadvm) {
1611 qxl_hard_reset(d, 0);
1612 }
1613
1614 d->guest_slots[0].slot = slot;
1615 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1616
1617 d->guest_primary.surface = surface;
1618 qxl_create_guest_primary(d, 0, QXL_SYNC);
1619
1620 d->mode = QXL_MODE_COMPAT;
1621 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1622 if (mode->bits == 16) {
1623 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1624 }
1625 d->shadow_rom.mode = cpu_to_le32(modenr);
1626 d->rom->mode = cpu_to_le32(modenr);
1627 qxl_rom_set_dirty(d);
1628 }
1629
1630 static void ioport_write(void *opaque, hwaddr addr,
1631 uint64_t val, unsigned size)
1632 {
1633 PCIQXLDevice *d = opaque;
1634 uint32_t io_port = addr;
1635 qxl_async_io async = QXL_SYNC;
1636 uint32_t orig_io_port = io_port;
1637
1638 if (d->guest_bug && io_port != QXL_IO_RESET) {
1639 return;
1640 }
1641
1642 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1643 io_port > QXL_IO_FLUSH_RELEASE) {
1644 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1645 io_port, d->revision);
1646 return;
1647 }
1648
1649 switch (io_port) {
1650 case QXL_IO_RESET:
1651 case QXL_IO_SET_MODE:
1652 case QXL_IO_MEMSLOT_ADD:
1653 case QXL_IO_MEMSLOT_DEL:
1654 case QXL_IO_CREATE_PRIMARY:
1655 case QXL_IO_UPDATE_IRQ:
1656 case QXL_IO_LOG:
1657 case QXL_IO_MEMSLOT_ADD_ASYNC:
1658 case QXL_IO_CREATE_PRIMARY_ASYNC:
1659 break;
1660 default:
1661 if (d->mode != QXL_MODE_VGA) {
1662 break;
1663 }
1664 trace_qxl_io_unexpected_vga_mode(d->id,
1665 addr, val, io_port_to_string(io_port));
1666 /* be nice to buggy guest drivers */
1667 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1668 io_port < QXL_IO_RANGE_SIZE) {
1669 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1670 }
1671 return;
1672 }
1673
1674 /* we change the io_port to avoid ifdeffery in the main switch */
1675 orig_io_port = io_port;
1676 switch (io_port) {
1677 case QXL_IO_UPDATE_AREA_ASYNC:
1678 io_port = QXL_IO_UPDATE_AREA;
1679 goto async_common;
1680 case QXL_IO_MEMSLOT_ADD_ASYNC:
1681 io_port = QXL_IO_MEMSLOT_ADD;
1682 goto async_common;
1683 case QXL_IO_CREATE_PRIMARY_ASYNC:
1684 io_port = QXL_IO_CREATE_PRIMARY;
1685 goto async_common;
1686 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1687 io_port = QXL_IO_DESTROY_PRIMARY;
1688 goto async_common;
1689 case QXL_IO_DESTROY_SURFACE_ASYNC:
1690 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1691 goto async_common;
1692 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1693 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1694 goto async_common;
1695 case QXL_IO_FLUSH_SURFACES_ASYNC:
1696 case QXL_IO_MONITORS_CONFIG_ASYNC:
1697 async_common:
1698 async = QXL_ASYNC;
1699 qemu_mutex_lock(&d->async_lock);
1700 if (d->current_async != QXL_UNDEFINED_IO) {
1701 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1702 io_port, d->current_async);
1703 qemu_mutex_unlock(&d->async_lock);
1704 return;
1705 }
1706 d->current_async = orig_io_port;
1707 qemu_mutex_unlock(&d->async_lock);
1708 break;
1709 default:
1710 break;
1711 }
1712 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1713 addr, io_port_to_string(addr),
1714 val, size, async);
1715
1716 switch (io_port) {
1717 case QXL_IO_UPDATE_AREA:
1718 {
1719 QXLCookie *cookie = NULL;
1720 QXLRect update = d->ram->update_area;
1721
1722 if (d->ram->update_surface > d->ssd.num_surfaces) {
1723 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1724 d->ram->update_surface);
1725 break;
1726 }
1727 if (update.left >= update.right || update.top >= update.bottom ||
1728 update.left < 0 || update.top < 0) {
1729 qxl_set_guest_bug(d,
1730 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1731 update.left, update.top, update.right, update.bottom);
1732 if (update.left == update.right || update.top == update.bottom) {
1733 /* old drivers may provide empty area, keep going */
1734 qxl_clear_guest_bug(d);
1735 goto cancel_async;
1736 }
1737 break;
1738 }
1739 if (async == QXL_ASYNC) {
1740 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1741 QXL_IO_UPDATE_AREA_ASYNC);
1742 cookie->u.area = update;
1743 }
1744 qxl_spice_update_area(d, d->ram->update_surface,
1745 cookie ? &cookie->u.area : &update,
1746 NULL, 0, 0, async, cookie);
1747 break;
1748 }
1749 case QXL_IO_NOTIFY_CMD:
1750 qemu_spice_wakeup(&d->ssd);
1751 break;
1752 case QXL_IO_NOTIFY_CURSOR:
1753 qemu_spice_wakeup(&d->ssd);
1754 break;
1755 case QXL_IO_UPDATE_IRQ:
1756 qxl_update_irq(d);
1757 break;
1758 case QXL_IO_NOTIFY_OOM:
1759 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1760 break;
1761 }
1762 d->oom_running = 1;
1763 qxl_spice_oom(d);
1764 d->oom_running = 0;
1765 break;
1766 case QXL_IO_SET_MODE:
1767 qxl_set_mode(d, val, 0);
1768 break;
1769 case QXL_IO_LOG:
1770 if (TRACE_QXL_IO_LOG_ENABLED || d->guestdebug) {
1771 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1772 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1773 sizeof(d->ram->log_buf));
1774 trace_qxl_io_log(d->id, log_buf);
1775 if (d->guestdebug) {
1776 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1777 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1778 }
1779 g_free(log_buf);
1780 }
1781 break;
1782 case QXL_IO_RESET:
1783 qxl_hard_reset(d, 0);
1784 break;
1785 case QXL_IO_MEMSLOT_ADD:
1786 if (val >= NUM_MEMSLOTS) {
1787 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1788 break;
1789 }
1790 if (d->guest_slots[val].active) {
1791 qxl_set_guest_bug(d,
1792 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1793 break;
1794 }
1795 d->guest_slots[val].slot = d->ram->mem_slot;
1796 qxl_add_memslot(d, val, 0, async);
1797 break;
1798 case QXL_IO_MEMSLOT_DEL:
1799 if (val >= NUM_MEMSLOTS) {
1800 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1801 break;
1802 }
1803 qxl_del_memslot(d, val);
1804 break;
1805 case QXL_IO_CREATE_PRIMARY:
1806 if (val != 0) {
1807 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1808 async);
1809 goto cancel_async;
1810 }
1811 d->guest_primary.surface = d->ram->create_surface;
1812 qxl_create_guest_primary(d, 0, async);
1813 break;
1814 case QXL_IO_DESTROY_PRIMARY:
1815 if (val != 0) {
1816 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1817 async);
1818 goto cancel_async;
1819 }
1820 if (!qxl_destroy_primary(d, async)) {
1821 trace_qxl_io_destroy_primary_ignored(d->id,
1822 qxl_mode_to_string(d->mode));
1823 goto cancel_async;
1824 }
1825 break;
1826 case QXL_IO_DESTROY_SURFACE_WAIT:
1827 if (val >= d->ssd.num_surfaces) {
1828 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1829 "%" PRIu64 " >= NUM_SURFACES", async, val);
1830 goto cancel_async;
1831 }
1832 qxl_spice_destroy_surface_wait(d, val, async);
1833 break;
1834 case QXL_IO_FLUSH_RELEASE: {
1835 QXLReleaseRing *ring = &d->ram->release_ring;
1836 if (ring->prod - ring->cons + 1 == ring->num_items) {
1837 fprintf(stderr,
1838 "ERROR: no flush, full release ring [p%d,%dc]\n",
1839 ring->prod, ring->cons);
1840 }
1841 qxl_push_free_res(d, 1 /* flush */);
1842 break;
1843 }
1844 case QXL_IO_FLUSH_SURFACES_ASYNC:
1845 qxl_spice_flush_surfaces_async(d);
1846 break;
1847 case QXL_IO_DESTROY_ALL_SURFACES:
1848 d->mode = QXL_MODE_UNDEFINED;
1849 qxl_spice_destroy_surfaces(d, async);
1850 break;
1851 case QXL_IO_MONITORS_CONFIG_ASYNC:
1852 qxl_spice_monitors_config_async(d, 0);
1853 break;
1854 default:
1855 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1856 }
1857 return;
1858 cancel_async:
1859 if (async) {
1860 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1861 qemu_mutex_lock(&d->async_lock);
1862 d->current_async = QXL_UNDEFINED_IO;
1863 qemu_mutex_unlock(&d->async_lock);
1864 }
1865 }
1866
1867 static uint64_t ioport_read(void *opaque, hwaddr addr,
1868 unsigned size)
1869 {
1870 PCIQXLDevice *qxl = opaque;
1871
1872 trace_qxl_io_read_unexpected(qxl->id);
1873 return 0xff;
1874 }
1875
1876 static const MemoryRegionOps qxl_io_ops = {
1877 .read = ioport_read,
1878 .write = ioport_write,
1879 .valid = {
1880 .min_access_size = 1,
1881 .max_access_size = 1,
1882 },
1883 };
1884
1885 static void qxl_update_irq_bh(void *opaque)
1886 {
1887 PCIQXLDevice *d = opaque;
1888 qxl_update_irq(d);
1889 }
1890
1891 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1892 {
1893 uint32_t old_pending;
1894 uint32_t le_events = cpu_to_le32(events);
1895
1896 trace_qxl_send_events(d->id, events);
1897 if (!qemu_spice_display_is_running(&d->ssd)) {
1898 /* spice-server tracks guest running state and should not do this */
1899 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1900 __func__);
1901 trace_qxl_send_events_vm_stopped(d->id, events);
1902 return;
1903 }
1904 /*
1905 * Older versions of Spice forgot to define the QXLRam struct
1906 * with the '__aligned__(4)' attribute. clang 7 and newer will
1907 * thus warn that atomic_fetch_or(&d->ram->int_pending, ...)
1908 * might be a misaligned atomic access, and will generate an
1909 * out-of-line call for it, which results in a link error since
1910 * we don't currently link against libatomic.
1911 *
1912 * In fact we set up d->ram in init_qxl_ram() so it always starts
1913 * at a 4K boundary, so we know that &d->ram->int_pending is
1914 * naturally aligned for a uint32_t. Newer Spice versions
1915 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1916 * will fix the bug directly. To deal with older versions,
1917 * we tell the compiler to assume the address really is aligned.
1918 * Any compiler which cares about the misalignment will have
1919 * __builtin_assume_aligned.
1920 */
1921 #ifdef HAS_ASSUME_ALIGNED
1922 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1923 #else
1924 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1925 #endif
1926
1927 old_pending = atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1928 le_events);
1929 if ((old_pending & le_events) == le_events) {
1930 return;
1931 }
1932 qemu_bh_schedule(d->update_irq);
1933 }
1934
1935 /* graphics console */
1936
1937 static void qxl_hw_update(void *opaque)
1938 {
1939 PCIQXLDevice *qxl = opaque;
1940
1941 qxl_render_update(qxl);
1942 }
1943
1944 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1945 uint32_t height, int32_t stride)
1946 {
1947 uint64_t offset, size;
1948 uint32_t slot;
1949 bool rc;
1950
1951 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
1952 assert(rc == true);
1953 size = (uint64_t)height * abs(stride);
1954 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1955 qxl_set_dirty(qxl->guest_slots[slot].mr,
1956 qxl->guest_slots[slot].offset + offset,
1957 qxl->guest_slots[slot].offset + offset + size);
1958 }
1959
1960 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1961 {
1962 int i;
1963
1964 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1965 return;
1966 }
1967
1968 /* dirty the primary surface */
1969 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1970 qxl->guest_primary.surface.height,
1971 qxl->guest_primary.surface.stride);
1972
1973 /* dirty the off-screen surfaces */
1974 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1975 QXLSurfaceCmd *cmd;
1976
1977 if (qxl->guest_surfaces.cmds[i] == 0) {
1978 continue;
1979 }
1980
1981 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1982 MEMSLOT_GROUP_GUEST);
1983 assert(cmd);
1984 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1985 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1986 cmd->u.surface_create.height,
1987 cmd->u.surface_create.stride);
1988 }
1989 }
1990
1991 static void qxl_vm_change_state_handler(void *opaque, int running,
1992 RunState state)
1993 {
1994 PCIQXLDevice *qxl = opaque;
1995
1996 if (running) {
1997 /*
1998 * if qxl_send_events was called from spice server context before
1999 * migration ended, qxl_update_irq for these events might not have been
2000 * called
2001 */
2002 qxl_update_irq(qxl);
2003 } else {
2004 /* make sure surfaces are saved before migration */
2005 qxl_dirty_surfaces(qxl);
2006 }
2007 }
2008
2009 /* display change listener */
2010
2011 static void display_update(DisplayChangeListener *dcl,
2012 int x, int y, int w, int h)
2013 {
2014 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2015
2016 if (qxl->mode == QXL_MODE_VGA) {
2017 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2018 }
2019 }
2020
2021 static void display_switch(DisplayChangeListener *dcl,
2022 struct DisplaySurface *surface)
2023 {
2024 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2025
2026 qxl->ssd.ds = surface;
2027 if (qxl->mode == QXL_MODE_VGA) {
2028 qemu_spice_display_switch(&qxl->ssd, surface);
2029 }
2030 }
2031
2032 static void display_refresh(DisplayChangeListener *dcl)
2033 {
2034 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2035
2036 if (qxl->mode == QXL_MODE_VGA) {
2037 qemu_spice_display_refresh(&qxl->ssd);
2038 }
2039 }
2040
2041 static DisplayChangeListenerOps display_listener_ops = {
2042 .dpy_name = "spice/qxl",
2043 .dpy_gfx_update = display_update,
2044 .dpy_gfx_switch = display_switch,
2045 .dpy_refresh = display_refresh,
2046 };
2047
2048 static void qxl_init_ramsize(PCIQXLDevice *qxl)
2049 {
2050 /* vga mode framebuffer / primary surface (bar 0, first part) */
2051 if (qxl->vgamem_size_mb < 8) {
2052 qxl->vgamem_size_mb = 8;
2053 }
2054 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2055 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2056 */
2057 if (qxl->vgamem_size_mb > 256) {
2058 qxl->vgamem_size_mb = 256;
2059 }
2060 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2061
2062 /* vga ram (bar 0, total) */
2063 if (qxl->ram_size_mb != -1) {
2064 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2065 }
2066 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2067 qxl->vga.vram_size = qxl->vgamem_size * 2;
2068 }
2069
2070 /* vram32 (surfaces, 32bit, bar 1) */
2071 if (qxl->vram32_size_mb != -1) {
2072 qxl->vram32_size = qxl->vram32_size_mb * MiB;
2073 }
2074 if (qxl->vram32_size < 4096) {
2075 qxl->vram32_size = 4096;
2076 }
2077
2078 /* vram (surfaces, 64bit, bar 4+5) */
2079 if (qxl->vram_size_mb != -1) {
2080 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2081 }
2082 if (qxl->vram_size < qxl->vram32_size) {
2083 qxl->vram_size = qxl->vram32_size;
2084 }
2085
2086 if (qxl->revision == 1) {
2087 qxl->vram32_size = 4096;
2088 qxl->vram_size = 4096;
2089 }
2090 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2091 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2092 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2093 qxl->vram_size = pow2ceil(qxl->vram_size);
2094 }
2095
2096 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2097 {
2098 uint8_t* config = qxl->pci.config;
2099 uint32_t pci_device_rev;
2100 uint32_t io_size;
2101
2102 qemu_spice_display_init_common(&qxl->ssd);
2103 qxl->mode = QXL_MODE_UNDEFINED;
2104 qxl->num_memslots = NUM_MEMSLOTS;
2105 qemu_mutex_init(&qxl->track_lock);
2106 qemu_mutex_init(&qxl->async_lock);
2107 qxl->current_async = QXL_UNDEFINED_IO;
2108 qxl->guest_bug = 0;
2109
2110 switch (qxl->revision) {
2111 case 1: /* spice 0.4 -- qxl-1 */
2112 pci_device_rev = QXL_REVISION_STABLE_V04;
2113 io_size = 8;
2114 break;
2115 case 2: /* spice 0.6 -- qxl-2 */
2116 pci_device_rev = QXL_REVISION_STABLE_V06;
2117 io_size = 16;
2118 break;
2119 case 3: /* qxl-3 */
2120 pci_device_rev = QXL_REVISION_STABLE_V10;
2121 io_size = 32; /* PCI region size must be pow2 */
2122 break;
2123 case 4: /* qxl-4 */
2124 pci_device_rev = QXL_REVISION_STABLE_V12;
2125 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2126 break;
2127 default:
2128 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2129 qxl->revision, QXL_DEFAULT_REVISION);
2130 return;
2131 }
2132
2133 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2134 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2135
2136 qxl->rom_size = qxl_rom_size();
2137 memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2138 qxl->rom_size, &error_fatal);
2139 init_qxl_rom(qxl);
2140 init_qxl_ram(qxl);
2141
2142 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2143 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2144 qxl->vram_size, &error_fatal);
2145 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2146 &qxl->vram_bar, 0, qxl->vram32_size);
2147
2148 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2149 "qxl-ioports", io_size);
2150 if (qxl->have_vga) {
2151 vga_dirty_log_start(&qxl->vga);
2152 }
2153 memory_region_set_flush_coalesced(&qxl->io_bar);
2154
2155
2156 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2157 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2158
2159 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2160 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2161
2162 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2163 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2164
2165 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2166 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2167
2168 if (qxl->vram32_size < qxl->vram_size) {
2169 /*
2170 * Make the 64bit vram bar show up only in case it is
2171 * configured to be larger than the 32bit vram bar.
2172 */
2173 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2174 PCI_BASE_ADDRESS_SPACE_MEMORY |
2175 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2176 PCI_BASE_ADDRESS_MEM_PREFETCH,
2177 &qxl->vram_bar);
2178 }
2179
2180 /* print pci bar details */
2181 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2182 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2183 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2184 qxl->vram32_size / MiB);
2185 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2186 qxl->vram_size / MiB,
2187 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2188
2189 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2190 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2191 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2192 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2193 return;
2194 }
2195
2196 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2197 char device_address[256] = "";
2198 if (qemu_spice_fill_device_address(qxl->vga.con, device_address, 256)) {
2199 spice_qxl_set_device_info(&qxl->ssd.qxl,
2200 device_address,
2201 0,
2202 qxl->max_outputs);
2203 }
2204 #endif
2205
2206 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2207
2208 qxl->update_irq = qemu_bh_new(qxl_update_irq_bh, qxl);
2209 qxl_reset_state(qxl);
2210
2211 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2212 qxl->ssd.cursor_bh = qemu_bh_new(qemu_spice_cursor_refresh_bh, &qxl->ssd);
2213 }
2214
2215 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2216 {
2217 PCIQXLDevice *qxl = PCI_QXL(dev);
2218 VGACommonState *vga = &qxl->vga;
2219 Error *local_err = NULL;
2220
2221 qxl_init_ramsize(qxl);
2222 vga->vbe_size = qxl->vgamem_size;
2223 vga->vram_size_mb = qxl->vga.vram_size / MiB;
2224 vga_common_init(vga, OBJECT(dev));
2225 vga_init(vga, OBJECT(dev),
2226 pci_address_space(dev), pci_address_space_io(dev), false);
2227 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2228 vga, "vga");
2229 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2230 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2231 qxl->have_vga = true;
2232
2233 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2234 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2235 if (qxl->id != 0) {
2236 error_setg(errp, "primary qxl-vga device must be console 0 "
2237 "(first display device on the command line)");
2238 return;
2239 }
2240
2241 qxl_realize_common(qxl, &local_err);
2242 if (local_err) {
2243 error_propagate(errp, local_err);
2244 return;
2245 }
2246
2247 qxl->ssd.dcl.ops = &display_listener_ops;
2248 qxl->ssd.dcl.con = vga->con;
2249 register_displaychangelistener(&qxl->ssd.dcl);
2250 }
2251
2252 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2253 {
2254 PCIQXLDevice *qxl = PCI_QXL(dev);
2255
2256 qxl_init_ramsize(qxl);
2257 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2258 qxl->vga.vram_size, &error_fatal);
2259 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2260 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2261 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2262
2263 qxl_realize_common(qxl, errp);
2264 }
2265
2266 static int qxl_pre_save(void *opaque)
2267 {
2268 PCIQXLDevice* d = opaque;
2269 uint8_t *ram_start = d->vga.vram_ptr;
2270
2271 trace_qxl_pre_save(d->id);
2272 if (d->last_release == NULL) {
2273 d->last_release_offset = 0;
2274 } else {
2275 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2276 }
2277 assert(d->last_release_offset < d->vga.vram_size);
2278
2279 return 0;
2280 }
2281
2282 static int qxl_pre_load(void *opaque)
2283 {
2284 PCIQXLDevice* d = opaque;
2285
2286 trace_qxl_pre_load(d->id);
2287 qxl_hard_reset(d, 1);
2288 qxl_exit_vga_mode(d);
2289 return 0;
2290 }
2291
2292 static void qxl_create_memslots(PCIQXLDevice *d)
2293 {
2294 int i;
2295
2296 for (i = 0; i < NUM_MEMSLOTS; i++) {
2297 if (!d->guest_slots[i].active) {
2298 continue;
2299 }
2300 qxl_add_memslot(d, i, 0, QXL_SYNC);
2301 }
2302 }
2303
2304 static int qxl_post_load(void *opaque, int version)
2305 {
2306 PCIQXLDevice* d = opaque;
2307 uint8_t *ram_start = d->vga.vram_ptr;
2308 QXLCommandExt *cmds;
2309 int in, out, newmode;
2310
2311 assert(d->last_release_offset < d->vga.vram_size);
2312 if (d->last_release_offset == 0) {
2313 d->last_release = NULL;
2314 } else {
2315 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2316 }
2317
2318 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2319
2320 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2321 newmode = d->mode;
2322 d->mode = QXL_MODE_UNDEFINED;
2323
2324 switch (newmode) {
2325 case QXL_MODE_UNDEFINED:
2326 qxl_create_memslots(d);
2327 break;
2328 case QXL_MODE_VGA:
2329 qxl_create_memslots(d);
2330 qxl_enter_vga_mode(d);
2331 break;
2332 case QXL_MODE_NATIVE:
2333 qxl_create_memslots(d);
2334 qxl_create_guest_primary(d, 1, QXL_SYNC);
2335
2336 /* replay surface-create and cursor-set commands */
2337 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2338 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2339 if (d->guest_surfaces.cmds[in] == 0) {
2340 continue;
2341 }
2342 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2343 cmds[out].cmd.type = QXL_CMD_SURFACE;
2344 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2345 out++;
2346 }
2347 if (d->guest_cursor) {
2348 cmds[out].cmd.data = d->guest_cursor;
2349 cmds[out].cmd.type = QXL_CMD_CURSOR;
2350 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2351 out++;
2352 }
2353 qxl_spice_loadvm_commands(d, cmds, out);
2354 g_free(cmds);
2355 if (d->guest_monitors_config) {
2356 qxl_spice_monitors_config_async(d, 1);
2357 }
2358 break;
2359 case QXL_MODE_COMPAT:
2360 /* note: no need to call qxl_create_memslots, qxl_set_mode
2361 * creates the mem slot. */
2362 qxl_set_mode(d, d->shadow_rom.mode, 1);
2363 break;
2364 }
2365 return 0;
2366 }
2367
2368 #define QXL_SAVE_VERSION 21
2369
2370 static bool qxl_monitors_config_needed(void *opaque)
2371 {
2372 PCIQXLDevice *qxl = opaque;
2373
2374 return qxl->guest_monitors_config != 0;
2375 }
2376
2377
2378 static VMStateDescription qxl_memslot = {
2379 .name = "qxl-memslot",
2380 .version_id = QXL_SAVE_VERSION,
2381 .minimum_version_id = QXL_SAVE_VERSION,
2382 .fields = (VMStateField[]) {
2383 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2384 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2385 VMSTATE_UINT32(active, struct guest_slots),
2386 VMSTATE_END_OF_LIST()
2387 }
2388 };
2389
2390 static VMStateDescription qxl_surface = {
2391 .name = "qxl-surface",
2392 .version_id = QXL_SAVE_VERSION,
2393 .minimum_version_id = QXL_SAVE_VERSION,
2394 .fields = (VMStateField[]) {
2395 VMSTATE_UINT32(width, QXLSurfaceCreate),
2396 VMSTATE_UINT32(height, QXLSurfaceCreate),
2397 VMSTATE_INT32(stride, QXLSurfaceCreate),
2398 VMSTATE_UINT32(format, QXLSurfaceCreate),
2399 VMSTATE_UINT32(position, QXLSurfaceCreate),
2400 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2401 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2402 VMSTATE_UINT32(type, QXLSurfaceCreate),
2403 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2404 VMSTATE_END_OF_LIST()
2405 }
2406 };
2407
2408 static VMStateDescription qxl_vmstate_monitors_config = {
2409 .name = "qxl/monitors-config",
2410 .version_id = 1,
2411 .minimum_version_id = 1,
2412 .needed = qxl_monitors_config_needed,
2413 .fields = (VMStateField[]) {
2414 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2415 VMSTATE_END_OF_LIST()
2416 },
2417 };
2418
2419 static VMStateDescription qxl_vmstate = {
2420 .name = "qxl",
2421 .version_id = QXL_SAVE_VERSION,
2422 .minimum_version_id = QXL_SAVE_VERSION,
2423 .pre_save = qxl_pre_save,
2424 .pre_load = qxl_pre_load,
2425 .post_load = qxl_post_load,
2426 .fields = (VMStateField[]) {
2427 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2428 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2429 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2430 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2431 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2432 VMSTATE_UINT32(mode, PCIQXLDevice),
2433 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2434 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2435 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2436 qxl_memslot, struct guest_slots),
2437 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2438 qxl_surface, QXLSurfaceCreate),
2439 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2440 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2441 ssd.num_surfaces, 0,
2442 vmstate_info_uint64, uint64_t),
2443 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2444 VMSTATE_END_OF_LIST()
2445 },
2446 .subsections = (const VMStateDescription*[]) {
2447 &qxl_vmstate_monitors_config,
2448 NULL
2449 }
2450 };
2451
2452 static Property qxl_properties[] = {
2453 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2454 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2455 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2456 QXL_DEFAULT_REVISION),
2457 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2458 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2459 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2460 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2461 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2462 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2463 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2464 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2465 #if SPICE_SERVER_VERSION >= 0x000c06 /* release 0.12.6 */
2466 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2467 #endif
2468 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2469 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2470 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2471 DEFINE_PROP_END_OF_LIST(),
2472 };
2473
2474 static void qxl_pci_class_init(ObjectClass *klass, void *data)
2475 {
2476 DeviceClass *dc = DEVICE_CLASS(klass);
2477 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2478
2479 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2480 k->device_id = QXL_DEVICE_ID_STABLE;
2481 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2482 dc->reset = qxl_reset_handler;
2483 dc->vmsd = &qxl_vmstate;
2484 dc->props = qxl_properties;
2485 }
2486
2487 static const TypeInfo qxl_pci_type_info = {
2488 .name = TYPE_PCI_QXL,
2489 .parent = TYPE_PCI_DEVICE,
2490 .instance_size = sizeof(PCIQXLDevice),
2491 .abstract = true,
2492 .class_init = qxl_pci_class_init,
2493 .interfaces = (InterfaceInfo[]) {
2494 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2495 { },
2496 },
2497 };
2498
2499 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2500 {
2501 DeviceClass *dc = DEVICE_CLASS(klass);
2502 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2503
2504 k->realize = qxl_realize_primary;
2505 k->romfile = "vgabios-qxl.bin";
2506 k->class_id = PCI_CLASS_DISPLAY_VGA;
2507 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2508 dc->hotpluggable = false;
2509 }
2510
2511 static const TypeInfo qxl_primary_info = {
2512 .name = "qxl-vga",
2513 .parent = TYPE_PCI_QXL,
2514 .class_init = qxl_primary_class_init,
2515 };
2516
2517 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2518 {
2519 DeviceClass *dc = DEVICE_CLASS(klass);
2520 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2521
2522 k->realize = qxl_realize_secondary;
2523 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2524 dc->desc = "Spice QXL GPU (secondary)";
2525 }
2526
2527 static const TypeInfo qxl_secondary_info = {
2528 .name = "qxl",
2529 .parent = TYPE_PCI_QXL,
2530 .class_init = qxl_secondary_class_init,
2531 };
2532
2533 static void qxl_register_types(void)
2534 {
2535 type_register_static(&qxl_pci_type_info);
2536 type_register_static(&qxl_primary_info);
2537 type_register_static(&qxl_secondary_info);
2538 }
2539
2540 type_init(qxl_register_types)
AR7 emulation for QEMU