hw/s390x/s390-pci-bus.c

   1 /*
   2  * s390 PCI BUS
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "s390-pci-bus.h"
  15 #include <hw/pci/pci_bus.h>
  16 #include <hw/pci/msi.h>
  17 #include <qemu/error-report.h>
  18
  19 /* #define DEBUG_S390PCI_BUS */
  20 #ifdef DEBUG_S390PCI_BUS
  21 #define DPRINTF(fmt, ...) \
  22     do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) \
  25     do { } while (0)
  26 #endif
  27
  28 int chsc_sei_nt2_get_event(void *res)
  29 {
  30     ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
  31     PciCcdfAvail *accdf;
  32     PciCcdfErr *eccdf;
  33     int rc = 1;
  34     SeiContainer *sei_cont;
  35     S390pciState *s = S390_PCI_HOST_BRIDGE(
  36         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  37
  38     if (!s) {
  39         return rc;
  40     }
  41
  42     sei_cont = QTAILQ_FIRST(&s->pending_sei);
  43     if (sei_cont) {
  44         QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
  45         nt2_res->nt = 2;
  46         nt2_res->cc = sei_cont->cc;
  47         nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
  48         switch (sei_cont->cc) {
  49         case 1: /* error event */
  50             eccdf = (PciCcdfErr *)nt2_res->ccdf;
  51             eccdf->fid = cpu_to_be32(sei_cont->fid);
  52             eccdf->fh = cpu_to_be32(sei_cont->fh);
  53             eccdf->e = cpu_to_be32(sei_cont->e);
  54             eccdf->faddr = cpu_to_be64(sei_cont->faddr);
  55             eccdf->pec = cpu_to_be16(sei_cont->pec);
  56             break;
  57         case 2: /* availability event */
  58             accdf = (PciCcdfAvail *)nt2_res->ccdf;
  59             accdf->fid = cpu_to_be32(sei_cont->fid);
  60             accdf->fh = cpu_to_be32(sei_cont->fh);
  61             accdf->pec = cpu_to_be16(sei_cont->pec);
  62             break;
  63         default:
  64             abort();
  65         }
  66         g_free(sei_cont);
  67         rc = 0;
  68     }
  69
  70     return rc;
  71 }
  72
  73 int chsc_sei_nt2_have_event(void)
  74 {
  75     S390pciState *s = S390_PCI_HOST_BRIDGE(
  76         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  77
  78     if (!s) {
  79         return 0;
  80     }
  81
  82     return !QTAILQ_EMPTY(&s->pending_sei);
  83 }
  84
  85 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
  86 {
  87     S390PCIBusDevice *pbdev;
  88     int i;
  89     S390pciState *s = S390_PCI_HOST_BRIDGE(
  90         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  91
  92     if (!s) {
  93         return NULL;
  94     }
  95
  96     for (i = 0; i < PCI_SLOT_MAX; i++) {
  97         pbdev = &s->pbdev[i];
  98         if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
  99             return pbdev;
 100         }
 101     }
 102
 103     return NULL;
 104 }
 105
 106 void s390_pci_sclp_configure(int configure, SCCB *sccb)
 107 {
 108     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 109     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 110     uint16_t rc;
 111
 112     if (pbdev) {
 113         if ((configure == 1 && pbdev->configured == true) ||
 114             (configure == 0 && pbdev->configured == false)) {
 115             rc = SCLP_RC_NO_ACTION_REQUIRED;
 116         } else {
 117             pbdev->configured = !pbdev->configured;
 118             rc = SCLP_RC_NORMAL_COMPLETION;
 119         }
 120     } else {
 121         DPRINTF("sclp config %d no dev found\n", configure);
 122         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 123     }
 124
 125     psccb->header.response_code = cpu_to_be16(rc);
 126 }
 127
 128 static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
 129 {
 130     return PCI_SLOT(pdev->devfn);
 131 }
 132
 133 static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
 134 {
 135     return PCI_SLOT(pdev->devfn) | FH_VIRT;
 136 }
 137
 138 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
 139 {
 140     S390PCIBusDevice *pbdev;
 141     int i;
 142     int j = 0;
 143     S390pciState *s = S390_PCI_HOST_BRIDGE(
 144         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 145
 146     if (!s) {
 147         return NULL;
 148     }
 149
 150     for (i = 0; i < PCI_SLOT_MAX; i++) {
 151         pbdev = &s->pbdev[i];
 152
 153         if (pbdev->fh == 0) {
 154             continue;
 155         }
 156
 157         if (j == idx) {
 158             return pbdev;
 159         }
 160         j++;
 161     }
 162
 163     return NULL;
 164 }
 165
 166 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
 167 {
 168     S390PCIBusDevice *pbdev;
 169     int i;
 170     S390pciState *s = S390_PCI_HOST_BRIDGE(
 171         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 172
 173     if (!s || !fh) {
 174         return NULL;
 175     }
 176
 177     for (i = 0; i < PCI_SLOT_MAX; i++) {
 178         pbdev = &s->pbdev[i];
 179         if (pbdev->fh == fh) {
 180             return pbdev;
 181         }
 182     }
 183
 184     return NULL;
 185 }
 186
 187 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
 188                                     uint32_t fid, uint64_t faddr, uint32_t e)
 189 {
 190     SeiContainer *sei_cont;
 191     S390pciState *s = S390_PCI_HOST_BRIDGE(
 192         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 193
 194     if (!s) {
 195         return;
 196     }
 197
 198     sei_cont = g_malloc0(sizeof(SeiContainer));
 199     sei_cont->fh = fh;
 200     sei_cont->fid = fid;
 201     sei_cont->cc = cc;
 202     sei_cont->pec = pec;
 203     sei_cont->faddr = faddr;
 204     sei_cont->e = e;
 205
 206     QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
 207     css_generate_css_crws(0);
 208 }
 209
 210 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
 211                                          uint32_t fid)
 212 {
 213     s390_pci_generate_event(2, pec, fh, fid, 0, 0);
 214 }
 215
 216 static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
 217                                           uint32_t fid, uint64_t faddr,
 218                                           uint32_t e)
 219 {
 220     s390_pci_generate_event(1, pec, fh, fid, faddr, e);
 221 }
 222
 223 static void s390_pci_set_irq(void *opaque, int irq, int level)
 224 {
 225     /* nothing to do */
 226 }
 227
 228 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 229 {
 230     /* nothing to do */
 231     return 0;
 232 }
 233
 234 static uint64_t s390_pci_get_table_origin(uint64_t iota)
 235 {
 236     return iota & ~ZPCI_IOTA_RTTO_FLAG;
 237 }
 238
 239 static unsigned int calc_rtx(dma_addr_t ptr)
 240 {
 241     return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
 242 }
 243
 244 static unsigned int calc_sx(dma_addr_t ptr)
 245 {
 246     return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
 247 }
 248
 249 static unsigned int calc_px(dma_addr_t ptr)
 250 {
 251     return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
 252 }
 253
 254 static uint64_t get_rt_sto(uint64_t entry)
 255 {
 256     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
 257                 ? (entry & ZPCI_RTE_ADDR_MASK)
 258                 : 0;
 259 }
 260
 261 static uint64_t get_st_pto(uint64_t entry)
 262 {
 263     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
 264             ? (entry & ZPCI_STE_ADDR_MASK)
 265             : 0;
 266 }
 267
 268 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
 269                                   uint64_t guest_dma_address)
 270 {
 271     uint64_t sto_a, pto_a, px_a;
 272     uint64_t sto, pto, pte;
 273     uint32_t rtx, sx, px;
 274
 275     rtx = calc_rtx(guest_dma_address);
 276     sx = calc_sx(guest_dma_address);
 277     px = calc_px(guest_dma_address);
 278
 279     sto_a = guest_iota + rtx * sizeof(uint64_t);
 280     sto = address_space_ldq(&address_space_memory, sto_a,
 281                             MEMTXATTRS_UNSPECIFIED, NULL);
 282     sto = get_rt_sto(sto);
 283     if (!sto) {
 284         pte = 0;
 285         goto out;
 286     }
 287
 288     pto_a = sto + sx * sizeof(uint64_t);
 289     pto = address_space_ldq(&address_space_memory, pto_a,
 290                             MEMTXATTRS_UNSPECIFIED, NULL);
 291     pto = get_st_pto(pto);
 292     if (!pto) {
 293         pte = 0;
 294         goto out;
 295     }
 296
 297     px_a = pto + px * sizeof(uint64_t);
 298     pte = address_space_ldq(&address_space_memory, px_a,
 299                             MEMTXATTRS_UNSPECIFIED, NULL);
 300
 301 out:
 302     return pte;
 303 }
 304
 305 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 306                                           bool is_write)
 307 {
 308     uint64_t pte;
 309     uint32_t flags;
 310     S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, iommu_mr);
 311     S390pciState *s;
 312     IOMMUTLBEntry ret = {
 313         .target_as = &address_space_memory,
 314         .iova = 0,
 315         .translated_addr = 0,
 316         .addr_mask = ~(hwaddr)0,
 317         .perm = IOMMU_NONE,
 318     };
 319
 320     if (!pbdev->configured || !pbdev->pdev || !(pbdev->fh & FH_ENABLED)) {
 321         return ret;
 322     }
 323
 324     DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
 325
 326     s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)->qbus.parent);
 327     /* s390 does not have an APIC mapped to main storage so we use
 328      * a separate AddressSpace only for msix notifications
 329      */
 330     if (addr == ZPCI_MSI_ADDR) {
 331         ret.target_as = &s->msix_notify_as;
 332         ret.iova = addr;
 333         ret.translated_addr = addr;
 334         ret.addr_mask = 0xfff;
 335         ret.perm = IOMMU_RW;
 336         return ret;
 337     }
 338
 339     if (!pbdev->g_iota) {
 340         pbdev->error_state = true;
 341         pbdev->lgstg_blocked = true;
 342         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 343                                       addr, 0);
 344         return ret;
 345     }
 346
 347     if (addr < pbdev->pba || addr > pbdev->pal) {
 348         pbdev->error_state = true;
 349         pbdev->lgstg_blocked = true;
 350         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 351                                       addr, 0);
 352         return ret;
 353     }
 354
 355     pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
 356                                    addr);
 357
 358     if (!pte) {
 359         pbdev->error_state = true;
 360         pbdev->lgstg_blocked = true;
 361         s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 362                                       addr, ERR_EVENT_Q_BIT);
 363         return ret;
 364     }
 365
 366     flags = pte & ZPCI_PTE_FLAG_MASK;
 367     ret.iova = addr;
 368     ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
 369     ret.addr_mask = 0xfff;
 370
 371     if (flags & ZPCI_PTE_INVALID) {
 372         ret.perm = IOMMU_NONE;
 373     } else {
 374         ret.perm = IOMMU_RW;
 375     }
 376
 377     return ret;
 378 }
 379
 380 static const MemoryRegionIOMMUOps s390_iommu_ops = {
 381     .translate = s390_translate_iommu,
 382 };
 383
 384 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 385 {
 386     S390pciState *s = opaque;
 387
 388     return &s->pbdev[PCI_SLOT(devfn)].as;
 389 }
 390
 391 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
 392 {
 393     uint8_t ind_old, ind_new;
 394     hwaddr len = 1;
 395     uint8_t *ind_addr;
 396
 397     ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
 398     if (!ind_addr) {
 399         s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
 400         return -1;
 401     }
 402     do {
 403         ind_old = *ind_addr;
 404         ind_new = ind_old | to_be_set;
 405     } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
 406     cpu_physical_memory_unmap(ind_addr, len, 1, len);
 407
 408     return ind_old;
 409 }
 410
 411 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
 412                                 unsigned int size)
 413 {
 414     S390PCIBusDevice *pbdev;
 415     uint32_t io_int_word;
 416     uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
 417     uint32_t vec = data & ZPCI_MSI_VEC_MASK;
 418     uint64_t ind_bit;
 419     uint32_t sum_bit;
 420     uint32_t e = 0;
 421
 422     DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
 423
 424     pbdev = s390_pci_find_dev_by_fid(fid);
 425     if (!pbdev) {
 426         e |= (vec << ERR_EVENT_MVN_OFFSET);
 427         s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
 428         return;
 429     }
 430
 431     if (!(pbdev->fh & FH_ENABLED)) {
 432         return;
 433     }
 434
 435     ind_bit = pbdev->routes.adapter.ind_offset;
 436     sum_bit = pbdev->routes.adapter.summary_offset;
 437
 438     set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
 439                    0x80 >> ((ind_bit + vec) % 8));
 440     if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
 441                                        0x80 >> (sum_bit % 8))) {
 442         io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
 443         s390_io_interrupt(0, 0, 0, io_int_word);
 444     }
 445 }
 446
 447 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
 448 {
 449     return 0xffffffff;
 450 }
 451
 452 static const MemoryRegionOps s390_msi_ctrl_ops = {
 453     .write = s390_msi_ctrl_write,
 454     .read = s390_msi_ctrl_read,
 455     .endianness = DEVICE_LITTLE_ENDIAN,
 456 };
 457
 458 void s390_pcihost_iommu_configure(S390PCIBusDevice *pbdev, bool enable)
 459 {
 460     pbdev->configured = false;
 461
 462     if (enable) {
 463         uint64_t size = pbdev->pal - pbdev->pba + 1;
 464         memory_region_init_iommu(&pbdev->iommu_mr, OBJECT(&pbdev->mr),
 465                                  &s390_iommu_ops, "iommu-s390", size);
 466         memory_region_add_subregion(&pbdev->mr, pbdev->pba, &pbdev->iommu_mr);
 467     } else {
 468         memory_region_del_subregion(&pbdev->mr, &pbdev->iommu_mr);
 469     }
 470
 471     pbdev->configured = true;
 472 }
 473
 474 static void s390_pcihost_init_as(S390pciState *s)
 475 {
 476     int i;
 477     S390PCIBusDevice *pbdev;
 478
 479     for (i = 0; i < PCI_SLOT_MAX; i++) {
 480         pbdev = &s->pbdev[i];
 481         memory_region_init(&pbdev->mr, OBJECT(s),
 482                            "iommu-root-s390", UINT64_MAX);
 483         address_space_init(&pbdev->as, &pbdev->mr, "iommu-pci");
 484     }
 485
 486     memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
 487                           &s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
 488     address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
 489 }
 490
 491 static int s390_pcihost_init(SysBusDevice *dev)
 492 {
 493     PCIBus *b;
 494     BusState *bus;
 495     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 496     S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
 497
 498     DPRINTF("host_init\n");
 499
 500     b = pci_register_bus(DEVICE(dev), NULL,
 501                          s390_pci_set_irq, s390_pci_map_irq, NULL,
 502                          get_system_memory(), get_system_io(), 0, 64,
 503                          TYPE_PCI_BUS);
 504     s390_pcihost_init_as(s);
 505     pci_setup_iommu(b, s390_pci_dma_iommu, s);
 506
 507     bus = BUS(b);
 508     qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
 509     phb->bus = b;
 510     QTAILQ_INIT(&s->pending_sei);
 511     return 0;
 512 }
 513
 514 static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
 515 {
 516     uint8_t pos;
 517     uint16_t ctrl;
 518     uint32_t table, pba;
 519
 520     pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
 521     if (!pos) {
 522         pbdev->msix.available = false;
 523         return 0;
 524     }
 525
 526     ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_CAP_FLAGS,
 527              pci_config_size(pbdev->pdev), sizeof(ctrl));
 528     table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
 529              pci_config_size(pbdev->pdev), sizeof(table));
 530     pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
 531              pci_config_size(pbdev->pdev), sizeof(pba));
 532
 533     pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
 534     pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
 535     pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
 536     pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
 537     pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
 538     pbdev->msix.available = true;
 539     return 0;
 540 }
 541
 542 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
 543                                   DeviceState *dev, Error **errp)
 544 {
 545     PCIDevice *pci_dev = PCI_DEVICE(dev);
 546     S390PCIBusDevice *pbdev;
 547     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 548                                            ->qbus.parent);
 549
 550     pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 551
 552     pbdev->fid = s390_pci_get_pfid(pci_dev);
 553     pbdev->pdev = pci_dev;
 554     pbdev->configured = true;
 555     pbdev->fh = s390_pci_get_pfh(pci_dev);
 556
 557     s390_pcihost_setup_msix(pbdev);
 558
 559     if (dev->hotplugged) {
 560         s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
 561                                      pbdev->fh, pbdev->fid);
 562         s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
 563                                      pbdev->fh, pbdev->fid);
 564     }
 565 }
 566
 567 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
 568                                     DeviceState *dev, Error **errp)
 569 {
 570     PCIDevice *pci_dev = PCI_DEVICE(dev);
 571     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 572                                            ->qbus.parent);
 573     S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 574
 575     if (pbdev->configured) {
 576         pbdev->configured = false;
 577         s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
 578                                      pbdev->fh, pbdev->fid);
 579     }
 580
 581     s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
 582                                  pbdev->fh, pbdev->fid);
 583     pbdev->fh = 0;
 584     pbdev->fid = 0;
 585     pbdev->pdev = NULL;
 586     object_unparent(OBJECT(pci_dev));
 587 }
 588
 589 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
 590 {
 591     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 592     DeviceClass *dc = DEVICE_CLASS(klass);
 593     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 594
 595     dc->cannot_instantiate_with_device_add_yet = true;
 596     k->init = s390_pcihost_init;
 597     hc->plug = s390_pcihost_hot_plug;
 598     hc->unplug = s390_pcihost_hot_unplug;
 599     msi_supported = true;
 600 }
 601
 602 static const TypeInfo s390_pcihost_info = {
 603     .name          = TYPE_S390_PCI_HOST_BRIDGE,
 604     .parent        = TYPE_PCI_HOST_BRIDGE,
 605     .instance_size = sizeof(S390pciState),
 606     .class_init    = s390_pcihost_class_init,
 607     .interfaces = (InterfaceInfo[]) {
 608         { TYPE_HOTPLUG_HANDLER },
 609         { }
 610     }
 611 };
 612
 613 static void s390_pci_register_types(void)
 614 {
 615     type_register_static(&s390_pcihost_info);
 616 }
 617
 618 type_init(s390_pci_register_types)