qapi: force a UTF-8 locale for running Python
[qemu/ar7.git] / hw / i2c / smbus_ich9.c
blob007cb6701dd9d300ca292db3091fa42592abf1a0
1 /*
2 * ACPI implementation
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
7 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 * This is based on acpi.c, but heavily rewritten.
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License version 2 as published by the Free Software Foundation.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, see <http://www.gnu.org/licenses/>
23 * Contributions after 2012-01-13 are licensed under the terms of the
24 * GNU GPL, version 2 or (at your option) any later version.
27 #include "qemu/osdep.h"
28 #include "hw/hw.h"
29 #include "hw/i2c/pm_smbus.h"
30 #include "hw/pci/pci.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/i2c/i2c.h"
33 #include "hw/i2c/smbus.h"
35 #include "hw/i386/ich9.h"
37 #define ICH9_SMB_DEVICE(obj) \
38 OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
40 typedef struct ICH9SMBState {
41 PCIDevice dev;
43 PMSMBus smb;
44 } ICH9SMBState;
46 static const VMStateDescription vmstate_ich9_smbus = {
47 .name = "ich9_smb",
48 .version_id = 1,
49 .minimum_version_id = 1,
50 .fields = (VMStateField[]) {
51 VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState),
52 VMSTATE_END_OF_LIST()
56 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
57 uint32_t val, int len)
59 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
61 pci_default_write_config(d, address, val, len);
62 if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
63 uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
64 if ((hostc & ICH9_SMB_HOSTC_HST_EN) &&
65 !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
66 memory_region_set_enabled(&s->smb.io, true);
67 } else {
68 memory_region_set_enabled(&s->smb.io, false);
73 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
75 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
77 /* TODO? D31IP.SMIP in chipset configuration space */
78 pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
80 pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
81 /* TODO bar0, bar1: 64bit BAR support*/
83 pm_smbus_init(&d->qdev, &s->smb);
84 pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
85 &s->smb.io);
88 static void ich9_smb_class_init(ObjectClass *klass, void *data)
90 DeviceClass *dc = DEVICE_CLASS(klass);
91 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
93 k->vendor_id = PCI_VENDOR_ID_INTEL;
94 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
95 k->revision = ICH9_A2_SMB_REVISION;
96 k->class_id = PCI_CLASS_SERIAL_SMBUS;
97 dc->vmsd = &vmstate_ich9_smbus;
98 dc->desc = "ICH9 SMBUS Bridge";
99 k->realize = ich9_smbus_realize;
100 k->config_write = ich9_smbus_write_config;
102 * Reason: part of ICH9 southbridge, needs to be wired up by
103 * pc_q35_init()
105 dc->user_creatable = false;
108 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
110 PCIDevice *d =
111 pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
112 ICH9SMBState *s = ICH9_SMB_DEVICE(d);
113 return s->smb.smbus;
116 static const TypeInfo ich9_smb_info = {
117 .name = TYPE_ICH9_SMB_DEVICE,
118 .parent = TYPE_PCI_DEVICE,
119 .instance_size = sizeof(ICH9SMBState),
120 .class_init = ich9_smb_class_init,
121 .interfaces = (InterfaceInfo[]) {
122 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
123 { },
127 static void ich9_smb_register(void)
129 type_register_static(&ich9_smb_info);
132 type_init(ich9_smb_register);