2 * QEMU PowerPC sPAPR IRQ backend definitions
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #ifndef HW_SPAPR_IRQ_H
11 #define HW_SPAPR_IRQ_H
13 #include "target/ppc/cpu-qom.h"
16 * IRQ range offsets per device type
18 #define SPAPR_IRQ_IPI 0x0
20 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
21 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
22 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
23 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
24 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
26 /* Offset of the dynamic range covered by the bitmap allocator */
27 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
29 #define SPAPR_NR_XIRQS 0x1000
31 typedef struct SpaprMachineState SpaprMachineState
;
33 typedef struct SpaprInterruptController SpaprInterruptController
;
35 #define TYPE_SPAPR_INTC "spapr-interrupt-controller"
36 #define SPAPR_INTC(obj) \
37 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
38 #define SPAPR_INTC_CLASS(klass) \
39 OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC)
40 #define SPAPR_INTC_GET_CLASS(obj) \
41 OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC)
43 typedef struct SpaprInterruptControllerClass
{
44 InterfaceClass parent
;
46 int (*activate
)(SpaprInterruptController
*intc
, Error
**errp
);
47 void (*deactivate
)(SpaprInterruptController
*intc
);
50 * These methods will typically be called on all intcs, active and
53 int (*cpu_intc_create
)(SpaprInterruptController
*intc
,
54 PowerPCCPU
*cpu
, Error
**errp
);
55 void (*cpu_intc_reset
)(SpaprInterruptController
*intc
, PowerPCCPU
*cpu
);
56 int (*claim_irq
)(SpaprInterruptController
*intc
, int irq
, bool lsi
,
58 void (*free_irq
)(SpaprInterruptController
*intc
, int irq
);
60 /* These methods should only be called on the active intc */
61 void (*set_irq
)(SpaprInterruptController
*intc
, int irq
, int val
);
62 void (*print_info
)(SpaprInterruptController
*intc
, Monitor
*mon
);
63 void (*dt
)(SpaprInterruptController
*intc
, uint32_t nr_servers
,
64 void *fdt
, uint32_t phandle
);
65 int (*post_load
)(SpaprInterruptController
*intc
, int version_id
);
66 } SpaprInterruptControllerClass
;
68 void spapr_irq_update_active_intc(SpaprMachineState
*spapr
);
70 int spapr_irq_cpu_intc_create(SpaprMachineState
*spapr
,
71 PowerPCCPU
*cpu
, Error
**errp
);
72 void spapr_irq_cpu_intc_reset(SpaprMachineState
*spapr
, PowerPCCPU
*cpu
);
73 void spapr_irq_print_info(SpaprMachineState
*spapr
, Monitor
*mon
);
74 void spapr_irq_dt(SpaprMachineState
*spapr
, uint32_t nr_servers
,
75 void *fdt
, uint32_t phandle
);
77 uint32_t spapr_irq_nr_msis(SpaprMachineState
*spapr
);
78 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
80 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
);
82 typedef struct SpaprIrq
{
87 extern SpaprIrq spapr_irq_xics
;
88 extern SpaprIrq spapr_irq_xics_legacy
;
89 extern SpaprIrq spapr_irq_xive
;
90 extern SpaprIrq spapr_irq_dual
;
92 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
);
93 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
);
94 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
);
95 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
);
96 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
);
97 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
);
98 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
);
99 int spapr_irq_init_kvm(int (*fn
)(SpaprInterruptController
*, Error
**),
100 SpaprInterruptController
*intc
,
104 * XICS legacy routines
106 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
);
107 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)