2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "hw/qdev-properties.h"
19 #include "migration/vmstate.h"
20 #include "monitor/monitor.h"
22 #include "hw/ppc/xive.h"
23 #include "hw/ppc/xive_regs.h"
26 * XIVE Thread Interrupt Management context
30 * Convert a priority number to an Interrupt Pending Buffer (IPB)
31 * register, which indicates a pending interrupt at the priority
32 * corresponding to the bit number
34 static uint8_t priority_to_ipb(uint8_t priority
)
36 return priority
> XIVE_PRIORITY_MAX
?
37 0 : 1 << (XIVE_PRIORITY_MAX
- priority
);
41 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
42 * Interrupt Priority Register (PIPR), which contains the priority of
43 * the most favored pending notification.
45 static uint8_t ipb_to_pipr(uint8_t ibp
)
47 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
50 static void ipb_update(uint8_t *regs
, uint8_t priority
)
52 regs
[TM_IPB
] |= priority_to_ipb(priority
);
53 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
56 static uint8_t exception_mask(uint8_t ring
)
64 g_assert_not_reached();
68 static qemu_irq
xive_tctx_output(XiveTCTX
*tctx
, uint8_t ring
)
72 return 0; /* Not supported */
74 return tctx
->os_output
;
77 return tctx
->hv_output
;
83 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
85 uint8_t *regs
= &tctx
->regs
[ring
];
86 uint8_t nsr
= regs
[TM_NSR
];
87 uint8_t mask
= exception_mask(ring
);
89 qemu_irq_lower(xive_tctx_output(tctx
, ring
));
91 if (regs
[TM_NSR
] & mask
) {
92 uint8_t cppr
= regs
[TM_PIPR
];
96 /* Reset the pending buffer bit */
97 regs
[TM_IPB
] &= ~priority_to_ipb(cppr
);
98 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
100 /* Drop Exception bit */
101 regs
[TM_NSR
] &= ~mask
;
104 return (nsr
<< 8) | regs
[TM_CPPR
];
107 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
109 uint8_t *regs
= &tctx
->regs
[ring
];
111 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
114 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
117 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
120 g_assert_not_reached();
122 qemu_irq_raise(xive_tctx_output(tctx
, ring
));
126 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
128 if (cppr
> XIVE_PRIORITY_MAX
) {
132 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
134 /* CPPR has changed, check if we need to raise a pending exception */
135 xive_tctx_notify(tctx
, ring
);
138 static inline uint32_t xive_tctx_word2(uint8_t *ring
)
140 return *((uint32_t *) &ring
[TM_WORD2
]);
144 * XIVE Thread Interrupt Management Area (TIMA)
147 static void xive_tm_set_hv_cppr(XiveTCTX
*tctx
, hwaddr offset
,
148 uint64_t value
, unsigned size
)
150 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
153 static uint64_t xive_tm_ack_hv_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
155 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
158 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX
*tctx
, hwaddr offset
,
161 uint32_t qw2w2_prev
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
164 qw2w2
= xive_set_field32(TM_QW2W2_VP
, qw2w2_prev
, 0);
165 memcpy(&tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
], &qw2w2
, 4);
169 static void xive_tm_vt_push(XiveTCTX
*tctx
, hwaddr offset
,
170 uint64_t value
, unsigned size
)
172 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
175 static uint64_t xive_tm_vt_poll(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
177 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
181 * Define an access map for each page of the TIMA that we will use in
182 * the memory region ops to filter values when doing loads and stores
183 * of raw registers values
185 * Registers accessibility bits :
193 static const uint8_t xive_tm_hw_view
[] = {
194 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
195 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
196 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
197 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
200 static const uint8_t xive_tm_hv_view
[] = {
201 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
202 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
203 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
204 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
207 static const uint8_t xive_tm_os_view
[] = {
208 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
209 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
214 static const uint8_t xive_tm_user_view
[] = {
215 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
222 * Overall TIMA access map for the thread interrupt management context
225 static const uint8_t *xive_tm_views
[] = {
226 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
227 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
228 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
229 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
233 * Computes a register access mask for a given offset in the TIMA
235 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
237 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
238 uint8_t reg_offset
= offset
& 0x3F;
239 uint8_t reg_mask
= write
? 0x1 : 0x2;
243 for (i
= 0; i
< size
; i
++) {
244 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
245 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
252 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
255 uint8_t ring_offset
= offset
& 0x30;
256 uint8_t reg_offset
= offset
& 0x3F;
257 uint64_t mask
= xive_tm_mask(offset
, size
, true);
261 * Only 4 or 8 bytes stores are allowed and the User ring is
264 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
265 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
266 HWADDR_PRIx
"\n", offset
);
271 * Use the register offset for the raw values and filter out
274 for (i
= 0; i
< size
; i
++) {
275 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
277 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
283 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
285 uint8_t ring_offset
= offset
& 0x30;
286 uint8_t reg_offset
= offset
& 0x3F;
287 uint64_t mask
= xive_tm_mask(offset
, size
, false);
292 * Only 4 or 8 bytes loads are allowed and the User ring is
295 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
296 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
297 HWADDR_PRIx
"\n", offset
);
301 /* Use the register offset for the raw values */
303 for (i
= 0; i
< size
; i
++) {
304 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
307 /* filter out reserved values */
312 * The TM context is mapped twice within each page. Stores and loads
313 * to the first mapping below 2K write and read the specified values
314 * without modification. The second mapping above 2K performs specific
315 * state changes (side effects) in addition to setting/returning the
316 * interrupt management area context of the processor thread.
318 static uint64_t xive_tm_ack_os_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
320 return xive_tctx_accept(tctx
, TM_QW1_OS
);
323 static void xive_tm_set_os_cppr(XiveTCTX
*tctx
, hwaddr offset
,
324 uint64_t value
, unsigned size
)
326 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
330 * Adjust the IPB to allow a CPU to process event queues of other
331 * priorities during one physical interrupt cycle.
333 static void xive_tm_set_os_pending(XiveTCTX
*tctx
, hwaddr offset
,
334 uint64_t value
, unsigned size
)
336 ipb_update(&tctx
->regs
[TM_QW1_OS
], value
& 0xff);
337 xive_tctx_notify(tctx
, TM_QW1_OS
);
340 static uint64_t xive_tm_pull_os_ctx(XiveTCTX
*tctx
, hwaddr offset
,
343 uint32_t qw1w2_prev
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
346 qw1w2
= xive_set_field32(TM_QW1W2_VO
, qw1w2_prev
, 0);
347 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &qw1w2
, 4);
352 * Define a mapping of "special" operations depending on the TIMA page
353 * offset and the size of the operation.
355 typedef struct XiveTmOp
{
359 void (*write_handler
)(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
361 uint64_t (*read_handler
)(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
);
364 static const XiveTmOp xive_tm_operations
[] = {
366 * MMIOs below 2K : raw values and special operations without side
369 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
370 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
371 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
372 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
374 /* MMIOs above 2K : special operations with side effects */
375 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
376 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
377 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_OS_CTX
, 4, NULL
, xive_tm_pull_os_ctx
},
378 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_OS_CTX
, 8, NULL
, xive_tm_pull_os_ctx
},
379 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
380 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
381 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
384 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
386 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
387 uint32_t op_offset
= offset
& 0xFFF;
390 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
391 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
393 /* Accesses done from a more privileged TIMA page is allowed */
394 if (xto
->page_offset
>= page_offset
&&
395 xto
->op_offset
== op_offset
&&
397 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
407 void xive_tctx_tm_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
413 * TODO: check V bit in Q[0-3]W2
417 * First, check for special operations in the 2K region
419 if (offset
& 0x800) {
420 xto
= xive_tm_find_op(offset
, size
, true);
422 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA "
423 "@%"HWADDR_PRIx
"\n", offset
);
425 xto
->write_handler(tctx
, offset
, value
, size
);
431 * Then, for special operations in the region below 2K.
433 xto
= xive_tm_find_op(offset
, size
, true);
435 xto
->write_handler(tctx
, offset
, value
, size
);
440 * Finish with raw access to the register values
442 xive_tm_raw_write(tctx
, offset
, value
, size
);
445 uint64_t xive_tctx_tm_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
450 * TODO: check V bit in Q[0-3]W2
454 * First, check for special operations in the 2K region
456 if (offset
& 0x800) {
457 xto
= xive_tm_find_op(offset
, size
, false);
459 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
460 "@%"HWADDR_PRIx
"\n", offset
);
463 return xto
->read_handler(tctx
, offset
, size
);
467 * Then, for special operations in the region below 2K.
469 xto
= xive_tm_find_op(offset
, size
, false);
471 return xto
->read_handler(tctx
, offset
, size
);
475 * Finish with raw access to the register values
477 return xive_tm_raw_read(tctx
, offset
, size
);
480 static void xive_tm_write(void *opaque
, hwaddr offset
,
481 uint64_t value
, unsigned size
)
483 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
485 xive_tctx_tm_write(tctx
, offset
, value
, size
);
488 static uint64_t xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
490 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
492 return xive_tctx_tm_read(tctx
, offset
, size
);
495 const MemoryRegionOps xive_tm_ops
= {
496 .read
= xive_tm_read
,
497 .write
= xive_tm_write
,
498 .endianness
= DEVICE_BIG_ENDIAN
,
500 .min_access_size
= 1,
501 .max_access_size
= 8,
504 .min_access_size
= 1,
505 .max_access_size
= 8,
509 static char *xive_tctx_ring_print(uint8_t *ring
)
511 uint32_t w2
= xive_tctx_word2(ring
);
513 return g_strdup_printf("%02x %02x %02x %02x %02x "
514 "%02x %02x %02x %08x",
515 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
516 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
520 static const char * const xive_tctx_ring_names
[] = {
521 "USER", "OS", "POOL", "PHYS",
524 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
526 int cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
529 if (kvm_irqchip_in_kernel()) {
530 Error
*local_err
= NULL
;
532 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
534 error_report_err(local_err
);
539 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
542 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
543 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
544 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
545 xive_tctx_ring_names
[i
], s
);
550 void xive_tctx_reset(XiveTCTX
*tctx
)
552 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
554 /* Set some defaults */
555 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
556 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
557 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
560 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
563 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
564 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
565 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
566 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
569 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
571 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
575 Error
*local_err
= NULL
;
577 obj
= object_property_get_link(OBJECT(dev
), "cpu", &local_err
);
579 error_propagate(errp
, local_err
);
580 error_prepend(errp
, "required link 'cpu' not found: ");
584 cpu
= POWERPC_CPU(obj
);
588 switch (PPC_INPUT(env
)) {
589 case PPC_FLAGS_INPUT_POWER9
:
590 tctx
->hv_output
= env
->irq_inputs
[POWER9_INPUT_HINT
];
591 tctx
->os_output
= env
->irq_inputs
[POWER9_INPUT_INT
];
595 error_setg(errp
, "XIVE interrupt controller does not support "
596 "this CPU bus model");
600 /* Connect the presenter to the VCPU (required for CPU hotplug) */
601 if (kvm_irqchip_in_kernel()) {
602 kvmppc_xive_cpu_connect(tctx
, &local_err
);
604 error_propagate(errp
, local_err
);
610 static int vmstate_xive_tctx_pre_save(void *opaque
)
612 Error
*local_err
= NULL
;
614 if (kvm_irqchip_in_kernel()) {
615 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque
), &local_err
);
617 error_report_err(local_err
);
625 static int vmstate_xive_tctx_post_load(void *opaque
, int version_id
)
627 Error
*local_err
= NULL
;
629 if (kvm_irqchip_in_kernel()) {
631 * Required for hotplugged CPU, for which the state comes
632 * after all states of the machine.
634 kvmppc_xive_cpu_set_state(XIVE_TCTX(opaque
), &local_err
);
636 error_report_err(local_err
);
644 static const VMStateDescription vmstate_xive_tctx
= {
645 .name
= TYPE_XIVE_TCTX
,
647 .minimum_version_id
= 1,
648 .pre_save
= vmstate_xive_tctx_pre_save
,
649 .post_load
= vmstate_xive_tctx_post_load
,
650 .fields
= (VMStateField
[]) {
651 VMSTATE_BUFFER(regs
, XiveTCTX
),
652 VMSTATE_END_OF_LIST()
656 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
658 DeviceClass
*dc
= DEVICE_CLASS(klass
);
660 dc
->desc
= "XIVE Interrupt Thread Context";
661 dc
->realize
= xive_tctx_realize
;
662 dc
->vmsd
= &vmstate_xive_tctx
;
664 * Reason: part of XIVE interrupt controller, needs to be wired up
665 * by xive_tctx_create().
667 dc
->user_creatable
= false;
670 static const TypeInfo xive_tctx_info
= {
671 .name
= TYPE_XIVE_TCTX
,
672 .parent
= TYPE_DEVICE
,
673 .instance_size
= sizeof(XiveTCTX
),
674 .class_init
= xive_tctx_class_init
,
677 Object
*xive_tctx_create(Object
*cpu
, XiveRouter
*xrtr
, Error
**errp
)
679 Error
*local_err
= NULL
;
682 obj
= object_new(TYPE_XIVE_TCTX
);
683 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
, &error_abort
);
685 object_property_add_const_link(obj
, "cpu", cpu
, &error_abort
);
686 object_property_set_bool(obj
, true, "realized", &local_err
);
694 object_unparent(obj
);
695 error_propagate(errp
, local_err
);
703 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
705 uint8_t old_pq
= *pq
& 0x3;
713 static bool xive_esb_trigger(uint8_t *pq
)
715 uint8_t old_pq
= *pq
& 0x3;
719 xive_esb_set(pq
, XIVE_ESB_PENDING
);
721 case XIVE_ESB_PENDING
:
722 case XIVE_ESB_QUEUED
:
723 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
726 xive_esb_set(pq
, XIVE_ESB_OFF
);
729 g_assert_not_reached();
733 static bool xive_esb_eoi(uint8_t *pq
)
735 uint8_t old_pq
= *pq
& 0x3;
739 case XIVE_ESB_PENDING
:
740 xive_esb_set(pq
, XIVE_ESB_RESET
);
742 case XIVE_ESB_QUEUED
:
743 xive_esb_set(pq
, XIVE_ESB_PENDING
);
746 xive_esb_set(pq
, XIVE_ESB_OFF
);
749 g_assert_not_reached();
754 * XIVE Interrupt Source (or IVSE)
757 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
759 assert(srcno
< xsrc
->nr_irqs
);
761 return xsrc
->status
[srcno
] & 0x3;
764 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
766 assert(srcno
< xsrc
->nr_irqs
);
768 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
772 * Returns whether the event notification should be forwarded.
774 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
776 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
778 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
782 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
790 * Returns whether the event notification should be forwarded.
792 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
796 assert(srcno
< xsrc
->nr_irqs
);
798 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
800 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
801 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
802 qemu_log_mask(LOG_GUEST_ERROR
,
803 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
810 * Returns whether the event notification should be forwarded.
812 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
816 assert(srcno
< xsrc
->nr_irqs
);
818 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
821 * LSI sources do not set the Q bit but they can still be
822 * asserted, in which case we should forward a new event
825 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
826 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
827 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
834 * Forward the source event notification to the Router
836 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
838 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
841 xnc
->notify(xsrc
->xive
, srcno
);
846 * In a two pages ESB MMIO setting, even page is the trigger page, odd
847 * page is for management
849 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
851 return !((addr
>> shift
) & 1);
854 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
856 return xive_source_esb_has_2page(xsrc
) &&
857 addr_is_even(addr
, xsrc
->esb_shift
- 1);
862 * Trigger page Management/EOI page
864 * ESB MMIO setting 2 pages 1 or 2 pages
866 * 0x000 .. 0x3FF -1 EOI and return 0|1
867 * 0x400 .. 0x7FF -1 EOI and return 0|1
868 * 0x800 .. 0xBFF -1 return PQ
869 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
870 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
871 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
872 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
874 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
876 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
877 uint32_t offset
= addr
& 0xFFF;
878 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
881 /* In a two pages ESB MMIO setting, trigger page should not be read */
882 if (xive_source_is_trigger_page(xsrc
, addr
)) {
883 qemu_log_mask(LOG_GUEST_ERROR
,
884 "XIVE: invalid load on IRQ %d trigger page at "
885 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
890 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
891 ret
= xive_source_esb_eoi(xsrc
, srcno
);
893 /* Forward the source event notification for routing */
895 xive_source_notify(xsrc
, srcno
);
899 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
900 ret
= xive_source_esb_get(xsrc
, srcno
);
903 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
904 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
905 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
906 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
907 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
910 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
919 * Trigger page Management/EOI page
921 * ESB MMIO setting 2 pages 1 or 2 pages
923 * 0x000 .. 0x3FF Trigger Trigger
924 * 0x400 .. 0x7FF Trigger EOI
925 * 0x800 .. 0xBFF Trigger undefined
926 * 0xC00 .. 0xCFF Trigger PQ=00
927 * 0xD00 .. 0xDFF Trigger PQ=01
928 * 0xE00 .. 0xDFF Trigger PQ=10
929 * 0xF00 .. 0xDFF Trigger PQ=11
931 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
932 uint64_t value
, unsigned size
)
934 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
935 uint32_t offset
= addr
& 0xFFF;
936 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
939 /* In a two pages ESB MMIO setting, trigger page only triggers */
940 if (xive_source_is_trigger_page(xsrc
, addr
)) {
941 notify
= xive_source_esb_trigger(xsrc
, srcno
);
947 notify
= xive_source_esb_trigger(xsrc
, srcno
);
950 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
951 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
952 qemu_log_mask(LOG_GUEST_ERROR
,
953 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
957 notify
= xive_source_esb_eoi(xsrc
, srcno
);
960 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
961 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
962 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
963 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
964 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
968 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
974 /* Forward the source event notification for routing */
976 xive_source_notify(xsrc
, srcno
);
980 static const MemoryRegionOps xive_source_esb_ops
= {
981 .read
= xive_source_esb_read
,
982 .write
= xive_source_esb_write
,
983 .endianness
= DEVICE_BIG_ENDIAN
,
985 .min_access_size
= 8,
986 .max_access_size
= 8,
989 .min_access_size
= 8,
990 .max_access_size
= 8,
994 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
996 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
999 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
1001 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
1003 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
1007 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1011 /* Forward the source event notification for routing */
1013 xive_source_notify(xsrc
, srcno
);
1017 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
1021 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
1022 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
1024 if (pq
== XIVE_ESB_OFF
) {
1028 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
1029 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
1030 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1031 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1032 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
1036 static void xive_source_reset(void *dev
)
1038 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1040 /* Do not clear the LSI bitmap */
1042 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
1043 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
1046 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1048 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1050 Error
*local_err
= NULL
;
1052 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1054 error_propagate(errp
, local_err
);
1055 error_prepend(errp
, "required link 'xive' not found: ");
1059 xsrc
->xive
= XIVE_NOTIFIER(obj
);
1061 if (!xsrc
->nr_irqs
) {
1062 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1066 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1067 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1068 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1069 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1070 error_setg(errp
, "Invalid ESB shift setting");
1074 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1075 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1077 if (!kvm_irqchip_in_kernel()) {
1078 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1079 &xive_source_esb_ops
, xsrc
, "xive.esb",
1080 (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
);
1083 qemu_register_reset(xive_source_reset
, dev
);
1086 static const VMStateDescription vmstate_xive_source
= {
1087 .name
= TYPE_XIVE_SOURCE
,
1089 .minimum_version_id
= 1,
1090 .fields
= (VMStateField
[]) {
1091 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1092 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1093 VMSTATE_END_OF_LIST()
1098 * The default XIVE interrupt source setting for the ESB MMIOs is two
1099 * 64k pages without Store EOI, to be in sync with KVM.
1101 static Property xive_source_properties
[] = {
1102 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1103 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1104 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1105 DEFINE_PROP_END_OF_LIST(),
1108 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1110 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1112 dc
->desc
= "XIVE Interrupt Source";
1113 dc
->props
= xive_source_properties
;
1114 dc
->realize
= xive_source_realize
;
1115 dc
->vmsd
= &vmstate_xive_source
;
1117 * Reason: part of XIVE interrupt controller, needs to be wired up,
1118 * e.g. by spapr_xive_instance_init().
1120 dc
->user_creatable
= false;
1123 static const TypeInfo xive_source_info
= {
1124 .name
= TYPE_XIVE_SOURCE
,
1125 .parent
= TYPE_DEVICE
,
1126 .instance_size
= sizeof(XiveSource
),
1127 .class_init
= xive_source_class_init
,
1134 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1136 uint64_t qaddr_base
= xive_end_qaddr(end
);
1137 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1138 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1139 uint32_t qentries
= 1 << (qsize
+ 10);
1143 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1145 monitor_printf(mon
, " [ ");
1146 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1147 for (i
= 0; i
< width
; i
++) {
1148 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1149 uint32_t qdata
= -1;
1151 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
1153 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1154 HWADDR_PRIx
"\n", qaddr
);
1157 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1158 be32_to_cpu(qdata
));
1159 qindex
= (qindex
+ 1) & (qentries
- 1);
1161 monitor_printf(mon
, "]");
1164 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1166 uint64_t qaddr_base
= xive_end_qaddr(end
);
1167 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1168 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1169 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1170 uint32_t qentries
= 1 << (qsize
+ 10);
1172 uint32_t nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
1173 uint32_t nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1174 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1177 if (!xive_end_is_valid(end
)) {
1181 pq
= xive_get_field32(END_W1_ESn
, end
->w1
);
1183 monitor_printf(mon
, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
1185 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1186 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1187 xive_end_is_valid(end
) ? 'v' : '-',
1188 xive_end_is_enqueue(end
) ? 'q' : '-',
1189 xive_end_is_notify(end
) ? 'n' : '-',
1190 xive_end_is_backlog(end
) ? 'b' : '-',
1191 xive_end_is_escalate(end
) ? 'e' : '-',
1192 xive_end_is_uncond_escalation(end
) ? 'u' : '-',
1193 xive_end_is_silent_escalation(end
) ? 's' : '-',
1194 priority
, nvt_blk
, nvt_idx
);
1197 monitor_printf(mon
, " eq:@%08"PRIx64
"% 6d/%5d ^%d",
1198 qaddr_base
, qindex
, qentries
, qgen
);
1199 xive_end_queue_pic_print_info(end
, 6, mon
);
1201 monitor_printf(mon
, "\n");
1204 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1206 uint64_t qaddr_base
= xive_end_qaddr(end
);
1207 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1208 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1209 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1211 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1212 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1213 uint32_t qentries
= 1 << (qsize
+ 10);
1215 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
1216 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1217 HWADDR_PRIx
"\n", qaddr
);
1221 qindex
= (qindex
+ 1) & (qentries
- 1);
1224 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1226 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1229 void xive_end_eas_pic_print_info(XiveEND
*end
, uint32_t end_idx
,
1232 XiveEAS
*eas
= (XiveEAS
*) &end
->w4
;
1235 if (!xive_end_is_escalate(end
)) {
1239 pq
= xive_get_field32(END_W1_ESe
, end
->w1
);
1241 monitor_printf(mon
, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
1243 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1244 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1245 xive_eas_is_valid(eas
) ? 'V' : ' ',
1246 xive_eas_is_masked(eas
) ? 'M' : ' ',
1247 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1248 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1249 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1253 * XIVE Router (aka. Virtualization Controller or IVRE)
1256 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1259 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1261 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1264 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1267 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1269 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1272 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1273 XiveEND
*end
, uint8_t word_number
)
1275 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1277 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1280 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1283 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1285 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1288 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1289 XiveNVT
*nvt
, uint8_t word_number
)
1291 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1293 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1296 XiveTCTX
*xive_router_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
1298 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1300 return xrc
->get_tctx(xrtr
, cs
);
1304 * Encode the HW CAM line in the block group mode format :
1306 * chip << 19 | 0000000 0 0001 thread (7Bit)
1308 static uint32_t xive_tctx_hw_cam_line(XiveTCTX
*tctx
)
1310 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1311 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1313 return xive_nvt_cam_line((pir
>> 8) & 0xf, 1 << 7 | (pir
& 0x7f));
1317 * The thread context register words are in big-endian format.
1319 static int xive_presenter_tctx_match(XiveTCTX
*tctx
, uint8_t format
,
1320 uint8_t nvt_blk
, uint32_t nvt_idx
,
1321 bool cam_ignore
, uint32_t logic_serv
)
1323 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1324 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1325 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1326 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1327 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1330 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1331 * identifier are ignored in the "CAM" match.
1335 if (cam_ignore
== true) {
1337 * F=0 & i=1: Logical server notification (bits ignored at
1338 * the end of the NVT identifier)
1340 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1345 /* F=0 & i=0: Specific NVT notification */
1348 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1349 cam
== xive_tctx_hw_cam_line(tctx
)) {
1350 return TM_QW3_HV_PHYS
;
1354 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1355 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1356 return TM_QW2_HV_POOL
;
1360 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1361 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1365 /* F=1 : User level Event-Based Branch (EBB) notification */
1368 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1369 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1370 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1371 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1378 typedef struct XiveTCTXMatch
{
1383 static bool xive_presenter_match(XiveRouter
*xrtr
, uint8_t format
,
1384 uint8_t nvt_blk
, uint32_t nvt_idx
,
1385 bool cam_ignore
, uint8_t priority
,
1386 uint32_t logic_serv
, XiveTCTXMatch
*match
)
1391 * TODO (PowerNV): handle chip_id overwrite of block field for
1392 * hardwired CAM compares
1396 XiveTCTX
*tctx
= xive_router_get_tctx(xrtr
, cs
);
1400 * Skip partially initialized vCPUs. This can happen when
1401 * vCPUs are hotplugged.
1408 * HW checks that the CPU is enabled in the Physical Thread
1409 * Enable Register (PTER).
1413 * Check the thread context CAM lines and record matches. We
1414 * will handle CPU exception delivery later
1416 ring
= xive_presenter_tctx_match(tctx
, format
, nvt_blk
, nvt_idx
,
1417 cam_ignore
, logic_serv
);
1419 * Save the context and follow on to catch duplicates, that we
1420 * don't support yet.
1424 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
1425 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
1435 qemu_log_mask(LOG_UNIMP
, "XIVE: NVT %x/%x is not dispatched\n",
1444 * This is our simple Xive Presenter Engine model. It is merged in the
1445 * Router as it does not require an extra object.
1447 * It receives notification requests sent by the IVRE to find one
1448 * matching NVT (or more) dispatched on the processor threads. In case
1449 * of a single NVT notification, the process is abreviated and the
1450 * thread is signaled if a match is found. In case of a logical server
1451 * notification (bits ignored at the end of the NVT identifier), the
1452 * IVPE and IVRE select a winning thread using different filters. This
1453 * involves 2 or 3 exchanges on the PowerBus that the model does not
1456 * The parameters represent what is sent on the PowerBus
1458 static bool xive_presenter_notify(XiveRouter
*xrtr
, uint8_t format
,
1459 uint8_t nvt_blk
, uint32_t nvt_idx
,
1460 bool cam_ignore
, uint8_t priority
,
1461 uint32_t logic_serv
)
1463 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1466 found
= xive_presenter_match(xrtr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1467 priority
, logic_serv
, &match
);
1469 ipb_update(&match
.tctx
->regs
[match
.ring
], priority
);
1470 xive_tctx_notify(match
.tctx
, match
.ring
);
1477 * Notification using the END ESe/ESn bit (Event State Buffer for
1478 * escalation and notification). Profide futher coalescing in the
1481 static bool xive_router_end_es_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1482 uint32_t end_idx
, XiveEND
*end
,
1483 uint32_t end_esmask
)
1485 uint8_t pq
= xive_get_field32(end_esmask
, end
->w1
);
1486 bool notify
= xive_esb_trigger(&pq
);
1488 if (pq
!= xive_get_field32(end_esmask
, end
->w1
)) {
1489 end
->w1
= xive_set_field32(end_esmask
, end
->w1
, pq
);
1490 xive_router_write_end(xrtr
, end_blk
, end_idx
, end
, 1);
1493 /* ESe/n[Q]=1 : end of notification */
1498 * An END trigger can come from an event trigger (IPI or HW) or from
1499 * another chip. We don't model the PowerBus but the END trigger
1500 * message has the same parameters than in the function below.
1502 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1503 uint32_t end_idx
, uint32_t end_data
)
1513 /* END cache lookup */
1514 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1515 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1520 if (!xive_end_is_valid(&end
)) {
1521 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1526 if (xive_end_is_enqueue(&end
)) {
1527 xive_end_enqueue(&end
, end_data
);
1528 /* Enqueuing event data modifies the EQ toggle and index */
1529 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1533 * When the END is silent, we skip the notification part.
1535 if (xive_end_is_silent_escalation(&end
)) {
1540 * The W7 format depends on the F bit in W6. It defines the type
1541 * of the notification :
1543 * F=0 : single or multiple NVT notification
1544 * F=1 : User level Event-Based Branch (EBB) notification, no
1547 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1548 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1550 /* The END is masked */
1551 if (format
== 0 && priority
== 0xff) {
1556 * Check the END ESn (Event State Buffer for notification) for
1557 * even futher coalescing in the Router
1559 if (!xive_end_is_notify(&end
)) {
1560 /* ESn[Q]=1 : end of notification */
1561 if (!xive_router_end_es_notify(xrtr
, end_blk
, end_idx
,
1562 &end
, END_W1_ESn
)) {
1568 * Follows IVPE notification
1570 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
);
1571 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
.w6
);
1573 /* NVT cache lookup */
1574 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1575 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1580 if (!xive_nvt_is_valid(&nvt
)) {
1581 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1586 found
= xive_presenter_notify(xrtr
, format
, nvt_blk
, nvt_idx
,
1587 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1589 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1591 /* TODO: Auto EOI. */
1598 * If no matching NVT is dispatched on a HW thread :
1599 * - specific VP: update the NVT structure if backlog is activated
1600 * - logical server : forward request to IVPE (not supported)
1602 if (xive_end_is_backlog(&end
)) {
1604 qemu_log_mask(LOG_GUEST_ERROR
,
1605 "XIVE: END %x/%x invalid config: F1 & backlog\n",
1609 /* Record the IPB in the associated NVT structure */
1610 ipb_update((uint8_t *) &nvt
.w4
, priority
);
1611 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1614 * On HW, follows a "Broadcast Backlog" to IVPEs
1620 * If activated, escalate notification using the ESe PQ bits and
1623 if (!xive_end_is_escalate(&end
)) {
1628 * Check the END ESe (Event State Buffer for escalation) for even
1629 * futher coalescing in the Router
1631 if (!xive_end_is_uncond_escalation(&end
)) {
1632 /* ESe[Q]=1 : end of notification */
1633 if (!xive_router_end_es_notify(xrtr
, end_blk
, end_idx
,
1634 &end
, END_W1_ESe
)) {
1640 * The END trigger becomes an Escalation trigger
1642 xive_router_end_notify(xrtr
,
1643 xive_get_field32(END_W4_ESC_END_BLOCK
, end
.w4
),
1644 xive_get_field32(END_W4_ESC_END_INDEX
, end
.w4
),
1645 xive_get_field32(END_W5_ESC_END_DATA
, end
.w5
));
1648 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
1650 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1651 uint8_t eas_blk
= XIVE_EAS_BLOCK(lisn
);
1652 uint32_t eas_idx
= XIVE_EAS_INDEX(lisn
);
1655 /* EAS cache lookup */
1656 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1657 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1662 * The IVRE checks the State Bit Cache at this point. We skip the
1663 * SBC lookup because the state bits of the sources are modeled
1664 * internally in QEMU.
1667 if (!xive_eas_is_valid(&eas
)) {
1668 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1672 if (xive_eas_is_masked(&eas
)) {
1673 /* Notification completed */
1678 * The event trigger becomes an END trigger
1680 xive_router_end_notify(xrtr
,
1681 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1682 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1683 xive_get_field64(EAS_END_DATA
, eas
.w
));
1686 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1688 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1689 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1691 dc
->desc
= "XIVE Router Engine";
1692 xnc
->notify
= xive_router_notify
;
1695 static const TypeInfo xive_router_info
= {
1696 .name
= TYPE_XIVE_ROUTER
,
1697 .parent
= TYPE_SYS_BUS_DEVICE
,
1699 .class_size
= sizeof(XiveRouterClass
),
1700 .class_init
= xive_router_class_init
,
1701 .interfaces
= (InterfaceInfo
[]) {
1702 { TYPE_XIVE_NOTIFIER
},
1707 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1709 if (!xive_eas_is_valid(eas
)) {
1713 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1714 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1715 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1716 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1717 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1721 * END ESB MMIO loads
1723 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1725 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1726 uint32_t offset
= addr
& 0xFFF;
1730 uint32_t end_esmask
;
1734 end_blk
= xsrc
->block_id
;
1735 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1737 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1738 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1743 if (!xive_end_is_valid(&end
)) {
1744 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1749 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1750 pq
= xive_get_field32(end_esmask
, end
.w1
);
1753 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1754 ret
= xive_esb_eoi(&pq
);
1756 /* Forward the source event notification for routing ?? */
1759 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1763 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1764 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1765 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1766 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1767 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1770 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1775 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1776 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1777 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1784 * END ESB MMIO stores are invalid
1786 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1787 uint64_t value
, unsigned size
)
1789 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1790 HWADDR_PRIx
"\n", addr
);
1793 static const MemoryRegionOps xive_end_source_ops
= {
1794 .read
= xive_end_source_read
,
1795 .write
= xive_end_source_write
,
1796 .endianness
= DEVICE_BIG_ENDIAN
,
1798 .min_access_size
= 8,
1799 .max_access_size
= 8,
1802 .min_access_size
= 8,
1803 .max_access_size
= 8,
1807 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1809 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1811 Error
*local_err
= NULL
;
1813 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1815 error_propagate(errp
, local_err
);
1816 error_prepend(errp
, "required link 'xive' not found: ");
1820 xsrc
->xrtr
= XIVE_ROUTER(obj
);
1822 if (!xsrc
->nr_ends
) {
1823 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1827 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1828 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1829 error_setg(errp
, "Invalid ESB shift setting");
1834 * Each END is assigned an even/odd pair of MMIO pages, the even page
1835 * manages the ESn field while the odd page manages the ESe field.
1837 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1838 &xive_end_source_ops
, xsrc
, "xive.end",
1839 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1842 static Property xive_end_source_properties
[] = {
1843 DEFINE_PROP_UINT8("block-id", XiveENDSource
, block_id
, 0),
1844 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1845 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1846 DEFINE_PROP_END_OF_LIST(),
1849 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1851 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1853 dc
->desc
= "XIVE END Source";
1854 dc
->props
= xive_end_source_properties
;
1855 dc
->realize
= xive_end_source_realize
;
1857 * Reason: part of XIVE interrupt controller, needs to be wired up,
1858 * e.g. by spapr_xive_instance_init().
1860 dc
->user_creatable
= false;
1863 static const TypeInfo xive_end_source_info
= {
1864 .name
= TYPE_XIVE_END_SOURCE
,
1865 .parent
= TYPE_DEVICE
,
1866 .instance_size
= sizeof(XiveENDSource
),
1867 .class_init
= xive_end_source_class_init
,
1873 static const TypeInfo xive_notifier_info
= {
1874 .name
= TYPE_XIVE_NOTIFIER
,
1875 .parent
= TYPE_INTERFACE
,
1876 .class_size
= sizeof(XiveNotifierClass
),
1879 static void xive_register_types(void)
1881 type_register_static(&xive_source_info
);
1882 type_register_static(&xive_notifier_info
);
1883 type_register_static(&xive_router_info
);
1884 type_register_static(&xive_end_source_info
);
1885 type_register_static(&xive_tctx_info
);
1888 type_init(xive_register_types
)