hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  48
  49     if (!icp->output) {
  50         return;
  51     }
  52
  53     if (kvm_irqchip_in_kernel()) {
  54         icp_synchronize_state(icp);
  55     }
  56
  57     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  58                    cpu_index, icp->xirr, icp->xirr_owner,
  59                    icp->pending_priority, icp->mfrr);
  60 }
  61
  62 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  63 {
  64     uint32_t i;
  65
  66     monitor_printf(mon, "ICS %4x..%4x %p\n",
  67                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  68
  69     if (!ics->irqs) {
  70         return;
  71     }
  72
  73     if (kvm_irqchip_in_kernel()) {
  74         ics_synchronize_state(ics);
  75     }
  76
  77     for (i = 0; i < ics->nr_irqs; i++) {
  78         ICSIRQState *irq = ics->irqs + i;
  79
  80         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  81             continue;
  82         }
  83         monitor_printf(mon, "  %4x %s %02x %02x\n",
  84                        ics->offset + i,
  85                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  86                        "LSI" : "MSI",
  87                        irq->priority, irq->status);
  88     }
  89 }
  90
  91 /*
  92  * ICP: Presentation layer
  93  */
  94
  95 #define XISR_MASK  0x00ffffff
  96 #define CPPR_MASK  0xff000000
  97
  98 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
  99 #define CPPR(icp)   (((icp)->xirr) >> 24)
 100
 101 static void ics_reject(ICSState *ics, uint32_t nr);
 102 static void ics_eoi(ICSState *ics, uint32_t nr);
 103
 104 static void icp_check_ipi(ICPState *icp)
 105 {
 106     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 107         return;
 108     }
 109
 110     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 111
 112     if (XISR(icp) && icp->xirr_owner) {
 113         ics_reject(icp->xirr_owner, XISR(icp));
 114     }
 115
 116     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 117     icp->pending_priority = icp->mfrr;
 118     icp->xirr_owner = NULL;
 119     qemu_irq_raise(icp->output);
 120 }
 121
 122 void icp_resend(ICPState *icp)
 123 {
 124     XICSFabric *xi = icp->xics;
 125     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 126
 127     if (icp->mfrr < CPPR(icp)) {
 128         icp_check_ipi(icp);
 129     }
 130
 131     xic->ics_resend(xi);
 132 }
 133
 134 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 135 {
 136     uint8_t old_cppr;
 137     uint32_t old_xisr;
 138
 139     old_cppr = CPPR(icp);
 140     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 141
 142     if (cppr < old_cppr) {
 143         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 144             old_xisr = XISR(icp);
 145             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 146             icp->pending_priority = 0xff;
 147             qemu_irq_lower(icp->output);
 148             if (icp->xirr_owner) {
 149                 ics_reject(icp->xirr_owner, old_xisr);
 150                 icp->xirr_owner = NULL;
 151             }
 152         }
 153     } else {
 154         if (!XISR(icp)) {
 155             icp_resend(icp);
 156         }
 157     }
 158 }
 159
 160 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 161 {
 162     icp->mfrr = mfrr;
 163     if (mfrr < CPPR(icp)) {
 164         icp_check_ipi(icp);
 165     }
 166 }
 167
 168 uint32_t icp_accept(ICPState *icp)
 169 {
 170     uint32_t xirr = icp->xirr;
 171
 172     qemu_irq_lower(icp->output);
 173     icp->xirr = icp->pending_priority << 24;
 174     icp->pending_priority = 0xff;
 175     icp->xirr_owner = NULL;
 176
 177     trace_xics_icp_accept(xirr, icp->xirr);
 178
 179     return xirr;
 180 }
 181
 182 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 183 {
 184     if (mfrr) {
 185         *mfrr = icp->mfrr;
 186     }
 187     return icp->xirr;
 188 }
 189
 190 void icp_eoi(ICPState *icp, uint32_t xirr)
 191 {
 192     XICSFabric *xi = icp->xics;
 193     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 194     ICSState *ics;
 195     uint32_t irq;
 196
 197     /* Send EOI -> ICS */
 198     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 199     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 200     irq = xirr & XISR_MASK;
 201
 202     ics = xic->ics_get(xi, irq);
 203     if (ics) {
 204         ics_eoi(ics, irq);
 205     }
 206     if (!XISR(icp)) {
 207         icp_resend(icp);
 208     }
 209 }
 210
 211 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 212 {
 213     ICPState *icp = xics_icp_get(ics->xics, server);
 214
 215     trace_xics_icp_irq(server, nr, priority);
 216
 217     if ((priority >= CPPR(icp))
 218         || (XISR(icp) && (icp->pending_priority <= priority))) {
 219         ics_reject(ics, nr);
 220     } else {
 221         if (XISR(icp) && icp->xirr_owner) {
 222             ics_reject(icp->xirr_owner, XISR(icp));
 223             icp->xirr_owner = NULL;
 224         }
 225         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 226         icp->xirr_owner = ics;
 227         icp->pending_priority = priority;
 228         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 229         qemu_irq_raise(icp->output);
 230     }
 231 }
 232
 233 static int icp_pre_save(void *opaque)
 234 {
 235     ICPState *icp = opaque;
 236
 237     if (kvm_irqchip_in_kernel()) {
 238         icp_get_kvm_state(icp);
 239     }
 240
 241     return 0;
 242 }
 243
 244 static int icp_post_load(void *opaque, int version_id)
 245 {
 246     ICPState *icp = opaque;
 247
 248     if (kvm_irqchip_in_kernel()) {
 249         Error *local_err = NULL;
 250         int ret;
 251
 252         ret = icp_set_kvm_state(icp, &local_err);
 253         if (ret < 0) {
 254             error_report_err(local_err);
 255             return ret;
 256         }
 257     }
 258
 259     return 0;
 260 }
 261
 262 static const VMStateDescription vmstate_icp_server = {
 263     .name = "icp/server",
 264     .version_id = 1,
 265     .minimum_version_id = 1,
 266     .pre_save = icp_pre_save,
 267     .post_load = icp_post_load,
 268     .fields = (VMStateField[]) {
 269         /* Sanity check */
 270         VMSTATE_UINT32(xirr, ICPState),
 271         VMSTATE_UINT8(pending_priority, ICPState),
 272         VMSTATE_UINT8(mfrr, ICPState),
 273         VMSTATE_END_OF_LIST()
 274     },
 275 };
 276
 277 void icp_reset(ICPState *icp)
 278 {
 279     icp->xirr = 0;
 280     icp->pending_priority = 0xff;
 281     icp->mfrr = 0xff;
 282
 283     /* Make all outputs are deasserted */
 284     qemu_set_irq(icp->output, 0);
 285
 286     if (kvm_irqchip_in_kernel()) {
 287         Error *local_err = NULL;
 288
 289         icp_set_kvm_state(icp, &local_err);
 290         if (local_err) {
 291             error_report_err(local_err);
 292         }
 293     }
 294 }
 295
 296 static void icp_realize(DeviceState *dev, Error **errp)
 297 {
 298     ICPState *icp = ICP(dev);
 299     PowerPCCPU *cpu;
 300     CPUPPCState *env;
 301     Object *obj;
 302     Error *err = NULL;
 303
 304     obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
 305     if (!obj) {
 306         error_propagate_prepend(errp, err,
 307                                 "required link '" ICP_PROP_XICS
 308                                 "' not found: ");
 309         return;
 310     }
 311
 312     icp->xics = XICS_FABRIC(obj);
 313
 314     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
 315     if (!obj) {
 316         error_propagate_prepend(errp, err,
 317                                 "required link '" ICP_PROP_CPU
 318                                 "' not found: ");
 319         return;
 320     }
 321
 322     cpu = POWERPC_CPU(obj);
 323     icp->cs = CPU(obj);
 324
 325     env = &cpu->env;
 326     switch (PPC_INPUT(env)) {
 327     case PPC_FLAGS_INPUT_POWER7:
 328         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 329         break;
 330     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 331         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 332         break;
 333
 334     case PPC_FLAGS_INPUT_970:
 335         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 336         break;
 337
 338     default:
 339         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 340         return;
 341     }
 342
 343     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 344     if (kvm_irqchip_in_kernel()) {
 345         icp_kvm_realize(dev, &err);
 346         if (err) {
 347             error_propagate(errp, err);
 348             return;
 349         }
 350     }
 351
 352     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 353 }
 354
 355 static void icp_unrealize(DeviceState *dev, Error **errp)
 356 {
 357     ICPState *icp = ICP(dev);
 358
 359     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 360 }
 361
 362 static void icp_class_init(ObjectClass *klass, void *data)
 363 {
 364     DeviceClass *dc = DEVICE_CLASS(klass);
 365
 366     dc->realize = icp_realize;
 367     dc->unrealize = icp_unrealize;
 368     /*
 369      * Reason: part of XICS interrupt controller, needs to be wired up
 370      * by icp_create().
 371      */
 372     dc->user_creatable = false;
 373 }
 374
 375 static const TypeInfo icp_info = {
 376     .name = TYPE_ICP,
 377     .parent = TYPE_DEVICE,
 378     .instance_size = sizeof(ICPState),
 379     .class_init = icp_class_init,
 380     .class_size = sizeof(ICPStateClass),
 381 };
 382
 383 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 384 {
 385     Error *local_err = NULL;
 386     Object *obj;
 387
 388     obj = object_new(type);
 389     object_property_add_child(cpu, type, obj, &error_abort);
 390     object_unref(obj);
 391     object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
 392                                    &error_abort);
 393     object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
 394     object_property_set_bool(obj, true, "realized", &local_err);
 395     if (local_err) {
 396         object_unparent(obj);
 397         error_propagate(errp, local_err);
 398         obj = NULL;
 399     }
 400
 401     return obj;
 402 }
 403
 404 /*
 405  * ICS: Source layer
 406  */
 407 static void ics_resend_msi(ICSState *ics, int srcno)
 408 {
 409     ICSIRQState *irq = ics->irqs + srcno;
 410
 411     /* FIXME: filter by server#? */
 412     if (irq->status & XICS_STATUS_REJECTED) {
 413         irq->status &= ~XICS_STATUS_REJECTED;
 414         if (irq->priority != 0xff) {
 415             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 416         }
 417     }
 418 }
 419
 420 static void ics_resend_lsi(ICSState *ics, int srcno)
 421 {
 422     ICSIRQState *irq = ics->irqs + srcno;
 423
 424     if ((irq->priority != 0xff)
 425         && (irq->status & XICS_STATUS_ASSERTED)
 426         && !(irq->status & XICS_STATUS_SENT)) {
 427         irq->status |= XICS_STATUS_SENT;
 428         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 429     }
 430 }
 431
 432 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 433 {
 434     ICSIRQState *irq = ics->irqs + srcno;
 435
 436     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 437
 438     if (val) {
 439         if (irq->priority == 0xff) {
 440             irq->status |= XICS_STATUS_MASKED_PENDING;
 441             trace_xics_masked_pending();
 442         } else  {
 443             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 444         }
 445     }
 446 }
 447
 448 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 449 {
 450     ICSIRQState *irq = ics->irqs + srcno;
 451
 452     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 453     if (val) {
 454         irq->status |= XICS_STATUS_ASSERTED;
 455     } else {
 456         irq->status &= ~XICS_STATUS_ASSERTED;
 457     }
 458     ics_resend_lsi(ics, srcno);
 459 }
 460
 461 void ics_set_irq(void *opaque, int srcno, int val)
 462 {
 463     ICSState *ics = (ICSState *)opaque;
 464
 465     if (kvm_irqchip_in_kernel()) {
 466         ics_kvm_set_irq(ics, srcno, val);
 467         return;
 468     }
 469
 470     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 471         ics_set_irq_lsi(ics, srcno, val);
 472     } else {
 473         ics_set_irq_msi(ics, srcno, val);
 474     }
 475 }
 476
 477 static void ics_write_xive_msi(ICSState *ics, int srcno)
 478 {
 479     ICSIRQState *irq = ics->irqs + srcno;
 480
 481     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 482         || (irq->priority == 0xff)) {
 483         return;
 484     }
 485
 486     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 487     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 488 }
 489
 490 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 491 {
 492     ics_resend_lsi(ics, srcno);
 493 }
 494
 495 void ics_write_xive(ICSState *ics, int srcno, int server,
 496                     uint8_t priority, uint8_t saved_priority)
 497 {
 498     ICSIRQState *irq = ics->irqs + srcno;
 499
 500     irq->server = server;
 501     irq->priority = priority;
 502     irq->saved_priority = saved_priority;
 503
 504     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 505
 506     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 507         ics_write_xive_lsi(ics, srcno);
 508     } else {
 509         ics_write_xive_msi(ics, srcno);
 510     }
 511 }
 512
 513 static void ics_reject(ICSState *ics, uint32_t nr)
 514 {
 515     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 516
 517     trace_xics_ics_reject(nr, nr - ics->offset);
 518     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 519         irq->status |= XICS_STATUS_REJECTED;
 520     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 521         irq->status &= ~XICS_STATUS_SENT;
 522     }
 523 }
 524
 525 void ics_resend(ICSState *ics)
 526 {
 527     int i;
 528
 529     for (i = 0; i < ics->nr_irqs; i++) {
 530         /* FIXME: filter by server#? */
 531         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 532             ics_resend_lsi(ics, i);
 533         } else {
 534             ics_resend_msi(ics, i);
 535         }
 536     }
 537 }
 538
 539 static void ics_eoi(ICSState *ics, uint32_t nr)
 540 {
 541     int srcno = nr - ics->offset;
 542     ICSIRQState *irq = ics->irqs + srcno;
 543
 544     trace_xics_ics_eoi(nr);
 545
 546     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 547         irq->status &= ~XICS_STATUS_SENT;
 548     }
 549 }
 550
 551 static void ics_reset_irq(ICSIRQState *irq)
 552 {
 553     irq->priority = 0xff;
 554     irq->saved_priority = 0xff;
 555 }
 556
 557 static void ics_reset(DeviceState *dev)
 558 {
 559     ICSState *ics = ICS(dev);
 560     int i;
 561     uint8_t flags[ics->nr_irqs];
 562
 563     for (i = 0; i < ics->nr_irqs; i++) {
 564         flags[i] = ics->irqs[i].flags;
 565     }
 566
 567     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 568
 569     for (i = 0; i < ics->nr_irqs; i++) {
 570         ics_reset_irq(ics->irqs + i);
 571         ics->irqs[i].flags = flags[i];
 572     }
 573
 574     if (kvm_irqchip_in_kernel()) {
 575         Error *local_err = NULL;
 576
 577         ics_set_kvm_state(ICS(dev), &local_err);
 578         if (local_err) {
 579             error_report_err(local_err);
 580         }
 581     }
 582 }
 583
 584 static void ics_reset_handler(void *dev)
 585 {
 586     ics_reset(dev);
 587 }
 588
 589 static void ics_realize(DeviceState *dev, Error **errp)
 590 {
 591     ICSState *ics = ICS(dev);
 592     Error *local_err = NULL;
 593     Object *obj;
 594
 595     obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &local_err);
 596     if (!obj) {
 597         error_propagate_prepend(errp, local_err,
 598                                 "required link '" ICS_PROP_XICS
 599                                 "' not found: ");
 600         return;
 601     }
 602     ics->xics = XICS_FABRIC(obj);
 603
 604     if (!ics->nr_irqs) {
 605         error_setg(errp, "Number of interrupts needs to be greater 0");
 606         return;
 607     }
 608     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 609
 610     qemu_register_reset(ics_reset_handler, ics);
 611 }
 612
 613 static void ics_instance_init(Object *obj)
 614 {
 615     ICSState *ics = ICS(obj);
 616
 617     ics->offset = XICS_IRQ_BASE;
 618 }
 619
 620 static int ics_pre_save(void *opaque)
 621 {
 622     ICSState *ics = opaque;
 623
 624     if (kvm_irqchip_in_kernel()) {
 625         ics_get_kvm_state(ics);
 626     }
 627
 628     return 0;
 629 }
 630
 631 static int ics_post_load(void *opaque, int version_id)
 632 {
 633     ICSState *ics = opaque;
 634
 635     if (kvm_irqchip_in_kernel()) {
 636         Error *local_err = NULL;
 637         int ret;
 638
 639         ret = ics_set_kvm_state(ics, &local_err);
 640         if (ret < 0) {
 641             error_report_err(local_err);
 642             return ret;
 643         }
 644     }
 645
 646     return 0;
 647 }
 648
 649 static const VMStateDescription vmstate_ics_irq = {
 650     .name = "ics/irq",
 651     .version_id = 2,
 652     .minimum_version_id = 1,
 653     .fields = (VMStateField[]) {
 654         VMSTATE_UINT32(server, ICSIRQState),
 655         VMSTATE_UINT8(priority, ICSIRQState),
 656         VMSTATE_UINT8(saved_priority, ICSIRQState),
 657         VMSTATE_UINT8(status, ICSIRQState),
 658         VMSTATE_UINT8(flags, ICSIRQState),
 659         VMSTATE_END_OF_LIST()
 660     },
 661 };
 662
 663 static const VMStateDescription vmstate_ics = {
 664     .name = "ics",
 665     .version_id = 1,
 666     .minimum_version_id = 1,
 667     .pre_save = ics_pre_save,
 668     .post_load = ics_post_load,
 669     .fields = (VMStateField[]) {
 670         /* Sanity check */
 671         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 672
 673         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 674                                              vmstate_ics_irq,
 675                                              ICSIRQState),
 676         VMSTATE_END_OF_LIST()
 677     },
 678 };
 679
 680 static Property ics_properties[] = {
 681     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 682     DEFINE_PROP_END_OF_LIST(),
 683 };
 684
 685 static void ics_class_init(ObjectClass *klass, void *data)
 686 {
 687     DeviceClass *dc = DEVICE_CLASS(klass);
 688
 689     dc->realize = ics_realize;
 690     dc->props = ics_properties;
 691     dc->reset = ics_reset;
 692     dc->vmsd = &vmstate_ics;
 693     /*
 694      * Reason: part of XICS interrupt controller, needs to be wired up,
 695      * e.g. by spapr_irq_init().
 696      */
 697     dc->user_creatable = false;
 698 }
 699
 700 static const TypeInfo ics_info = {
 701     .name = TYPE_ICS,
 702     .parent = TYPE_DEVICE,
 703     .instance_size = sizeof(ICSState),
 704     .instance_init = ics_instance_init,
 705     .class_init = ics_class_init,
 706     .class_size = sizeof(ICSStateClass),
 707 };
 708
 709 static const TypeInfo xics_fabric_info = {
 710     .name = TYPE_XICS_FABRIC,
 711     .parent = TYPE_INTERFACE,
 712     .class_size = sizeof(XICSFabricClass),
 713 };
 714
 715 /*
 716  * Exported functions
 717  */
 718 ICPState *xics_icp_get(XICSFabric *xi, int server)
 719 {
 720     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 721
 722     return xic->icp_get(xi, server);
 723 }
 724
 725 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 726 {
 727     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 728
 729     ics->irqs[srcno].flags |=
 730         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 731
 732     if (kvm_irqchip_in_kernel()) {
 733         Error *local_err = NULL;
 734
 735         ics_reset_irq(ics->irqs + srcno);
 736         ics_set_kvm_state_one(ics, srcno, &local_err);
 737         if (local_err) {
 738             error_report_err(local_err);
 739         }
 740     }
 741 }
 742
 743 static void xics_register_types(void)
 744 {
 745     type_register_static(&ics_info);
 746     type_register_static(&icp_info);
 747     type_register_static(&xics_fabric_info);
 748 }
 749
 750 type_init(xics_register_types)