hw/ppc/pnv_lpc.c

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "sysemu/sysemu.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qapi/error.h"
  24 #include "qemu/log.h"
  25 #include "hw/isa/isa.h"
  26
  27 #include "hw/ppc/pnv.h"
  28 #include "hw/ppc/pnv_lpc.h"
  29 #include "hw/ppc/pnv_xscom.h"
  30 #include "hw/ppc/fdt.h"
  31
  32 #include <libfdt.h>
  33
  34 enum {
  35     ECCB_CTL    = 0,
  36     ECCB_RESET  = 1,
  37     ECCB_STAT   = 2,
  38     ECCB_DATA   = 3,
  39 };
  40
  41 /* OPB Master LS registers */
  42 #define OPB_MASTER_LS_IRQ_STAT  0x50
  43 #define   OPB_MASTER_IRQ_LPC            0x00000800
  44 #define OPB_MASTER_LS_IRQ_MASK  0x54
  45 #define OPB_MASTER_LS_IRQ_POL   0x58
  46 #define OPB_MASTER_LS_IRQ_INPUT 0x5c
  47
  48 /* LPC HC registers */
  49 #define LPC_HC_FW_SEG_IDSEL     0x24
  50 #define LPC_HC_FW_RD_ACC_SIZE   0x28
  51 #define   LPC_HC_FW_RD_1B               0x00000000
  52 #define   LPC_HC_FW_RD_2B               0x01000000
  53 #define   LPC_HC_FW_RD_4B               0x02000000
  54 #define   LPC_HC_FW_RD_16B              0x04000000
  55 #define   LPC_HC_FW_RD_128B             0x07000000
  56 #define LPC_HC_IRQSER_CTRL      0x30
  57 #define   LPC_HC_IRQSER_EN              0x80000000
  58 #define   LPC_HC_IRQSER_QMODE           0x40000000
  59 #define   LPC_HC_IRQSER_START_MASK      0x03000000
  60 #define   LPC_HC_IRQSER_START_4CLK      0x00000000
  61 #define   LPC_HC_IRQSER_START_6CLK      0x01000000
  62 #define   LPC_HC_IRQSER_START_8CLK      0x02000000
  63 #define LPC_HC_IRQMASK          0x34    /* same bit defs as LPC_HC_IRQSTAT */
  64 #define LPC_HC_IRQSTAT          0x38
  65 #define   LPC_HC_IRQ_SERIRQ0            0x80000000 /* all bits down to ... */
  66 #define   LPC_HC_IRQ_SERIRQ16           0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */
  67 #define   LPC_HC_IRQ_SERIRQ_ALL         0xffff8000
  68 #define   LPC_HC_IRQ_LRESET             0x00000400
  69 #define   LPC_HC_IRQ_SYNC_ABNORM_ERR    0x00000080
  70 #define   LPC_HC_IRQ_SYNC_NORESP_ERR    0x00000040
  71 #define   LPC_HC_IRQ_SYNC_NORM_ERR      0x00000020
  72 #define   LPC_HC_IRQ_SYNC_TIMEOUT_ERR   0x00000010
  73 #define   LPC_HC_IRQ_SYNC_TARG_TAR_ERR  0x00000008
  74 #define   LPC_HC_IRQ_SYNC_BM_TAR_ERR    0x00000004
  75 #define   LPC_HC_IRQ_SYNC_BM0_REQ       0x00000002
  76 #define   LPC_HC_IRQ_SYNC_BM1_REQ       0x00000001
  77 #define LPC_HC_ERROR_ADDRESS    0x40
  78
  79 #define LPC_OPB_SIZE            0x100000000ull
  80
  81 #define ISA_IO_SIZE             0x00010000
  82 #define ISA_MEM_SIZE            0x10000000
  83 #define ISA_FW_SIZE             0x10000000
  84 #define LPC_IO_OPB_ADDR         0xd0010000
  85 #define LPC_IO_OPB_SIZE         0x00010000
  86 #define LPC_MEM_OPB_ADDR        0xe0010000
  87 #define LPC_MEM_OPB_SIZE        0x10000000
  88 #define LPC_FW_OPB_ADDR         0xf0000000
  89 #define LPC_FW_OPB_SIZE         0x10000000
  90
  91 #define LPC_OPB_REGS_OPB_ADDR   0xc0010000
  92 #define LPC_OPB_REGS_OPB_SIZE   0x00002000
  93 #define LPC_HC_REGS_OPB_ADDR    0xc0012000
  94 #define LPC_HC_REGS_OPB_SIZE    0x00001000
  95
  96
  97 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
  98 {
  99     const char compat[] = "ibm,power8-lpc\0ibm,lpc";
 100     char *name;
 101     int offset;
 102     uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE;
 103     uint32_t reg[] = {
 104         cpu_to_be32(lpc_pcba),
 105         cpu_to_be32(PNV_XSCOM_LPC_SIZE)
 106     };
 107
 108     name = g_strdup_printf("isa@%x", lpc_pcba);
 109     offset = fdt_add_subnode(fdt, xscom_offset, name);
 110     _FDT(offset);
 111     g_free(name);
 112
 113     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 114     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2)));
 115     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1)));
 116     _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
 117     return 0;
 118 }
 119
 120 /*
 121  * These read/write handlers of the OPB address space should be common
 122  * with the P9 LPC Controller which uses direct MMIOs.
 123  *
 124  * TODO: rework to use address_space_stq() and address_space_ldq()
 125  * instead.
 126  */
 127 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 128                      int sz)
 129 {
 130     /* XXX Handle access size limits and FW read caching here */
 131     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 132                              data, sz, false);
 133 }
 134
 135 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data,
 136                       int sz)
 137 {
 138     /* XXX Handle access size limits here */
 139     return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED,
 140                              data, sz, true);
 141 }
 142
 143 #define ECCB_CTL_READ           PPC_BIT(15)
 144 #define ECCB_CTL_SZ_LSH         (63 - 7)
 145 #define ECCB_CTL_SZ_MASK        PPC_BITMASK(4, 7)
 146 #define ECCB_CTL_ADDR_MASK      PPC_BITMASK(32, 63)
 147
 148 #define ECCB_STAT_OP_DONE       PPC_BIT(52)
 149 #define ECCB_STAT_OP_ERR        PPC_BIT(52)
 150 #define ECCB_STAT_RD_DATA_LSH   (63 - 37)
 151 #define ECCB_STAT_RD_DATA_MASK  (0xffffffff << ECCB_STAT_RD_DATA_LSH)
 152
 153 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd)
 154 {
 155     /* XXX Check for magic bits at the top, addr size etc... */
 156     unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH;
 157     uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK;
 158     uint8_t data[4];
 159     bool success;
 160
 161     if (cmd & ECCB_CTL_READ) {
 162         success = opb_read(lpc, opb_addr, data, sz);
 163         if (success) {
 164             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 165                     (((uint64_t)data[0]) << 24 |
 166                      ((uint64_t)data[1]) << 16 |
 167                      ((uint64_t)data[2]) <<  8 |
 168                      ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH;
 169         } else {
 170             lpc->eccb_stat_reg = ECCB_STAT_OP_DONE |
 171                     (0xffffffffull << ECCB_STAT_RD_DATA_LSH);
 172         }
 173     } else {
 174         data[0] = lpc->eccb_data_reg >> 24;
 175         data[1] = lpc->eccb_data_reg >> 16;
 176         data[2] = lpc->eccb_data_reg >>  8;
 177         data[3] = lpc->eccb_data_reg;
 178
 179         success = opb_write(lpc, opb_addr, data, sz);
 180         lpc->eccb_stat_reg = ECCB_STAT_OP_DONE;
 181     }
 182     /* XXX Which error bit (if any) to signal OPB error ? */
 183 }
 184
 185 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size)
 186 {
 187     PnvLpcController *lpc = PNV_LPC(opaque);
 188     uint32_t offset = addr >> 3;
 189     uint64_t val = 0;
 190
 191     switch (offset & 3) {
 192     case ECCB_CTL:
 193     case ECCB_RESET:
 194         val = 0;
 195         break;
 196     case ECCB_STAT:
 197         val = lpc->eccb_stat_reg;
 198         lpc->eccb_stat_reg = 0;
 199         break;
 200     case ECCB_DATA:
 201         val = ((uint64_t)lpc->eccb_data_reg) << 32;
 202         break;
 203     }
 204     return val;
 205 }
 206
 207 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr,
 208                                 uint64_t val, unsigned size)
 209 {
 210     PnvLpcController *lpc = PNV_LPC(opaque);
 211     uint32_t offset = addr >> 3;
 212
 213     switch (offset & 3) {
 214     case ECCB_CTL:
 215         pnv_lpc_do_eccb(lpc, val);
 216         break;
 217     case ECCB_RESET:
 218         /*  XXXX  */
 219         break;
 220     case ECCB_STAT:
 221         break;
 222     case ECCB_DATA:
 223         lpc->eccb_data_reg = val >> 32;
 224         break;
 225     }
 226 }
 227
 228 static const MemoryRegionOps pnv_lpc_xscom_ops = {
 229     .read = pnv_lpc_xscom_read,
 230     .write = pnv_lpc_xscom_write,
 231     .valid.min_access_size = 8,
 232     .valid.max_access_size = 8,
 233     .impl.min_access_size = 8,
 234     .impl.max_access_size = 8,
 235     .endianness = DEVICE_BIG_ENDIAN,
 236 };
 237
 238 static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
 239 {
 240     bool lpc_to_opb_irq = false;
 241
 242     /* Update LPC controller to OPB line */
 243     if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
 244         uint32_t irqs;
 245
 246         irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask;
 247         lpc_to_opb_irq = (irqs != 0);
 248     }
 249
 250     /* We don't honor the polarity register, it's pointless and unused
 251      * anyway
 252      */
 253     if (lpc_to_opb_irq) {
 254         lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC;
 255     } else {
 256         lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC;
 257     }
 258
 259     /* Update OPB internal latch */
 260     lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
 261
 262     /* Reflect the interrupt */
 263     pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0);
 264 }
 265
 266 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
 267 {
 268     PnvLpcController *lpc = opaque;
 269     uint64_t val = 0xfffffffffffffffful;
 270
 271     switch (addr) {
 272     case LPC_HC_FW_SEG_IDSEL:
 273         val =  lpc->lpc_hc_fw_seg_idsel;
 274         break;
 275     case LPC_HC_FW_RD_ACC_SIZE:
 276         val =  lpc->lpc_hc_fw_rd_acc_size;
 277         break;
 278     case LPC_HC_IRQSER_CTRL:
 279         val =  lpc->lpc_hc_irqser_ctrl;
 280         break;
 281     case LPC_HC_IRQMASK:
 282         val =  lpc->lpc_hc_irqmask;
 283         break;
 284     case LPC_HC_IRQSTAT:
 285         val =  lpc->lpc_hc_irqstat;
 286         break;
 287     case LPC_HC_ERROR_ADDRESS:
 288         val =  lpc->lpc_hc_error_addr;
 289         break;
 290     default:
 291         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
 292                       HWADDR_PRIx "\n", addr);
 293     }
 294     return val;
 295 }
 296
 297 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val,
 298                          unsigned size)
 299 {
 300     PnvLpcController *lpc = opaque;
 301
 302     /* XXX Filter out reserved bits */
 303
 304     switch (addr) {
 305     case LPC_HC_FW_SEG_IDSEL:
 306         /* XXX Actually figure out how that works as this impact
 307          * memory regions/aliases
 308          */
 309         lpc->lpc_hc_fw_seg_idsel = val;
 310         break;
 311     case LPC_HC_FW_RD_ACC_SIZE:
 312         lpc->lpc_hc_fw_rd_acc_size = val;
 313         break;
 314     case LPC_HC_IRQSER_CTRL:
 315         lpc->lpc_hc_irqser_ctrl = val;
 316         pnv_lpc_eval_irqs(lpc);
 317         break;
 318     case LPC_HC_IRQMASK:
 319         lpc->lpc_hc_irqmask = val;
 320         pnv_lpc_eval_irqs(lpc);
 321         break;
 322     case LPC_HC_IRQSTAT:
 323         lpc->lpc_hc_irqstat &= ~val;
 324         pnv_lpc_eval_irqs(lpc);
 325         break;
 326     case LPC_HC_ERROR_ADDRESS:
 327         break;
 328     default:
 329         qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%"
 330                       HWADDR_PRIx "\n", addr);
 331     }
 332 }
 333
 334 static const MemoryRegionOps lpc_hc_ops = {
 335     .read = lpc_hc_read,
 336     .write = lpc_hc_write,
 337     .endianness = DEVICE_BIG_ENDIAN,
 338     .valid = {
 339         .min_access_size = 4,
 340         .max_access_size = 4,
 341     },
 342     .impl = {
 343         .min_access_size = 4,
 344         .max_access_size = 4,
 345     },
 346 };
 347
 348 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size)
 349 {
 350     PnvLpcController *lpc = opaque;
 351     uint64_t val = 0xfffffffffffffffful;
 352
 353     switch (addr) {
 354     case OPB_MASTER_LS_IRQ_STAT:
 355         val = lpc->opb_irq_stat;
 356         break;
 357     case OPB_MASTER_LS_IRQ_MASK:
 358         val = lpc->opb_irq_mask;
 359         break;
 360     case OPB_MASTER_LS_IRQ_POL:
 361         val = lpc->opb_irq_pol;
 362         break;
 363     case OPB_MASTER_LS_IRQ_INPUT:
 364         val = lpc->opb_irq_input;
 365         break;
 366     default:
 367         qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
 368                       HWADDR_PRIx "\n", addr);
 369     }
 370
 371     return val;
 372 }
 373
 374 static void opb_master_write(void *opaque, hwaddr addr,
 375                              uint64_t val, unsigned size)
 376 {
 377     PnvLpcController *lpc = opaque;
 378
 379     switch (addr) {
 380     case OPB_MASTER_LS_IRQ_STAT:
 381         lpc->opb_irq_stat &= ~val;
 382         pnv_lpc_eval_irqs(lpc);
 383         break;
 384     case OPB_MASTER_LS_IRQ_MASK:
 385         lpc->opb_irq_mask = val;
 386         pnv_lpc_eval_irqs(lpc);
 387         break;
 388     case OPB_MASTER_LS_IRQ_POL:
 389         lpc->opb_irq_pol = val;
 390         pnv_lpc_eval_irqs(lpc);
 391         break;
 392     case OPB_MASTER_LS_IRQ_INPUT:
 393         /* Read only */
 394         break;
 395     default:
 396         qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%"
 397                       HWADDR_PRIx "\n", addr);
 398     }
 399 }
 400
 401 static const MemoryRegionOps opb_master_ops = {
 402     .read = opb_master_read,
 403     .write = opb_master_write,
 404     .endianness = DEVICE_BIG_ENDIAN,
 405     .valid = {
 406         .min_access_size = 4,
 407         .max_access_size = 4,
 408     },
 409     .impl = {
 410         .min_access_size = 4,
 411         .max_access_size = 4,
 412     },
 413 };
 414
 415 static void pnv_lpc_realize(DeviceState *dev, Error **errp)
 416 {
 417     PnvLpcController *lpc = PNV_LPC(dev);
 418     Object *obj;
 419     Error *error = NULL;
 420
 421     /* Reg inits */
 422     lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
 423
 424     /* Create address space and backing MR for the OPB bus */
 425     memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull);
 426     address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb");
 427
 428     /* Create ISA IO and Mem space regions which are the root of
 429      * the ISA bus (ie, ISA address spaces). We don't create a
 430      * separate one for FW which we alias to memory.
 431      */
 432     memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE);
 433     memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE);
 434     memory_region_init(&lpc->isa_fw, OBJECT(dev),  "isa-fw", ISA_FW_SIZE);
 435
 436     /* Create windows from the OPB space to the ISA space */
 437     memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io",
 438                              &lpc->isa_io, 0, LPC_IO_OPB_SIZE);
 439     memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR,
 440                                 &lpc->opb_isa_io);
 441     memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem",
 442                              &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE);
 443     memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR,
 444                                 &lpc->opb_isa_mem);
 445     memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw",
 446                              &lpc->isa_fw, 0, LPC_FW_OPB_SIZE);
 447     memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR,
 448                                 &lpc->opb_isa_fw);
 449
 450     /* Create MMIO regions for LPC HC and OPB registers */
 451     memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops,
 452                           lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE);
 453     memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR,
 454                                 &lpc->opb_master_regs);
 455     memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc,
 456                           "lpc-hc", LPC_HC_REGS_OPB_SIZE);
 457     memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
 458                                 &lpc->lpc_hc_regs);
 459
 460     /* XScom region for LPC registers */
 461     pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev),
 462                           &pnv_lpc_xscom_ops, lpc, "xscom-lpc",
 463                           PNV_XSCOM_LPC_SIZE);
 464
 465     /* get PSI object from chip */
 466     obj = object_property_get_link(OBJECT(dev), "psi", &error);
 467     if (!obj) {
 468         error_setg(errp, "%s: required link 'psi' not found: %s",
 469                    __func__, error_get_pretty(error));
 470         return;
 471     }
 472     lpc->psi = PNV_PSI(obj);
 473 }
 474
 475 static void pnv_lpc_class_init(ObjectClass *klass, void *data)
 476 {
 477     DeviceClass *dc = DEVICE_CLASS(klass);
 478     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 479
 480     xdc->dt_xscom = pnv_lpc_dt_xscom;
 481
 482     dc->realize = pnv_lpc_realize;
 483 }
 484
 485 static const TypeInfo pnv_lpc_info = {
 486     .name          = TYPE_PNV_LPC,
 487     .parent        = TYPE_DEVICE,
 488     .instance_size = sizeof(PnvLpcController),
 489     .class_init    = pnv_lpc_class_init,
 490     .interfaces = (InterfaceInfo[]) {
 491         { TYPE_PNV_XSCOM_INTERFACE },
 492         { }
 493     }
 494 };
 495
 496 static void pnv_lpc_register_types(void)
 497 {
 498     type_register_static(&pnv_lpc_info);
 499 }
 500
 501 type_init(pnv_lpc_register_types)
 502
 503 /* If we don't use the built-in LPC interrupt deserializer, we need
 504  * to provide a set of qirqs for the ISA bus or things will go bad.
 505  *
 506  * Most machines using pre-Naples chips (without said deserializer)
 507  * have a CPLD that will collect the SerIRQ and shoot them as a
 508  * single level interrupt to the P8 chip. So let's setup a hook
 509  * for doing just that.
 510  */
 511 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
 512 {
 513     PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
 514     uint32_t old_state = pnv->cpld_irqstate;
 515     PnvLpcController *lpc = PNV_LPC(opaque);
 516
 517     if (level) {
 518         pnv->cpld_irqstate |= 1u << n;
 519     } else {
 520         pnv->cpld_irqstate &= ~(1u << n);
 521     }
 522
 523     if (pnv->cpld_irqstate != old_state) {
 524         pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
 525     }
 526 }
 527
 528 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
 529 {
 530     PnvLpcController *lpc = PNV_LPC(opaque);
 531
 532     /* The Naples HW latches the 1 levels, clearing is done by SW */
 533     if (level) {
 534         lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n;
 535         pnv_lpc_eval_irqs(lpc);
 536     }
 537 }
 538
 539 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
 540 {
 541     Error *local_err = NULL;
 542     ISABus *isa_bus;
 543     qemu_irq *irqs;
 544     qemu_irq_handler handler;
 545
 546     /* let isa_bus_new() create its own bridge on SysBus otherwise
 547      * devices speficied on the command line won't find the bus and
 548      * will fail to create.
 549      */
 550     isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
 551     if (local_err) {
 552         error_propagate(errp, local_err);
 553         return NULL;
 554     }
 555
 556     /* Not all variants have a working serial irq decoder. If not,
 557      * handling of LPC interrupts becomes a platform issue (some
 558      * platforms have a CPLD to do it).
 559      */
 560     if (use_cpld) {
 561         handler = pnv_lpc_isa_irq_handler_cpld;
 562     } else {
 563         handler = pnv_lpc_isa_irq_handler;
 564     }
 565
 566     irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
 567
 568     isa_bus_irqs(isa_bus, irqs);
 569     return isa_bus;
 570 }