2 * QEMU i8255x (PRO100) emulation
4 * Copyright (C) 2006-2011 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559c):
23 * PXE boot (i386 guest, i386 / ppc host) ok
24 * Linux networking (i386 guest, i386 / ppc / ppc64 host) ok
25 * Linux networking e100 driver (mips / mipsel guest, i386 host) ok
26 * Linux networking eepro100 driver (mipsel guest) not ok
27 * Windows networking (Vista) not ok
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
43 #include "qemu/osdep.h"
44 #include "qemu/units.h"
45 #include "hw/pci/pci.h"
46 #include "hw/qdev-properties.h"
47 #include "migration/vmstate.h"
50 #include "hw/nvram/eeprom93xx.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/dma.h"
53 #include "sysemu/reset.h"
54 #include "qemu/bitops.h"
55 #include "qemu/module.h"
56 #include "qapi/error.h"
58 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
59 * This should be fixed in the networking code because normally
60 * such frames are rejected by real nics and their emulations.
61 * To avoid this behaviour, other nic emulations pad received
62 * frames. The following definition enables this workaround for
64 #define CONFIG_PAD_RECEIVED_FRAMES
66 /* Debug EEPRO100 card. */
68 # define DEBUG_EEPRO100
72 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
74 #define logout(fmt, ...) ((void)0)
77 /* Set flags to 0 to disable debug output. */
78 #define INT 1 /* interrupt related actions */
79 #define MDI 1 /* mdi related actions */
82 #define EEPROM 1 /* eeprom related actions */
84 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
86 #define UNEXPECTED() logout("%s:%u unexpected\n", __FILE__, __LINE__)
89 #define missing(text) assert(!"feature is missing in this emulation: " text)
91 #define missing(text) logout("feature is missing in this emulation: " text "\n")
94 #define MAX_ETH_FRAME_SIZE 1514
96 /* This driver supports several different devices which are declared here. */
97 #define i82550 0x82550
98 #define i82551 0x82551
99 #define i82557A 0x82557a
100 #define i82557B 0x82557b
101 #define i82557C 0x82557c
102 #define i82558A 0x82558a
103 #define i82558B 0x82558b
104 #define i82559A 0x82559a
105 #define i82559B 0x82559b
106 #define i82559C 0x82559c
107 #define i82559ER 0x82559e
108 #define i82562 0x82562
109 #define i82801 0x82801
111 /* Use 64 word EEPROM. TODO: could be a runtime option. */
112 #define EEPROM_SIZE 64
114 #define PCI_MEM_SIZE (4 * KiB)
115 #define PCI_IO_SIZE 64
116 #define PCI_FLASH_SIZE (128 * KiB)
118 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
120 /* The SCB accepts the following controls for the Tx and Rx units: */
121 #define CU_NOP 0x0000 /* No operation. */
122 #define CU_START 0x0010 /* CU start. */
123 #define CU_RESUME 0x0020 /* CU resume. */
124 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
125 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
126 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
127 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
128 #define CU_SRESUME 0x00a0 /* CU static resume. */
130 #define RU_NOP 0x0000
131 #define RX_START 0x0001
132 #define RX_RESUME 0x0002
133 #define RU_ABORT 0x0004
134 #define RX_ADDR_LOAD 0x0006
135 #define RX_RESUMENR 0x0007
136 #define INT_MASK 0x0100
137 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
144 uint16_t subsystem_vendor_id
;
145 uint16_t subsystem_id
;
149 bool has_extended_tcb_support
;
150 bool power_management
;
153 /* Offsets to the various registers.
154 All accesses need not be longword aligned. */
156 SCBStatus
= 0, /* Status Word. */
158 SCBCmd
= 2, /* Rx/Command Unit command and status. */
160 SCBPointer
= 4, /* General purpose pointer. */
161 SCBPort
= 8, /* Misc. commands and operands. */
162 SCBflash
= 12, /* Flash memory control. */
163 SCBeeprom
= 14, /* EEPROM control. */
164 SCBCtrlMDI
= 16, /* MDI interface control. */
165 SCBEarlyRx
= 20, /* Early receive byte count. */
166 SCBFlow
= 24, /* Flow Control. */
167 SCBpmdr
= 27, /* Power Management Driver. */
168 SCBgctrl
= 28, /* General Control. */
169 SCBgstat
= 29, /* General Status. */
170 } E100RegisterOffset
;
172 /* A speedo3 transmit buffer descriptor with two buffers... */
176 uint32_t link
; /* void * */
177 uint32_t tbd_array_addr
; /* transmit buffer descriptor array address. */
178 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
179 uint8_t tx_threshold
; /* transmit threshold */
180 uint8_t tbd_count
; /* TBD number */
182 /* This constitutes two "TBD" entries: hdr and data */
183 uint32_t tx_buf_addr0
; /* void *, header of frame to be transmitted. */
184 int32_t tx_buf_size0
; /* Length of Tx hdr. */
185 uint32_t tx_buf_addr1
; /* void *, data to be transmitted. */
186 int32_t tx_buf_size1
; /* Length of Tx data. */
190 /* Receive frame descriptor. */
194 uint32_t link
; /* struct RxFD * */
195 uint32_t rx_buf_addr
; /* void * */
198 /* Ethernet frame data follows. */
202 COMMAND_EL
= BIT(15),
207 COMMAND_CMD
= BITS(2, 0),
216 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
217 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
218 tx_multiple_collisions
, tx_total_collisions
;
219 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
220 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
221 rx_short_frame_errors
;
222 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
223 uint16_t xmt_tco_frames
, rcv_tco_frames
;
224 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
225 uint32_t reserved
[4];
245 /* Hash register (multicast mask array, multiple individual addresses). */
247 MemoryRegion mmio_bar
;
249 MemoryRegion flash_bar
;
252 uint8_t scb_stat
; /* SCB stat/ack byte */
253 uint8_t int_stat
; /* PCI interrupt status */
254 /* region must not be saved by nic_save. */
257 uint32_t device
; /* device variant */
258 /* (cu_base + cu_offset) address the next command block in the command block list. */
259 uint32_t cu_base
; /* CU base address */
260 uint32_t cu_offset
; /* CU address offset */
261 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
262 uint32_t ru_base
; /* RU base address */
263 uint32_t ru_offset
; /* RU address offset */
264 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
266 /* Temporary status information (no need to save these values),
267 * used while processing CU commands. */
268 eepro100_tx_t tx
; /* transmit buffer descriptor */
269 uint32_t cb_address
; /* = cu_base + cu_offset */
271 /* Statistical counters. Also used for wake-up packet (i82559). */
272 eepro100_stats_t statistics
;
274 /* Data in mem is always in the byte order of the controller (le).
275 * It must be dword aligned to allow direct access to 32 bit values. */
276 uint8_t mem
[PCI_MEM_SIZE
] __attribute__((aligned(8)));
278 /* Configuration bytes. */
279 uint8_t configuration
[22];
281 /* vmstate for each particular nic */
282 VMStateDescription
*vmstate
;
284 /* Quasi static device properties (no need to save them). */
286 bool has_extended_tcb_support
;
289 /* Word indices in EEPROM. */
291 EEPROM_CNFG_MDIX
= 0x03,
293 EEPROM_PHY_ID
= 0x06,
294 EEPROM_VENDOR_ID
= 0x0c,
295 EEPROM_CONFIG_ASF
= 0x0d,
296 EEPROM_DEVICE_ID
= 0x23,
297 EEPROM_SMBUS_ADDR
= 0x90,
300 /* Bit values for EEPROM ID word (offset 0x0a). */
302 EEPROM_ID_MDM
= BIT(0), /* Modem */
303 EEPROM_ID_STB
= BIT(1), /* Standby Enable */
304 EEPROM_ID_WMR
= BIT(2), /* ??? */
305 EEPROM_ID_WOL
= BIT(5), /* Wake on LAN */
306 EEPROM_ID_DPD
= BIT(6), /* Deep Power Down */
307 EEPROM_ID_ALT
= BIT(7), /* */
308 /* BITS(10, 8) device revision */
309 EEPROM_ID_BD
= BIT(11), /* boot disable */
310 EEPROM_ID_ID
= BIT(13), /* id bit */
311 /* BITS(15, 14) signature */
312 EEPROM_ID_VALID
= BIT(14), /* signature for valid eeprom */
315 /* Default values for MDI (PHY) registers */
316 static const uint16_t eepro100_mdi_default
[] = {
317 /* MDI Registers 0 - 6, 7 */
318 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
319 /* MDI Registers 8 - 15 */
320 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
321 /* MDI Registers 16 - 31 */
322 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
323 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
326 /* Readonly mask for MDI (PHY) registers */
327 static const uint16_t eepro100_mdi_mask
[] = {
328 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
329 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
330 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
331 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
334 static E100PCIDeviceInfo
*eepro100_get_class(EEPRO100State
*s
);
336 /* Read a 16 bit control/status (CSR) register. */
337 static uint16_t e100_read_reg2(EEPRO100State
*s
, E100RegisterOffset addr
)
339 assert(!((uintptr_t)&s
->mem
[addr
] & 1));
340 return lduw_le_p(&s
->mem
[addr
]);
343 /* Read a 32 bit control/status (CSR) register. */
344 static uint32_t e100_read_reg4(EEPRO100State
*s
, E100RegisterOffset addr
)
346 assert(!((uintptr_t)&s
->mem
[addr
] & 3));
347 return ldl_le_p(&s
->mem
[addr
]);
350 /* Write a 16 bit control/status (CSR) register. */
351 static void e100_write_reg2(EEPRO100State
*s
, E100RegisterOffset addr
,
354 assert(!((uintptr_t)&s
->mem
[addr
] & 1));
355 stw_le_p(&s
->mem
[addr
], val
);
358 /* Read a 32 bit control/status (CSR) register. */
359 static void e100_write_reg4(EEPRO100State
*s
, E100RegisterOffset addr
,
362 assert(!((uintptr_t)&s
->mem
[addr
] & 3));
363 stl_le_p(&s
->mem
[addr
], val
);
366 #if defined(DEBUG_EEPRO100)
367 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
369 static char dump
[3 * 16 + 1];
375 p
+= sprintf(p
, " %02x", *buf
++);
379 #endif /* DEBUG_EEPRO100 */
383 stat_ack_not_ours
= 0x00,
384 stat_ack_sw_gen
= 0x04,
386 stat_ack_cu_idle
= 0x20,
387 stat_ack_frame_rx
= 0x40,
388 stat_ack_cu_cmd_done
= 0x80,
389 stat_ack_not_present
= 0xFF,
390 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
391 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
395 static void disable_interrupt(EEPRO100State
* s
)
398 TRACE(INT
, logout("interrupt disabled\n"));
399 pci_irq_deassert(&s
->dev
);
404 static void enable_interrupt(EEPRO100State
* s
)
407 TRACE(INT
, logout("interrupt enabled\n"));
408 pci_irq_assert(&s
->dev
);
413 static void eepro100_acknowledge(EEPRO100State
* s
)
415 s
->scb_stat
&= ~s
->mem
[SCBAck
];
416 s
->mem
[SCBAck
] = s
->scb_stat
;
417 if (s
->scb_stat
== 0) {
418 disable_interrupt(s
);
422 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t status
)
424 uint8_t mask
= ~s
->mem
[SCBIntmask
];
425 s
->mem
[SCBAck
] |= status
;
426 status
= s
->scb_stat
= s
->mem
[SCBAck
];
427 status
&= (mask
| 0x0f);
429 status
&= (~s
->mem
[SCBIntmask
] | 0x0xf
);
431 if (status
&& (mask
& 0x01)) {
432 /* SCB mask and SCB Bit M do not disable interrupt. */
434 } else if (s
->int_stat
) {
435 disable_interrupt(s
);
439 static void eepro100_cx_interrupt(EEPRO100State
* s
)
441 /* CU completed action command. */
442 /* Transmit not ok (82557 only, not in emulation). */
443 eepro100_interrupt(s
, 0x80);
446 static void eepro100_cna_interrupt(EEPRO100State
* s
)
448 /* CU left the active state. */
449 eepro100_interrupt(s
, 0x20);
452 static void eepro100_fr_interrupt(EEPRO100State
* s
)
454 /* RU received a complete frame. */
455 eepro100_interrupt(s
, 0x40);
458 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
460 /* RU is not ready. */
461 eepro100_interrupt(s
, 0x10);
464 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
466 /* MDI completed read or write cycle. */
467 eepro100_interrupt(s
, 0x08);
470 static void eepro100_swi_interrupt(EEPRO100State
* s
)
472 /* Software has requested an interrupt. */
473 eepro100_interrupt(s
, 0x04);
477 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
479 /* Flow control pause interrupt (82558 and later). */
480 eepro100_interrupt(s
, 0x01);
484 static void e100_pci_reset(EEPRO100State
*s
, Error
**errp
)
486 E100PCIDeviceInfo
*info
= eepro100_get_class(s
);
487 uint32_t device
= s
->device
;
488 uint8_t *pci_conf
= s
->dev
.config
;
490 TRACE(OTHER
, logout("%p\n", s
));
493 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
|
494 PCI_STATUS_FAST_BACK
);
495 /* PCI Latency Timer */
496 pci_set_byte(pci_conf
+ PCI_LATENCY_TIMER
, 0x20); /* latency timer = 32 clocks */
497 /* Capability Pointer is set by PCI framework. */
500 pci_set_byte(pci_conf
+ PCI_INTERRUPT_PIN
, 1); /* interrupt pin A */
502 pci_set_byte(pci_conf
+ PCI_MIN_GNT
, 0x08);
503 /* Maximum Latency */
504 pci_set_byte(pci_conf
+ PCI_MAX_LAT
, 0x18);
506 s
->stats_size
= info
->stats_size
;
507 s
->has_extended_tcb_support
= info
->has_extended_tcb_support
;
525 logout("Device %X is undefined!\n", device
);
529 s
->configuration
[6] |= BIT(4);
531 /* Standard statistical counters. */
532 s
->configuration
[6] |= BIT(5);
534 if (s
->stats_size
== 80) {
535 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
536 if (s
->configuration
[6] & BIT(2)) {
537 /* TCO statistical counters. */
538 assert(s
->configuration
[6] & BIT(5));
540 if (s
->configuration
[6] & BIT(5)) {
541 /* No extended statistical counters, i82557 compatible. */
544 /* i82558 compatible. */
549 if (s
->configuration
[6] & BIT(5)) {
550 /* No extended statistical counters. */
554 assert(s
->stats_size
> 0 && s
->stats_size
<= sizeof(s
->statistics
));
556 if (info
->power_management
) {
557 /* Power Management Capabilities */
558 int cfg_offset
= 0xdc;
559 int r
= pci_add_capability(&s
->dev
, PCI_CAP_ID_PM
,
560 cfg_offset
, PCI_PM_SIZEOF
,
566 pci_set_word(pci_conf
+ cfg_offset
+ PCI_PM_PMC
, 0x7e21);
567 #if 0 /* TODO: replace dummy code for power management emulation. */
568 /* TODO: Power Management Control / Status. */
569 pci_set_word(pci_conf
+ cfg_offset
+ PCI_PM_CTRL
, 0x0000);
570 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
571 pci_set_byte(pci_conf
+ cfg_offset
+ PCI_PM_PPB_EXTENSIONS
, 0x0000);
576 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
578 TODO: get vendor id from EEPROM for i82557C or later.
579 TODO: get device id from EEPROM for i82557C or later.
580 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
581 TODO: header type is determined by EEPROM for i82559.
582 TODO: get subsystem id from EEPROM for i82557C or later.
583 TODO: get subsystem vendor id from EEPROM for i82557C or later.
584 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
585 TODO: capability pointer depends on EEPROM for i82558.
587 logout("Get device id and revision from EEPROM!!!\n");
589 #endif /* EEPROM_SIZE > 0 */
592 static void nic_selective_reset(EEPRO100State
* s
)
595 static const uint16_t eeprom_i82559
[] = {
596 /* 0x0000 */ 0x0000, 0x0000, 0x0000, 0x020b,
597 /* 0x0008 */ 0xffff, 0x0201, 0x4701, 0xffff,
598 /* 0x0010 */ 0x7517, 0x6704, 0x50a2, 0x0040,
599 /* 0x0018 */ 0x8086, 0x0064, 0xffff, 0xffff,
600 /* 0x0020 */ 0xffff, 0xffff, 0xffff, 0xffff,
601 /* 0x0028 */ 0xffff, 0xffff, 0xffff, 0xffff,
602 /* 0x0030 */ 0xffff, 0xffff, 0xffff, 0xffff,
603 /* 0x0038 */ 0xffff, 0xffff, 0xffff, 0xffff,
604 /* 0x0040 */ 0xffff, 0xffff, 0xffff, 0x1229,
605 /* 0x0048 */ 0xffff, 0xffff, 0xffff, 0xffff,
606 /* 0x0050 */ 0xffff, 0xffff, 0xffff, 0xffff,
607 /* 0x0058 */ 0xffff, 0xffff, 0xffff, 0xffff,
608 /* 0x0060 */ 0x002c, 0x4000, 0x3003, 0xffff,
609 /* 0x0068 */ 0xffff, 0xffff, 0xffff, 0xffff,
610 /* 0x0070 */ 0xffff, 0xffff, 0xffff, 0xffff,
611 /* 0x0078 */ 0xffff, 0xffff, 0xffff, 0xffff,
614 uint8_t *pci_conf
= s
->dev
.config
;
615 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
617 eeprom93xx_reset(s
->eeprom
);
619 memcpy(eeprom_contents
, eeprom_i82559
, EEPROM_SIZE
* 2);
620 memcpy(eeprom_contents
, s
->conf
.macaddr
.a
, 6);
621 #if defined(WORDS_BIGENDIAN)
622 bswap16s(&eeprom_contents
[0]);
623 bswap16s(&eeprom_contents
[1]);
624 bswap16s(&eeprom_contents
[2]);
627 /* Only needed to set a different vendor id. */
628 memcpy(eeprom_contents
+ eeprom_vendor_id
, pci_conf
+ PCI_VENDOR_ID
, 2);
629 #if defined(WORDS_BIGENDIAN)
630 bswap16s(&eeprom_contents
[eeprom_vendor_id
]);
632 #endif /* EEPROM_SIZE > 0 */
633 memcpy(eeprom_contents
+ EEPROM_DEVICE_ID
, pci_conf
+ PCI_DEVICE_ID
, 2);
634 #if defined(WORDS_BIGENDIAN)
635 bswap16s(&eeprom_contents
[EEPROM_DEVICE_ID
]);
638 /* We might change the phy id here. */
639 eeprom_contents
[EEPROM_PHY_ID
] =
640 (eeprom_contents
[EEPROM_PHY_ID
] & 0xff00) + 1;
642 /* TODO: eeprom_id_alt for i82559 */
643 eeprom_contents
[EEPROM_ID
] |= EEPROM_ID_VALID
;
644 if (s
->device
>= i82557A
&& s
->device
<= i82557C
) {
646 eeprom_contents
[EEPROM_ID
] |= BIT(8);
648 /* TODO: source of next statement? */
649 eeprom_contents
[0xa] = 0x4000;
650 if (s
->device
== i82557B
|| s
->device
== i82557C
)
651 eeprom_contents
[5] = 0x0100;
652 eeprom_contents
[EEPROM_PHY_ID
] = 1;
654 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
655 sum
+= eeprom_contents
[i
];
657 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
658 TRACE(EEPROM
, logout("checksum=0x%04x\n", eeprom_contents
[EEPROM_SIZE
- 1]));
661 memset(s
->mem
, 0, sizeof(s
->mem
));
662 e100_write_reg4(s
, SCBCtrlMDI
, BIT(21));
664 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
665 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
668 static void nic_reset(void *opaque
)
670 EEPRO100State
*s
= opaque
;
671 TRACE(OTHER
, logout("%p\n", s
));
672 /* TODO: Clearing of hash register for selective reset, too? */
673 memset(&s
->mult
[0], 0, sizeof(s
->mult
));
674 nic_selective_reset(s
);
677 #if defined(DEBUG_EEPRO100)
678 static const char * const e100_reg
[PCI_IO_SIZE
/ 4] = {
682 "EEPROM/Flash Control",
684 "Receive DMA Byte Count",
686 "General Status/Control"
689 static char *regname(uint32_t addr
)
692 if (addr
< PCI_IO_SIZE
) {
693 const char *r
= e100_reg
[addr
/ 4];
695 snprintf(buf
, sizeof(buf
), "%s+%u", r
, addr
% 4);
697 snprintf(buf
, sizeof(buf
), "0x%02x", addr
);
700 snprintf(buf
, sizeof(buf
), "??? 0x%08x", addr
);
704 #endif /* DEBUG_EEPRO100 */
706 /*****************************************************************************
710 ****************************************************************************/
713 static uint16_t eepro100_read_command(EEPRO100State
* s
)
715 uint16_t val
= 0xffff;
716 TRACE(OTHER
, logout("val=0x%04x\n", val
));
721 /* Commands that can be put in a command list entry. */
726 CmdMulticastList
= 3,
728 CmdTDR
= 5, /* load microcode */
732 /* And some extra flags: */
733 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
736 static cu_state_t
get_cu_state(EEPRO100State
* s
)
738 return ((s
->mem
[SCBStatus
] & BITS(7, 6)) >> 6);
741 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
743 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & ~BITS(7, 6)) + (state
<< 6);
746 static ru_state_t
get_ru_state(EEPRO100State
* s
)
748 return ((s
->mem
[SCBStatus
] & BITS(5, 2)) >> 2);
751 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
753 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & ~BITS(5, 2)) + (state
<< 2);
756 static void dump_statistics(EEPRO100State
* s
)
758 /* Dump statistical data. Most data is never changed by the emulation
759 * and always 0, so we first just copy the whole block and then those
760 * values which really matter.
761 * Number of data should check configuration!!!
763 pci_dma_write(&s
->dev
, s
->statsaddr
, &s
->statistics
, s
->stats_size
);
764 stl_le_pci_dma(&s
->dev
, s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
765 stl_le_pci_dma(&s
->dev
, s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
766 stl_le_pci_dma(&s
->dev
, s
->statsaddr
+ 48,
767 s
->statistics
.rx_resource_errors
);
768 stl_le_pci_dma(&s
->dev
, s
->statsaddr
+ 60,
769 s
->statistics
.rx_short_frame_errors
);
771 stw_le_pci_dma(&s
->dev
, s
->statsaddr
+ 76, s
->statistics
.xmt_tco_frames
);
772 stw_le_pci_dma(&s
->dev
, s
->statsaddr
+ 78, s
->statistics
.rcv_tco_frames
);
773 missing("CU dump statistical counters");
777 static void read_cb(EEPRO100State
*s
)
779 pci_dma_read(&s
->dev
, s
->cb_address
, &s
->tx
, sizeof(s
->tx
));
780 s
->tx
.status
= le16_to_cpu(s
->tx
.status
);
781 s
->tx
.command
= le16_to_cpu(s
->tx
.command
);
782 s
->tx
.link
= le32_to_cpu(s
->tx
.link
);
783 s
->tx
.tbd_array_addr
= le32_to_cpu(s
->tx
.tbd_array_addr
);
784 s
->tx
.tcb_bytes
= le16_to_cpu(s
->tx
.tcb_bytes
);
787 static void tx_command(EEPRO100State
*s
)
789 uint32_t tbd_array
= s
->tx
.tbd_array_addr
;
790 uint16_t tcb_bytes
= s
->tx
.tcb_bytes
& 0x3fff;
791 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
794 uint32_t tbd_address
= s
->cb_address
+ 0x10;
796 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
797 tbd_array
, tcb_bytes
, s
->tx
.tbd_count
));
798 assert(!(s
->tx
.command
& COMMAND_NC
));
799 assert(tcb_bytes
<= sizeof(buf
));
800 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
802 ("illegal values of TBD array address and TCB byte count!\n");
804 if (s
->tx
.command
& COMMAND_SF
) {
805 /* No simplified mode. TODO: check code in this block. */
806 for (size
= 0; size
< tcb_bytes
; ) {
807 uint32_t tx_buffer_address
= ldl_le_pci_dma(&s
->dev
, tbd_address
);
808 uint16_t tx_buffer_size
= lduw_le_pci_dma(&s
->dev
, tbd_address
+ 4);
810 uint16_t tx_buffer_el
= lduw_le_pci_dma(&s
->dev
, tbd_address
+ 6);
812 if (tx_buffer_size
== 0) {
813 /* Prevent an endless loop. */
814 logout("loop in %s:%u\n", __FILE__
, __LINE__
);
819 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
820 tx_buffer_address
, tx_buffer_size
));
821 if (size
+ tx_buffer_size
> sizeof(buf
)) {
822 logout("bad simple TCB with size 0x%04x\n", tx_buffer_size
);
824 pci_dma_read(&s
->dev
, tx_buffer_address
, &buf
[size
],
827 size
+= tx_buffer_size
;
830 if (!(s
->tx
.command
& COMMAND_SF
)) {
831 /* Simplified mode. */
832 if (tcb_bytes
> sizeof(buf
)) {
833 logout("bad TCB byte count 0x%04x (simplified mode)\n", tcb_bytes
);
834 } else if (tbd_array
!= 0xffffffff) {
835 logout("bad TCB array address 0x%04x (simplified mode)\n", tbd_array
);
838 cpu_physical_memory_read(tbd_address
, &buf
[0], tcb_bytes
);
842 uint8_t tbd_count
= 0;
843 if (!(s
->configuration
[6] & BIT(4))) {
845 assert(tcb_bytes
== 0);
846 for (; tbd_count
< 2 && tbd_count
< s
->tx
.tbd_count
; tbd_count
++) {
847 uint32_t tx_buffer_address
= ldl_le_pci_dma(&s
->dev
, tbd_address
);
848 uint16_t tx_buffer_size
= lduw_le_pci_dma(&s
->dev
, tbd_address
+ 4);
849 uint16_t tx_buffer_el
= lduw_le_pci_dma(&s
->dev
, tbd_address
+ 6);
852 ("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
853 tx_buffer_address
, tx_buffer_size
));
854 if (size
+ tx_buffer_size
> sizeof(buf
)) {
855 logout("bad extended TCB with size 0x%04x\n", tx_buffer_size
);
856 } else if (tx_buffer_size
> 0) {
857 assert(tx_buffer_address
!= 0);
858 pci_dma_read(&s
->dev
, tx_buffer_address
, &buf
[size
],
860 size
+= tx_buffer_size
;
862 if (tx_buffer_el
& 1) {
867 tbd_address
= tbd_array
;
868 for (; tbd_count
< s
->tx
.tbd_count
; tbd_count
++) {
869 uint32_t tx_buffer_address
= ldl_le_pci_dma(&s
->dev
, tbd_address
);
870 uint16_t tx_buffer_size
= lduw_le_pci_dma(&s
->dev
, tbd_address
+ 4);
871 uint16_t tx_buffer_el
= lduw_le_pci_dma(&s
->dev
, tbd_address
+ 6);
874 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
875 tx_buffer_address
, tx_buffer_size
));
876 if (size
+ tx_buffer_size
> sizeof(buf
)) {
877 logout("bad flexible TCB with size 0x%04x\n", tx_buffer_size
);
879 pci_dma_read(&s
->dev
, tx_buffer_address
, &buf
[size
],
881 size
+= tx_buffer_size
;
883 if (tx_buffer_el
& 1) {
888 TRACE(RXTX
, logout("%p sending frame, len=%d,%s\n", s
, size
, nic_dump(buf
, size
)));
889 assert(size
<= sizeof(buf
));
890 qemu_send_packet(qemu_get_queue(s
->nic
), buf
, size
);
891 s
->statistics
.tx_good_frames
++;
892 /* Transmit with bad status would raise an CX/TNO interrupt.
893 * (82557 only). Emulation never has bad status. */
895 eepro100_cx_interrupt(s
);
899 static void set_multicast_list(EEPRO100State
*s
)
901 uint16_t multicast_count
= s
->tx
.tbd_array_addr
& BITS(13, 0);
903 memset(&s
->mult
[0], 0, sizeof(s
->mult
));
904 TRACE(OTHER
, logout("multicast list, multicast count = %u\n", multicast_count
));
905 for (i
= 0; i
< multicast_count
; i
+= 6) {
906 uint8_t multicast_addr
[6];
907 pci_dma_read(&s
->dev
, s
->cb_address
+ 10 + i
, multicast_addr
, 6);
908 TRACE(OTHER
, logout("multicast entry %s\n", nic_dump(multicast_addr
, 6)));
909 unsigned mcast_idx
= (net_crc32(multicast_addr
, ETH_ALEN
) &
911 assert(mcast_idx
< 64);
912 s
->mult
[mcast_idx
>> 3] |= (1 << (mcast_idx
& 7));
916 static void action_command(EEPRO100State
*s
)
918 /* The loop below won't stop if it gets special handcrafted data.
919 Therefore we limit the number of iterations. */
920 unsigned max_loop_count
= 16;
927 uint16_t ok_status
= STATUS_OK
;
928 s
->cb_address
= s
->cu_base
+ s
->cu_offset
;
930 bit_el
= ((s
->tx
.command
& COMMAND_EL
) != 0);
931 bit_s
= ((s
->tx
.command
& COMMAND_S
) != 0);
932 bit_i
= ((s
->tx
.command
& COMMAND_I
) != 0);
933 bit_nc
= ((s
->tx
.command
& COMMAND_NC
) != 0);
935 if (max_loop_count
-- == 0) {
936 /* Prevent an endless loop. */
937 logout("loop in %s:%u\n", __FILE__
, __LINE__
);
941 s
->cu_offset
= s
->tx
.link
;
943 ("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
944 s
->tx
.status
, s
->tx
.command
, s
->cu_offset
));
945 switch (s
->tx
.command
& COMMAND_CMD
) {
950 pci_dma_read(&s
->dev
, s
->cb_address
+ 8, &s
->conf
.macaddr
.a
[0], 6);
951 TRACE(OTHER
, logout("macaddr: %s\n", nic_dump(&s
->conf
.macaddr
.a
[0], 6)));
952 /* TODO: missing code. */
955 pci_dma_read(&s
->dev
, s
->cb_address
+ 8, &s
->configuration
[0],
956 sizeof(s
->configuration
));
957 if (!s
->has_extended_tcb_support
) {
958 /* Force standard TxCB. */
959 s
->configuration
[6] |= BIT(4);
961 TRACE(OTHER
, logout("configuration: %s\n",
962 nic_dump(&s
->configuration
[0], 16)));
963 TRACE(OTHER
, logout("configuration: %s\n",
964 nic_dump(&s
->configuration
[16],
965 ARRAY_SIZE(s
->configuration
) - 16)));
966 if (s
->configuration
[20] & BIT(6)) {
967 TRACE(OTHER
, logout("Multiple IA bit\n"));
970 case CmdMulticastList
:
971 set_multicast_list(s
);
975 missing("CmdTx: NC = 0");
982 TRACE(OTHER
, logout("load microcode\n"));
983 /* Starting with offset 8, the command contains
984 * 64 dwords microcode which we just ignore here. */
987 TRACE(OTHER
, logout("diagnose\n"));
988 /* Make sure error flag is not set. */
992 missing("undefined command");
996 /* Write new status. */
997 stw_le_pci_dma(&s
->dev
, s
->cb_address
,
998 s
->tx
.status
| ok_status
| STATUS_C
);
1000 /* CU completed action. */
1001 eepro100_cx_interrupt(s
);
1004 /* CU becomes idle. Terminate command loop. */
1005 set_cu_state(s
, cu_idle
);
1006 eepro100_cna_interrupt(s
);
1009 /* CU becomes suspended. Terminate command loop. */
1010 set_cu_state(s
, cu_suspended
);
1011 eepro100_cna_interrupt(s
);
1014 /* More entries in list. */
1015 TRACE(OTHER
, logout("CU list with at least one more entry\n"));
1018 TRACE(OTHER
, logout("CU list empty\n"));
1019 /* List is empty. Now CU is idle or suspended. */
1022 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
1024 cu_state_t cu_state
;
1030 cu_state
= get_cu_state(s
);
1031 if (cu_state
!= cu_idle
&& cu_state
!= cu_suspended
) {
1032 /* Intel documentation says that CU must be idle or suspended
1033 * for the CU start command. */
1034 logout("unexpected CU state is %u\n", cu_state
);
1036 set_cu_state(s
, cu_active
);
1037 s
->cu_offset
= e100_read_reg4(s
, SCBPointer
);
1041 if (get_cu_state(s
) != cu_suspended
) {
1042 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
1043 /* Workaround for bad Linux eepro100 driver which resumes
1044 * from idle state. */
1046 missing("cu resume");
1048 set_cu_state(s
, cu_suspended
);
1050 if (get_cu_state(s
) == cu_suspended
) {
1051 TRACE(OTHER
, logout("CU resuming\n"));
1052 set_cu_state(s
, cu_active
);
1057 /* Load dump counters address. */
1058 s
->statsaddr
= e100_read_reg4(s
, SCBPointer
);
1059 TRACE(OTHER
, logout("val=0x%02x (dump counters address)\n", val
));
1060 if (s
->statsaddr
& 3) {
1061 /* Memory must be Dword aligned. */
1062 logout("unaligned dump counters address\n");
1063 /* Handling of misaligned addresses is undefined.
1064 * Here we align the address by ignoring the lower bits. */
1065 /* TODO: Test unaligned dump counter address on real hardware. */
1070 /* Dump statistical counters. */
1071 TRACE(OTHER
, logout("val=0x%02x (dump stats)\n", val
));
1073 stl_le_pci_dma(&s
->dev
, s
->statsaddr
+ s
->stats_size
, 0xa005);
1077 TRACE(OTHER
, logout("val=0x%02x (CU base address)\n", val
));
1078 s
->cu_base
= e100_read_reg4(s
, SCBPointer
);
1081 /* Dump and reset statistical counters. */
1082 TRACE(OTHER
, logout("val=0x%02x (dump stats and reset)\n", val
));
1084 stl_le_pci_dma(&s
->dev
, s
->statsaddr
+ s
->stats_size
, 0xa007);
1085 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
1088 /* CU static resume. */
1089 missing("CU static resume");
1092 missing("Undefined CU command");
1096 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
1104 if (get_ru_state(s
) != ru_idle
) {
1105 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
1107 assert(!"wrong RU state");
1110 set_ru_state(s
, ru_ready
);
1111 s
->ru_offset
= e100_read_reg4(s
, SCBPointer
);
1112 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
1113 TRACE(OTHER
, logout("val=0x%02x (rx start)\n", val
));
1117 if (get_ru_state(s
) != ru_suspended
) {
1118 logout("RU state is %u, should be %u\n", get_ru_state(s
),
1121 assert(!"wrong RU state");
1124 set_ru_state(s
, ru_ready
);
1128 if (get_ru_state(s
) == ru_ready
) {
1129 eepro100_rnr_interrupt(s
);
1131 set_ru_state(s
, ru_idle
);
1135 TRACE(OTHER
, logout("val=0x%02x (RU base address)\n", val
));
1136 s
->ru_base
= e100_read_reg4(s
, SCBPointer
);
1139 logout("val=0x%02x (undefined RU command)\n", val
);
1140 missing("Undefined RU command");
1144 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
1146 eepro100_ru_command(s
, val
& 0x0f);
1147 eepro100_cu_command(s
, val
& 0xf0);
1149 TRACE(OTHER
, logout("val=0x%02x\n", val
));
1151 /* Clear command byte after command was accepted. */
1155 /*****************************************************************************
1159 ****************************************************************************/
1161 #define EEPROM_CS 0x02
1162 #define EEPROM_SK 0x01
1163 #define EEPROM_DI 0x04
1164 #define EEPROM_DO 0x08
1166 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
1168 uint16_t val
= e100_read_reg2(s
, SCBeeprom
);
1169 if (eeprom93xx_read(s
->eeprom
)) {
1174 TRACE(EEPROM
, logout("val=0x%04x\n", val
));
1178 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
1180 TRACE(EEPROM
, logout("val=0x%02x\n", val
));
1182 /* mask unwritable bits */
1184 val
= SET_MASKED(val
, 0x31, eeprom
->value
);
1187 int eecs
= ((val
& EEPROM_CS
) != 0);
1188 int eesk
= ((val
& EEPROM_SK
) != 0);
1189 int eedi
= ((val
& EEPROM_DI
) != 0);
1190 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
1193 /*****************************************************************************
1197 ****************************************************************************/
1199 #if defined(DEBUG_EEPRO100)
1200 static const char * const mdi_op_name
[] = {
1207 static const char * const mdi_reg_name
[] = {
1210 "PHY Identification (Word 1)",
1211 "PHY Identification (Word 2)",
1212 "Auto-Negotiation Advertisement",
1213 "Auto-Negotiation Link Partner Ability",
1214 "Auto-Negotiation Expansion"
1217 static const char *reg2name(uint8_t reg
)
1219 static char buffer
[10];
1220 const char *p
= buffer
;
1221 if (reg
< ARRAY_SIZE(mdi_reg_name
)) {
1222 p
= mdi_reg_name
[reg
];
1224 snprintf(buffer
, sizeof(buffer
), "reg=0x%02x", reg
);
1228 #endif /* DEBUG_EEPRO100 */
1230 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
1232 uint32_t val
= e100_read_reg4(s
, SCBCtrlMDI
);
1234 #ifdef DEBUG_EEPRO100
1235 uint8_t raiseint
= (val
& BIT(29)) >> 29;
1236 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
1237 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1238 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1239 uint16_t data
= (val
& BITS(15, 0));
1241 /* Emulation takes no time to finish MDI transaction. */
1243 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1244 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1245 reg2name(reg
), data
));
1249 static void eepro100_write_mdi(EEPRO100State
*s
)
1251 uint32_t val
= e100_read_reg4(s
, SCBCtrlMDI
);
1252 uint8_t raiseint
= (val
& BIT(29)) >> 29;
1253 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
1254 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
1255 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
1256 uint16_t data
= (val
& BITS(15, 0));
1257 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1258 val
, raiseint
, mdi_op_name
[opcode
], phy
, reg2name(reg
), data
));
1260 /* Unsupported PHY address. */
1262 logout("phy must be 1 but is %u\n", phy
);
1265 } else if (opcode
!= 1 && opcode
!= 2) {
1266 /* Unsupported opcode. */
1267 logout("opcode must be 1 or 2 but is %u\n", opcode
);
1269 } else if (reg
> 6) {
1270 /* Unsupported register. */
1271 logout("register must be 0...6 but is %u\n", reg
);
1274 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1275 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1276 reg2name(reg
), data
));
1280 case 0: /* Control Register */
1281 if (data
& 0x8000) {
1282 /* Reset status and control registers to default. */
1283 s
->mdimem
[0] = eepro100_mdi_default
[0];
1284 s
->mdimem
[1] = eepro100_mdi_default
[1];
1285 data
= s
->mdimem
[reg
];
1287 /* Restart Auto Configuration = Normal Operation */
1291 case 1: /* Status Register */
1292 missing("not writable");
1294 case 2: /* PHY Identification Register (Word 1) */
1295 case 3: /* PHY Identification Register (Word 2) */
1296 missing("not implemented");
1298 case 4: /* Auto-Negotiation Advertisement Register */
1299 case 5: /* Auto-Negotiation Link Partner Ability Register */
1301 case 6: /* Auto-Negotiation Expansion Register */
1303 missing("not implemented");
1305 s
->mdimem
[reg
] &= eepro100_mdi_mask
[reg
];
1306 s
->mdimem
[reg
] |= data
& ~eepro100_mdi_mask
[reg
];
1307 } else if (opcode
== 2) {
1310 case 0: /* Control Register */
1311 if (data
& 0x8000) {
1312 /* Reset status and control registers to default. */
1313 s
->mdimem
[0] = eepro100_mdi_default
[0];
1314 s
->mdimem
[1] = eepro100_mdi_default
[1];
1317 case 1: /* Status Register */
1318 s
->mdimem
[reg
] |= 0x0020;
1320 case 2: /* PHY Identification Register (Word 1) */
1321 case 3: /* PHY Identification Register (Word 2) */
1322 case 4: /* Auto-Negotiation Advertisement Register */
1324 case 5: /* Auto-Negotiation Link Partner Ability Register */
1325 s
->mdimem
[reg
] = 0x41fe;
1327 case 6: /* Auto-Negotiation Expansion Register */
1328 s
->mdimem
[reg
] = 0x0001;
1331 data
= s
->mdimem
[reg
];
1333 /* Emulation takes no time to finish MDI transaction.
1334 * Set MDI bit in SCB status register. */
1335 s
->mem
[SCBAck
] |= 0x08;
1338 eepro100_mdi_interrupt(s
);
1341 val
= (val
& 0xffff0000) + data
;
1342 e100_write_reg4(s
, SCBCtrlMDI
, val
);
1345 /*****************************************************************************
1349 ****************************************************************************/
1351 #define PORT_SOFTWARE_RESET 0
1352 #define PORT_SELFTEST 1
1353 #define PORT_SELECTIVE_RESET 2
1355 #define PORT_SELECTION_MASK 3
1358 uint32_t st_sign
; /* Self Test Signature */
1359 uint32_t st_result
; /* Self Test Results */
1360 } eepro100_selftest_t
;
1362 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1367 static void eepro100_write_port(EEPRO100State
*s
)
1369 uint32_t val
= e100_read_reg4(s
, SCBPort
);
1370 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1371 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1372 switch (selection
) {
1373 case PORT_SOFTWARE_RESET
:
1377 TRACE(OTHER
, logout("selftest address=0x%08x\n", address
));
1378 eepro100_selftest_t data
;
1379 pci_dma_read(&s
->dev
, address
, (uint8_t *) &data
, sizeof(data
));
1380 data
.st_sign
= 0xffffffff;
1382 pci_dma_write(&s
->dev
, address
, (uint8_t *) &data
, sizeof(data
));
1384 case PORT_SELECTIVE_RESET
:
1385 TRACE(OTHER
, logout("selective reset, selftest address=0x%08x\n", address
));
1386 nic_selective_reset(s
);
1389 logout("val=0x%08x\n", val
);
1390 missing("unknown port selection");
1394 /*****************************************************************************
1396 * General hardware emulation.
1398 ****************************************************************************/
1400 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1403 assert(addr
<= sizeof(s
->mem
) - sizeof(val
));
1404 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1411 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1414 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1416 val
= eepro100_read_command(s
);
1420 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1423 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1426 val
= eepro100_read_eeprom(s
);
1429 case SCBCtrlMDI
+ 1:
1430 case SCBCtrlMDI
+ 2:
1431 case SCBCtrlMDI
+ 3:
1432 val
= (uint8_t)(eepro100_read_mdi(s
) >> (8 * (addr
& 3)));
1433 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1435 case SCBpmdr
: /* Power Management Driver Register */
1437 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1439 case SCBgctrl
: /* General Control Register */
1440 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1442 case SCBgstat
: /* General Status Register */
1443 /* 100 Mbps full duplex, valid link */
1445 TRACE(OTHER
, logout("addr=General Status val=%02x\n", val
));
1448 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1449 missing("unknown byte read");
1454 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1457 assert(addr
<= sizeof(s
->mem
) - sizeof(val
));
1458 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1459 val
= e100_read_reg2(s
, addr
);
1465 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1468 val
= eepro100_read_eeprom(s
);
1469 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1472 case SCBCtrlMDI
+ 2:
1473 val
= (uint16_t)(eepro100_read_mdi(s
) >> (8 * (addr
& 3)));
1474 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1477 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1478 missing("unknown word read");
1483 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1486 assert(addr
<= sizeof(s
->mem
) - sizeof(val
));
1487 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1488 val
= e100_read_reg4(s
, addr
);
1493 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1496 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1499 val
= eepro100_read_port(s
);
1500 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1503 val
= eepro100_read_eeprom(s
);
1504 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1507 val
= eepro100_read_mdi(s
);
1510 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1511 missing("unknown longword read");
1516 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1518 assert(addr
<= sizeof(s
->mem
) - sizeof(val
));
1519 /* SCBStatus is readonly. */
1520 if (addr
> SCBStatus
&& addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1526 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1529 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1530 eepro100_acknowledge(s
);
1533 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1534 eepro100_write_command(s
, val
);
1537 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1539 eepro100_swi_interrupt(s
);
1541 eepro100_interrupt(s
, 0);
1544 case SCBPointer
+ 1:
1545 case SCBPointer
+ 2:
1546 case SCBPointer
+ 3:
1547 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1552 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1555 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1556 eepro100_write_port(s
);
1558 case SCBFlow
: /* does not exist on 82557 */
1561 case SCBpmdr
: /* does not exist on 82557 */
1562 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1565 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1566 eepro100_write_eeprom(s
->eeprom
, val
);
1569 case SCBCtrlMDI
+ 1:
1570 case SCBCtrlMDI
+ 2:
1571 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1573 case SCBCtrlMDI
+ 3:
1574 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1575 eepro100_write_mdi(s
);
1578 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1579 missing("unknown byte write");
1583 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1585 assert(addr
<= sizeof(s
->mem
) - sizeof(val
));
1586 /* SCBStatus is readonly. */
1587 if (addr
> SCBStatus
&& addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1588 e100_write_reg2(s
, addr
, val
);
1593 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1594 s
->mem
[SCBAck
] = (val
>> 8);
1595 eepro100_acknowledge(s
);
1598 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1599 eepro100_write_command(s
, val
);
1600 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1603 case SCBPointer
+ 2:
1604 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1607 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1610 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1611 eepro100_write_port(s
);
1614 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1615 eepro100_write_eeprom(s
->eeprom
, val
);
1618 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1620 case SCBCtrlMDI
+ 2:
1621 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1622 eepro100_write_mdi(s
);
1625 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1626 missing("unknown word write");
1630 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1632 assert(addr
<= sizeof(s
->mem
) - sizeof(val
));
1633 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1634 e100_write_reg4(s
, addr
, val
);
1639 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1642 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1643 eepro100_write_port(s
);
1646 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1648 eepro100_write_eeprom(s
->eeprom
, val
);
1651 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1652 eepro100_write_mdi(s
);
1655 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1656 missing("unknown longword write");
1660 static uint64_t eepro100_read(void *opaque
, hwaddr addr
,
1663 EEPRO100State
*s
= opaque
;
1666 case 1: return eepro100_read1(s
, addr
);
1667 case 2: return eepro100_read2(s
, addr
);
1668 case 4: return eepro100_read4(s
, addr
);
1673 static void eepro100_write(void *opaque
, hwaddr addr
,
1674 uint64_t data
, unsigned size
)
1676 EEPRO100State
*s
= opaque
;
1680 eepro100_write1(s
, addr
, data
);
1683 eepro100_write2(s
, addr
, data
);
1686 eepro100_write4(s
, addr
, data
);
1693 static const MemoryRegionOps eepro100_ops
= {
1694 .read
= eepro100_read
,
1695 .write
= eepro100_write
,
1696 .endianness
= DEVICE_LITTLE_ENDIAN
,
1699 static ssize_t
nic_receive(NetClientState
*nc
, const uint8_t * buf
, size_t size
)
1702 * - Magic packets should set bit 30 in power management driver register.
1703 * - Interesting packets should set bit 29 in power management driver register.
1705 EEPRO100State
*s
= qemu_get_nic_opaque(nc
);
1706 uint16_t rfd_status
= 0xa000;
1707 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1708 uint8_t min_buf
[60];
1710 static const uint8_t broadcast_macaddr
[6] =
1711 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1713 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1714 /* Pad to minimum Ethernet frame length */
1715 if (size
< sizeof(min_buf
)) {
1716 memcpy(min_buf
, buf
, size
);
1717 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
1719 size
= sizeof(min_buf
);
1723 if (s
->configuration
[8] & 0x80) {
1724 /* CSMA is disabled. */
1725 logout("%p received while CSMA is disabled\n", s
);
1727 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1728 } else if (size
< 64 && (s
->configuration
[7] & BIT(0))) {
1729 /* Short frame and configuration byte 7/0 (discard short receive) set:
1730 * Short frame is discarded */
1731 logout("%p received short frame (%zu byte)\n", s
, size
);
1732 s
->statistics
.rx_short_frame_errors
++;
1735 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & BIT(3))) {
1736 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1737 * Long frames are discarded. */
1738 logout("%p received long frame (%zu byte), ignored\n", s
, size
);
1740 } else if (memcmp(buf
, s
->conf
.macaddr
.a
, 6) == 0) { /* !!! */
1741 /* Frame matches individual address. */
1742 /* TODO: check configuration byte 15/4 (ignore U/L). */
1743 TRACE(RXTX
, logout("%p received frame for me, len=%zu\n", s
, size
));
1744 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1745 /* Broadcast frame. */
1746 TRACE(RXTX
, logout("%p received broadcast, len=%zu\n", s
, size
));
1747 rfd_status
|= 0x0002;
1748 } else if (buf
[0] & 0x01) {
1749 /* Multicast frame. */
1750 TRACE(RXTX
, logout("%p received multicast, len=%zu,%s\n", s
, size
, nic_dump(buf
, size
)));
1751 if (s
->configuration
[21] & BIT(3)) {
1752 /* Multicast all bit is set, receive all multicast frames. */
1754 unsigned mcast_idx
= (net_crc32(buf
, ETH_ALEN
) & BITS(7, 2)) >> 2;
1755 assert(mcast_idx
< 64);
1756 if (s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))) {
1757 /* Multicast frame is allowed in hash table. */
1758 } else if (s
->configuration
[15] & BIT(0)) {
1759 /* Promiscuous: receive all. */
1760 rfd_status
|= 0x0004;
1762 TRACE(RXTX
, logout("%p multicast ignored\n", s
));
1766 /* TODO: Next not for promiscuous mode? */
1767 rfd_status
|= 0x0002;
1768 } else if (s
->configuration
[15] & BIT(0)) {
1769 /* Promiscuous: receive all. */
1770 TRACE(RXTX
, logout("%p received frame in promiscuous mode, len=%zu\n", s
, size
));
1771 rfd_status
|= 0x0004;
1772 } else if (s
->configuration
[20] & BIT(6)) {
1773 /* Multiple IA bit set. */
1774 unsigned mcast_idx
= net_crc32(buf
, ETH_ALEN
) >> 26;
1775 assert(mcast_idx
< 64);
1776 if (s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))) {
1777 TRACE(RXTX
, logout("%p accepted, multiple IA bit set\n", s
));
1779 TRACE(RXTX
, logout("%p frame ignored, multiple IA bit set\n", s
));
1783 TRACE(RXTX
, logout("%p received frame, ignored, len=%zu,%s\n", s
, size
,
1784 nic_dump(buf
, size
)));
1788 if (get_ru_state(s
) != ru_ready
) {
1789 /* No resources available. */
1790 logout("no resources, state=%u\n", get_ru_state(s
));
1791 /* TODO: RNR interrupt only at first failed frame? */
1792 eepro100_rnr_interrupt(s
);
1793 s
->statistics
.rx_resource_errors
++;
1795 assert(!"no resources");
1801 pci_dma_read(&s
->dev
, s
->ru_base
+ s
->ru_offset
, &rx
,
1802 sizeof(eepro100_rx_t
));
1804 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1805 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1807 if (size
> rfd_size
) {
1808 /* TODO: does real hardware truncate, too? */
1809 logout("received frame with %zu > %u\n", size
, rfd_size
);
1813 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1815 rfd_status
|= 0x0080;
1818 TRACE(OTHER
, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1819 rfd_command
, rx
.link
, rx
.rx_buf_addr
, rfd_size
));
1820 stw_le_pci_dma(&s
->dev
, s
->ru_base
+ s
->ru_offset
+
1821 offsetof(eepro100_rx_t
, status
), rfd_status
);
1822 stw_le_pci_dma(&s
->dev
, s
->ru_base
+ s
->ru_offset
+
1823 offsetof(eepro100_rx_t
, count
), size
);
1824 /* Early receive interrupt not supported. */
1826 eepro100_er_interrupt(s
);
1828 /* Receive CRC Transfer not supported. */
1829 if (s
->configuration
[18] & BIT(2)) {
1830 missing("Receive CRC Transfer");
1833 /* TODO: check stripping enable bit. */
1835 assert(!(s
->configuration
[17] & BIT(0)));
1837 pci_dma_write(&s
->dev
, s
->ru_base
+ s
->ru_offset
+
1838 sizeof(eepro100_rx_t
), buf
, size
);
1839 s
->statistics
.rx_good_frames
++;
1840 eepro100_fr_interrupt(s
);
1841 s
->ru_offset
= le32_to_cpu(rx
.link
);
1842 if (rfd_command
& COMMAND_EL
) {
1843 /* EL bit is set, so this was the last frame. */
1844 set_ru_state(s
, ru_idle
);
1846 logout("receive: Running out of frames\n");
1847 // TODO: do we need ru_suspended here?
1848 set_ru_state(s
, ru_suspended
);
1850 set_ru_state(s
, ru_no_resources
);
1851 eepro100_rnr_interrupt(s
);
1853 if (rfd_command
& COMMAND_S
) {
1855 set_ru_state(s
, ru_suspended
);
1860 static const VMStateDescription vmstate_eepro100
= {
1862 .minimum_version_id
= 2,
1863 .fields
= (VMStateField
[]) {
1864 VMSTATE_PCI_DEVICE(dev
, EEPRO100State
),
1866 VMSTATE_BUFFER(mult
, EEPRO100State
),
1867 VMSTATE_BUFFER(mem
, EEPRO100State
),
1868 /* Save all members of struct between scb_stat and mem. */
1869 VMSTATE_UINT8(scb_stat
, EEPRO100State
),
1870 VMSTATE_UINT8(int_stat
, EEPRO100State
),
1871 VMSTATE_UNUSED(3*4),
1872 VMSTATE_MACADDR(conf
.macaddr
, EEPRO100State
),
1873 VMSTATE_UNUSED(19*4),
1874 VMSTATE_UINT16_ARRAY(mdimem
, EEPRO100State
, 32),
1875 /* The eeprom should be saved and restored by its own routines. */
1876 VMSTATE_UINT32(device
, EEPRO100State
),
1877 /* TODO check device. */
1878 VMSTATE_UINT32(cu_base
, EEPRO100State
),
1879 VMSTATE_UINT32(cu_offset
, EEPRO100State
),
1880 VMSTATE_UINT32(ru_base
, EEPRO100State
),
1881 VMSTATE_UINT32(ru_offset
, EEPRO100State
),
1882 VMSTATE_UINT32(statsaddr
, EEPRO100State
),
1883 /* Save eepro100_stats_t statistics. */
1884 VMSTATE_UINT32(statistics
.tx_good_frames
, EEPRO100State
),
1885 VMSTATE_UINT32(statistics
.tx_max_collisions
, EEPRO100State
),
1886 VMSTATE_UINT32(statistics
.tx_late_collisions
, EEPRO100State
),
1887 VMSTATE_UINT32(statistics
.tx_underruns
, EEPRO100State
),
1888 VMSTATE_UINT32(statistics
.tx_lost_crs
, EEPRO100State
),
1889 VMSTATE_UINT32(statistics
.tx_deferred
, EEPRO100State
),
1890 VMSTATE_UINT32(statistics
.tx_single_collisions
, EEPRO100State
),
1891 VMSTATE_UINT32(statistics
.tx_multiple_collisions
, EEPRO100State
),
1892 VMSTATE_UINT32(statistics
.tx_total_collisions
, EEPRO100State
),
1893 VMSTATE_UINT32(statistics
.rx_good_frames
, EEPRO100State
),
1894 VMSTATE_UINT32(statistics
.rx_crc_errors
, EEPRO100State
),
1895 VMSTATE_UINT32(statistics
.rx_alignment_errors
, EEPRO100State
),
1896 VMSTATE_UINT32(statistics
.rx_resource_errors
, EEPRO100State
),
1897 VMSTATE_UINT32(statistics
.rx_overrun_errors
, EEPRO100State
),
1898 VMSTATE_UINT32(statistics
.rx_cdt_errors
, EEPRO100State
),
1899 VMSTATE_UINT32(statistics
.rx_short_frame_errors
, EEPRO100State
),
1900 VMSTATE_UINT32(statistics
.fc_xmt_pause
, EEPRO100State
),
1901 VMSTATE_UINT32(statistics
.fc_rcv_pause
, EEPRO100State
),
1902 VMSTATE_UINT32(statistics
.fc_rcv_unsupported
, EEPRO100State
),
1903 VMSTATE_UINT16(statistics
.xmt_tco_frames
, EEPRO100State
),
1904 VMSTATE_UINT16(statistics
.rcv_tco_frames
, EEPRO100State
),
1905 /* Configuration bytes. */
1906 VMSTATE_BUFFER(configuration
, EEPRO100State
),
1907 VMSTATE_END_OF_LIST()
1911 static void pci_nic_uninit(PCIDevice
*pci_dev
)
1913 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1915 vmstate_unregister(VMSTATE_IF(&pci_dev
->qdev
), s
->vmstate
, s
);
1917 eeprom93xx_free(&pci_dev
->qdev
, s
->eeprom
);
1918 qemu_del_nic(s
->nic
);
1921 static NetClientInfo net_eepro100_info
= {
1922 .type
= NET_CLIENT_DRIVER_NIC
,
1923 .size
= sizeof(NICState
),
1924 .receive
= nic_receive
,
1927 static void e100_nic_realize(PCIDevice
*pci_dev
, Error
**errp
)
1929 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1930 E100PCIDeviceInfo
*info
= eepro100_get_class(s
);
1931 Error
*local_err
= NULL
;
1933 TRACE(OTHER
, logout("\n"));
1935 s
->device
= info
->device
;
1937 e100_pci_reset(s
, &local_err
);
1939 error_propagate(errp
, local_err
);
1944 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1945 * i82559 and later support 64 or 256 word EEPROM. */
1946 s
->eeprom
= eeprom93xx_new(&pci_dev
->qdev
, EEPROM_SIZE
);
1949 /* Handler for memory-mapped I/O */
1950 memory_region_init_io(&s
->mmio_bar
, OBJECT(s
), &eepro100_ops
, s
,
1951 "eepro100-mmio", PCI_MEM_SIZE
);
1952 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_MEM_PREFETCH
, &s
->mmio_bar
);
1953 memory_region_init_io(&s
->io_bar
, OBJECT(s
), &eepro100_ops
, s
,
1954 "eepro100-io", PCI_IO_SIZE
);
1955 pci_register_bar(&s
->dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1956 /* FIXME: flash aliases to mmio?! */
1957 memory_region_init_io(&s
->flash_bar
, OBJECT(s
), &eepro100_ops
, s
,
1958 "eepro100-flash", PCI_FLASH_SIZE
);
1959 pci_register_bar(&s
->dev
, 2, 0, &s
->flash_bar
);
1961 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1962 logout("macaddr: %s\n", nic_dump(&s
->conf
.macaddr
.a
[0], 6));
1966 s
->nic
= qemu_new_nic(&net_eepro100_info
, &s
->conf
,
1967 object_get_typename(OBJECT(pci_dev
)), pci_dev
->qdev
.id
, s
);
1969 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1970 TRACE(OTHER
, logout("%s\n", qemu_get_queue(s
->nic
)->info_str
));
1972 qemu_register_reset(nic_reset
, s
);
1974 s
->vmstate
= g_memdup(&vmstate_eepro100
, sizeof(vmstate_eepro100
));
1975 s
->vmstate
->name
= qemu_get_queue(s
->nic
)->model
;
1976 vmstate_register(VMSTATE_IF(&pci_dev
->qdev
), VMSTATE_INSTANCE_ID_ANY
,
1980 static void eepro100_instance_init(Object
*obj
)
1982 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, PCI_DEVICE(obj
));
1983 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
1984 "bootindex", "/ethernet-phy@0",
1988 static E100PCIDeviceInfo e100_devices
[] = {
1991 .desc
= "Intel i82550 Ethernet",
1993 /* TODO: check device id. */
1994 .device_id
= PCI_DEVICE_ID_INTEL_82551IT
,
1995 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1997 /* TODO: check size of statistical counters. */
1999 /* TODO: check extended tcb support. */
2000 .has_extended_tcb_support
= true,
2001 .power_management
= true,
2004 .desc
= "Intel i82551 Ethernet",
2006 .device_id
= PCI_DEVICE_ID_INTEL_82551IT
,
2007 /* Revision ID: 0x0f, 0x10. */
2009 /* TODO: check size of statistical counters. */
2011 /* TODO: check extended tcb support. */
2012 .has_extended_tcb_support
= true,
2013 .power_management
= true,
2016 .desc
= "Intel i82557A Ethernet",
2018 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2020 .power_management
= false,
2023 .desc
= "Intel i82557B Ethernet",
2025 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2027 .power_management
= false,
2030 .desc
= "Intel i82557C Ethernet",
2032 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2034 .power_management
= false,
2037 .desc
= "Intel i82558A Ethernet",
2039 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2042 .has_extended_tcb_support
= true,
2043 .power_management
= true,
2046 .desc
= "Intel i82558B Ethernet",
2048 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2051 .has_extended_tcb_support
= true,
2052 .power_management
= true,
2055 .desc
= "Intel i82559A Ethernet",
2057 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2060 .has_extended_tcb_support
= true,
2061 .power_management
= true,
2064 .desc
= "Intel i82559B Ethernet",
2066 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2069 .has_extended_tcb_support
= true,
2070 .power_management
= true,
2073 .desc
= "Intel i82559C Ethernet",
2075 .device_id
= PCI_DEVICE_ID_INTEL_82557
,
2079 /* TODO: Windows wants revision id 0x0c. */
2082 .subsystem_vendor_id
= PCI_VENDOR_ID_INTEL
,
2083 .subsystem_id
= 0x0040,
2086 .has_extended_tcb_support
= true,
2087 .power_management
= true,
2090 .desc
= "Intel i82559ER Ethernet",
2092 .device_id
= PCI_DEVICE_ID_INTEL_82551IT
,
2095 .has_extended_tcb_support
= true,
2096 .power_management
= true,
2099 .desc
= "Intel i82562 Ethernet",
2101 /* TODO: check device id. */
2102 .device_id
= PCI_DEVICE_ID_INTEL_82551IT
,
2103 /* TODO: wrong revision id. */
2106 .has_extended_tcb_support
= true,
2107 .power_management
= true,
2109 /* Toshiba Tecra 8200. */
2111 .desc
= "Intel i82801 Ethernet",
2113 .device_id
= 0x2449,
2116 .has_extended_tcb_support
= true,
2117 .power_management
= true,
2121 static E100PCIDeviceInfo
*eepro100_get_class_by_name(const char *typename
)
2123 E100PCIDeviceInfo
*info
= NULL
;
2126 /* This is admittedly awkward but also temporary. QOM allows for
2127 * parameterized typing and for subclassing both of which would suitable
2128 * handle what's going on here. But class_data is already being used as
2129 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2130 * right now. Once we merge the final QOM series, we can come back here and
2131 * do this in a much more elegant fashion.
2133 for (i
= 0; i
< ARRAY_SIZE(e100_devices
); i
++) {
2134 if (strcmp(e100_devices
[i
].name
, typename
) == 0) {
2135 info
= &e100_devices
[i
];
2139 assert(info
!= NULL
);
2144 static E100PCIDeviceInfo
*eepro100_get_class(EEPRO100State
*s
)
2146 return eepro100_get_class_by_name(object_get_typename(OBJECT(s
)));
2149 static Property e100_properties
[] = {
2150 DEFINE_NIC_PROPERTIES(EEPRO100State
, conf
),
2151 DEFINE_PROP_END_OF_LIST(),
2154 static void eepro100_class_init(ObjectClass
*klass
, void *data
)
2156 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2157 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2158 E100PCIDeviceInfo
*info
;
2160 info
= eepro100_get_class_by_name(object_class_get_name(klass
));
2162 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2163 device_class_set_props(dc
, e100_properties
);
2164 dc
->desc
= info
->desc
;
2165 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2166 k
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2167 k
->romfile
= "pxe-eepro100.rom";
2168 k
->realize
= e100_nic_realize
;
2169 k
->exit
= pci_nic_uninit
;
2170 k
->device_id
= info
->device_id
;
2171 k
->revision
= info
->revision
;
2172 k
->subsystem_vendor_id
= info
->subsystem_vendor_id
;
2173 k
->subsystem_id
= info
->subsystem_id
;
2176 static void eepro100_register_types(void)
2179 for (i
= 0; i
< ARRAY_SIZE(e100_devices
); i
++) {
2180 TypeInfo type_info
= {};
2181 E100PCIDeviceInfo
*info
= &e100_devices
[i
];
2183 type_info
.name
= info
->name
;
2184 type_info
.parent
= TYPE_PCI_DEVICE
;
2185 type_info
.class_init
= eepro100_class_init
;
2186 type_info
.instance_size
= sizeof(EEPRO100State
);
2187 type_info
.instance_init
= eepro100_instance_init
;
2188 type_info
.interfaces
= (InterfaceInfo
[]) {
2189 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
2193 type_register(&type_info
);
2197 type_init(eepro100_register_types
)