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x86: avoid AREG0 for FPU helpers
[qemu/ar7.git] / target-i386 / translate.c
blob5e9da9df161e6f3deebfd86111547ae750fe4b65
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define CODE64(s) ((s)->code64)
42 #define REX_X(s) ((s)->rex_x)
43 #define REX_B(s) ((s)->rex_b)
44 #else
45 #define CODE64(s) 0
46 #define REX_X(s) 0
47 #define REX_B(s) 0
48 #endif
49
50 //#define MACRO_TEST 1
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
55 static TCGv_i32 cpu_cc_op;
56 static TCGv cpu_regs[CPU_NB_REGS];
57 /* local temps */
58 static TCGv cpu_T[2], cpu_T3;
59 /* local register indexes (only used inside old micro ops) */
60 static TCGv cpu_tmp0, cpu_tmp4;
61 static TCGv_ptr cpu_ptr0, cpu_ptr1;
62 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
63 static TCGv_i64 cpu_tmp1_i64;
64 static TCGv cpu_tmp5;
65
66 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
67
68 #include "gen-icount.h"
69
70 #ifdef TARGET_X86_64
71 static int x86_64_hregs;
72 #endif
73
74 typedef struct DisasContext {
75 /* current insn context */
76 int override; /* -1 if no override */
77 int prefix;
78 int aflag, dflag;
79 target_ulong pc; /* pc = eip + cs_base */
80 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base; /* base of CS segment */
84 int pe; /* protected mode */
85 int code32; /* 32 bit code segment */
86 #ifdef TARGET_X86_64
87 int lma; /* long mode active */
88 int code64; /* 64 bit code segment */
89 int rex_x, rex_b;
90 #endif
91 int ss32; /* 32 bit stack segment */
92 int cc_op; /* current CC operation */
93 int addseg; /* non zero if either DS/ES/SS have a non zero base */
94 int f_st; /* currently unused */
95 int vm86; /* vm86 mode */
96 int cpl;
97 int iopl;
98 int tf; /* TF cpu flag */
99 int singlestep_enabled; /* "hardware" single step enabled */
100 int jmp_opt; /* use direct block chaining for direct jumps */
101 int mem_index; /* select memory access functions */
102 uint64_t flags; /* all execution flags */
103 struct TranslationBlock *tb;
104 int popl_esp_hack; /* for correct popl with esp base handling */
105 int rip_offset; /* only used in x86_64, but left for simplicity */
106 int cpuid_features;
107 int cpuid_ext_features;
108 int cpuid_ext2_features;
109 int cpuid_ext3_features;
110 } DisasContext;
111
112 static void gen_eob(DisasContext *s);
113 static void gen_jmp(DisasContext *s, target_ulong eip);
114 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
115
116 /* i386 arith/logic operations */
117 enum {
118 OP_ADDL,
119 OP_ORL,
120 OP_ADCL,
121 OP_SBBL,
122 OP_ANDL,
123 OP_SUBL,
124 OP_XORL,
125 OP_CMPL,
126 };
127
128 /* i386 shift ops */
129 enum {
130 OP_ROL,
131 OP_ROR,
132 OP_RCL,
133 OP_RCR,
134 OP_SHL,
135 OP_SHR,
136 OP_SHL1, /* undocumented */
137 OP_SAR = 7,
138 };
139
140 enum {
141 JCC_O,
142 JCC_B,
143 JCC_Z,
144 JCC_BE,
145 JCC_S,
146 JCC_P,
147 JCC_L,
148 JCC_LE,
149 };
150
151 /* operand size */
152 enum {
153 OT_BYTE = 0,
154 OT_WORD,
155 OT_LONG,
156 OT_QUAD,
157 };
158
159 enum {
160 /* I386 int registers */
161 OR_EAX, /* MUST be even numbered */
162 OR_ECX,
163 OR_EDX,
164 OR_EBX,
165 OR_ESP,
166 OR_EBP,
167 OR_ESI,
168 OR_EDI,
169
170 OR_TMP0 = 16, /* temporary operand register */
171 OR_TMP1,
172 OR_A0, /* temporary register used when doing address evaluation */
173 };
174
175 static inline void gen_op_movl_T0_0(void)
176 {
177 tcg_gen_movi_tl(cpu_T[0], 0);
178 }
179
180 static inline void gen_op_movl_T0_im(int32_t val)
181 {
182 tcg_gen_movi_tl(cpu_T[0], val);
183 }
184
185 static inline void gen_op_movl_T0_imu(uint32_t val)
186 {
187 tcg_gen_movi_tl(cpu_T[0], val);
188 }
189
190 static inline void gen_op_movl_T1_im(int32_t val)
191 {
192 tcg_gen_movi_tl(cpu_T[1], val);
193 }
194
195 static inline void gen_op_movl_T1_imu(uint32_t val)
196 {
197 tcg_gen_movi_tl(cpu_T[1], val);
198 }
199
200 static inline void gen_op_movl_A0_im(uint32_t val)
201 {
202 tcg_gen_movi_tl(cpu_A0, val);
203 }
204
205 #ifdef TARGET_X86_64
206 static inline void gen_op_movq_A0_im(int64_t val)
207 {
208 tcg_gen_movi_tl(cpu_A0, val);
209 }
210 #endif
211
212 static inline void gen_movtl_T0_im(target_ulong val)
213 {
214 tcg_gen_movi_tl(cpu_T[0], val);
215 }
216
217 static inline void gen_movtl_T1_im(target_ulong val)
218 {
219 tcg_gen_movi_tl(cpu_T[1], val);
220 }
221
222 static inline void gen_op_andl_T0_ffff(void)
223 {
224 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
225 }
226
227 static inline void gen_op_andl_T0_im(uint32_t val)
228 {
229 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
230 }
231
232 static inline void gen_op_movl_T0_T1(void)
233 {
234 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
235 }
236
237 static inline void gen_op_andl_A0_ffff(void)
238 {
239 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
240 }
241
242 #ifdef TARGET_X86_64
243
244 #define NB_OP_SIZES 4
245
246 #else /* !TARGET_X86_64 */
247
248 #define NB_OP_SIZES 3
249
250 #endif /* !TARGET_X86_64 */
251
252 #if defined(HOST_WORDS_BIGENDIAN)
253 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
254 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
255 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
256 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
257 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
258 #else
259 #define REG_B_OFFSET 0
260 #define REG_H_OFFSET 1
261 #define REG_W_OFFSET 0
262 #define REG_L_OFFSET 0
263 #define REG_LH_OFFSET 4
264 #endif
265
266 /* In instruction encodings for byte register accesses the
267 * register number usually indicates "low 8 bits of register N";
268 * however there are some special cases where N 4..7 indicates
269 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
270 * true for this special case, false otherwise.
271 */
272 static inline bool byte_reg_is_xH(int reg)
273 {
274 if (reg < 4) {
275 return false;
276 }
277 #ifdef TARGET_X86_64
278 if (reg >= 8 || x86_64_hregs) {
279 return false;
280 }
281 #endif
282 return true;
283 }
284
285 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
286 {
287 switch(ot) {
288 case OT_BYTE:
289 if (!byte_reg_is_xH(reg)) {
290 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
291 } else {
292 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
293 }
294 break;
295 case OT_WORD:
296 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
297 break;
298 default: /* XXX this shouldn't be reached; abort? */
299 case OT_LONG:
300 /* For x86_64, this sets the higher half of register to zero.
301 For i386, this is equivalent to a mov. */
302 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
303 break;
304 #ifdef TARGET_X86_64
305 case OT_QUAD:
306 tcg_gen_mov_tl(cpu_regs[reg], t0);
307 break;
308 #endif
309 }
310 }
311
312 static inline void gen_op_mov_reg_T0(int ot, int reg)
313 {
314 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
315 }
316
317 static inline void gen_op_mov_reg_T1(int ot, int reg)
318 {
319 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
320 }
321
322 static inline void gen_op_mov_reg_A0(int size, int reg)
323 {
324 switch(size) {
325 case 0:
326 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
327 break;
328 default: /* XXX this shouldn't be reached; abort? */
329 case 1:
330 /* For x86_64, this sets the higher half of register to zero.
331 For i386, this is equivalent to a mov. */
332 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
333 break;
334 #ifdef TARGET_X86_64
335 case 2:
336 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
337 break;
338 #endif
339 }
340 }
341
342 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
343 {
344 if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
345 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
346 tcg_gen_ext8u_tl(t0, t0);
347 } else {
348 tcg_gen_mov_tl(t0, cpu_regs[reg]);
349 }
350 }
351
352 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
353 {
354 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
355 }
356
357 static inline void gen_op_movl_A0_reg(int reg)
358 {
359 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
360 }
361
362 static inline void gen_op_addl_A0_im(int32_t val)
363 {
364 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
365 #ifdef TARGET_X86_64
366 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
367 #endif
368 }
369
370 #ifdef TARGET_X86_64
371 static inline void gen_op_addq_A0_im(int64_t val)
372 {
373 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374 }
375 #endif
376
377 static void gen_add_A0_im(DisasContext *s, int val)
378 {
379 #ifdef TARGET_X86_64
380 if (CODE64(s))
381 gen_op_addq_A0_im(val);
382 else
383 #endif
384 gen_op_addl_A0_im(val);
385 }
386
387 static inline void gen_op_addl_T0_T1(void)
388 {
389 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390 }
391
392 static inline void gen_op_jmp_T0(void)
393 {
394 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
395 }
396
397 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
398 {
399 switch(size) {
400 case 0:
401 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
402 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
403 break;
404 case 1:
405 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
406 /* For x86_64, this sets the higher half of register to zero.
407 For i386, this is equivalent to a nop. */
408 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
409 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
410 break;
411 #ifdef TARGET_X86_64
412 case 2:
413 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
414 break;
415 #endif
416 }
417 }
418
419 static inline void gen_op_add_reg_T0(int size, int reg)
420 {
421 switch(size) {
422 case 0:
423 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
424 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
425 break;
426 case 1:
427 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
428 /* For x86_64, this sets the higher half of register to zero.
429 For i386, this is equivalent to a nop. */
430 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
431 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
432 break;
433 #ifdef TARGET_X86_64
434 case 2:
435 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
436 break;
437 #endif
438 }
439 }
440
441 static inline void gen_op_set_cc_op(int32_t val)
442 {
443 tcg_gen_movi_i32(cpu_cc_op, val);
444 }
445
446 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
447 {
448 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
449 if (shift != 0)
450 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
451 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
452 /* For x86_64, this sets the higher half of register to zero.
453 For i386, this is equivalent to a nop. */
454 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
455 }
456
457 static inline void gen_op_movl_A0_seg(int reg)
458 {
459 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
460 }
461
462 static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
463 {
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
465 #ifdef TARGET_X86_64
466 if (CODE64(s)) {
467 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
468 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
469 } else {
470 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
471 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
472 }
473 #else
474 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
475 #endif
476 }
477
478 #ifdef TARGET_X86_64
479 static inline void gen_op_movq_A0_seg(int reg)
480 {
481 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
482 }
483
484 static inline void gen_op_addq_A0_seg(int reg)
485 {
486 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
487 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
488 }
489
490 static inline void gen_op_movq_A0_reg(int reg)
491 {
492 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
493 }
494
495 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
496 {
497 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
498 if (shift != 0)
499 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
500 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
501 }
502 #endif
503
504 static inline void gen_op_lds_T0_A0(int idx)
505 {
506 int mem_index = (idx >> 2) - 1;
507 switch(idx & 3) {
508 case 0:
509 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
510 break;
511 case 1:
512 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
513 break;
514 default:
515 case 2:
516 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
517 break;
518 }
519 }
520
521 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
522 {
523 int mem_index = (idx >> 2) - 1;
524 switch(idx & 3) {
525 case 0:
526 tcg_gen_qemu_ld8u(t0, a0, mem_index);
527 break;
528 case 1:
529 tcg_gen_qemu_ld16u(t0, a0, mem_index);
530 break;
531 case 2:
532 tcg_gen_qemu_ld32u(t0, a0, mem_index);
533 break;
534 default:
535 case 3:
536 /* Should never happen on 32-bit targets. */
537 #ifdef TARGET_X86_64
538 tcg_gen_qemu_ld64(t0, a0, mem_index);
539 #endif
540 break;
541 }
542 }
543
544 /* XXX: always use ldu or lds */
545 static inline void gen_op_ld_T0_A0(int idx)
546 {
547 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
548 }
549
550 static inline void gen_op_ldu_T0_A0(int idx)
551 {
552 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
553 }
554
555 static inline void gen_op_ld_T1_A0(int idx)
556 {
557 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
558 }
559
560 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
561 {
562 int mem_index = (idx >> 2) - 1;
563 switch(idx & 3) {
564 case 0:
565 tcg_gen_qemu_st8(t0, a0, mem_index);
566 break;
567 case 1:
568 tcg_gen_qemu_st16(t0, a0, mem_index);
569 break;
570 case 2:
571 tcg_gen_qemu_st32(t0, a0, mem_index);
572 break;
573 default:
574 case 3:
575 /* Should never happen on 32-bit targets. */
576 #ifdef TARGET_X86_64
577 tcg_gen_qemu_st64(t0, a0, mem_index);
578 #endif
579 break;
580 }
581 }
582
583 static inline void gen_op_st_T0_A0(int idx)
584 {
585 gen_op_st_v(idx, cpu_T[0], cpu_A0);
586 }
587
588 static inline void gen_op_st_T1_A0(int idx)
589 {
590 gen_op_st_v(idx, cpu_T[1], cpu_A0);
591 }
592
593 static inline void gen_jmp_im(target_ulong pc)
594 {
595 tcg_gen_movi_tl(cpu_tmp0, pc);
596 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
597 }
598
599 static inline void gen_string_movl_A0_ESI(DisasContext *s)
600 {
601 int override;
602
603 override = s->override;
604 #ifdef TARGET_X86_64
605 if (s->aflag == 2) {
606 if (override >= 0) {
607 gen_op_movq_A0_seg(override);
608 gen_op_addq_A0_reg_sN(0, R_ESI);
609 } else {
610 gen_op_movq_A0_reg(R_ESI);
611 }
612 } else
613 #endif
614 if (s->aflag) {
615 /* 32 bit address */
616 if (s->addseg && override < 0)
617 override = R_DS;
618 if (override >= 0) {
619 gen_op_movl_A0_seg(override);
620 gen_op_addl_A0_reg_sN(0, R_ESI);
621 } else {
622 gen_op_movl_A0_reg(R_ESI);
623 }
624 } else {
625 /* 16 address, always override */
626 if (override < 0)
627 override = R_DS;
628 gen_op_movl_A0_reg(R_ESI);
629 gen_op_andl_A0_ffff();
630 gen_op_addl_A0_seg(s, override);
631 }
632 }
633
634 static inline void gen_string_movl_A0_EDI(DisasContext *s)
635 {
636 #ifdef TARGET_X86_64
637 if (s->aflag == 2) {
638 gen_op_movq_A0_reg(R_EDI);
639 } else
640 #endif
641 if (s->aflag) {
642 if (s->addseg) {
643 gen_op_movl_A0_seg(R_ES);
644 gen_op_addl_A0_reg_sN(0, R_EDI);
645 } else {
646 gen_op_movl_A0_reg(R_EDI);
647 }
648 } else {
649 gen_op_movl_A0_reg(R_EDI);
650 gen_op_andl_A0_ffff();
651 gen_op_addl_A0_seg(s, R_ES);
652 }
653 }
654
655 static inline void gen_op_movl_T0_Dshift(int ot)
656 {
657 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
658 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
659 };
660
661 static void gen_extu(int ot, TCGv reg)
662 {
663 switch(ot) {
664 case OT_BYTE:
665 tcg_gen_ext8u_tl(reg, reg);
666 break;
667 case OT_WORD:
668 tcg_gen_ext16u_tl(reg, reg);
669 break;
670 case OT_LONG:
671 tcg_gen_ext32u_tl(reg, reg);
672 break;
673 default:
674 break;
675 }
676 }
677
678 static void gen_exts(int ot, TCGv reg)
679 {
680 switch(ot) {
681 case OT_BYTE:
682 tcg_gen_ext8s_tl(reg, reg);
683 break;
684 case OT_WORD:
685 tcg_gen_ext16s_tl(reg, reg);
686 break;
687 case OT_LONG:
688 tcg_gen_ext32s_tl(reg, reg);
689 break;
690 default:
691 break;
692 }
693 }
694
695 static inline void gen_op_jnz_ecx(int size, int label1)
696 {
697 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
698 gen_extu(size + 1, cpu_tmp0);
699 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
700 }
701
702 static inline void gen_op_jz_ecx(int size, int label1)
703 {
704 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
705 gen_extu(size + 1, cpu_tmp0);
706 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
707 }
708
709 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
710 {
711 switch (ot) {
712 case 0: gen_helper_inb(v, n); break;
713 case 1: gen_helper_inw(v, n); break;
714 case 2: gen_helper_inl(v, n); break;
715 }
716
717 }
718
719 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
720 {
721 switch (ot) {
722 case 0: gen_helper_outb(v, n); break;
723 case 1: gen_helper_outw(v, n); break;
724 case 2: gen_helper_outl(v, n); break;
725 }
726
727 }
728
729 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
730 uint32_t svm_flags)
731 {
732 int state_saved;
733 target_ulong next_eip;
734
735 state_saved = 0;
736 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
737 if (s->cc_op != CC_OP_DYNAMIC)
738 gen_op_set_cc_op(s->cc_op);
739 gen_jmp_im(cur_eip);
740 state_saved = 1;
741 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
742 switch (ot) {
743 case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
744 case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
745 case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
746 }
747 }
748 if(s->flags & HF_SVMI_MASK) {
749 if (!state_saved) {
750 if (s->cc_op != CC_OP_DYNAMIC)
751 gen_op_set_cc_op(s->cc_op);
752 gen_jmp_im(cur_eip);
753 }
754 svm_flags |= (1 << (4 + ot));
755 next_eip = s->pc - s->cs_base;
756 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
757 gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
758 tcg_const_i32(next_eip - cur_eip));
759 }
760 }
761
762 static inline void gen_movs(DisasContext *s, int ot)
763 {
764 gen_string_movl_A0_ESI(s);
765 gen_op_ld_T0_A0(ot + s->mem_index);
766 gen_string_movl_A0_EDI(s);
767 gen_op_st_T0_A0(ot + s->mem_index);
768 gen_op_movl_T0_Dshift(ot);
769 gen_op_add_reg_T0(s->aflag, R_ESI);
770 gen_op_add_reg_T0(s->aflag, R_EDI);
771 }
772
773 static inline void gen_update_cc_op(DisasContext *s)
774 {
775 if (s->cc_op != CC_OP_DYNAMIC) {
776 gen_op_set_cc_op(s->cc_op);
777 s->cc_op = CC_OP_DYNAMIC;
778 }
779 }
780
781 static void gen_op_update1_cc(void)
782 {
783 tcg_gen_discard_tl(cpu_cc_src);
784 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
785 }
786
787 static void gen_op_update2_cc(void)
788 {
789 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
790 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
791 }
792
793 static inline void gen_op_cmpl_T0_T1_cc(void)
794 {
795 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
796 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
797 }
798
799 static inline void gen_op_testl_T0_T1_cc(void)
800 {
801 tcg_gen_discard_tl(cpu_cc_src);
802 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
803 }
804
805 static void gen_op_update_neg_cc(void)
806 {
807 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
808 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
809 }
810
811 /* compute eflags.C to reg */
812 static void gen_compute_eflags_c(TCGv reg)
813 {
814 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
815 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
816 }
817
818 /* compute all eflags to cc_src */
819 static void gen_compute_eflags(TCGv reg)
820 {
821 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
822 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
823 }
824
825 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
826 {
827 if (s->cc_op != CC_OP_DYNAMIC)
828 gen_op_set_cc_op(s->cc_op);
829 switch(jcc_op) {
830 case JCC_O:
831 gen_compute_eflags(cpu_T[0]);
832 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
833 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
834 break;
835 case JCC_B:
836 gen_compute_eflags_c(cpu_T[0]);
837 break;
838 case JCC_Z:
839 gen_compute_eflags(cpu_T[0]);
840 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
841 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
842 break;
843 case JCC_BE:
844 gen_compute_eflags(cpu_tmp0);
845 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
846 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
847 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
848 break;
849 case JCC_S:
850 gen_compute_eflags(cpu_T[0]);
851 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
852 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
853 break;
854 case JCC_P:
855 gen_compute_eflags(cpu_T[0]);
856 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
857 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
858 break;
859 case JCC_L:
860 gen_compute_eflags(cpu_tmp0);
861 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
862 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
863 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
864 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865 break;
866 default:
867 case JCC_LE:
868 gen_compute_eflags(cpu_tmp0);
869 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
870 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
871 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
872 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
873 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
874 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
875 break;
876 }
877 }
878
879 /* return true if setcc_slow is not needed (WARNING: must be kept in
880 sync with gen_jcc1) */
881 static int is_fast_jcc_case(DisasContext *s, int b)
882 {
883 int jcc_op;
884 jcc_op = (b >> 1) & 7;
885 switch(s->cc_op) {
886 /* we optimize the cmp/jcc case */
887 case CC_OP_SUBB:
888 case CC_OP_SUBW:
889 case CC_OP_SUBL:
890 case CC_OP_SUBQ:
891 if (jcc_op == JCC_O || jcc_op == JCC_P)
892 goto slow_jcc;
893 break;
894
895 /* some jumps are easy to compute */
896 case CC_OP_ADDB:
897 case CC_OP_ADDW:
898 case CC_OP_ADDL:
899 case CC_OP_ADDQ:
900
901 case CC_OP_LOGICB:
902 case CC_OP_LOGICW:
903 case CC_OP_LOGICL:
904 case CC_OP_LOGICQ:
905
906 case CC_OP_INCB:
907 case CC_OP_INCW:
908 case CC_OP_INCL:
909 case CC_OP_INCQ:
910
911 case CC_OP_DECB:
912 case CC_OP_DECW:
913 case CC_OP_DECL:
914 case CC_OP_DECQ:
915
916 case CC_OP_SHLB:
917 case CC_OP_SHLW:
918 case CC_OP_SHLL:
919 case CC_OP_SHLQ:
920 if (jcc_op != JCC_Z && jcc_op != JCC_S)
921 goto slow_jcc;
922 break;
923 default:
924 slow_jcc:
925 return 0;
926 }
927 return 1;
928 }
929
930 /* generate a conditional jump to label 'l1' according to jump opcode
931 value 'b'. In the fast case, T0 is guaranted not to be used. */
932 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
933 {
934 int inv, jcc_op, size, cond;
935 TCGv t0;
936
937 inv = b & 1;
938 jcc_op = (b >> 1) & 7;
939
940 switch(cc_op) {
941 /* we optimize the cmp/jcc case */
942 case CC_OP_SUBB:
943 case CC_OP_SUBW:
944 case CC_OP_SUBL:
945 case CC_OP_SUBQ:
946
947 size = cc_op - CC_OP_SUBB;
948 switch(jcc_op) {
949 case JCC_Z:
950 fast_jcc_z:
951 switch(size) {
952 case 0:
953 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
954 t0 = cpu_tmp0;
955 break;
956 case 1:
957 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
958 t0 = cpu_tmp0;
959 break;
960 #ifdef TARGET_X86_64
961 case 2:
962 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
963 t0 = cpu_tmp0;
964 break;
965 #endif
966 default:
967 t0 = cpu_cc_dst;
968 break;
969 }
970 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
971 break;
972 case JCC_S:
973 fast_jcc_s:
974 switch(size) {
975 case 0:
976 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
977 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
978 0, l1);
979 break;
980 case 1:
981 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
982 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
983 0, l1);
984 break;
985 #ifdef TARGET_X86_64
986 case 2:
987 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
988 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
989 0, l1);
990 break;
991 #endif
992 default:
993 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
994 0, l1);
995 break;
996 }
997 break;
998
999 case JCC_B:
1000 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1001 goto fast_jcc_b;
1002 case JCC_BE:
1003 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1004 fast_jcc_b:
1005 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1006 switch(size) {
1007 case 0:
1008 t0 = cpu_tmp0;
1009 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1010 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1011 break;
1012 case 1:
1013 t0 = cpu_tmp0;
1014 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1015 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1016 break;
1017 #ifdef TARGET_X86_64
1018 case 2:
1019 t0 = cpu_tmp0;
1020 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1021 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1022 break;
1023 #endif
1024 default:
1025 t0 = cpu_cc_src;
1026 break;
1027 }
1028 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1029 break;
1030
1031 case JCC_L:
1032 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1033 goto fast_jcc_l;
1034 case JCC_LE:
1035 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1036 fast_jcc_l:
1037 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1038 switch(size) {
1039 case 0:
1040 t0 = cpu_tmp0;
1041 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1042 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1043 break;
1044 case 1:
1045 t0 = cpu_tmp0;
1046 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1047 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1048 break;
1049 #ifdef TARGET_X86_64
1050 case 2:
1051 t0 = cpu_tmp0;
1052 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1053 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1054 break;
1055 #endif
1056 default:
1057 t0 = cpu_cc_src;
1058 break;
1059 }
1060 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1061 break;
1062
1063 default:
1064 goto slow_jcc;
1065 }
1066 break;
1067
1068 /* some jumps are easy to compute */
1069 case CC_OP_ADDB:
1070 case CC_OP_ADDW:
1071 case CC_OP_ADDL:
1072 case CC_OP_ADDQ:
1073
1074 case CC_OP_ADCB:
1075 case CC_OP_ADCW:
1076 case CC_OP_ADCL:
1077 case CC_OP_ADCQ:
1078
1079 case CC_OP_SBBB:
1080 case CC_OP_SBBW:
1081 case CC_OP_SBBL:
1082 case CC_OP_SBBQ:
1083
1084 case CC_OP_LOGICB:
1085 case CC_OP_LOGICW:
1086 case CC_OP_LOGICL:
1087 case CC_OP_LOGICQ:
1088
1089 case CC_OP_INCB:
1090 case CC_OP_INCW:
1091 case CC_OP_INCL:
1092 case CC_OP_INCQ:
1093
1094 case CC_OP_DECB:
1095 case CC_OP_DECW:
1096 case CC_OP_DECL:
1097 case CC_OP_DECQ:
1098
1099 case CC_OP_SHLB:
1100 case CC_OP_SHLW:
1101 case CC_OP_SHLL:
1102 case CC_OP_SHLQ:
1103
1104 case CC_OP_SARB:
1105 case CC_OP_SARW:
1106 case CC_OP_SARL:
1107 case CC_OP_SARQ:
1108 switch(jcc_op) {
1109 case JCC_Z:
1110 size = (cc_op - CC_OP_ADDB) & 3;
1111 goto fast_jcc_z;
1112 case JCC_S:
1113 size = (cc_op - CC_OP_ADDB) & 3;
1114 goto fast_jcc_s;
1115 default:
1116 goto slow_jcc;
1117 }
1118 break;
1119 default:
1120 slow_jcc:
1121 gen_setcc_slow_T0(s, jcc_op);
1122 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1123 cpu_T[0], 0, l1);
1124 break;
1125 }
1126 }
1127
1128 /* XXX: does not work with gdbstub "ice" single step - not a
1129 serious problem */
1130 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1131 {
1132 int l1, l2;
1133
1134 l1 = gen_new_label();
1135 l2 = gen_new_label();
1136 gen_op_jnz_ecx(s->aflag, l1);
1137 gen_set_label(l2);
1138 gen_jmp_tb(s, next_eip, 1);
1139 gen_set_label(l1);
1140 return l2;
1141 }
1142
1143 static inline void gen_stos(DisasContext *s, int ot)
1144 {
1145 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1146 gen_string_movl_A0_EDI(s);
1147 gen_op_st_T0_A0(ot + s->mem_index);
1148 gen_op_movl_T0_Dshift(ot);
1149 gen_op_add_reg_T0(s->aflag, R_EDI);
1150 }
1151
1152 static inline void gen_lods(DisasContext *s, int ot)
1153 {
1154 gen_string_movl_A0_ESI(s);
1155 gen_op_ld_T0_A0(ot + s->mem_index);
1156 gen_op_mov_reg_T0(ot, R_EAX);
1157 gen_op_movl_T0_Dshift(ot);
1158 gen_op_add_reg_T0(s->aflag, R_ESI);
1159 }
1160
1161 static inline void gen_scas(DisasContext *s, int ot)
1162 {
1163 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1164 gen_string_movl_A0_EDI(s);
1165 gen_op_ld_T1_A0(ot + s->mem_index);
1166 gen_op_cmpl_T0_T1_cc();
1167 gen_op_movl_T0_Dshift(ot);
1168 gen_op_add_reg_T0(s->aflag, R_EDI);
1169 }
1170
1171 static inline void gen_cmps(DisasContext *s, int ot)
1172 {
1173 gen_string_movl_A0_ESI(s);
1174 gen_op_ld_T0_A0(ot + s->mem_index);
1175 gen_string_movl_A0_EDI(s);
1176 gen_op_ld_T1_A0(ot + s->mem_index);
1177 gen_op_cmpl_T0_T1_cc();
1178 gen_op_movl_T0_Dshift(ot);
1179 gen_op_add_reg_T0(s->aflag, R_ESI);
1180 gen_op_add_reg_T0(s->aflag, R_EDI);
1181 }
1182
1183 static inline void gen_ins(DisasContext *s, int ot)
1184 {
1185 if (use_icount)
1186 gen_io_start();
1187 gen_string_movl_A0_EDI(s);
1188 /* Note: we must do this dummy write first to be restartable in
1189 case of page fault. */
1190 gen_op_movl_T0_0();
1191 gen_op_st_T0_A0(ot + s->mem_index);
1192 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1193 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1194 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1195 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1196 gen_op_st_T0_A0(ot + s->mem_index);
1197 gen_op_movl_T0_Dshift(ot);
1198 gen_op_add_reg_T0(s->aflag, R_EDI);
1199 if (use_icount)
1200 gen_io_end();
1201 }
1202
1203 static inline void gen_outs(DisasContext *s, int ot)
1204 {
1205 if (use_icount)
1206 gen_io_start();
1207 gen_string_movl_A0_ESI(s);
1208 gen_op_ld_T0_A0(ot + s->mem_index);
1209
1210 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1211 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1212 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1213 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1214 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1215
1216 gen_op_movl_T0_Dshift(ot);
1217 gen_op_add_reg_T0(s->aflag, R_ESI);
1218 if (use_icount)
1219 gen_io_end();
1220 }
1221
1222 /* same method as Valgrind : we generate jumps to current or next
1223 instruction */
1224 #define GEN_REPZ(op) \
1225 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1226 target_ulong cur_eip, target_ulong next_eip) \
1227 { \
1228 int l2;\
1229 gen_update_cc_op(s); \
1230 l2 = gen_jz_ecx_string(s, next_eip); \
1231 gen_ ## op(s, ot); \
1232 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1233 /* a loop would cause two single step exceptions if ECX = 1 \
1234 before rep string_insn */ \
1235 if (!s->jmp_opt) \
1236 gen_op_jz_ecx(s->aflag, l2); \
1237 gen_jmp(s, cur_eip); \
1238 }
1239
1240 #define GEN_REPZ2(op) \
1241 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1242 target_ulong cur_eip, \
1243 target_ulong next_eip, \
1244 int nz) \
1245 { \
1246 int l2;\
1247 gen_update_cc_op(s); \
1248 l2 = gen_jz_ecx_string(s, next_eip); \
1249 gen_ ## op(s, ot); \
1250 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1251 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1252 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1253 if (!s->jmp_opt) \
1254 gen_op_jz_ecx(s->aflag, l2); \
1255 gen_jmp(s, cur_eip); \
1256 }
1257
1258 GEN_REPZ(movs)
1259 GEN_REPZ(stos)
1260 GEN_REPZ(lods)
1261 GEN_REPZ(ins)
1262 GEN_REPZ(outs)
1263 GEN_REPZ2(scas)
1264 GEN_REPZ2(cmps)
1265
1266 static void gen_helper_fp_arith_ST0_FT0(int op)
1267 {
1268 switch (op) {
1269 case 0:
1270 gen_helper_fadd_ST0_FT0(cpu_env);
1271 break;
1272 case 1:
1273 gen_helper_fmul_ST0_FT0(cpu_env);
1274 break;
1275 case 2:
1276 gen_helper_fcom_ST0_FT0(cpu_env);
1277 break;
1278 case 3:
1279 gen_helper_fcom_ST0_FT0(cpu_env);
1280 break;
1281 case 4:
1282 gen_helper_fsub_ST0_FT0(cpu_env);
1283 break;
1284 case 5:
1285 gen_helper_fsubr_ST0_FT0(cpu_env);
1286 break;
1287 case 6:
1288 gen_helper_fdiv_ST0_FT0(cpu_env);
1289 break;
1290 case 7:
1291 gen_helper_fdivr_ST0_FT0(cpu_env);
1292 break;
1293 }
1294 }
1295
1296 /* NOTE the exception in "r" op ordering */
1297 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1298 {
1299 TCGv_i32 tmp = tcg_const_i32(opreg);
1300 switch (op) {
1301 case 0:
1302 gen_helper_fadd_STN_ST0(cpu_env, tmp);
1303 break;
1304 case 1:
1305 gen_helper_fmul_STN_ST0(cpu_env, tmp);
1306 break;
1307 case 4:
1308 gen_helper_fsubr_STN_ST0(cpu_env, tmp);
1309 break;
1310 case 5:
1311 gen_helper_fsub_STN_ST0(cpu_env, tmp);
1312 break;
1313 case 6:
1314 gen_helper_fdivr_STN_ST0(cpu_env, tmp);
1315 break;
1316 case 7:
1317 gen_helper_fdiv_STN_ST0(cpu_env, tmp);
1318 break;
1319 }
1320 }
1321
1322 /* if d == OR_TMP0, it means memory operand (address in A0) */
1323 static void gen_op(DisasContext *s1, int op, int ot, int d)
1324 {
1325 if (d != OR_TMP0) {
1326 gen_op_mov_TN_reg(ot, 0, d);
1327 } else {
1328 gen_op_ld_T0_A0(ot + s1->mem_index);
1329 }
1330 switch(op) {
1331 case OP_ADCL:
1332 if (s1->cc_op != CC_OP_DYNAMIC)
1333 gen_op_set_cc_op(s1->cc_op);
1334 gen_compute_eflags_c(cpu_tmp4);
1335 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1336 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1337 if (d != OR_TMP0)
1338 gen_op_mov_reg_T0(ot, d);
1339 else
1340 gen_op_st_T0_A0(ot + s1->mem_index);
1341 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1342 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1343 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1344 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1345 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1346 s1->cc_op = CC_OP_DYNAMIC;
1347 break;
1348 case OP_SBBL:
1349 if (s1->cc_op != CC_OP_DYNAMIC)
1350 gen_op_set_cc_op(s1->cc_op);
1351 gen_compute_eflags_c(cpu_tmp4);
1352 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1353 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1354 if (d != OR_TMP0)
1355 gen_op_mov_reg_T0(ot, d);
1356 else
1357 gen_op_st_T0_A0(ot + s1->mem_index);
1358 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1359 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1360 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1361 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1362 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1363 s1->cc_op = CC_OP_DYNAMIC;
1364 break;
1365 case OP_ADDL:
1366 gen_op_addl_T0_T1();
1367 if (d != OR_TMP0)
1368 gen_op_mov_reg_T0(ot, d);
1369 else
1370 gen_op_st_T0_A0(ot + s1->mem_index);
1371 gen_op_update2_cc();
1372 s1->cc_op = CC_OP_ADDB + ot;
1373 break;
1374 case OP_SUBL:
1375 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1376 if (d != OR_TMP0)
1377 gen_op_mov_reg_T0(ot, d);
1378 else
1379 gen_op_st_T0_A0(ot + s1->mem_index);
1380 gen_op_update2_cc();
1381 s1->cc_op = CC_OP_SUBB + ot;
1382 break;
1383 default:
1384 case OP_ANDL:
1385 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1386 if (d != OR_TMP0)
1387 gen_op_mov_reg_T0(ot, d);
1388 else
1389 gen_op_st_T0_A0(ot + s1->mem_index);
1390 gen_op_update1_cc();
1391 s1->cc_op = CC_OP_LOGICB + ot;
1392 break;
1393 case OP_ORL:
1394 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1395 if (d != OR_TMP0)
1396 gen_op_mov_reg_T0(ot, d);
1397 else
1398 gen_op_st_T0_A0(ot + s1->mem_index);
1399 gen_op_update1_cc();
1400 s1->cc_op = CC_OP_LOGICB + ot;
1401 break;
1402 case OP_XORL:
1403 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1404 if (d != OR_TMP0)
1405 gen_op_mov_reg_T0(ot, d);
1406 else
1407 gen_op_st_T0_A0(ot + s1->mem_index);
1408 gen_op_update1_cc();
1409 s1->cc_op = CC_OP_LOGICB + ot;
1410 break;
1411 case OP_CMPL:
1412 gen_op_cmpl_T0_T1_cc();
1413 s1->cc_op = CC_OP_SUBB + ot;
1414 break;
1415 }
1416 }
1417
1418 /* if d == OR_TMP0, it means memory operand (address in A0) */
1419 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1420 {
1421 if (d != OR_TMP0)
1422 gen_op_mov_TN_reg(ot, 0, d);
1423 else
1424 gen_op_ld_T0_A0(ot + s1->mem_index);
1425 if (s1->cc_op != CC_OP_DYNAMIC)
1426 gen_op_set_cc_op(s1->cc_op);
1427 if (c > 0) {
1428 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1429 s1->cc_op = CC_OP_INCB + ot;
1430 } else {
1431 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1432 s1->cc_op = CC_OP_DECB + ot;
1433 }
1434 if (d != OR_TMP0)
1435 gen_op_mov_reg_T0(ot, d);
1436 else
1437 gen_op_st_T0_A0(ot + s1->mem_index);
1438 gen_compute_eflags_c(cpu_cc_src);
1439 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1440 }
1441
1442 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1443 int is_right, int is_arith)
1444 {
1445 target_ulong mask;
1446 int shift_label;
1447 TCGv t0, t1, t2;
1448
1449 if (ot == OT_QUAD) {
1450 mask = 0x3f;
1451 } else {
1452 mask = 0x1f;
1453 }
1454
1455 /* load */
1456 if (op1 == OR_TMP0) {
1457 gen_op_ld_T0_A0(ot + s->mem_index);
1458 } else {
1459 gen_op_mov_TN_reg(ot, 0, op1);
1460 }
1461
1462 t0 = tcg_temp_local_new();
1463 t1 = tcg_temp_local_new();
1464 t2 = tcg_temp_local_new();
1465
1466 tcg_gen_andi_tl(t2, cpu_T[1], mask);
1467
1468 if (is_right) {
1469 if (is_arith) {
1470 gen_exts(ot, cpu_T[0]);
1471 tcg_gen_mov_tl(t0, cpu_T[0]);
1472 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2);
1473 } else {
1474 gen_extu(ot, cpu_T[0]);
1475 tcg_gen_mov_tl(t0, cpu_T[0]);
1476 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2);
1477 }
1478 } else {
1479 tcg_gen_mov_tl(t0, cpu_T[0]);
1480 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2);
1481 }
1482
1483 /* store */
1484 if (op1 == OR_TMP0) {
1485 gen_op_st_T0_A0(ot + s->mem_index);
1486 } else {
1487 gen_op_mov_reg_T0(ot, op1);
1488 }
1489
1490 /* update eflags if non zero shift */
1491 if (s->cc_op != CC_OP_DYNAMIC) {
1492 gen_op_set_cc_op(s->cc_op);
1493 }
1494
1495 tcg_gen_mov_tl(t1, cpu_T[0]);
1496
1497 shift_label = gen_new_label();
1498 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label);
1499
1500 tcg_gen_addi_tl(t2, t2, -1);
1501 tcg_gen_mov_tl(cpu_cc_dst, t1);
1502
1503 if (is_right) {
1504 if (is_arith) {
1505 tcg_gen_sar_tl(cpu_cc_src, t0, t2);
1506 } else {
1507 tcg_gen_shr_tl(cpu_cc_src, t0, t2);
1508 }
1509 } else {
1510 tcg_gen_shl_tl(cpu_cc_src, t0, t2);
1511 }
1512
1513 if (is_right) {
1514 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1515 } else {
1516 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1517 }
1518
1519 gen_set_label(shift_label);
1520 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1521
1522 tcg_temp_free(t0);
1523 tcg_temp_free(t1);
1524 tcg_temp_free(t2);
1525 }
1526
1527 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1528 int is_right, int is_arith)
1529 {
1530 int mask;
1531
1532 if (ot == OT_QUAD)
1533 mask = 0x3f;
1534 else
1535 mask = 0x1f;
1536
1537 /* load */
1538 if (op1 == OR_TMP0)
1539 gen_op_ld_T0_A0(ot + s->mem_index);
1540 else
1541 gen_op_mov_TN_reg(ot, 0, op1);
1542
1543 op2 &= mask;
1544 if (op2 != 0) {
1545 if (is_right) {
1546 if (is_arith) {
1547 gen_exts(ot, cpu_T[0]);
1548 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1549 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1550 } else {
1551 gen_extu(ot, cpu_T[0]);
1552 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1553 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1554 }
1555 } else {
1556 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1557 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1558 }
1559 }
1560
1561 /* store */
1562 if (op1 == OR_TMP0)
1563 gen_op_st_T0_A0(ot + s->mem_index);
1564 else
1565 gen_op_mov_reg_T0(ot, op1);
1566
1567 /* update eflags if non zero shift */
1568 if (op2 != 0) {
1569 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1570 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1571 if (is_right)
1572 s->cc_op = CC_OP_SARB + ot;
1573 else
1574 s->cc_op = CC_OP_SHLB + ot;
1575 }
1576 }
1577
1578 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1579 {
1580 if (arg2 >= 0)
1581 tcg_gen_shli_tl(ret, arg1, arg2);
1582 else
1583 tcg_gen_shri_tl(ret, arg1, -arg2);
1584 }
1585
1586 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1587 int is_right)
1588 {
1589 target_ulong mask;
1590 int label1, label2, data_bits;
1591 TCGv t0, t1, t2, a0;
1592
1593 /* XXX: inefficient, but we must use local temps */
1594 t0 = tcg_temp_local_new();
1595 t1 = tcg_temp_local_new();
1596 t2 = tcg_temp_local_new();
1597 a0 = tcg_temp_local_new();
1598
1599 if (ot == OT_QUAD)
1600 mask = 0x3f;
1601 else
1602 mask = 0x1f;
1603
1604 /* load */
1605 if (op1 == OR_TMP0) {
1606 tcg_gen_mov_tl(a0, cpu_A0);
1607 gen_op_ld_v(ot + s->mem_index, t0, a0);
1608 } else {
1609 gen_op_mov_v_reg(ot, t0, op1);
1610 }
1611
1612 tcg_gen_mov_tl(t1, cpu_T[1]);
1613
1614 tcg_gen_andi_tl(t1, t1, mask);
1615
1616 /* Must test zero case to avoid using undefined behaviour in TCG
1617 shifts. */
1618 label1 = gen_new_label();
1619 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1620
1621 if (ot <= OT_WORD)
1622 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1623 else
1624 tcg_gen_mov_tl(cpu_tmp0, t1);
1625
1626 gen_extu(ot, t0);
1627 tcg_gen_mov_tl(t2, t0);
1628
1629 data_bits = 8 << ot;
1630 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1631 fix TCG definition) */
1632 if (is_right) {
1633 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1634 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1635 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1636 } else {
1637 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1638 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1639 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1640 }
1641 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1642
1643 gen_set_label(label1);
1644 /* store */
1645 if (op1 == OR_TMP0) {
1646 gen_op_st_v(ot + s->mem_index, t0, a0);
1647 } else {
1648 gen_op_mov_reg_v(ot, op1, t0);
1649 }
1650
1651 /* update eflags */
1652 if (s->cc_op != CC_OP_DYNAMIC)
1653 gen_op_set_cc_op(s->cc_op);
1654
1655 label2 = gen_new_label();
1656 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1657
1658 gen_compute_eflags(cpu_cc_src);
1659 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1660 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1661 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1662 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1663 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1664 if (is_right) {
1665 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1666 }
1667 tcg_gen_andi_tl(t0, t0, CC_C);
1668 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1669
1670 tcg_gen_discard_tl(cpu_cc_dst);
1671 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1672
1673 gen_set_label(label2);
1674 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1675
1676 tcg_temp_free(t0);
1677 tcg_temp_free(t1);
1678 tcg_temp_free(t2);
1679 tcg_temp_free(a0);
1680 }
1681
1682 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1683 int is_right)
1684 {
1685 int mask;
1686 int data_bits;
1687 TCGv t0, t1, a0;
1688
1689 /* XXX: inefficient, but we must use local temps */
1690 t0 = tcg_temp_local_new();
1691 t1 = tcg_temp_local_new();
1692 a0 = tcg_temp_local_new();
1693
1694 if (ot == OT_QUAD)
1695 mask = 0x3f;
1696 else
1697 mask = 0x1f;
1698
1699 /* load */
1700 if (op1 == OR_TMP0) {
1701 tcg_gen_mov_tl(a0, cpu_A0);
1702 gen_op_ld_v(ot + s->mem_index, t0, a0);
1703 } else {
1704 gen_op_mov_v_reg(ot, t0, op1);
1705 }
1706
1707 gen_extu(ot, t0);
1708 tcg_gen_mov_tl(t1, t0);
1709
1710 op2 &= mask;
1711 data_bits = 8 << ot;
1712 if (op2 != 0) {
1713 int shift = op2 & ((1 << (3 + ot)) - 1);
1714 if (is_right) {
1715 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1716 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1717 }
1718 else {
1719 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1720 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1721 }
1722 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1723 }
1724
1725 /* store */
1726 if (op1 == OR_TMP0) {
1727 gen_op_st_v(ot + s->mem_index, t0, a0);
1728 } else {
1729 gen_op_mov_reg_v(ot, op1, t0);
1730 }
1731
1732 if (op2 != 0) {
1733 /* update eflags */
1734 if (s->cc_op != CC_OP_DYNAMIC)
1735 gen_op_set_cc_op(s->cc_op);
1736
1737 gen_compute_eflags(cpu_cc_src);
1738 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1739 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1740 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1741 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1742 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1743 if (is_right) {
1744 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1745 }
1746 tcg_gen_andi_tl(t0, t0, CC_C);
1747 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1748
1749 tcg_gen_discard_tl(cpu_cc_dst);
1750 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1751 s->cc_op = CC_OP_EFLAGS;
1752 }
1753
1754 tcg_temp_free(t0);
1755 tcg_temp_free(t1);
1756 tcg_temp_free(a0);
1757 }
1758
1759 /* XXX: add faster immediate = 1 case */
1760 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1761 int is_right)
1762 {
1763 int label1;
1764
1765 if (s->cc_op != CC_OP_DYNAMIC)
1766 gen_op_set_cc_op(s->cc_op);
1767
1768 /* load */
1769 if (op1 == OR_TMP0)
1770 gen_op_ld_T0_A0(ot + s->mem_index);
1771 else
1772 gen_op_mov_TN_reg(ot, 0, op1);
1773
1774 if (is_right) {
1775 switch (ot) {
1776 case 0: gen_helper_rcrb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1777 case 1: gen_helper_rcrw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1778 case 2: gen_helper_rcrl(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1779 #ifdef TARGET_X86_64
1780 case 3: gen_helper_rcrq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1781 #endif
1782 }
1783 } else {
1784 switch (ot) {
1785 case 0: gen_helper_rclb(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1786 case 1: gen_helper_rclw(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1787 case 2: gen_helper_rcll(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1788 #ifdef TARGET_X86_64
1789 case 3: gen_helper_rclq(cpu_T[0], cpu_T[0], cpu_T[1]); break;
1790 #endif
1791 }
1792 }
1793 /* store */
1794 if (op1 == OR_TMP0)
1795 gen_op_st_T0_A0(ot + s->mem_index);
1796 else
1797 gen_op_mov_reg_T0(ot, op1);
1798
1799 /* update eflags */
1800 label1 = gen_new_label();
1801 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1802
1803 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1804 tcg_gen_discard_tl(cpu_cc_dst);
1805 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1806
1807 gen_set_label(label1);
1808 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1809 }
1810
1811 /* XXX: add faster immediate case */
1812 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1813 int is_right)
1814 {
1815 int label1, label2, data_bits;
1816 target_ulong mask;
1817 TCGv t0, t1, t2, a0;
1818
1819 t0 = tcg_temp_local_new();
1820 t1 = tcg_temp_local_new();
1821 t2 = tcg_temp_local_new();
1822 a0 = tcg_temp_local_new();
1823
1824 if (ot == OT_QUAD)
1825 mask = 0x3f;
1826 else
1827 mask = 0x1f;
1828
1829 /* load */
1830 if (op1 == OR_TMP0) {
1831 tcg_gen_mov_tl(a0, cpu_A0);
1832 gen_op_ld_v(ot + s->mem_index, t0, a0);
1833 } else {
1834 gen_op_mov_v_reg(ot, t0, op1);
1835 }
1836
1837 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1838
1839 tcg_gen_mov_tl(t1, cpu_T[1]);
1840 tcg_gen_mov_tl(t2, cpu_T3);
1841
1842 /* Must test zero case to avoid using undefined behaviour in TCG
1843 shifts. */
1844 label1 = gen_new_label();
1845 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1846
1847 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1848 if (ot == OT_WORD) {
1849 /* Note: we implement the Intel behaviour for shift count > 16 */
1850 if (is_right) {
1851 tcg_gen_andi_tl(t0, t0, 0xffff);
1852 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1853 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1854 tcg_gen_ext32u_tl(t0, t0);
1855
1856 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1857
1858 /* only needed if count > 16, but a test would complicate */
1859 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1860 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1861
1862 tcg_gen_shr_tl(t0, t0, t2);
1863
1864 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1865 } else {
1866 /* XXX: not optimal */
1867 tcg_gen_andi_tl(t0, t0, 0xffff);
1868 tcg_gen_shli_tl(t1, t1, 16);
1869 tcg_gen_or_tl(t1, t1, t0);
1870 tcg_gen_ext32u_tl(t1, t1);
1871
1872 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1873 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1874 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1875 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1876
1877 tcg_gen_shl_tl(t0, t0, t2);
1878 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1879 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1880 tcg_gen_or_tl(t0, t0, t1);
1881 }
1882 } else {
1883 data_bits = 8 << ot;
1884 if (is_right) {
1885 if (ot == OT_LONG)
1886 tcg_gen_ext32u_tl(t0, t0);
1887
1888 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1889
1890 tcg_gen_shr_tl(t0, t0, t2);
1891 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1892 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1893 tcg_gen_or_tl(t0, t0, t1);
1894
1895 } else {
1896 if (ot == OT_LONG)
1897 tcg_gen_ext32u_tl(t1, t1);
1898
1899 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1900
1901 tcg_gen_shl_tl(t0, t0, t2);
1902 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1903 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1904 tcg_gen_or_tl(t0, t0, t1);
1905 }
1906 }
1907 tcg_gen_mov_tl(t1, cpu_tmp4);
1908
1909 gen_set_label(label1);
1910 /* store */
1911 if (op1 == OR_TMP0) {
1912 gen_op_st_v(ot + s->mem_index, t0, a0);
1913 } else {
1914 gen_op_mov_reg_v(ot, op1, t0);
1915 }
1916
1917 /* update eflags */
1918 if (s->cc_op != CC_OP_DYNAMIC)
1919 gen_op_set_cc_op(s->cc_op);
1920
1921 label2 = gen_new_label();
1922 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1923
1924 tcg_gen_mov_tl(cpu_cc_src, t1);
1925 tcg_gen_mov_tl(cpu_cc_dst, t0);
1926 if (is_right) {
1927 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1928 } else {
1929 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1930 }
1931 gen_set_label(label2);
1932 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1933
1934 tcg_temp_free(t0);
1935 tcg_temp_free(t1);
1936 tcg_temp_free(t2);
1937 tcg_temp_free(a0);
1938 }
1939
1940 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1941 {
1942 if (s != OR_TMP1)
1943 gen_op_mov_TN_reg(ot, 1, s);
1944 switch(op) {
1945 case OP_ROL:
1946 gen_rot_rm_T1(s1, ot, d, 0);
1947 break;
1948 case OP_ROR:
1949 gen_rot_rm_T1(s1, ot, d, 1);
1950 break;
1951 case OP_SHL:
1952 case OP_SHL1:
1953 gen_shift_rm_T1(s1, ot, d, 0, 0);
1954 break;
1955 case OP_SHR:
1956 gen_shift_rm_T1(s1, ot, d, 1, 0);
1957 break;
1958 case OP_SAR:
1959 gen_shift_rm_T1(s1, ot, d, 1, 1);
1960 break;
1961 case OP_RCL:
1962 gen_rotc_rm_T1(s1, ot, d, 0);
1963 break;
1964 case OP_RCR:
1965 gen_rotc_rm_T1(s1, ot, d, 1);
1966 break;
1967 }
1968 }
1969
1970 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1971 {
1972 switch(op) {
1973 case OP_ROL:
1974 gen_rot_rm_im(s1, ot, d, c, 0);
1975 break;
1976 case OP_ROR:
1977 gen_rot_rm_im(s1, ot, d, c, 1);
1978 break;
1979 case OP_SHL:
1980 case OP_SHL1:
1981 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1982 break;
1983 case OP_SHR:
1984 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1985 break;
1986 case OP_SAR:
1987 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1988 break;
1989 default:
1990 /* currently not optimized */
1991 gen_op_movl_T1_im(c);
1992 gen_shift(s1, op, ot, d, OR_TMP1);
1993 break;
1994 }
1995 }
1996
1997 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1998 {
1999 target_long disp;
2000 int havesib;
2001 int base;
2002 int index;
2003 int scale;
2004 int opreg;
2005 int mod, rm, code, override, must_add_seg;
2006
2007 override = s->override;
2008 must_add_seg = s->addseg;
2009 if (override >= 0)
2010 must_add_seg = 1;
2011 mod = (modrm >> 6) & 3;
2012 rm = modrm & 7;
2013
2014 if (s->aflag) {
2015
2016 havesib = 0;
2017 base = rm;
2018 index = 0;
2019 scale = 0;
2020
2021 if (base == 4) {
2022 havesib = 1;
2023 code = ldub_code(s->pc++);
2024 scale = (code >> 6) & 3;
2025 index = ((code >> 3) & 7) | REX_X(s);
2026 base = (code & 7);
2027 }
2028 base |= REX_B(s);
2029
2030 switch (mod) {
2031 case 0:
2032 if ((base & 7) == 5) {
2033 base = -1;
2034 disp = (int32_t)ldl_code(s->pc);
2035 s->pc += 4;
2036 if (CODE64(s) && !havesib) {
2037 disp += s->pc + s->rip_offset;
2038 }
2039 } else {
2040 disp = 0;
2041 }
2042 break;
2043 case 1:
2044 disp = (int8_t)ldub_code(s->pc++);
2045 break;
2046 default:
2047 case 2:
2048 disp = (int32_t)ldl_code(s->pc);
2049 s->pc += 4;
2050 break;
2051 }
2052
2053 if (base >= 0) {
2054 /* for correct popl handling with esp */
2055 if (base == 4 && s->popl_esp_hack)
2056 disp += s->popl_esp_hack;
2057 #ifdef TARGET_X86_64
2058 if (s->aflag == 2) {
2059 gen_op_movq_A0_reg(base);
2060 if (disp != 0) {
2061 gen_op_addq_A0_im(disp);
2062 }
2063 } else
2064 #endif
2065 {
2066 gen_op_movl_A0_reg(base);
2067 if (disp != 0)
2068 gen_op_addl_A0_im(disp);
2069 }
2070 } else {
2071 #ifdef TARGET_X86_64
2072 if (s->aflag == 2) {
2073 gen_op_movq_A0_im(disp);
2074 } else
2075 #endif
2076 {
2077 gen_op_movl_A0_im(disp);
2078 }
2079 }
2080 /* index == 4 means no index */
2081 if (havesib && (index != 4)) {
2082 #ifdef TARGET_X86_64
2083 if (s->aflag == 2) {
2084 gen_op_addq_A0_reg_sN(scale, index);
2085 } else
2086 #endif
2087 {
2088 gen_op_addl_A0_reg_sN(scale, index);
2089 }
2090 }
2091 if (must_add_seg) {
2092 if (override < 0) {
2093 if (base == R_EBP || base == R_ESP)
2094 override = R_SS;
2095 else
2096 override = R_DS;
2097 }
2098 #ifdef TARGET_X86_64
2099 if (s->aflag == 2) {
2100 gen_op_addq_A0_seg(override);
2101 } else
2102 #endif
2103 {
2104 gen_op_addl_A0_seg(s, override);
2105 }
2106 }
2107 } else {
2108 switch (mod) {
2109 case 0:
2110 if (rm == 6) {
2111 disp = lduw_code(s->pc);
2112 s->pc += 2;
2113 gen_op_movl_A0_im(disp);
2114 rm = 0; /* avoid SS override */
2115 goto no_rm;
2116 } else {
2117 disp = 0;
2118 }
2119 break;
2120 case 1:
2121 disp = (int8_t)ldub_code(s->pc++);
2122 break;
2123 default:
2124 case 2:
2125 disp = lduw_code(s->pc);
2126 s->pc += 2;
2127 break;
2128 }
2129 switch(rm) {
2130 case 0:
2131 gen_op_movl_A0_reg(R_EBX);
2132 gen_op_addl_A0_reg_sN(0, R_ESI);
2133 break;
2134 case 1:
2135 gen_op_movl_A0_reg(R_EBX);
2136 gen_op_addl_A0_reg_sN(0, R_EDI);
2137 break;
2138 case 2:
2139 gen_op_movl_A0_reg(R_EBP);
2140 gen_op_addl_A0_reg_sN(0, R_ESI);
2141 break;
2142 case 3:
2143 gen_op_movl_A0_reg(R_EBP);
2144 gen_op_addl_A0_reg_sN(0, R_EDI);
2145 break;
2146 case 4:
2147 gen_op_movl_A0_reg(R_ESI);
2148 break;
2149 case 5:
2150 gen_op_movl_A0_reg(R_EDI);
2151 break;
2152 case 6:
2153 gen_op_movl_A0_reg(R_EBP);
2154 break;
2155 default:
2156 case 7:
2157 gen_op_movl_A0_reg(R_EBX);
2158 break;
2159 }
2160 if (disp != 0)
2161 gen_op_addl_A0_im(disp);
2162 gen_op_andl_A0_ffff();
2163 no_rm:
2164 if (must_add_seg) {
2165 if (override < 0) {
2166 if (rm == 2 || rm == 3 || rm == 6)
2167 override = R_SS;
2168 else
2169 override = R_DS;
2170 }
2171 gen_op_addl_A0_seg(s, override);
2172 }
2173 }
2174
2175 opreg = OR_A0;
2176 disp = 0;
2177 *reg_ptr = opreg;
2178 *offset_ptr = disp;
2179 }
2180
2181 static void gen_nop_modrm(DisasContext *s, int modrm)
2182 {
2183 int mod, rm, base, code;
2184
2185 mod = (modrm >> 6) & 3;
2186 if (mod == 3)
2187 return;
2188 rm = modrm & 7;
2189
2190 if (s->aflag) {
2191
2192 base = rm;
2193
2194 if (base == 4) {
2195 code = ldub_code(s->pc++);
2196 base = (code & 7);
2197 }
2198
2199 switch (mod) {
2200 case 0:
2201 if (base == 5) {
2202 s->pc += 4;
2203 }
2204 break;
2205 case 1:
2206 s->pc++;
2207 break;
2208 default:
2209 case 2:
2210 s->pc += 4;
2211 break;
2212 }
2213 } else {
2214 switch (mod) {
2215 case 0:
2216 if (rm == 6) {
2217 s->pc += 2;
2218 }
2219 break;
2220 case 1:
2221 s->pc++;
2222 break;
2223 default:
2224 case 2:
2225 s->pc += 2;
2226 break;
2227 }
2228 }
2229 }
2230
2231 /* used for LEA and MOV AX, mem */
2232 static void gen_add_A0_ds_seg(DisasContext *s)
2233 {
2234 int override, must_add_seg;
2235 must_add_seg = s->addseg;
2236 override = R_DS;
2237 if (s->override >= 0) {
2238 override = s->override;
2239 must_add_seg = 1;
2240 }
2241 if (must_add_seg) {
2242 #ifdef TARGET_X86_64
2243 if (CODE64(s)) {
2244 gen_op_addq_A0_seg(override);
2245 } else
2246 #endif
2247 {
2248 gen_op_addl_A0_seg(s, override);
2249 }
2250 }
2251 }
2252
2253 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2254 OR_TMP0 */
2255 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2256 {
2257 int mod, rm, opreg, disp;
2258
2259 mod = (modrm >> 6) & 3;
2260 rm = (modrm & 7) | REX_B(s);
2261 if (mod == 3) {
2262 if (is_store) {
2263 if (reg != OR_TMP0)
2264 gen_op_mov_TN_reg(ot, 0, reg);
2265 gen_op_mov_reg_T0(ot, rm);
2266 } else {
2267 gen_op_mov_TN_reg(ot, 0, rm);
2268 if (reg != OR_TMP0)
2269 gen_op_mov_reg_T0(ot, reg);
2270 }
2271 } else {
2272 gen_lea_modrm(s, modrm, &opreg, &disp);
2273 if (is_store) {
2274 if (reg != OR_TMP0)
2275 gen_op_mov_TN_reg(ot, 0, reg);
2276 gen_op_st_T0_A0(ot + s->mem_index);
2277 } else {
2278 gen_op_ld_T0_A0(ot + s->mem_index);
2279 if (reg != OR_TMP0)
2280 gen_op_mov_reg_T0(ot, reg);
2281 }
2282 }
2283 }
2284
2285 static inline uint32_t insn_get(DisasContext *s, int ot)
2286 {
2287 uint32_t ret;
2288
2289 switch(ot) {
2290 case OT_BYTE:
2291 ret = ldub_code(s->pc);
2292 s->pc++;
2293 break;
2294 case OT_WORD:
2295 ret = lduw_code(s->pc);
2296 s->pc += 2;
2297 break;
2298 default:
2299 case OT_LONG:
2300 ret = ldl_code(s->pc);
2301 s->pc += 4;
2302 break;
2303 }
2304 return ret;
2305 }
2306
2307 static inline int insn_const_size(unsigned int ot)
2308 {
2309 if (ot <= OT_LONG)
2310 return 1 << ot;
2311 else
2312 return 4;
2313 }
2314
2315 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2316 {
2317 TranslationBlock *tb;
2318 target_ulong pc;
2319
2320 pc = s->cs_base + eip;
2321 tb = s->tb;
2322 /* NOTE: we handle the case where the TB spans two pages here */
2323 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2324 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2325 /* jump to same page: we can use a direct jump */
2326 tcg_gen_goto_tb(tb_num);
2327 gen_jmp_im(eip);
2328 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2329 } else {
2330 /* jump to another page: currently not optimized */
2331 gen_jmp_im(eip);
2332 gen_eob(s);
2333 }
2334 }
2335
2336 static inline void gen_jcc(DisasContext *s, int b,
2337 target_ulong val, target_ulong next_eip)
2338 {
2339 int l1, l2, cc_op;
2340
2341 cc_op = s->cc_op;
2342 gen_update_cc_op(s);
2343 if (s->jmp_opt) {
2344 l1 = gen_new_label();
2345 gen_jcc1(s, cc_op, b, l1);
2346
2347 gen_goto_tb(s, 0, next_eip);
2348
2349 gen_set_label(l1);
2350 gen_goto_tb(s, 1, val);
2351 s->is_jmp = DISAS_TB_JUMP;
2352 } else {
2353
2354 l1 = gen_new_label();
2355 l2 = gen_new_label();
2356 gen_jcc1(s, cc_op, b, l1);
2357
2358 gen_jmp_im(next_eip);
2359 tcg_gen_br(l2);
2360
2361 gen_set_label(l1);
2362 gen_jmp_im(val);
2363 gen_set_label(l2);
2364 gen_eob(s);
2365 }
2366 }
2367
2368 static void gen_setcc(DisasContext *s, int b)
2369 {
2370 int inv, jcc_op, l1;
2371 TCGv t0;
2372
2373 if (is_fast_jcc_case(s, b)) {
2374 /* nominal case: we use a jump */
2375 /* XXX: make it faster by adding new instructions in TCG */
2376 t0 = tcg_temp_local_new();
2377 tcg_gen_movi_tl(t0, 0);
2378 l1 = gen_new_label();
2379 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2380 tcg_gen_movi_tl(t0, 1);
2381 gen_set_label(l1);
2382 tcg_gen_mov_tl(cpu_T[0], t0);
2383 tcg_temp_free(t0);
2384 } else {
2385 /* slow case: it is more efficient not to generate a jump,
2386 although it is questionnable whether this optimization is
2387 worth to */
2388 inv = b & 1;
2389 jcc_op = (b >> 1) & 7;
2390 gen_setcc_slow_T0(s, jcc_op);
2391 if (inv) {
2392 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2393 }
2394 }
2395 }
2396
2397 static inline void gen_op_movl_T0_seg(int seg_reg)
2398 {
2399 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2400 offsetof(CPUX86State,segs[seg_reg].selector));
2401 }
2402
2403 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2404 {
2405 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2406 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2407 offsetof(CPUX86State,segs[seg_reg].selector));
2408 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2409 tcg_gen_st_tl(cpu_T[0], cpu_env,
2410 offsetof(CPUX86State,segs[seg_reg].base));
2411 }
2412
2413 /* move T0 to seg_reg and compute if the CPU state may change. Never
2414 call this function with seg_reg == R_CS */
2415 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2416 {
2417 if (s->pe && !s->vm86) {
2418 /* XXX: optimize by finding processor state dynamically */
2419 if (s->cc_op != CC_OP_DYNAMIC)
2420 gen_op_set_cc_op(s->cc_op);
2421 gen_jmp_im(cur_eip);
2422 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2423 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2424 /* abort translation because the addseg value may change or
2425 because ss32 may change. For R_SS, translation must always
2426 stop as a special handling must be done to disable hardware
2427 interrupts for the next instruction */
2428 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2429 s->is_jmp = DISAS_TB_JUMP;
2430 } else {
2431 gen_op_movl_seg_T0_vm(seg_reg);
2432 if (seg_reg == R_SS)
2433 s->is_jmp = DISAS_TB_JUMP;
2434 }
2435 }
2436
2437 static inline int svm_is_rep(int prefixes)
2438 {
2439 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2440 }
2441
2442 static inline void
2443 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2444 uint32_t type, uint64_t param)
2445 {
2446 /* no SVM activated; fast case */
2447 if (likely(!(s->flags & HF_SVMI_MASK)))
2448 return;
2449 if (s->cc_op != CC_OP_DYNAMIC)
2450 gen_op_set_cc_op(s->cc_op);
2451 gen_jmp_im(pc_start - s->cs_base);
2452 gen_helper_svm_check_intercept_param(tcg_const_i32(type),
2453 tcg_const_i64(param));
2454 }
2455
2456 static inline void
2457 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2458 {
2459 gen_svm_check_intercept_param(s, pc_start, type, 0);
2460 }
2461
2462 static inline void gen_stack_update(DisasContext *s, int addend)
2463 {
2464 #ifdef TARGET_X86_64
2465 if (CODE64(s)) {
2466 gen_op_add_reg_im(2, R_ESP, addend);
2467 } else
2468 #endif
2469 if (s->ss32) {
2470 gen_op_add_reg_im(1, R_ESP, addend);
2471 } else {
2472 gen_op_add_reg_im(0, R_ESP, addend);
2473 }
2474 }
2475
2476 /* generate a push. It depends on ss32, addseg and dflag */
2477 static void gen_push_T0(DisasContext *s)
2478 {
2479 #ifdef TARGET_X86_64
2480 if (CODE64(s)) {
2481 gen_op_movq_A0_reg(R_ESP);
2482 if (s->dflag) {
2483 gen_op_addq_A0_im(-8);
2484 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2485 } else {
2486 gen_op_addq_A0_im(-2);
2487 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2488 }
2489 gen_op_mov_reg_A0(2, R_ESP);
2490 } else
2491 #endif
2492 {
2493 gen_op_movl_A0_reg(R_ESP);
2494 if (!s->dflag)
2495 gen_op_addl_A0_im(-2);
2496 else
2497 gen_op_addl_A0_im(-4);
2498 if (s->ss32) {
2499 if (s->addseg) {
2500 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2501 gen_op_addl_A0_seg(s, R_SS);
2502 }
2503 } else {
2504 gen_op_andl_A0_ffff();
2505 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2506 gen_op_addl_A0_seg(s, R_SS);
2507 }
2508 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2509 if (s->ss32 && !s->addseg)
2510 gen_op_mov_reg_A0(1, R_ESP);
2511 else
2512 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2513 }
2514 }
2515
2516 /* generate a push. It depends on ss32, addseg and dflag */
2517 /* slower version for T1, only used for call Ev */
2518 static void gen_push_T1(DisasContext *s)
2519 {
2520 #ifdef TARGET_X86_64
2521 if (CODE64(s)) {
2522 gen_op_movq_A0_reg(R_ESP);
2523 if (s->dflag) {
2524 gen_op_addq_A0_im(-8);
2525 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2526 } else {
2527 gen_op_addq_A0_im(-2);
2528 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2529 }
2530 gen_op_mov_reg_A0(2, R_ESP);
2531 } else
2532 #endif
2533 {
2534 gen_op_movl_A0_reg(R_ESP);
2535 if (!s->dflag)
2536 gen_op_addl_A0_im(-2);
2537 else
2538 gen_op_addl_A0_im(-4);
2539 if (s->ss32) {
2540 if (s->addseg) {
2541 gen_op_addl_A0_seg(s, R_SS);
2542 }
2543 } else {
2544 gen_op_andl_A0_ffff();
2545 gen_op_addl_A0_seg(s, R_SS);
2546 }
2547 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2548
2549 if (s->ss32 && !s->addseg)
2550 gen_op_mov_reg_A0(1, R_ESP);
2551 else
2552 gen_stack_update(s, (-2) << s->dflag);
2553 }
2554 }
2555
2556 /* two step pop is necessary for precise exceptions */
2557 static void gen_pop_T0(DisasContext *s)
2558 {
2559 #ifdef TARGET_X86_64
2560 if (CODE64(s)) {
2561 gen_op_movq_A0_reg(R_ESP);
2562 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2563 } else
2564 #endif
2565 {
2566 gen_op_movl_A0_reg(R_ESP);
2567 if (s->ss32) {
2568 if (s->addseg)
2569 gen_op_addl_A0_seg(s, R_SS);
2570 } else {
2571 gen_op_andl_A0_ffff();
2572 gen_op_addl_A0_seg(s, R_SS);
2573 }
2574 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2575 }
2576 }
2577
2578 static void gen_pop_update(DisasContext *s)
2579 {
2580 #ifdef TARGET_X86_64
2581 if (CODE64(s) && s->dflag) {
2582 gen_stack_update(s, 8);
2583 } else
2584 #endif
2585 {
2586 gen_stack_update(s, 2 << s->dflag);
2587 }
2588 }
2589
2590 static void gen_stack_A0(DisasContext *s)
2591 {
2592 gen_op_movl_A0_reg(R_ESP);
2593 if (!s->ss32)
2594 gen_op_andl_A0_ffff();
2595 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2596 if (s->addseg)
2597 gen_op_addl_A0_seg(s, R_SS);
2598 }
2599
2600 /* NOTE: wrap around in 16 bit not fully handled */
2601 static void gen_pusha(DisasContext *s)
2602 {
2603 int i;
2604 gen_op_movl_A0_reg(R_ESP);
2605 gen_op_addl_A0_im(-16 << s->dflag);
2606 if (!s->ss32)
2607 gen_op_andl_A0_ffff();
2608 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2609 if (s->addseg)
2610 gen_op_addl_A0_seg(s, R_SS);
2611 for(i = 0;i < 8; i++) {
2612 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2613 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2614 gen_op_addl_A0_im(2 << s->dflag);
2615 }
2616 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2617 }
2618
2619 /* NOTE: wrap around in 16 bit not fully handled */
2620 static void gen_popa(DisasContext *s)
2621 {
2622 int i;
2623 gen_op_movl_A0_reg(R_ESP);
2624 if (!s->ss32)
2625 gen_op_andl_A0_ffff();
2626 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2627 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2628 if (s->addseg)
2629 gen_op_addl_A0_seg(s, R_SS);
2630 for(i = 0;i < 8; i++) {
2631 /* ESP is not reloaded */
2632 if (i != 3) {
2633 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2634 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2635 }
2636 gen_op_addl_A0_im(2 << s->dflag);
2637 }
2638 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2639 }
2640
2641 static void gen_enter(DisasContext *s, int esp_addend, int level)
2642 {
2643 int ot, opsize;
2644
2645 level &= 0x1f;
2646 #ifdef TARGET_X86_64
2647 if (CODE64(s)) {
2648 ot = s->dflag ? OT_QUAD : OT_WORD;
2649 opsize = 1 << ot;
2650
2651 gen_op_movl_A0_reg(R_ESP);
2652 gen_op_addq_A0_im(-opsize);
2653 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2654
2655 /* push bp */
2656 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2657 gen_op_st_T0_A0(ot + s->mem_index);
2658 if (level) {
2659 /* XXX: must save state */
2660 gen_helper_enter64_level(tcg_const_i32(level),
2661 tcg_const_i32((ot == OT_QUAD)),
2662 cpu_T[1]);
2663 }
2664 gen_op_mov_reg_T1(ot, R_EBP);
2665 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2666 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2667 } else
2668 #endif
2669 {
2670 ot = s->dflag + OT_WORD;
2671 opsize = 2 << s->dflag;
2672
2673 gen_op_movl_A0_reg(R_ESP);
2674 gen_op_addl_A0_im(-opsize);
2675 if (!s->ss32)
2676 gen_op_andl_A0_ffff();
2677 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2678 if (s->addseg)
2679 gen_op_addl_A0_seg(s, R_SS);
2680 /* push bp */
2681 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2682 gen_op_st_T0_A0(ot + s->mem_index);
2683 if (level) {
2684 /* XXX: must save state */
2685 gen_helper_enter_level(tcg_const_i32(level),
2686 tcg_const_i32(s->dflag),
2687 cpu_T[1]);
2688 }
2689 gen_op_mov_reg_T1(ot, R_EBP);
2690 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2691 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2692 }
2693 }
2694
2695 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2696 {
2697 if (s->cc_op != CC_OP_DYNAMIC)
2698 gen_op_set_cc_op(s->cc_op);
2699 gen_jmp_im(cur_eip);
2700 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2701 s->is_jmp = DISAS_TB_JUMP;
2702 }
2703
2704 /* an interrupt is different from an exception because of the
2705 privilege checks */
2706 static void gen_interrupt(DisasContext *s, int intno,
2707 target_ulong cur_eip, target_ulong next_eip)
2708 {
2709 if (s->cc_op != CC_OP_DYNAMIC)
2710 gen_op_set_cc_op(s->cc_op);
2711 gen_jmp_im(cur_eip);
2712 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2713 tcg_const_i32(next_eip - cur_eip));
2714 s->is_jmp = DISAS_TB_JUMP;
2715 }
2716
2717 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2718 {
2719 if (s->cc_op != CC_OP_DYNAMIC)
2720 gen_op_set_cc_op(s->cc_op);
2721 gen_jmp_im(cur_eip);
2722 gen_helper_debug();
2723 s->is_jmp = DISAS_TB_JUMP;
2724 }
2725
2726 /* generate a generic end of block. Trace exception is also generated
2727 if needed */
2728 static void gen_eob(DisasContext *s)
2729 {
2730 if (s->cc_op != CC_OP_DYNAMIC)
2731 gen_op_set_cc_op(s->cc_op);
2732 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2733 gen_helper_reset_inhibit_irq();
2734 }
2735 if (s->tb->flags & HF_RF_MASK) {
2736 gen_helper_reset_rf();
2737 }
2738 if (s->singlestep_enabled) {
2739 gen_helper_debug();
2740 } else if (s->tf) {
2741 gen_helper_single_step();
2742 } else {
2743 tcg_gen_exit_tb(0);
2744 }
2745 s->is_jmp = DISAS_TB_JUMP;
2746 }
2747
2748 /* generate a jump to eip. No segment change must happen before as a
2749 direct call to the next block may occur */
2750 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2751 {
2752 if (s->jmp_opt) {
2753 gen_update_cc_op(s);
2754 gen_goto_tb(s, tb_num, eip);
2755 s->is_jmp = DISAS_TB_JUMP;
2756 } else {
2757 gen_jmp_im(eip);
2758 gen_eob(s);
2759 }
2760 }
2761
2762 static void gen_jmp(DisasContext *s, target_ulong eip)
2763 {
2764 gen_jmp_tb(s, eip, 0);
2765 }
2766
2767 static inline void gen_ldq_env_A0(int idx, int offset)
2768 {
2769 int mem_index = (idx >> 2) - 1;
2770 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2771 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2772 }
2773
2774 static inline void gen_stq_env_A0(int idx, int offset)
2775 {
2776 int mem_index = (idx >> 2) - 1;
2777 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2778 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2779 }
2780
2781 static inline void gen_ldo_env_A0(int idx, int offset)
2782 {
2783 int mem_index = (idx >> 2) - 1;
2784 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2785 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2786 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2787 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2788 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2789 }
2790
2791 static inline void gen_sto_env_A0(int idx, int offset)
2792 {
2793 int mem_index = (idx >> 2) - 1;
2794 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2795 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2796 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2797 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2798 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2799 }
2800
2801 static inline void gen_op_movo(int d_offset, int s_offset)
2802 {
2803 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2804 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2805 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2806 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2807 }
2808
2809 static inline void gen_op_movq(int d_offset, int s_offset)
2810 {
2811 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2812 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2813 }
2814
2815 static inline void gen_op_movl(int d_offset, int s_offset)
2816 {
2817 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2818 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2819 }
2820
2821 static inline void gen_op_movq_env_0(int d_offset)
2822 {
2823 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2824 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2825 }
2826
2827 typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
2828 typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
2829 typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val);
2830 typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val);
2831 typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b);
2832 typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2833 TCGv_i32 val);
2834 typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2835 typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2836 TCGv val);
2837
2838 #define SSE_SPECIAL ((void *)1)
2839 #define SSE_DUMMY ((void *)2)
2840
2841 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2842 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2843 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2844
2845 static const SSEFunc_0_epp sse_op_table1[256][4] = {
2846 /* 3DNow! extensions */
2847 [0x0e] = { SSE_DUMMY }, /* femms */
2848 [0x0f] = { SSE_DUMMY }, /* pf... */
2849 /* pure SSE operations */
2850 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2851 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2852 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2853 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2854 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2855 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2856 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2857 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2858
2859 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2860 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2861 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2862 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2863 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2864 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2865 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2866 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2867 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2868 [0x51] = SSE_FOP(sqrt),
2869 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2870 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2871 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2872 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2873 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2874 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2875 [0x58] = SSE_FOP(add),
2876 [0x59] = SSE_FOP(mul),
2877 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2878 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2879 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2880 [0x5c] = SSE_FOP(sub),
2881 [0x5d] = SSE_FOP(min),
2882 [0x5e] = SSE_FOP(div),
2883 [0x5f] = SSE_FOP(max),
2884
2885 [0xc2] = SSE_FOP(cmpeq),
2886 [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps,
2887 (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
2888
2889 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2890 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2891
2892 /* MMX ops and their SSE extensions */
2893 [0x60] = MMX_OP2(punpcklbw),
2894 [0x61] = MMX_OP2(punpcklwd),
2895 [0x62] = MMX_OP2(punpckldq),
2896 [0x63] = MMX_OP2(packsswb),
2897 [0x64] = MMX_OP2(pcmpgtb),
2898 [0x65] = MMX_OP2(pcmpgtw),
2899 [0x66] = MMX_OP2(pcmpgtl),
2900 [0x67] = MMX_OP2(packuswb),
2901 [0x68] = MMX_OP2(punpckhbw),
2902 [0x69] = MMX_OP2(punpckhwd),
2903 [0x6a] = MMX_OP2(punpckhdq),
2904 [0x6b] = MMX_OP2(packssdw),
2905 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2906 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2907 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2908 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2909 [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx,
2910 (SSEFunc_0_epp)gen_helper_pshufd_xmm,
2911 (SSEFunc_0_epp)gen_helper_pshufhw_xmm,
2912 (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */
2913 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2914 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2915 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2916 [0x74] = MMX_OP2(pcmpeqb),
2917 [0x75] = MMX_OP2(pcmpeqw),
2918 [0x76] = MMX_OP2(pcmpeql),
2919 [0x77] = { SSE_DUMMY }, /* emms */
2920 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2921 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2922 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2923 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2924 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2925 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2926 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2927 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2928 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2929 [0xd1] = MMX_OP2(psrlw),
2930 [0xd2] = MMX_OP2(psrld),
2931 [0xd3] = MMX_OP2(psrlq),
2932 [0xd4] = MMX_OP2(paddq),
2933 [0xd5] = MMX_OP2(pmullw),
2934 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2935 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2936 [0xd8] = MMX_OP2(psubusb),
2937 [0xd9] = MMX_OP2(psubusw),
2938 [0xda] = MMX_OP2(pminub),
2939 [0xdb] = MMX_OP2(pand),
2940 [0xdc] = MMX_OP2(paddusb),
2941 [0xdd] = MMX_OP2(paddusw),
2942 [0xde] = MMX_OP2(pmaxub),
2943 [0xdf] = MMX_OP2(pandn),
2944 [0xe0] = MMX_OP2(pavgb),
2945 [0xe1] = MMX_OP2(psraw),
2946 [0xe2] = MMX_OP2(psrad),
2947 [0xe3] = MMX_OP2(pavgw),
2948 [0xe4] = MMX_OP2(pmulhuw),
2949 [0xe5] = MMX_OP2(pmulhw),
2950 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2951 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2952 [0xe8] = MMX_OP2(psubsb),
2953 [0xe9] = MMX_OP2(psubsw),
2954 [0xea] = MMX_OP2(pminsw),
2955 [0xeb] = MMX_OP2(por),
2956 [0xec] = MMX_OP2(paddsb),
2957 [0xed] = MMX_OP2(paddsw),
2958 [0xee] = MMX_OP2(pmaxsw),
2959 [0xef] = MMX_OP2(pxor),
2960 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2961 [0xf1] = MMX_OP2(psllw),
2962 [0xf2] = MMX_OP2(pslld),
2963 [0xf3] = MMX_OP2(psllq),
2964 [0xf4] = MMX_OP2(pmuludq),
2965 [0xf5] = MMX_OP2(pmaddwd),
2966 [0xf6] = MMX_OP2(psadbw),
2967 [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx,
2968 (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */
2969 [0xf8] = MMX_OP2(psubb),
2970 [0xf9] = MMX_OP2(psubw),
2971 [0xfa] = MMX_OP2(psubl),
2972 [0xfb] = MMX_OP2(psubq),
2973 [0xfc] = MMX_OP2(paddb),
2974 [0xfd] = MMX_OP2(paddw),
2975 [0xfe] = MMX_OP2(paddl),
2976 };
2977
2978 static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
2979 [0 + 2] = MMX_OP2(psrlw),
2980 [0 + 4] = MMX_OP2(psraw),
2981 [0 + 6] = MMX_OP2(psllw),
2982 [8 + 2] = MMX_OP2(psrld),
2983 [8 + 4] = MMX_OP2(psrad),
2984 [8 + 6] = MMX_OP2(pslld),
2985 [16 + 2] = MMX_OP2(psrlq),
2986 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
2987 [16 + 6] = MMX_OP2(psllq),
2988 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
2989 };
2990
2991 static const SSEFunc_0_epi sse_op_table3ai[] = {
2992 gen_helper_cvtsi2ss,
2993 gen_helper_cvtsi2sd
2994 };
2995
2996 #ifdef TARGET_X86_64
2997 static const SSEFunc_0_epl sse_op_table3aq[] = {
2998 gen_helper_cvtsq2ss,
2999 gen_helper_cvtsq2sd
3000 };
3001 #endif
3002
3003 static const SSEFunc_i_ep sse_op_table3bi[] = {
3004 gen_helper_cvttss2si,
3005 gen_helper_cvtss2si,
3006 gen_helper_cvttsd2si,
3007 gen_helper_cvtsd2si
3008 };
3009
3010 #ifdef TARGET_X86_64
3011 static const SSEFunc_l_ep sse_op_table3bq[] = {
3012 gen_helper_cvttss2sq,
3013 gen_helper_cvtss2sq,
3014 gen_helper_cvttsd2sq,
3015 gen_helper_cvtsd2sq
3016 };
3017 #endif
3018
3019 static const SSEFunc_0_epp sse_op_table4[8][4] = {
3020 SSE_FOP(cmpeq),
3021 SSE_FOP(cmplt),
3022 SSE_FOP(cmple),
3023 SSE_FOP(cmpunord),
3024 SSE_FOP(cmpneq),
3025 SSE_FOP(cmpnlt),
3026 SSE_FOP(cmpnle),
3027 SSE_FOP(cmpord),
3028 };
3029
3030 static const SSEFunc_0_epp sse_op_table5[256] = {
3031 [0x0c] = gen_helper_pi2fw,
3032 [0x0d] = gen_helper_pi2fd,
3033 [0x1c] = gen_helper_pf2iw,
3034 [0x1d] = gen_helper_pf2id,
3035 [0x8a] = gen_helper_pfnacc,
3036 [0x8e] = gen_helper_pfpnacc,
3037 [0x90] = gen_helper_pfcmpge,
3038 [0x94] = gen_helper_pfmin,
3039 [0x96] = gen_helper_pfrcp,
3040 [0x97] = gen_helper_pfrsqrt,
3041 [0x9a] = gen_helper_pfsub,
3042 [0x9e] = gen_helper_pfadd,
3043 [0xa0] = gen_helper_pfcmpgt,
3044 [0xa4] = gen_helper_pfmax,
3045 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3046 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3047 [0xaa] = gen_helper_pfsubr,
3048 [0xae] = gen_helper_pfacc,
3049 [0xb0] = gen_helper_pfcmpeq,
3050 [0xb4] = gen_helper_pfmul,
3051 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3052 [0xb7] = gen_helper_pmulhrw_mmx,
3053 [0xbb] = gen_helper_pswapd,
3054 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3055 };
3056
3057 struct SSEOpHelper_epp {
3058 SSEFunc_0_epp op[2];
3059 uint32_t ext_mask;
3060 };
3061
3062 struct SSEOpHelper_eppi {
3063 SSEFunc_0_eppi op[2];
3064 uint32_t ext_mask;
3065 };
3066
3067 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3068 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3069 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3070 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3071
3072 static const struct SSEOpHelper_epp sse_op_table6[256] = {
3073 [0x00] = SSSE3_OP(pshufb),
3074 [0x01] = SSSE3_OP(phaddw),
3075 [0x02] = SSSE3_OP(phaddd),
3076 [0x03] = SSSE3_OP(phaddsw),
3077 [0x04] = SSSE3_OP(pmaddubsw),
3078 [0x05] = SSSE3_OP(phsubw),
3079 [0x06] = SSSE3_OP(phsubd),
3080 [0x07] = SSSE3_OP(phsubsw),
3081 [0x08] = SSSE3_OP(psignb),
3082 [0x09] = SSSE3_OP(psignw),
3083 [0x0a] = SSSE3_OP(psignd),
3084 [0x0b] = SSSE3_OP(pmulhrsw),
3085 [0x10] = SSE41_OP(pblendvb),
3086 [0x14] = SSE41_OP(blendvps),
3087 [0x15] = SSE41_OP(blendvpd),
3088 [0x17] = SSE41_OP(ptest),
3089 [0x1c] = SSSE3_OP(pabsb),
3090 [0x1d] = SSSE3_OP(pabsw),
3091 [0x1e] = SSSE3_OP(pabsd),
3092 [0x20] = SSE41_OP(pmovsxbw),
3093 [0x21] = SSE41_OP(pmovsxbd),
3094 [0x22] = SSE41_OP(pmovsxbq),
3095 [0x23] = SSE41_OP(pmovsxwd),
3096 [0x24] = SSE41_OP(pmovsxwq),
3097 [0x25] = SSE41_OP(pmovsxdq),
3098 [0x28] = SSE41_OP(pmuldq),
3099 [0x29] = SSE41_OP(pcmpeqq),
3100 [0x2a] = SSE41_SPECIAL, /* movntqda */
3101 [0x2b] = SSE41_OP(packusdw),
3102 [0x30] = SSE41_OP(pmovzxbw),
3103 [0x31] = SSE41_OP(pmovzxbd),
3104 [0x32] = SSE41_OP(pmovzxbq),
3105 [0x33] = SSE41_OP(pmovzxwd),
3106 [0x34] = SSE41_OP(pmovzxwq),
3107 [0x35] = SSE41_OP(pmovzxdq),
3108 [0x37] = SSE42_OP(pcmpgtq),
3109 [0x38] = SSE41_OP(pminsb),
3110 [0x39] = SSE41_OP(pminsd),
3111 [0x3a] = SSE41_OP(pminuw),
3112 [0x3b] = SSE41_OP(pminud),
3113 [0x3c] = SSE41_OP(pmaxsb),
3114 [0x3d] = SSE41_OP(pmaxsd),
3115 [0x3e] = SSE41_OP(pmaxuw),
3116 [0x3f] = SSE41_OP(pmaxud),
3117 [0x40] = SSE41_OP(pmulld),
3118 [0x41] = SSE41_OP(phminposuw),
3119 };
3120
3121 static const struct SSEOpHelper_eppi sse_op_table7[256] = {
3122 [0x08] = SSE41_OP(roundps),
3123 [0x09] = SSE41_OP(roundpd),
3124 [0x0a] = SSE41_OP(roundss),
3125 [0x0b] = SSE41_OP(roundsd),
3126 [0x0c] = SSE41_OP(blendps),
3127 [0x0d] = SSE41_OP(blendpd),
3128 [0x0e] = SSE41_OP(pblendw),
3129 [0x0f] = SSSE3_OP(palignr),
3130 [0x14] = SSE41_SPECIAL, /* pextrb */
3131 [0x15] = SSE41_SPECIAL, /* pextrw */
3132 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3133 [0x17] = SSE41_SPECIAL, /* extractps */
3134 [0x20] = SSE41_SPECIAL, /* pinsrb */
3135 [0x21] = SSE41_SPECIAL, /* insertps */
3136 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3137 [0x40] = SSE41_OP(dpps),
3138 [0x41] = SSE41_OP(dppd),
3139 [0x42] = SSE41_OP(mpsadbw),
3140 [0x60] = SSE42_OP(pcmpestrm),
3141 [0x61] = SSE42_OP(pcmpestri),
3142 [0x62] = SSE42_OP(pcmpistrm),
3143 [0x63] = SSE42_OP(pcmpistri),
3144 };
3145
3146 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3147 {
3148 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3149 int modrm, mod, rm, reg, reg_addr, offset_addr;
3150 SSEFunc_0_epp sse_fn_epp;
3151 SSEFunc_0_eppi sse_fn_eppi;
3152 SSEFunc_0_ppi sse_fn_ppi;
3153 SSEFunc_0_eppt sse_fn_eppt;
3154
3155 b &= 0xff;
3156 if (s->prefix & PREFIX_DATA)
3157 b1 = 1;
3158 else if (s->prefix & PREFIX_REPZ)
3159 b1 = 2;
3160 else if (s->prefix & PREFIX_REPNZ)
3161 b1 = 3;
3162 else
3163 b1 = 0;
3164 sse_fn_epp = sse_op_table1[b][b1];
3165 if (!sse_fn_epp) {
3166 goto illegal_op;
3167 }
3168 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3169 is_xmm = 1;
3170 } else {
3171 if (b1 == 0) {
3172 /* MMX case */
3173 is_xmm = 0;
3174 } else {
3175 is_xmm = 1;
3176 }
3177 }
3178 /* simple MMX/SSE operation */
3179 if (s->flags & HF_TS_MASK) {
3180 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3181 return;
3182 }
3183 if (s->flags & HF_EM_MASK) {
3184 illegal_op:
3185 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3186 return;
3187 }
3188 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3189 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3190 goto illegal_op;
3191 if (b == 0x0e) {
3192 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3193 goto illegal_op;
3194 /* femms */
3195 gen_helper_emms(cpu_env);
3196 return;
3197 }
3198 if (b == 0x77) {
3199 /* emms */
3200 gen_helper_emms(cpu_env);
3201 return;
3202 }
3203 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3204 the static cpu state) */
3205 if (!is_xmm) {
3206 gen_helper_enter_mmx(cpu_env);
3207 }
3208
3209 modrm = ldub_code(s->pc++);
3210 reg = ((modrm >> 3) & 7);
3211 if (is_xmm)
3212 reg |= rex_r;
3213 mod = (modrm >> 6) & 3;
3214 if (sse_fn_epp == SSE_SPECIAL) {
3215 b |= (b1 << 8);
3216 switch(b) {
3217 case 0x0e7: /* movntq */
3218 if (mod == 3)
3219 goto illegal_op;
3220 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3221 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3222 break;
3223 case 0x1e7: /* movntdq */
3224 case 0x02b: /* movntps */
3225 case 0x12b: /* movntps */
3226 if (mod == 3)
3227 goto illegal_op;
3228 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3229 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3230 break;
3231 case 0x3f0: /* lddqu */
3232 if (mod == 3)
3233 goto illegal_op;
3234 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3235 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3236 break;
3237 case 0x22b: /* movntss */
3238 case 0x32b: /* movntsd */
3239 if (mod == 3)
3240 goto illegal_op;
3241 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3242 if (b1 & 1) {
3243 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3244 xmm_regs[reg]));
3245 } else {
3246 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3247 xmm_regs[reg].XMM_L(0)));
3248 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3249 }
3250 break;
3251 case 0x6e: /* movd mm, ea */
3252 #ifdef TARGET_X86_64
3253 if (s->dflag == 2) {
3254 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3255 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3256 } else
3257 #endif
3258 {
3259 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3260 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3261 offsetof(CPUX86State,fpregs[reg].mmx));
3262 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3263 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3264 }
3265 break;
3266 case 0x16e: /* movd xmm, ea */
3267 #ifdef TARGET_X86_64
3268 if (s->dflag == 2) {
3269 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3270 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3271 offsetof(CPUX86State,xmm_regs[reg]));
3272 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3273 } else
3274 #endif
3275 {
3276 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3277 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3278 offsetof(CPUX86State,xmm_regs[reg]));
3279 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3280 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3281 }
3282 break;
3283 case 0x6f: /* movq mm, ea */
3284 if (mod != 3) {
3285 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3286 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3287 } else {
3288 rm = (modrm & 7);
3289 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3290 offsetof(CPUX86State,fpregs[rm].mmx));
3291 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3292 offsetof(CPUX86State,fpregs[reg].mmx));
3293 }
3294 break;
3295 case 0x010: /* movups */
3296 case 0x110: /* movupd */
3297 case 0x028: /* movaps */
3298 case 0x128: /* movapd */
3299 case 0x16f: /* movdqa xmm, ea */
3300 case 0x26f: /* movdqu xmm, ea */
3301 if (mod != 3) {
3302 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3303 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3304 } else {
3305 rm = (modrm & 7) | REX_B(s);
3306 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3307 offsetof(CPUX86State,xmm_regs[rm]));
3308 }
3309 break;
3310 case 0x210: /* movss xmm, ea */
3311 if (mod != 3) {
3312 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3313 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3314 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3315 gen_op_movl_T0_0();
3316 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3317 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3318 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3319 } else {
3320 rm = (modrm & 7) | REX_B(s);
3321 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3322 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3323 }
3324 break;
3325 case 0x310: /* movsd xmm, ea */
3326 if (mod != 3) {
3327 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3328 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3329 gen_op_movl_T0_0();
3330 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3331 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3332 } else {
3333 rm = (modrm & 7) | REX_B(s);
3334 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3335 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3336 }
3337 break;
3338 case 0x012: /* movlps */
3339 case 0x112: /* movlpd */
3340 if (mod != 3) {
3341 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3342 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3343 } else {
3344 /* movhlps */
3345 rm = (modrm & 7) | REX_B(s);
3346 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3347 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3348 }
3349 break;
3350 case 0x212: /* movsldup */
3351 if (mod != 3) {
3352 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3353 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3354 } else {
3355 rm = (modrm & 7) | REX_B(s);
3356 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3357 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3358 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3359 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3360 }
3361 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3362 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3363 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3364 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3365 break;
3366 case 0x312: /* movddup */
3367 if (mod != 3) {
3368 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3369 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3370 } else {
3371 rm = (modrm & 7) | REX_B(s);
3372 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3373 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3374 }
3375 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3376 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3377 break;
3378 case 0x016: /* movhps */
3379 case 0x116: /* movhpd */
3380 if (mod != 3) {
3381 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3382 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3383 } else {
3384 /* movlhps */
3385 rm = (modrm & 7) | REX_B(s);
3386 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3387 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3388 }
3389 break;
3390 case 0x216: /* movshdup */
3391 if (mod != 3) {
3392 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3393 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3394 } else {
3395 rm = (modrm & 7) | REX_B(s);
3396 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3397 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3398 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3399 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3400 }
3401 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3402 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3403 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3404 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3405 break;
3406 case 0x178:
3407 case 0x378:
3408 {
3409 int bit_index, field_length;
3410
3411 if (b1 == 1 && reg != 0)
3412 goto illegal_op;
3413 field_length = ldub_code(s->pc++) & 0x3F;
3414 bit_index = ldub_code(s->pc++) & 0x3F;
3415 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3416 offsetof(CPUX86State,xmm_regs[reg]));
3417 if (b1 == 1)
3418 gen_helper_extrq_i(cpu_env, cpu_ptr0,
3419 tcg_const_i32(bit_index),
3420 tcg_const_i32(field_length));
3421 else
3422 gen_helper_insertq_i(cpu_env, cpu_ptr0,
3423 tcg_const_i32(bit_index),
3424 tcg_const_i32(field_length));
3425 }
3426 break;
3427 case 0x7e: /* movd ea, mm */
3428 #ifdef TARGET_X86_64
3429 if (s->dflag == 2) {
3430 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3431 offsetof(CPUX86State,fpregs[reg].mmx));
3432 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3433 } else
3434 #endif
3435 {
3436 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3437 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3438 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3439 }
3440 break;
3441 case 0x17e: /* movd ea, xmm */
3442 #ifdef TARGET_X86_64
3443 if (s->dflag == 2) {
3444 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3445 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3446 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3447 } else
3448 #endif
3449 {
3450 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3451 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3452 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3453 }
3454 break;
3455 case 0x27e: /* movq xmm, ea */
3456 if (mod != 3) {
3457 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3458 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3459 } else {
3460 rm = (modrm & 7) | REX_B(s);
3461 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3462 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3463 }
3464 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3465 break;
3466 case 0x7f: /* movq ea, mm */
3467 if (mod != 3) {
3468 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3469 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3470 } else {
3471 rm = (modrm & 7);
3472 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3473 offsetof(CPUX86State,fpregs[reg].mmx));
3474 }
3475 break;
3476 case 0x011: /* movups */
3477 case 0x111: /* movupd */
3478 case 0x029: /* movaps */
3479 case 0x129: /* movapd */
3480 case 0x17f: /* movdqa ea, xmm */
3481 case 0x27f: /* movdqu ea, xmm */
3482 if (mod != 3) {
3483 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3484 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3485 } else {
3486 rm = (modrm & 7) | REX_B(s);
3487 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3488 offsetof(CPUX86State,xmm_regs[reg]));
3489 }
3490 break;
3491 case 0x211: /* movss ea, xmm */
3492 if (mod != 3) {
3493 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3494 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3495 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3496 } else {
3497 rm = (modrm & 7) | REX_B(s);
3498 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3499 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3500 }
3501 break;
3502 case 0x311: /* movsd ea, xmm */
3503 if (mod != 3) {
3504 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3505 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3506 } else {
3507 rm = (modrm & 7) | REX_B(s);
3508 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3509 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3510 }
3511 break;
3512 case 0x013: /* movlps */
3513 case 0x113: /* movlpd */
3514 if (mod != 3) {
3515 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3516 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3517 } else {
3518 goto illegal_op;
3519 }
3520 break;
3521 case 0x017: /* movhps */
3522 case 0x117: /* movhpd */
3523 if (mod != 3) {
3524 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3525 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3526 } else {
3527 goto illegal_op;
3528 }
3529 break;
3530 case 0x71: /* shift mm, im */
3531 case 0x72:
3532 case 0x73:
3533 case 0x171: /* shift xmm, im */
3534 case 0x172:
3535 case 0x173:
3536 if (b1 >= 2) {
3537 goto illegal_op;
3538 }
3539 val = ldub_code(s->pc++);
3540 if (is_xmm) {
3541 gen_op_movl_T0_im(val);
3542 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3543 gen_op_movl_T0_0();
3544 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3545 op1_offset = offsetof(CPUX86State,xmm_t0);
3546 } else {
3547 gen_op_movl_T0_im(val);
3548 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3549 gen_op_movl_T0_0();
3550 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3551 op1_offset = offsetof(CPUX86State,mmx_t0);
3552 }
3553 sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
3554 (((modrm >> 3)) & 7)][b1];
3555 if (!sse_fn_epp) {
3556 goto illegal_op;
3557 }
3558 if (is_xmm) {
3559 rm = (modrm & 7) | REX_B(s);
3560 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3561 } else {
3562 rm = (modrm & 7);
3563 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3564 }
3565 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3566 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3567 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3568 break;
3569 case 0x050: /* movmskps */
3570 rm = (modrm & 7) | REX_B(s);
3571 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3572 offsetof(CPUX86State,xmm_regs[rm]));
3573 gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3574 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3575 gen_op_mov_reg_T0(OT_LONG, reg);
3576 break;
3577 case 0x150: /* movmskpd */
3578 rm = (modrm & 7) | REX_B(s);
3579 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3580 offsetof(CPUX86State,xmm_regs[rm]));
3581 gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3582 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3583 gen_op_mov_reg_T0(OT_LONG, reg);
3584 break;
3585 case 0x02a: /* cvtpi2ps */
3586 case 0x12a: /* cvtpi2pd */
3587 gen_helper_enter_mmx(cpu_env);
3588 if (mod != 3) {
3589 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3590 op2_offset = offsetof(CPUX86State,mmx_t0);
3591 gen_ldq_env_A0(s->mem_index, op2_offset);
3592 } else {
3593 rm = (modrm & 7);
3594 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3595 }
3596 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3597 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3598 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3599 switch(b >> 8) {
3600 case 0x0:
3601 gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1);
3602 break;
3603 default:
3604 case 0x1:
3605 gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1);
3606 break;
3607 }
3608 break;
3609 case 0x22a: /* cvtsi2ss */
3610 case 0x32a: /* cvtsi2sd */
3611 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3612 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3613 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3614 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3615 if (ot == OT_LONG) {
3616 SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
3617 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3618 sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
3619 } else {
3620 #ifdef TARGET_X86_64
3621 SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
3622 sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]);
3623 #else
3624 goto illegal_op;
3625 #endif
3626 }
3627 break;
3628 case 0x02c: /* cvttps2pi */
3629 case 0x12c: /* cvttpd2pi */
3630 case 0x02d: /* cvtps2pi */
3631 case 0x12d: /* cvtpd2pi */
3632 gen_helper_enter_mmx(cpu_env);
3633 if (mod != 3) {
3634 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3635 op2_offset = offsetof(CPUX86State,xmm_t0);
3636 gen_ldo_env_A0(s->mem_index, op2_offset);
3637 } else {
3638 rm = (modrm & 7) | REX_B(s);
3639 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3640 }
3641 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3642 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3643 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3644 switch(b) {
3645 case 0x02c:
3646 gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3647 break;
3648 case 0x12c:
3649 gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3650 break;
3651 case 0x02d:
3652 gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3653 break;
3654 case 0x12d:
3655 gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3656 break;
3657 }
3658 break;
3659 case 0x22c: /* cvttss2si */
3660 case 0x32c: /* cvttsd2si */
3661 case 0x22d: /* cvtss2si */
3662 case 0x32d: /* cvtsd2si */
3663 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3664 if (mod != 3) {
3665 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3666 if ((b >> 8) & 1) {
3667 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3668 } else {
3669 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3670 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3671 }
3672 op2_offset = offsetof(CPUX86State,xmm_t0);
3673 } else {
3674 rm = (modrm & 7) | REX_B(s);
3675 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3676 }
3677 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3678 if (ot == OT_LONG) {
3679 SSEFunc_i_ep sse_fn_i_ep =
3680 sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3681 sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3682 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3683 } else {
3684 #ifdef TARGET_X86_64
3685 SSEFunc_l_ep sse_fn_l_ep =
3686 sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3687 sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
3688 #else
3689 goto illegal_op;
3690 #endif
3691 }
3692 gen_op_mov_reg_T0(ot, reg);
3693 break;
3694 case 0xc4: /* pinsrw */
3695 case 0x1c4:
3696 s->rip_offset = 1;
3697 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3698 val = ldub_code(s->pc++);
3699 if (b1) {
3700 val &= 7;
3701 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3702 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3703 } else {
3704 val &= 3;
3705 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3706 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3707 }
3708 break;
3709 case 0xc5: /* pextrw */
3710 case 0x1c5:
3711 if (mod != 3)
3712 goto illegal_op;
3713 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3714 val = ldub_code(s->pc++);
3715 if (b1) {
3716 val &= 7;
3717 rm = (modrm & 7) | REX_B(s);
3718 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3719 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3720 } else {
3721 val &= 3;
3722 rm = (modrm & 7);
3723 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3724 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3725 }
3726 reg = ((modrm >> 3) & 7) | rex_r;
3727 gen_op_mov_reg_T0(ot, reg);
3728 break;
3729 case 0x1d6: /* movq ea, xmm */
3730 if (mod != 3) {
3731 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3732 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3733 } else {
3734 rm = (modrm & 7) | REX_B(s);
3735 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3736 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3737 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3738 }
3739 break;
3740 case 0x2d6: /* movq2dq */
3741 gen_helper_enter_mmx(cpu_env);
3742 rm = (modrm & 7);
3743 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3744 offsetof(CPUX86State,fpregs[rm].mmx));
3745 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3746 break;
3747 case 0x3d6: /* movdq2q */
3748 gen_helper_enter_mmx(cpu_env);
3749 rm = (modrm & 7) | REX_B(s);
3750 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3751 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3752 break;
3753 case 0xd7: /* pmovmskb */
3754 case 0x1d7:
3755 if (mod != 3)
3756 goto illegal_op;
3757 if (b1) {
3758 rm = (modrm & 7) | REX_B(s);
3759 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3760 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3761 } else {
3762 rm = (modrm & 7);
3763 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3764 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3765 }
3766 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3767 reg = ((modrm >> 3) & 7) | rex_r;
3768 gen_op_mov_reg_T0(OT_LONG, reg);
3769 break;
3770 case 0x138:
3771 if (s->prefix & PREFIX_REPNZ)
3772 goto crc32;
3773 case 0x038:
3774 b = modrm;
3775 modrm = ldub_code(s->pc++);
3776 rm = modrm & 7;
3777 reg = ((modrm >> 3) & 7) | rex_r;
3778 mod = (modrm >> 6) & 3;
3779 if (b1 >= 2) {
3780 goto illegal_op;
3781 }
3782
3783 sse_fn_epp = sse_op_table6[b].op[b1];
3784 if (!sse_fn_epp) {
3785 goto illegal_op;
3786 }
3787 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3788 goto illegal_op;
3789
3790 if (b1) {
3791 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3792 if (mod == 3) {
3793 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3794 } else {
3795 op2_offset = offsetof(CPUX86State,xmm_t0);
3796 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3797 switch (b) {
3798 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3799 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3800 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3801 gen_ldq_env_A0(s->mem_index, op2_offset +
3802 offsetof(XMMReg, XMM_Q(0)));
3803 break;
3804 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3805 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3806 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3807 (s->mem_index >> 2) - 1);
3808 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3809 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3810 offsetof(XMMReg, XMM_L(0)));
3811 break;
3812 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3813 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3814 (s->mem_index >> 2) - 1);
3815 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3816 offsetof(XMMReg, XMM_W(0)));
3817 break;
3818 case 0x2a: /* movntqda */
3819 gen_ldo_env_A0(s->mem_index, op1_offset);
3820 return;
3821 default:
3822 gen_ldo_env_A0(s->mem_index, op2_offset);
3823 }
3824 }
3825 } else {
3826 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3827 if (mod == 3) {
3828 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3829 } else {
3830 op2_offset = offsetof(CPUX86State,mmx_t0);
3831 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3832 gen_ldq_env_A0(s->mem_index, op2_offset);
3833 }
3834 }
3835 if (sse_fn_epp == SSE_SPECIAL) {
3836 goto illegal_op;
3837 }
3838
3839 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3840 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3841 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3842
3843 if (b == 0x17)
3844 s->cc_op = CC_OP_EFLAGS;
3845 break;
3846 case 0x338: /* crc32 */
3847 crc32:
3848 b = modrm;
3849 modrm = ldub_code(s->pc++);
3850 reg = ((modrm >> 3) & 7) | rex_r;
3851
3852 if (b != 0xf0 && b != 0xf1)
3853 goto illegal_op;
3854 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3855 goto illegal_op;
3856
3857 if (b == 0xf0)
3858 ot = OT_BYTE;
3859 else if (b == 0xf1 && s->dflag != 2)
3860 if (s->prefix & PREFIX_DATA)
3861 ot = OT_WORD;
3862 else
3863 ot = OT_LONG;
3864 else
3865 ot = OT_QUAD;
3866
3867 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3868 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3869 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3870 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3871 cpu_T[0], tcg_const_i32(8 << ot));
3872
3873 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3874 gen_op_mov_reg_T0(ot, reg);
3875 break;
3876 case 0x03a:
3877 case 0x13a:
3878 b = modrm;
3879 modrm = ldub_code(s->pc++);
3880 rm = modrm & 7;
3881 reg = ((modrm >> 3) & 7) | rex_r;
3882 mod = (modrm >> 6) & 3;
3883 if (b1 >= 2) {
3884 goto illegal_op;
3885 }
3886
3887 sse_fn_eppi = sse_op_table7[b].op[b1];
3888 if (!sse_fn_eppi) {
3889 goto illegal_op;
3890 }
3891 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3892 goto illegal_op;
3893
3894 if (sse_fn_eppi == SSE_SPECIAL) {
3895 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3896 rm = (modrm & 7) | REX_B(s);
3897 if (mod != 3)
3898 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3899 reg = ((modrm >> 3) & 7) | rex_r;
3900 val = ldub_code(s->pc++);
3901 switch (b) {
3902 case 0x14: /* pextrb */
3903 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3904 xmm_regs[reg].XMM_B(val & 15)));
3905 if (mod == 3)
3906 gen_op_mov_reg_T0(ot, rm);
3907 else
3908 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3909 (s->mem_index >> 2) - 1);
3910 break;
3911 case 0x15: /* pextrw */
3912 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3913 xmm_regs[reg].XMM_W(val & 7)));
3914 if (mod == 3)
3915 gen_op_mov_reg_T0(ot, rm);
3916 else
3917 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3918 (s->mem_index >> 2) - 1);
3919 break;
3920 case 0x16:
3921 if (ot == OT_LONG) { /* pextrd */
3922 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3923 offsetof(CPUX86State,
3924 xmm_regs[reg].XMM_L(val & 3)));
3925 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3926 if (mod == 3)
3927 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3928 else
3929 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3930 (s->mem_index >> 2) - 1);
3931 } else { /* pextrq */
3932 #ifdef TARGET_X86_64
3933 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3934 offsetof(CPUX86State,
3935 xmm_regs[reg].XMM_Q(val & 1)));
3936 if (mod == 3)
3937 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3938 else
3939 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3940 (s->mem_index >> 2) - 1);
3941 #else
3942 goto illegal_op;
3943 #endif
3944 }
3945 break;
3946 case 0x17: /* extractps */
3947 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3948 xmm_regs[reg].XMM_L(val & 3)));
3949 if (mod == 3)
3950 gen_op_mov_reg_T0(ot, rm);
3951 else
3952 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3953 (s->mem_index >> 2) - 1);
3954 break;
3955 case 0x20: /* pinsrb */
3956 if (mod == 3)
3957 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3958 else
3959 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3960 (s->mem_index >> 2) - 1);
3961 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3962 xmm_regs[reg].XMM_B(val & 15)));
3963 break;
3964 case 0x21: /* insertps */
3965 if (mod == 3) {
3966 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3967 offsetof(CPUX86State,xmm_regs[rm]
3968 .XMM_L((val >> 6) & 3)));
3969 } else {
3970 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3971 (s->mem_index >> 2) - 1);
3972 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3973 }
3974 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3975 offsetof(CPUX86State,xmm_regs[reg]
3976 .XMM_L((val >> 4) & 3)));
3977 if ((val >> 0) & 1)
3978 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3979 cpu_env, offsetof(CPUX86State,
3980 xmm_regs[reg].XMM_L(0)));
3981 if ((val >> 1) & 1)
3982 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3983 cpu_env, offsetof(CPUX86State,
3984 xmm_regs[reg].XMM_L(1)));
3985 if ((val >> 2) & 1)
3986 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3987 cpu_env, offsetof(CPUX86State,
3988 xmm_regs[reg].XMM_L(2)));
3989 if ((val >> 3) & 1)
3990 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3991 cpu_env, offsetof(CPUX86State,
3992 xmm_regs[reg].XMM_L(3)));
3993 break;
3994 case 0x22:
3995 if (ot == OT_LONG) { /* pinsrd */
3996 if (mod == 3)
3997 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
3998 else
3999 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4000 (s->mem_index >> 2) - 1);
4001 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4002 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4003 offsetof(CPUX86State,
4004 xmm_regs[reg].XMM_L(val & 3)));
4005 } else { /* pinsrq */
4006 #ifdef TARGET_X86_64
4007 if (mod == 3)
4008 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
4009 else
4010 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4011 (s->mem_index >> 2) - 1);
4012 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
4013 offsetof(CPUX86State,
4014 xmm_regs[reg].XMM_Q(val & 1)));
4015 #else
4016 goto illegal_op;
4017 #endif
4018 }
4019 break;
4020 }
4021 return;
4022 }
4023
4024 if (b1) {
4025 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4026 if (mod == 3) {
4027 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
4028 } else {
4029 op2_offset = offsetof(CPUX86State,xmm_t0);
4030 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4031 gen_ldo_env_A0(s->mem_index, op2_offset);
4032 }
4033 } else {
4034 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4035 if (mod == 3) {
4036 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4037 } else {
4038 op2_offset = offsetof(CPUX86State,mmx_t0);
4039 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4040 gen_ldq_env_A0(s->mem_index, op2_offset);
4041 }
4042 }
4043 val = ldub_code(s->pc++);
4044
4045 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4046 s->cc_op = CC_OP_EFLAGS;
4047
4048 if (s->dflag == 2)
4049 /* The helper must use entire 64-bit gp registers */
4050 val |= 1 << 8;
4051 }
4052
4053 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4054 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4055 sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4056 break;
4057 default:
4058 goto illegal_op;
4059 }
4060 } else {
4061 /* generic MMX or SSE operation */
4062 switch(b) {
4063 case 0x70: /* pshufx insn */
4064 case 0xc6: /* pshufx insn */
4065 case 0xc2: /* compare insns */
4066 s->rip_offset = 1;
4067 break;
4068 default:
4069 break;
4070 }
4071 if (is_xmm) {
4072 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4073 if (mod != 3) {
4074 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4075 op2_offset = offsetof(CPUX86State,xmm_t0);
4076 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
4077 b == 0xc2)) {
4078 /* specific case for SSE single instructions */
4079 if (b1 == 2) {
4080 /* 32 bit access */
4081 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4082 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4083 } else {
4084 /* 64 bit access */
4085 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
4086 }
4087 } else {
4088 gen_ldo_env_A0(s->mem_index, op2_offset);
4089 }
4090 } else {
4091 rm = (modrm & 7) | REX_B(s);
4092 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4093 }
4094 } else {
4095 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4096 if (mod != 3) {
4097 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4098 op2_offset = offsetof(CPUX86State,mmx_t0);
4099 gen_ldq_env_A0(s->mem_index, op2_offset);
4100 } else {
4101 rm = (modrm & 7);
4102 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4103 }
4104 }
4105 switch(b) {
4106 case 0x0f: /* 3DNow! data insns */
4107 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4108 goto illegal_op;
4109 val = ldub_code(s->pc++);
4110 sse_fn_epp = sse_op_table5[val];
4111 if (!sse_fn_epp) {
4112 goto illegal_op;
4113 }
4114 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4115 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4116 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4117 break;
4118 case 0x70: /* pshufx insn */
4119 case 0xc6: /* pshufx insn */
4120 val = ldub_code(s->pc++);
4121 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4122 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4123 /* XXX: introduce a new table? */
4124 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
4125 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4126 break;
4127 case 0xc2:
4128 /* compare insns */
4129 val = ldub_code(s->pc++);
4130 if (val >= 8)
4131 goto illegal_op;
4132 sse_fn_epp = sse_op_table4[val][b1];
4133
4134 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4135 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4136 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4137 break;
4138 case 0xf7:
4139 /* maskmov : we must prepare A0 */
4140 if (mod != 3)
4141 goto illegal_op;
4142 #ifdef TARGET_X86_64
4143 if (s->aflag == 2) {
4144 gen_op_movq_A0_reg(R_EDI);
4145 } else
4146 #endif
4147 {
4148 gen_op_movl_A0_reg(R_EDI);
4149 if (s->aflag == 0)
4150 gen_op_andl_A0_ffff();
4151 }
4152 gen_add_A0_ds_seg(s);
4153
4154 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4155 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4156 /* XXX: introduce a new table? */
4157 sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
4158 sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0);
4159 break;
4160 default:
4161 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4162 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4163 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4164 break;
4165 }
4166 if (b == 0x2e || b == 0x2f) {
4167 s->cc_op = CC_OP_EFLAGS;
4168 }
4169 }
4170 }
4171
4172 /* convert one instruction. s->is_jmp is set if the translation must
4173 be stopped. Return the next pc value */
4174 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4175 {
4176 int b, prefixes, aflag, dflag;
4177 int shift, ot;
4178 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4179 target_ulong next_eip, tval;
4180 int rex_w, rex_r;
4181
4182 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4183 tcg_gen_debug_insn_start(pc_start);
4184 s->pc = pc_start;
4185 prefixes = 0;
4186 aflag = s->code32;
4187 dflag = s->code32;
4188 s->override = -1;
4189 rex_w = -1;
4190 rex_r = 0;
4191 #ifdef TARGET_X86_64
4192 s->rex_x = 0;
4193 s->rex_b = 0;
4194 x86_64_hregs = 0;
4195 #endif
4196 s->rip_offset = 0; /* for relative ip address */
4197 next_byte:
4198 b = ldub_code(s->pc);
4199 s->pc++;
4200 /* check prefixes */
4201 #ifdef TARGET_X86_64
4202 if (CODE64(s)) {
4203 switch (b) {
4204 case 0xf3:
4205 prefixes |= PREFIX_REPZ;
4206 goto next_byte;
4207 case 0xf2:
4208 prefixes |= PREFIX_REPNZ;
4209 goto next_byte;
4210 case 0xf0:
4211 prefixes |= PREFIX_LOCK;
4212 goto next_byte;
4213 case 0x2e:
4214 s->override = R_CS;
4215 goto next_byte;
4216 case 0x36:
4217 s->override = R_SS;
4218 goto next_byte;
4219 case 0x3e:
4220 s->override = R_DS;
4221 goto next_byte;
4222 case 0x26:
4223 s->override = R_ES;
4224 goto next_byte;
4225 case 0x64:
4226 s->override = R_FS;
4227 goto next_byte;
4228 case 0x65:
4229 s->override = R_GS;
4230 goto next_byte;
4231 case 0x66:
4232 prefixes |= PREFIX_DATA;
4233 goto next_byte;
4234 case 0x67:
4235 prefixes |= PREFIX_ADR;
4236 goto next_byte;
4237 case 0x40 ... 0x4f:
4238 /* REX prefix */
4239 rex_w = (b >> 3) & 1;
4240 rex_r = (b & 0x4) << 1;
4241 s->rex_x = (b & 0x2) << 2;
4242 REX_B(s) = (b & 0x1) << 3;
4243 x86_64_hregs = 1; /* select uniform byte register addressing */
4244 goto next_byte;
4245 }
4246 if (rex_w == 1) {
4247 /* 0x66 is ignored if rex.w is set */
4248 dflag = 2;
4249 } else {
4250 if (prefixes & PREFIX_DATA)
4251 dflag ^= 1;
4252 }
4253 if (!(prefixes & PREFIX_ADR))
4254 aflag = 2;
4255 } else
4256 #endif
4257 {
4258 switch (b) {
4259 case 0xf3:
4260 prefixes |= PREFIX_REPZ;
4261 goto next_byte;
4262 case 0xf2:
4263 prefixes |= PREFIX_REPNZ;
4264 goto next_byte;
4265 case 0xf0:
4266 prefixes |= PREFIX_LOCK;
4267 goto next_byte;
4268 case 0x2e:
4269 s->override = R_CS;
4270 goto next_byte;
4271 case 0x36:
4272 s->override = R_SS;
4273 goto next_byte;
4274 case 0x3e:
4275 s->override = R_DS;
4276 goto next_byte;
4277 case 0x26:
4278 s->override = R_ES;
4279 goto next_byte;
4280 case 0x64:
4281 s->override = R_FS;
4282 goto next_byte;
4283 case 0x65:
4284 s->override = R_GS;
4285 goto next_byte;
4286 case 0x66:
4287 prefixes |= PREFIX_DATA;
4288 goto next_byte;
4289 case 0x67:
4290 prefixes |= PREFIX_ADR;
4291 goto next_byte;
4292 }
4293 if (prefixes & PREFIX_DATA)
4294 dflag ^= 1;
4295 if (prefixes & PREFIX_ADR)
4296 aflag ^= 1;
4297 }
4298
4299 s->prefix = prefixes;
4300 s->aflag = aflag;
4301 s->dflag = dflag;
4302
4303 /* lock generation */
4304 if (prefixes & PREFIX_LOCK)
4305 gen_helper_lock();
4306
4307 /* now check op code */
4308 reswitch:
4309 switch(b) {
4310 case 0x0f:
4311 /**************************/
4312 /* extended op code */
4313 b = ldub_code(s->pc++) | 0x100;
4314 goto reswitch;
4315
4316 /**************************/
4317 /* arith & logic */
4318 case 0x00 ... 0x05:
4319 case 0x08 ... 0x0d:
4320 case 0x10 ... 0x15:
4321 case 0x18 ... 0x1d:
4322 case 0x20 ... 0x25:
4323 case 0x28 ... 0x2d:
4324 case 0x30 ... 0x35:
4325 case 0x38 ... 0x3d:
4326 {
4327 int op, f, val;
4328 op = (b >> 3) & 7;
4329 f = (b >> 1) & 3;
4330
4331 if ((b & 1) == 0)
4332 ot = OT_BYTE;
4333 else
4334 ot = dflag + OT_WORD;
4335
4336 switch(f) {
4337 case 0: /* OP Ev, Gv */
4338 modrm = ldub_code(s->pc++);
4339 reg = ((modrm >> 3) & 7) | rex_r;
4340 mod = (modrm >> 6) & 3;
4341 rm = (modrm & 7) | REX_B(s);
4342 if (mod != 3) {
4343 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4344 opreg = OR_TMP0;
4345 } else if (op == OP_XORL && rm == reg) {
4346 xor_zero:
4347 /* xor reg, reg optimisation */
4348 gen_op_movl_T0_0();
4349 s->cc_op = CC_OP_LOGICB + ot;
4350 gen_op_mov_reg_T0(ot, reg);
4351 gen_op_update1_cc();
4352 break;
4353 } else {
4354 opreg = rm;
4355 }
4356 gen_op_mov_TN_reg(ot, 1, reg);
4357 gen_op(s, op, ot, opreg);
4358 break;
4359 case 1: /* OP Gv, Ev */
4360 modrm = ldub_code(s->pc++);
4361 mod = (modrm >> 6) & 3;
4362 reg = ((modrm >> 3) & 7) | rex_r;
4363 rm = (modrm & 7) | REX_B(s);
4364 if (mod != 3) {
4365 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4366 gen_op_ld_T1_A0(ot + s->mem_index);
4367 } else if (op == OP_XORL && rm == reg) {
4368 goto xor_zero;
4369 } else {
4370 gen_op_mov_TN_reg(ot, 1, rm);
4371 }
4372 gen_op(s, op, ot, reg);
4373 break;
4374 case 2: /* OP A, Iv */
4375 val = insn_get(s, ot);
4376 gen_op_movl_T1_im(val);
4377 gen_op(s, op, ot, OR_EAX);
4378 break;
4379 }
4380 }
4381 break;
4382
4383 case 0x82:
4384 if (CODE64(s))
4385 goto illegal_op;
4386 case 0x80: /* GRP1 */
4387 case 0x81:
4388 case 0x83:
4389 {
4390 int val;
4391
4392 if ((b & 1) == 0)
4393 ot = OT_BYTE;
4394 else
4395 ot = dflag + OT_WORD;
4396
4397 modrm = ldub_code(s->pc++);
4398 mod = (modrm >> 6) & 3;
4399 rm = (modrm & 7) | REX_B(s);
4400 op = (modrm >> 3) & 7;
4401
4402 if (mod != 3) {
4403 if (b == 0x83)
4404 s->rip_offset = 1;
4405 else
4406 s->rip_offset = insn_const_size(ot);
4407 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4408 opreg = OR_TMP0;
4409 } else {
4410 opreg = rm;
4411 }
4412
4413 switch(b) {
4414 default:
4415 case 0x80:
4416 case 0x81:
4417 case 0x82:
4418 val = insn_get(s, ot);
4419 break;
4420 case 0x83:
4421 val = (int8_t)insn_get(s, OT_BYTE);
4422 break;
4423 }
4424 gen_op_movl_T1_im(val);
4425 gen_op(s, op, ot, opreg);
4426 }
4427 break;
4428
4429 /**************************/
4430 /* inc, dec, and other misc arith */
4431 case 0x40 ... 0x47: /* inc Gv */
4432 ot = dflag ? OT_LONG : OT_WORD;
4433 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4434 break;
4435 case 0x48 ... 0x4f: /* dec Gv */
4436 ot = dflag ? OT_LONG : OT_WORD;
4437 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4438 break;
4439 case 0xf6: /* GRP3 */
4440 case 0xf7:
4441 if ((b & 1) == 0)
4442 ot = OT_BYTE;
4443 else
4444 ot = dflag + OT_WORD;
4445
4446 modrm = ldub_code(s->pc++);
4447 mod = (modrm >> 6) & 3;
4448 rm = (modrm & 7) | REX_B(s);
4449 op = (modrm >> 3) & 7;
4450 if (mod != 3) {
4451 if (op == 0)
4452 s->rip_offset = insn_const_size(ot);
4453 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4454 gen_op_ld_T0_A0(ot + s->mem_index);
4455 } else {
4456 gen_op_mov_TN_reg(ot, 0, rm);
4457 }
4458
4459 switch(op) {
4460 case 0: /* test */
4461 val = insn_get(s, ot);
4462 gen_op_movl_T1_im(val);
4463 gen_op_testl_T0_T1_cc();
4464 s->cc_op = CC_OP_LOGICB + ot;
4465 break;
4466 case 2: /* not */
4467 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4468 if (mod != 3) {
4469 gen_op_st_T0_A0(ot + s->mem_index);
4470 } else {
4471 gen_op_mov_reg_T0(ot, rm);
4472 }
4473 break;
4474 case 3: /* neg */
4475 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4476 if (mod != 3) {
4477 gen_op_st_T0_A0(ot + s->mem_index);
4478 } else {
4479 gen_op_mov_reg_T0(ot, rm);
4480 }
4481 gen_op_update_neg_cc();
4482 s->cc_op = CC_OP_SUBB + ot;
4483 break;
4484 case 4: /* mul */
4485 switch(ot) {
4486 case OT_BYTE:
4487 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4488 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4489 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4490 /* XXX: use 32 bit mul which could be faster */
4491 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4492 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4493 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4494 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4495 s->cc_op = CC_OP_MULB;
4496 break;
4497 case OT_WORD:
4498 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4499 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4500 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4501 /* XXX: use 32 bit mul which could be faster */
4502 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4503 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4504 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4505 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4506 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4507 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4508 s->cc_op = CC_OP_MULW;
4509 break;
4510 default:
4511 case OT_LONG:
4512 #ifdef TARGET_X86_64
4513 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4514 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4515 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4516 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4517 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4518 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4519 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4520 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4521 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4522 #else
4523 {
4524 TCGv_i64 t0, t1;
4525 t0 = tcg_temp_new_i64();
4526 t1 = tcg_temp_new_i64();
4527 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4528 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4529 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4530 tcg_gen_mul_i64(t0, t0, t1);
4531 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4532 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4533 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4534 tcg_gen_shri_i64(t0, t0, 32);
4535 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4536 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4537 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4538 }
4539 #endif
4540 s->cc_op = CC_OP_MULL;
4541 break;
4542 #ifdef TARGET_X86_64
4543 case OT_QUAD:
4544 gen_helper_mulq_EAX_T0(cpu_T[0]);
4545 s->cc_op = CC_OP_MULQ;
4546 break;
4547 #endif
4548 }
4549 break;
4550 case 5: /* imul */
4551 switch(ot) {
4552 case OT_BYTE:
4553 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4554 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4555 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4556 /* XXX: use 32 bit mul which could be faster */
4557 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4558 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4559 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4560 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4561 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4562 s->cc_op = CC_OP_MULB;
4563 break;
4564 case OT_WORD:
4565 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4566 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4567 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4568 /* XXX: use 32 bit mul which could be faster */
4569 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4570 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4571 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4572 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4573 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4574 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4575 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4576 s->cc_op = CC_OP_MULW;
4577 break;
4578 default:
4579 case OT_LONG:
4580 #ifdef TARGET_X86_64
4581 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4582 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4583 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4584 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4585 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4586 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4587 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4588 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4589 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4590 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4591 #else
4592 {
4593 TCGv_i64 t0, t1;
4594 t0 = tcg_temp_new_i64();
4595 t1 = tcg_temp_new_i64();
4596 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4597 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4598 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4599 tcg_gen_mul_i64(t0, t0, t1);
4600 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4601 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4602 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4603 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4604 tcg_gen_shri_i64(t0, t0, 32);
4605 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4606 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4607 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4608 }
4609 #endif
4610 s->cc_op = CC_OP_MULL;
4611 break;
4612 #ifdef TARGET_X86_64
4613 case OT_QUAD:
4614 gen_helper_imulq_EAX_T0(cpu_T[0]);
4615 s->cc_op = CC_OP_MULQ;
4616 break;
4617 #endif
4618 }
4619 break;
4620 case 6: /* div */
4621 switch(ot) {
4622 case OT_BYTE:
4623 gen_jmp_im(pc_start - s->cs_base);
4624 gen_helper_divb_AL(cpu_T[0]);
4625 break;
4626 case OT_WORD:
4627 gen_jmp_im(pc_start - s->cs_base);
4628 gen_helper_divw_AX(cpu_T[0]);
4629 break;
4630 default:
4631 case OT_LONG:
4632 gen_jmp_im(pc_start - s->cs_base);
4633 gen_helper_divl_EAX(cpu_T[0]);
4634 break;
4635 #ifdef TARGET_X86_64
4636 case OT_QUAD:
4637 gen_jmp_im(pc_start - s->cs_base);
4638 gen_helper_divq_EAX(cpu_T[0]);
4639 break;
4640 #endif
4641 }
4642 break;
4643 case 7: /* idiv */
4644 switch(ot) {
4645 case OT_BYTE:
4646 gen_jmp_im(pc_start - s->cs_base);
4647 gen_helper_idivb_AL(cpu_T[0]);
4648 break;
4649 case OT_WORD:
4650 gen_jmp_im(pc_start - s->cs_base);
4651 gen_helper_idivw_AX(cpu_T[0]);
4652 break;
4653 default:
4654 case OT_LONG:
4655 gen_jmp_im(pc_start - s->cs_base);
4656 gen_helper_idivl_EAX(cpu_T[0]);
4657 break;
4658 #ifdef TARGET_X86_64
4659 case OT_QUAD:
4660 gen_jmp_im(pc_start - s->cs_base);
4661 gen_helper_idivq_EAX(cpu_T[0]);
4662 break;
4663 #endif
4664 }
4665 break;
4666 default:
4667 goto illegal_op;
4668 }
4669 break;
4670
4671 case 0xfe: /* GRP4 */
4672 case 0xff: /* GRP5 */
4673 if ((b & 1) == 0)
4674 ot = OT_BYTE;
4675 else
4676 ot = dflag + OT_WORD;
4677
4678 modrm = ldub_code(s->pc++);
4679 mod = (modrm >> 6) & 3;
4680 rm = (modrm & 7) | REX_B(s);
4681 op = (modrm >> 3) & 7;
4682 if (op >= 2 && b == 0xfe) {
4683 goto illegal_op;
4684 }
4685 if (CODE64(s)) {
4686 if (op == 2 || op == 4) {
4687 /* operand size for jumps is 64 bit */
4688 ot = OT_QUAD;
4689 } else if (op == 3 || op == 5) {
4690 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4691 } else if (op == 6) {
4692 /* default push size is 64 bit */
4693 ot = dflag ? OT_QUAD : OT_WORD;
4694 }
4695 }
4696 if (mod != 3) {
4697 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4698 if (op >= 2 && op != 3 && op != 5)
4699 gen_op_ld_T0_A0(ot + s->mem_index);
4700 } else {
4701 gen_op_mov_TN_reg(ot, 0, rm);
4702 }
4703
4704 switch(op) {
4705 case 0: /* inc Ev */
4706 if (mod != 3)
4707 opreg = OR_TMP0;
4708 else
4709 opreg = rm;
4710 gen_inc(s, ot, opreg, 1);
4711 break;
4712 case 1: /* dec Ev */
4713 if (mod != 3)
4714 opreg = OR_TMP0;
4715 else
4716 opreg = rm;
4717 gen_inc(s, ot, opreg, -1);
4718 break;
4719 case 2: /* call Ev */
4720 /* XXX: optimize if memory (no 'and' is necessary) */
4721 if (s->dflag == 0)
4722 gen_op_andl_T0_ffff();
4723 next_eip = s->pc - s->cs_base;
4724 gen_movtl_T1_im(next_eip);
4725 gen_push_T1(s);
4726 gen_op_jmp_T0();
4727 gen_eob(s);
4728 break;
4729 case 3: /* lcall Ev */
4730 gen_op_ld_T1_A0(ot + s->mem_index);
4731 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4732 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4733 do_lcall:
4734 if (s->pe && !s->vm86) {
4735 if (s->cc_op != CC_OP_DYNAMIC)
4736 gen_op_set_cc_op(s->cc_op);
4737 gen_jmp_im(pc_start - s->cs_base);
4738 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4739 gen_helper_lcall_protected(cpu_tmp2_i32, cpu_T[1],
4740 tcg_const_i32(dflag),
4741 tcg_const_i32(s->pc - pc_start));
4742 } else {
4743 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4744 gen_helper_lcall_real(cpu_tmp2_i32, cpu_T[1],
4745 tcg_const_i32(dflag),
4746 tcg_const_i32(s->pc - s->cs_base));
4747 }
4748 gen_eob(s);
4749 break;
4750 case 4: /* jmp Ev */
4751 if (s->dflag == 0)
4752 gen_op_andl_T0_ffff();
4753 gen_op_jmp_T0();
4754 gen_eob(s);
4755 break;
4756 case 5: /* ljmp Ev */
4757 gen_op_ld_T1_A0(ot + s->mem_index);
4758 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4759 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4760 do_ljmp:
4761 if (s->pe && !s->vm86) {
4762 if (s->cc_op != CC_OP_DYNAMIC)
4763 gen_op_set_cc_op(s->cc_op);
4764 gen_jmp_im(pc_start - s->cs_base);
4765 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4766 gen_helper_ljmp_protected(cpu_tmp2_i32, cpu_T[1],
4767 tcg_const_i32(s->pc - pc_start));
4768 } else {
4769 gen_op_movl_seg_T0_vm(R_CS);
4770 gen_op_movl_T0_T1();
4771 gen_op_jmp_T0();
4772 }
4773 gen_eob(s);
4774 break;
4775 case 6: /* push Ev */
4776 gen_push_T0(s);
4777 break;
4778 default:
4779 goto illegal_op;
4780 }
4781 break;
4782
4783 case 0x84: /* test Ev, Gv */
4784 case 0x85:
4785 if ((b & 1) == 0)
4786 ot = OT_BYTE;
4787 else
4788 ot = dflag + OT_WORD;
4789
4790 modrm = ldub_code(s->pc++);
4791 reg = ((modrm >> 3) & 7) | rex_r;
4792
4793 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4794 gen_op_mov_TN_reg(ot, 1, reg);
4795 gen_op_testl_T0_T1_cc();
4796 s->cc_op = CC_OP_LOGICB + ot;
4797 break;
4798
4799 case 0xa8: /* test eAX, Iv */
4800 case 0xa9:
4801 if ((b & 1) == 0)
4802 ot = OT_BYTE;
4803 else
4804 ot = dflag + OT_WORD;
4805 val = insn_get(s, ot);
4806
4807 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4808 gen_op_movl_T1_im(val);
4809 gen_op_testl_T0_T1_cc();
4810 s->cc_op = CC_OP_LOGICB + ot;
4811 break;
4812
4813 case 0x98: /* CWDE/CBW */
4814 #ifdef TARGET_X86_64
4815 if (dflag == 2) {
4816 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4817 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4818 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4819 } else
4820 #endif
4821 if (dflag == 1) {
4822 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4823 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4824 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4825 } else {
4826 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4827 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4828 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4829 }
4830 break;
4831 case 0x99: /* CDQ/CWD */
4832 #ifdef TARGET_X86_64
4833 if (dflag == 2) {
4834 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4835 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4836 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4837 } else
4838 #endif
4839 if (dflag == 1) {
4840 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4841 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4842 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4843 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4844 } else {
4845 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4846 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4847 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4848 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4849 }
4850 break;
4851 case 0x1af: /* imul Gv, Ev */
4852 case 0x69: /* imul Gv, Ev, I */
4853 case 0x6b:
4854 ot = dflag + OT_WORD;
4855 modrm = ldub_code(s->pc++);
4856 reg = ((modrm >> 3) & 7) | rex_r;
4857 if (b == 0x69)
4858 s->rip_offset = insn_const_size(ot);
4859 else if (b == 0x6b)
4860 s->rip_offset = 1;
4861 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4862 if (b == 0x69) {
4863 val = insn_get(s, ot);
4864 gen_op_movl_T1_im(val);
4865 } else if (b == 0x6b) {
4866 val = (int8_t)insn_get(s, OT_BYTE);
4867 gen_op_movl_T1_im(val);
4868 } else {
4869 gen_op_mov_TN_reg(ot, 1, reg);
4870 }
4871
4872 #ifdef TARGET_X86_64
4873 if (ot == OT_QUAD) {
4874 gen_helper_imulq_T0_T1(cpu_T[0], cpu_T[0], cpu_T[1]);
4875 } else
4876 #endif
4877 if (ot == OT_LONG) {
4878 #ifdef TARGET_X86_64
4879 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4880 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4881 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4882 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4883 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4884 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4885 #else
4886 {
4887 TCGv_i64 t0, t1;
4888 t0 = tcg_temp_new_i64();
4889 t1 = tcg_temp_new_i64();
4890 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4891 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4892 tcg_gen_mul_i64(t0, t0, t1);
4893 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4894 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4895 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4896 tcg_gen_shri_i64(t0, t0, 32);
4897 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4898 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4899 }
4900 #endif
4901 } else {
4902 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4903 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4904 /* XXX: use 32 bit mul which could be faster */
4905 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4906 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4907 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4908 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4909 }
4910 gen_op_mov_reg_T0(ot, reg);
4911 s->cc_op = CC_OP_MULB + ot;
4912 break;
4913 case 0x1c0:
4914 case 0x1c1: /* xadd Ev, Gv */
4915 if ((b & 1) == 0)
4916 ot = OT_BYTE;
4917 else
4918 ot = dflag + OT_WORD;
4919 modrm = ldub_code(s->pc++);
4920 reg = ((modrm >> 3) & 7) | rex_r;
4921 mod = (modrm >> 6) & 3;
4922 if (mod == 3) {
4923 rm = (modrm & 7) | REX_B(s);
4924 gen_op_mov_TN_reg(ot, 0, reg);
4925 gen_op_mov_TN_reg(ot, 1, rm);
4926 gen_op_addl_T0_T1();
4927 gen_op_mov_reg_T1(ot, reg);
4928 gen_op_mov_reg_T0(ot, rm);
4929 } else {
4930 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4931 gen_op_mov_TN_reg(ot, 0, reg);
4932 gen_op_ld_T1_A0(ot + s->mem_index);
4933 gen_op_addl_T0_T1();
4934 gen_op_st_T0_A0(ot + s->mem_index);
4935 gen_op_mov_reg_T1(ot, reg);
4936 }
4937 gen_op_update2_cc();
4938 s->cc_op = CC_OP_ADDB + ot;
4939 break;
4940 case 0x1b0:
4941 case 0x1b1: /* cmpxchg Ev, Gv */
4942 {
4943 int label1, label2;
4944 TCGv t0, t1, t2, a0;
4945
4946 if ((b & 1) == 0)
4947 ot = OT_BYTE;
4948 else
4949 ot = dflag + OT_WORD;
4950 modrm = ldub_code(s->pc++);
4951 reg = ((modrm >> 3) & 7) | rex_r;
4952 mod = (modrm >> 6) & 3;
4953 t0 = tcg_temp_local_new();
4954 t1 = tcg_temp_local_new();
4955 t2 = tcg_temp_local_new();
4956 a0 = tcg_temp_local_new();
4957 gen_op_mov_v_reg(ot, t1, reg);
4958 if (mod == 3) {
4959 rm = (modrm & 7) | REX_B(s);
4960 gen_op_mov_v_reg(ot, t0, rm);
4961 } else {
4962 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4963 tcg_gen_mov_tl(a0, cpu_A0);
4964 gen_op_ld_v(ot + s->mem_index, t0, a0);
4965 rm = 0; /* avoid warning */
4966 }
4967 label1 = gen_new_label();
4968 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
4969 gen_extu(ot, t2);
4970 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4971 label2 = gen_new_label();
4972 if (mod == 3) {
4973 gen_op_mov_reg_v(ot, R_EAX, t0);
4974 tcg_gen_br(label2);
4975 gen_set_label(label1);
4976 gen_op_mov_reg_v(ot, rm, t1);
4977 } else {
4978 /* perform no-op store cycle like physical cpu; must be
4979 before changing accumulator to ensure idempotency if
4980 the store faults and the instruction is restarted */
4981 gen_op_st_v(ot + s->mem_index, t0, a0);
4982 gen_op_mov_reg_v(ot, R_EAX, t0);
4983 tcg_gen_br(label2);
4984 gen_set_label(label1);
4985 gen_op_st_v(ot + s->mem_index, t1, a0);
4986 }
4987 gen_set_label(label2);
4988 tcg_gen_mov_tl(cpu_cc_src, t0);
4989 tcg_gen_mov_tl(cpu_cc_dst, t2);
4990 s->cc_op = CC_OP_SUBB + ot;
4991 tcg_temp_free(t0);
4992 tcg_temp_free(t1);
4993 tcg_temp_free(t2);
4994 tcg_temp_free(a0);
4995 }
4996 break;
4997 case 0x1c7: /* cmpxchg8b */
4998 modrm = ldub_code(s->pc++);
4999 mod = (modrm >> 6) & 3;
5000 if ((mod == 3) || ((modrm & 0x38) != 0x8))
5001 goto illegal_op;
5002 #ifdef TARGET_X86_64
5003 if (dflag == 2) {
5004 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
5005 goto illegal_op;
5006 gen_jmp_im(pc_start - s->cs_base);
5007 if (s->cc_op != CC_OP_DYNAMIC)
5008 gen_op_set_cc_op(s->cc_op);
5009 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5010 gen_helper_cmpxchg16b(cpu_A0);
5011 } else
5012 #endif
5013 {
5014 if (!(s->cpuid_features & CPUID_CX8))
5015 goto illegal_op;
5016 gen_jmp_im(pc_start - s->cs_base);
5017 if (s->cc_op != CC_OP_DYNAMIC)
5018 gen_op_set_cc_op(s->cc_op);
5019 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5020 gen_helper_cmpxchg8b(cpu_A0);
5021 }
5022 s->cc_op = CC_OP_EFLAGS;
5023 break;
5024
5025 /**************************/
5026 /* push/pop */
5027 case 0x50 ... 0x57: /* push */
5028 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
5029 gen_push_T0(s);
5030 break;
5031 case 0x58 ... 0x5f: /* pop */
5032 if (CODE64(s)) {
5033 ot = dflag ? OT_QUAD : OT_WORD;
5034 } else {
5035 ot = dflag + OT_WORD;
5036 }
5037 gen_pop_T0(s);
5038 /* NOTE: order is important for pop %sp */
5039 gen_pop_update(s);
5040 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
5041 break;
5042 case 0x60: /* pusha */
5043 if (CODE64(s))
5044 goto illegal_op;
5045 gen_pusha(s);
5046 break;
5047 case 0x61: /* popa */
5048 if (CODE64(s))
5049 goto illegal_op;
5050 gen_popa(s);
5051 break;
5052 case 0x68: /* push Iv */
5053 case 0x6a:
5054 if (CODE64(s)) {
5055 ot = dflag ? OT_QUAD : OT_WORD;
5056 } else {
5057 ot = dflag + OT_WORD;
5058 }
5059 if (b == 0x68)
5060 val = insn_get(s, ot);
5061 else
5062 val = (int8_t)insn_get(s, OT_BYTE);
5063 gen_op_movl_T0_im(val);
5064 gen_push_T0(s);
5065 break;
5066 case 0x8f: /* pop Ev */
5067 if (CODE64(s)) {
5068 ot = dflag ? OT_QUAD : OT_WORD;
5069 } else {
5070 ot = dflag + OT_WORD;
5071 }
5072 modrm = ldub_code(s->pc++);
5073 mod = (modrm >> 6) & 3;
5074 gen_pop_T0(s);
5075 if (mod == 3) {
5076 /* NOTE: order is important for pop %sp */
5077 gen_pop_update(s);
5078 rm = (modrm & 7) | REX_B(s);
5079 gen_op_mov_reg_T0(ot, rm);
5080 } else {
5081 /* NOTE: order is important too for MMU exceptions */
5082 s->popl_esp_hack = 1 << ot;
5083 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5084 s->popl_esp_hack = 0;
5085 gen_pop_update(s);
5086 }
5087 break;
5088 case 0xc8: /* enter */
5089 {
5090 int level;
5091 val = lduw_code(s->pc);
5092 s->pc += 2;
5093 level = ldub_code(s->pc++);
5094 gen_enter(s, val, level);
5095 }
5096 break;
5097 case 0xc9: /* leave */
5098 /* XXX: exception not precise (ESP is updated before potential exception) */
5099 if (CODE64(s)) {
5100 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5101 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5102 } else if (s->ss32) {
5103 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5104 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5105 } else {
5106 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5107 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5108 }
5109 gen_pop_T0(s);
5110 if (CODE64(s)) {
5111 ot = dflag ? OT_QUAD : OT_WORD;
5112 } else {
5113 ot = dflag + OT_WORD;
5114 }
5115 gen_op_mov_reg_T0(ot, R_EBP);
5116 gen_pop_update(s);
5117 break;
5118 case 0x06: /* push es */
5119 case 0x0e: /* push cs */
5120 case 0x16: /* push ss */
5121 case 0x1e: /* push ds */
5122 if (CODE64(s))
5123 goto illegal_op;
5124 gen_op_movl_T0_seg(b >> 3);
5125 gen_push_T0(s);
5126 break;
5127 case 0x1a0: /* push fs */
5128 case 0x1a8: /* push gs */
5129 gen_op_movl_T0_seg((b >> 3) & 7);
5130 gen_push_T0(s);
5131 break;
5132 case 0x07: /* pop es */
5133 case 0x17: /* pop ss */
5134 case 0x1f: /* pop ds */
5135 if (CODE64(s))
5136 goto illegal_op;
5137 reg = b >> 3;
5138 gen_pop_T0(s);
5139 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5140 gen_pop_update(s);
5141 if (reg == R_SS) {
5142 /* if reg == SS, inhibit interrupts/trace. */
5143 /* If several instructions disable interrupts, only the
5144 _first_ does it */
5145 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5146 gen_helper_set_inhibit_irq();
5147 s->tf = 0;
5148 }
5149 if (s->is_jmp) {
5150 gen_jmp_im(s->pc - s->cs_base);
5151 gen_eob(s);
5152 }
5153 break;
5154 case 0x1a1: /* pop fs */
5155 case 0x1a9: /* pop gs */
5156 gen_pop_T0(s);
5157 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5158 gen_pop_update(s);
5159 if (s->is_jmp) {
5160 gen_jmp_im(s->pc - s->cs_base);
5161 gen_eob(s);
5162 }
5163 break;
5164
5165 /**************************/
5166 /* mov */
5167 case 0x88:
5168 case 0x89: /* mov Gv, Ev */
5169 if ((b & 1) == 0)
5170 ot = OT_BYTE;
5171 else
5172 ot = dflag + OT_WORD;
5173 modrm = ldub_code(s->pc++);
5174 reg = ((modrm >> 3) & 7) | rex_r;
5175
5176 /* generate a generic store */
5177 gen_ldst_modrm(s, modrm, ot, reg, 1);
5178 break;
5179 case 0xc6:
5180 case 0xc7: /* mov Ev, Iv */
5181 if ((b & 1) == 0)
5182 ot = OT_BYTE;
5183 else
5184 ot = dflag + OT_WORD;
5185 modrm = ldub_code(s->pc++);
5186 mod = (modrm >> 6) & 3;
5187 if (mod != 3) {
5188 s->rip_offset = insn_const_size(ot);
5189 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5190 }
5191 val = insn_get(s, ot);
5192 gen_op_movl_T0_im(val);
5193 if (mod != 3)
5194 gen_op_st_T0_A0(ot + s->mem_index);
5195 else
5196 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5197 break;
5198 case 0x8a:
5199 case 0x8b: /* mov Ev, Gv */
5200 if ((b & 1) == 0)
5201 ot = OT_BYTE;
5202 else
5203 ot = OT_WORD + dflag;
5204 modrm = ldub_code(s->pc++);
5205 reg = ((modrm >> 3) & 7) | rex_r;
5206
5207 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5208 gen_op_mov_reg_T0(ot, reg);
5209 break;
5210 case 0x8e: /* mov seg, Gv */
5211 modrm = ldub_code(s->pc++);
5212 reg = (modrm >> 3) & 7;
5213 if (reg >= 6 || reg == R_CS)
5214 goto illegal_op;
5215 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5216 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5217 if (reg == R_SS) {
5218 /* if reg == SS, inhibit interrupts/trace */
5219 /* If several instructions disable interrupts, only the
5220 _first_ does it */
5221 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5222 gen_helper_set_inhibit_irq();
5223 s->tf = 0;
5224 }
5225 if (s->is_jmp) {
5226 gen_jmp_im(s->pc - s->cs_base);
5227 gen_eob(s);
5228 }
5229 break;
5230 case 0x8c: /* mov Gv, seg */
5231 modrm = ldub_code(s->pc++);
5232 reg = (modrm >> 3) & 7;
5233 mod = (modrm >> 6) & 3;
5234 if (reg >= 6)
5235 goto illegal_op;
5236 gen_op_movl_T0_seg(reg);
5237 if (mod == 3)
5238 ot = OT_WORD + dflag;
5239 else
5240 ot = OT_WORD;
5241 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5242 break;
5243
5244 case 0x1b6: /* movzbS Gv, Eb */
5245 case 0x1b7: /* movzwS Gv, Eb */
5246 case 0x1be: /* movsbS Gv, Eb */
5247 case 0x1bf: /* movswS Gv, Eb */
5248 {
5249 int d_ot;
5250 /* d_ot is the size of destination */
5251 d_ot = dflag + OT_WORD;
5252 /* ot is the size of source */
5253 ot = (b & 1) + OT_BYTE;
5254 modrm = ldub_code(s->pc++);
5255 reg = ((modrm >> 3) & 7) | rex_r;
5256 mod = (modrm >> 6) & 3;
5257 rm = (modrm & 7) | REX_B(s);
5258
5259 if (mod == 3) {
5260 gen_op_mov_TN_reg(ot, 0, rm);
5261 switch(ot | (b & 8)) {
5262 case OT_BYTE:
5263 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5264 break;
5265 case OT_BYTE | 8:
5266 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5267 break;
5268 case OT_WORD:
5269 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5270 break;
5271 default:
5272 case OT_WORD | 8:
5273 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5274 break;
5275 }
5276 gen_op_mov_reg_T0(d_ot, reg);
5277 } else {
5278 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5279 if (b & 8) {
5280 gen_op_lds_T0_A0(ot + s->mem_index);
5281 } else {
5282 gen_op_ldu_T0_A0(ot + s->mem_index);
5283 }
5284 gen_op_mov_reg_T0(d_ot, reg);
5285 }
5286 }
5287 break;
5288
5289 case 0x8d: /* lea */
5290 ot = dflag + OT_WORD;
5291 modrm = ldub_code(s->pc++);
5292 mod = (modrm >> 6) & 3;
5293 if (mod == 3)
5294 goto illegal_op;
5295 reg = ((modrm >> 3) & 7) | rex_r;
5296 /* we must ensure that no segment is added */
5297 s->override = -1;
5298 val = s->addseg;
5299 s->addseg = 0;
5300 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5301 s->addseg = val;
5302 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5303 break;
5304
5305 case 0xa0: /* mov EAX, Ov */
5306 case 0xa1:
5307 case 0xa2: /* mov Ov, EAX */
5308 case 0xa3:
5309 {
5310 target_ulong offset_addr;
5311
5312 if ((b & 1) == 0)
5313 ot = OT_BYTE;
5314 else
5315 ot = dflag + OT_WORD;
5316 #ifdef TARGET_X86_64
5317 if (s->aflag == 2) {
5318 offset_addr = ldq_code(s->pc);
5319 s->pc += 8;
5320 gen_op_movq_A0_im(offset_addr);
5321 } else
5322 #endif
5323 {
5324 if (s->aflag) {
5325 offset_addr = insn_get(s, OT_LONG);
5326 } else {
5327 offset_addr = insn_get(s, OT_WORD);
5328 }
5329 gen_op_movl_A0_im(offset_addr);
5330 }
5331 gen_add_A0_ds_seg(s);
5332 if ((b & 2) == 0) {
5333 gen_op_ld_T0_A0(ot + s->mem_index);
5334 gen_op_mov_reg_T0(ot, R_EAX);
5335 } else {
5336 gen_op_mov_TN_reg(ot, 0, R_EAX);
5337 gen_op_st_T0_A0(ot + s->mem_index);
5338 }
5339 }
5340 break;
5341 case 0xd7: /* xlat */
5342 #ifdef TARGET_X86_64
5343 if (s->aflag == 2) {
5344 gen_op_movq_A0_reg(R_EBX);
5345 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5346 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5347 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5348 } else
5349 #endif
5350 {
5351 gen_op_movl_A0_reg(R_EBX);
5352 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5353 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5354 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5355 if (s->aflag == 0)
5356 gen_op_andl_A0_ffff();
5357 else
5358 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5359 }
5360 gen_add_A0_ds_seg(s);
5361 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5362 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5363 break;
5364 case 0xb0 ... 0xb7: /* mov R, Ib */
5365 val = insn_get(s, OT_BYTE);
5366 gen_op_movl_T0_im(val);
5367 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5368 break;
5369 case 0xb8 ... 0xbf: /* mov R, Iv */
5370 #ifdef TARGET_X86_64
5371 if (dflag == 2) {
5372 uint64_t tmp;
5373 /* 64 bit case */
5374 tmp = ldq_code(s->pc);
5375 s->pc += 8;
5376 reg = (b & 7) | REX_B(s);
5377 gen_movtl_T0_im(tmp);
5378 gen_op_mov_reg_T0(OT_QUAD, reg);
5379 } else
5380 #endif
5381 {
5382 ot = dflag ? OT_LONG : OT_WORD;
5383 val = insn_get(s, ot);
5384 reg = (b & 7) | REX_B(s);
5385 gen_op_movl_T0_im(val);
5386 gen_op_mov_reg_T0(ot, reg);
5387 }
5388 break;
5389
5390 case 0x91 ... 0x97: /* xchg R, EAX */
5391 do_xchg_reg_eax:
5392 ot = dflag + OT_WORD;
5393 reg = (b & 7) | REX_B(s);
5394 rm = R_EAX;
5395 goto do_xchg_reg;
5396 case 0x86:
5397 case 0x87: /* xchg Ev, Gv */
5398 if ((b & 1) == 0)
5399 ot = OT_BYTE;
5400 else
5401 ot = dflag + OT_WORD;
5402 modrm = ldub_code(s->pc++);
5403 reg = ((modrm >> 3) & 7) | rex_r;
5404 mod = (modrm >> 6) & 3;
5405 if (mod == 3) {
5406 rm = (modrm & 7) | REX_B(s);
5407 do_xchg_reg:
5408 gen_op_mov_TN_reg(ot, 0, reg);
5409 gen_op_mov_TN_reg(ot, 1, rm);
5410 gen_op_mov_reg_T0(ot, rm);
5411 gen_op_mov_reg_T1(ot, reg);
5412 } else {
5413 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5414 gen_op_mov_TN_reg(ot, 0, reg);
5415 /* for xchg, lock is implicit */
5416 if (!(prefixes & PREFIX_LOCK))
5417 gen_helper_lock();
5418 gen_op_ld_T1_A0(ot + s->mem_index);
5419 gen_op_st_T0_A0(ot + s->mem_index);
5420 if (!(prefixes & PREFIX_LOCK))
5421 gen_helper_unlock();
5422 gen_op_mov_reg_T1(ot, reg);
5423 }
5424 break;
5425 case 0xc4: /* les Gv */
5426 if (CODE64(s))
5427 goto illegal_op;
5428 op = R_ES;
5429 goto do_lxx;
5430 case 0xc5: /* lds Gv */
5431 if (CODE64(s))
5432 goto illegal_op;
5433 op = R_DS;
5434 goto do_lxx;
5435 case 0x1b2: /* lss Gv */
5436 op = R_SS;
5437 goto do_lxx;
5438 case 0x1b4: /* lfs Gv */
5439 op = R_FS;
5440 goto do_lxx;
5441 case 0x1b5: /* lgs Gv */
5442 op = R_GS;
5443 do_lxx:
5444 ot = dflag ? OT_LONG : OT_WORD;
5445 modrm = ldub_code(s->pc++);
5446 reg = ((modrm >> 3) & 7) | rex_r;
5447 mod = (modrm >> 6) & 3;
5448 if (mod == 3)
5449 goto illegal_op;
5450 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5451 gen_op_ld_T1_A0(ot + s->mem_index);
5452 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5453 /* load the segment first to handle exceptions properly */
5454 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5455 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5456 /* then put the data */
5457 gen_op_mov_reg_T1(ot, reg);
5458 if (s->is_jmp) {
5459 gen_jmp_im(s->pc - s->cs_base);
5460 gen_eob(s);
5461 }
5462 break;
5463
5464 /************************/
5465 /* shifts */
5466 case 0xc0:
5467 case 0xc1:
5468 /* shift Ev,Ib */
5469 shift = 2;
5470 grp2:
5471 {
5472 if ((b & 1) == 0)
5473 ot = OT_BYTE;
5474 else
5475 ot = dflag + OT_WORD;
5476
5477 modrm = ldub_code(s->pc++);
5478 mod = (modrm >> 6) & 3;
5479 op = (modrm >> 3) & 7;
5480
5481 if (mod != 3) {
5482 if (shift == 2) {
5483 s->rip_offset = 1;
5484 }
5485 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5486 opreg = OR_TMP0;
5487 } else {
5488 opreg = (modrm & 7) | REX_B(s);
5489 }
5490
5491 /* simpler op */
5492 if (shift == 0) {
5493 gen_shift(s, op, ot, opreg, OR_ECX);
5494 } else {
5495 if (shift == 2) {
5496 shift = ldub_code(s->pc++);
5497 }
5498 gen_shifti(s, op, ot, opreg, shift);
5499 }
5500 }
5501 break;
5502 case 0xd0:
5503 case 0xd1:
5504 /* shift Ev,1 */
5505 shift = 1;
5506 goto grp2;
5507 case 0xd2:
5508 case 0xd3:
5509 /* shift Ev,cl */
5510 shift = 0;
5511 goto grp2;
5512
5513 case 0x1a4: /* shld imm */
5514 op = 0;
5515 shift = 1;
5516 goto do_shiftd;
5517 case 0x1a5: /* shld cl */
5518 op = 0;
5519 shift = 0;
5520 goto do_shiftd;
5521 case 0x1ac: /* shrd imm */
5522 op = 1;
5523 shift = 1;
5524 goto do_shiftd;
5525 case 0x1ad: /* shrd cl */
5526 op = 1;
5527 shift = 0;
5528 do_shiftd:
5529 ot = dflag + OT_WORD;
5530 modrm = ldub_code(s->pc++);
5531 mod = (modrm >> 6) & 3;
5532 rm = (modrm & 7) | REX_B(s);
5533 reg = ((modrm >> 3) & 7) | rex_r;
5534 if (mod != 3) {
5535 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5536 opreg = OR_TMP0;
5537 } else {
5538 opreg = rm;
5539 }
5540 gen_op_mov_TN_reg(ot, 1, reg);
5541
5542 if (shift) {
5543 val = ldub_code(s->pc++);
5544 tcg_gen_movi_tl(cpu_T3, val);
5545 } else {
5546 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5547 }
5548 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5549 break;
5550
5551 /************************/
5552 /* floats */
5553 case 0xd8 ... 0xdf:
5554 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5555 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5556 /* XXX: what to do if illegal op ? */
5557 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5558 break;
5559 }
5560 modrm = ldub_code(s->pc++);
5561 mod = (modrm >> 6) & 3;
5562 rm = modrm & 7;
5563 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5564 if (mod != 3) {
5565 /* memory op */
5566 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5567 switch(op) {
5568 case 0x00 ... 0x07: /* fxxxs */
5569 case 0x10 ... 0x17: /* fixxxl */
5570 case 0x20 ... 0x27: /* fxxxl */
5571 case 0x30 ... 0x37: /* fixxx */
5572 {
5573 int op1;
5574 op1 = op & 7;
5575
5576 switch(op >> 4) {
5577 case 0:
5578 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5579 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5580 gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
5581 break;
5582 case 1:
5583 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5584 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5585 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5586 break;
5587 case 2:
5588 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5589 (s->mem_index >> 2) - 1);
5590 gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
5591 break;
5592 case 3:
5593 default:
5594 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5595 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5596 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5597 break;
5598 }
5599
5600 gen_helper_fp_arith_ST0_FT0(op1);
5601 if (op1 == 3) {
5602 /* fcomp needs pop */
5603 gen_helper_fpop(cpu_env);
5604 }
5605 }
5606 break;
5607 case 0x08: /* flds */
5608 case 0x0a: /* fsts */
5609 case 0x0b: /* fstps */
5610 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5611 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5612 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5613 switch(op & 7) {
5614 case 0:
5615 switch(op >> 4) {
5616 case 0:
5617 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5618 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5619 gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
5620 break;
5621 case 1:
5622 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5623 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5624 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5625 break;
5626 case 2:
5627 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5628 (s->mem_index >> 2) - 1);
5629 gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
5630 break;
5631 case 3:
5632 default:
5633 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5634 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5635 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5636 break;
5637 }
5638 break;
5639 case 1:
5640 /* XXX: the corresponding CPUID bit must be tested ! */
5641 switch(op >> 4) {
5642 case 1:
5643 gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
5644 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5645 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5646 break;
5647 case 2:
5648 gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
5649 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5650 (s->mem_index >> 2) - 1);
5651 break;
5652 case 3:
5653 default:
5654 gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
5655 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5656 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5657 break;
5658 }
5659 gen_helper_fpop(cpu_env);
5660 break;
5661 default:
5662 switch(op >> 4) {
5663 case 0:
5664 gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
5665 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5666 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5667 break;
5668 case 1:
5669 gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
5670 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5671 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5672 break;
5673 case 2:
5674 gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
5675 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5676 (s->mem_index >> 2) - 1);
5677 break;
5678 case 3:
5679 default:
5680 gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
5681 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5682 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5683 break;
5684 }
5685 if ((op & 7) == 3)
5686 gen_helper_fpop(cpu_env);
5687 break;
5688 }
5689 break;
5690 case 0x0c: /* fldenv mem */
5691 if (s->cc_op != CC_OP_DYNAMIC)
5692 gen_op_set_cc_op(s->cc_op);
5693 gen_jmp_im(pc_start - s->cs_base);
5694 gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5695 break;
5696 case 0x0d: /* fldcw mem */
5697 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5698 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5699 gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
5700 break;
5701 case 0x0e: /* fnstenv mem */
5702 if (s->cc_op != CC_OP_DYNAMIC)
5703 gen_op_set_cc_op(s->cc_op);
5704 gen_jmp_im(pc_start - s->cs_base);
5705 gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5706 break;
5707 case 0x0f: /* fnstcw mem */
5708 gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
5709 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5710 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5711 break;
5712 case 0x1d: /* fldt mem */
5713 if (s->cc_op != CC_OP_DYNAMIC)
5714 gen_op_set_cc_op(s->cc_op);
5715 gen_jmp_im(pc_start - s->cs_base);
5716 gen_helper_fldt_ST0(cpu_env, cpu_A0);
5717 break;
5718 case 0x1f: /* fstpt mem */
5719 if (s->cc_op != CC_OP_DYNAMIC)
5720 gen_op_set_cc_op(s->cc_op);
5721 gen_jmp_im(pc_start - s->cs_base);
5722 gen_helper_fstt_ST0(cpu_env, cpu_A0);
5723 gen_helper_fpop(cpu_env);
5724 break;
5725 case 0x2c: /* frstor mem */
5726 if (s->cc_op != CC_OP_DYNAMIC)
5727 gen_op_set_cc_op(s->cc_op);
5728 gen_jmp_im(pc_start - s->cs_base);
5729 gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5730 break;
5731 case 0x2e: /* fnsave mem */
5732 if (s->cc_op != CC_OP_DYNAMIC)
5733 gen_op_set_cc_op(s->cc_op);
5734 gen_jmp_im(pc_start - s->cs_base);
5735 gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5736 break;
5737 case 0x2f: /* fnstsw mem */
5738 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
5739 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5740 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5741 break;
5742 case 0x3c: /* fbld */
5743 if (s->cc_op != CC_OP_DYNAMIC)
5744 gen_op_set_cc_op(s->cc_op);
5745 gen_jmp_im(pc_start - s->cs_base);
5746 gen_helper_fbld_ST0(cpu_env, cpu_A0);
5747 break;
5748 case 0x3e: /* fbstp */
5749 if (s->cc_op != CC_OP_DYNAMIC)
5750 gen_op_set_cc_op(s->cc_op);
5751 gen_jmp_im(pc_start - s->cs_base);
5752 gen_helper_fbst_ST0(cpu_env, cpu_A0);
5753 gen_helper_fpop(cpu_env);
5754 break;
5755 case 0x3d: /* fildll */
5756 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5757 (s->mem_index >> 2) - 1);
5758 gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
5759 break;
5760 case 0x3f: /* fistpll */
5761 gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
5762 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5763 (s->mem_index >> 2) - 1);
5764 gen_helper_fpop(cpu_env);
5765 break;
5766 default:
5767 goto illegal_op;
5768 }
5769 } else {
5770 /* register float ops */
5771 opreg = rm;
5772
5773 switch(op) {
5774 case 0x08: /* fld sti */
5775 gen_helper_fpush(cpu_env);
5776 gen_helper_fmov_ST0_STN(cpu_env,
5777 tcg_const_i32((opreg + 1) & 7));
5778 break;
5779 case 0x09: /* fxchg sti */
5780 case 0x29: /* fxchg4 sti, undocumented op */
5781 case 0x39: /* fxchg7 sti, undocumented op */
5782 gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
5783 break;
5784 case 0x0a: /* grp d9/2 */
5785 switch(rm) {
5786 case 0: /* fnop */
5787 /* check exceptions (FreeBSD FPU probe) */
5788 if (s->cc_op != CC_OP_DYNAMIC)
5789 gen_op_set_cc_op(s->cc_op);
5790 gen_jmp_im(pc_start - s->cs_base);
5791 gen_helper_fwait(cpu_env);
5792 break;
5793 default:
5794 goto illegal_op;
5795 }
5796 break;
5797 case 0x0c: /* grp d9/4 */
5798 switch(rm) {
5799 case 0: /* fchs */
5800 gen_helper_fchs_ST0(cpu_env);
5801 break;
5802 case 1: /* fabs */
5803 gen_helper_fabs_ST0(cpu_env);
5804 break;
5805 case 4: /* ftst */
5806 gen_helper_fldz_FT0(cpu_env);
5807 gen_helper_fcom_ST0_FT0(cpu_env);
5808 break;
5809 case 5: /* fxam */
5810 gen_helper_fxam_ST0(cpu_env);
5811 break;
5812 default:
5813 goto illegal_op;
5814 }
5815 break;
5816 case 0x0d: /* grp d9/5 */
5817 {
5818 switch(rm) {
5819 case 0:
5820 gen_helper_fpush(cpu_env);
5821 gen_helper_fld1_ST0(cpu_env);
5822 break;
5823 case 1:
5824 gen_helper_fpush(cpu_env);
5825 gen_helper_fldl2t_ST0(cpu_env);
5826 break;
5827 case 2:
5828 gen_helper_fpush(cpu_env);
5829 gen_helper_fldl2e_ST0(cpu_env);
5830 break;
5831 case 3:
5832 gen_helper_fpush(cpu_env);
5833 gen_helper_fldpi_ST0(cpu_env);
5834 break;
5835 case 4:
5836 gen_helper_fpush(cpu_env);
5837 gen_helper_fldlg2_ST0(cpu_env);
5838 break;
5839 case 5:
5840 gen_helper_fpush(cpu_env);
5841 gen_helper_fldln2_ST0(cpu_env);
5842 break;
5843 case 6:
5844 gen_helper_fpush(cpu_env);
5845 gen_helper_fldz_ST0(cpu_env);
5846 break;
5847 default:
5848 goto illegal_op;
5849 }
5850 }
5851 break;
5852 case 0x0e: /* grp d9/6 */
5853 switch(rm) {
5854 case 0: /* f2xm1 */
5855 gen_helper_f2xm1(cpu_env);
5856 break;
5857 case 1: /* fyl2x */
5858 gen_helper_fyl2x(cpu_env);
5859 break;
5860 case 2: /* fptan */
5861 gen_helper_fptan(cpu_env);
5862 break;
5863 case 3: /* fpatan */
5864 gen_helper_fpatan(cpu_env);
5865 break;
5866 case 4: /* fxtract */
5867 gen_helper_fxtract(cpu_env);
5868 break;
5869 case 5: /* fprem1 */
5870 gen_helper_fprem1(cpu_env);
5871 break;
5872 case 6: /* fdecstp */
5873 gen_helper_fdecstp(cpu_env);
5874 break;
5875 default:
5876 case 7: /* fincstp */
5877 gen_helper_fincstp(cpu_env);
5878 break;
5879 }
5880 break;
5881 case 0x0f: /* grp d9/7 */
5882 switch(rm) {
5883 case 0: /* fprem */
5884 gen_helper_fprem(cpu_env);
5885 break;
5886 case 1: /* fyl2xp1 */
5887 gen_helper_fyl2xp1(cpu_env);
5888 break;
5889 case 2: /* fsqrt */
5890 gen_helper_fsqrt(cpu_env);
5891 break;
5892 case 3: /* fsincos */
5893 gen_helper_fsincos(cpu_env);
5894 break;
5895 case 5: /* fscale */
5896 gen_helper_fscale(cpu_env);
5897 break;
5898 case 4: /* frndint */
5899 gen_helper_frndint(cpu_env);
5900 break;
5901 case 6: /* fsin */
5902 gen_helper_fsin(cpu_env);
5903 break;
5904 default:
5905 case 7: /* fcos */
5906 gen_helper_fcos(cpu_env);
5907 break;
5908 }
5909 break;
5910 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5911 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5912 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5913 {
5914 int op1;
5915
5916 op1 = op & 7;
5917 if (op >= 0x20) {
5918 gen_helper_fp_arith_STN_ST0(op1, opreg);
5919 if (op >= 0x30)
5920 gen_helper_fpop(cpu_env);
5921 } else {
5922 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5923 gen_helper_fp_arith_ST0_FT0(op1);
5924 }
5925 }
5926 break;
5927 case 0x02: /* fcom */
5928 case 0x22: /* fcom2, undocumented op */
5929 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5930 gen_helper_fcom_ST0_FT0(cpu_env);
5931 break;
5932 case 0x03: /* fcomp */
5933 case 0x23: /* fcomp3, undocumented op */
5934 case 0x32: /* fcomp5, undocumented op */
5935 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5936 gen_helper_fcom_ST0_FT0(cpu_env);
5937 gen_helper_fpop(cpu_env);
5938 break;
5939 case 0x15: /* da/5 */
5940 switch(rm) {
5941 case 1: /* fucompp */
5942 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
5943 gen_helper_fucom_ST0_FT0(cpu_env);
5944 gen_helper_fpop(cpu_env);
5945 gen_helper_fpop(cpu_env);
5946 break;
5947 default:
5948 goto illegal_op;
5949 }
5950 break;
5951 case 0x1c:
5952 switch(rm) {
5953 case 0: /* feni (287 only, just do nop here) */
5954 break;
5955 case 1: /* fdisi (287 only, just do nop here) */
5956 break;
5957 case 2: /* fclex */
5958 gen_helper_fclex(cpu_env);
5959 break;
5960 case 3: /* fninit */
5961 gen_helper_fninit(cpu_env);
5962 break;
5963 case 4: /* fsetpm (287 only, just do nop here) */
5964 break;
5965 default:
5966 goto illegal_op;
5967 }
5968 break;
5969 case 0x1d: /* fucomi */
5970 if (s->cc_op != CC_OP_DYNAMIC)
5971 gen_op_set_cc_op(s->cc_op);
5972 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5973 gen_helper_fucomi_ST0_FT0(cpu_env);
5974 s->cc_op = CC_OP_EFLAGS;
5975 break;
5976 case 0x1e: /* fcomi */
5977 if (s->cc_op != CC_OP_DYNAMIC)
5978 gen_op_set_cc_op(s->cc_op);
5979 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5980 gen_helper_fcomi_ST0_FT0(cpu_env);
5981 s->cc_op = CC_OP_EFLAGS;
5982 break;
5983 case 0x28: /* ffree sti */
5984 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
5985 break;
5986 case 0x2a: /* fst sti */
5987 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
5988 break;
5989 case 0x2b: /* fstp sti */
5990 case 0x0b: /* fstp1 sti, undocumented op */
5991 case 0x3a: /* fstp8 sti, undocumented op */
5992 case 0x3b: /* fstp9 sti, undocumented op */
5993 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
5994 gen_helper_fpop(cpu_env);
5995 break;
5996 case 0x2c: /* fucom st(i) */
5997 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5998 gen_helper_fucom_ST0_FT0(cpu_env);
5999 break;
6000 case 0x2d: /* fucomp st(i) */
6001 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6002 gen_helper_fucom_ST0_FT0(cpu_env);
6003 gen_helper_fpop(cpu_env);
6004 break;
6005 case 0x33: /* de/3 */
6006 switch(rm) {
6007 case 1: /* fcompp */
6008 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6009 gen_helper_fcom_ST0_FT0(cpu_env);
6010 gen_helper_fpop(cpu_env);
6011 gen_helper_fpop(cpu_env);
6012 break;
6013 default:
6014 goto illegal_op;
6015 }
6016 break;
6017 case 0x38: /* ffreep sti, undocumented op */
6018 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6019 gen_helper_fpop(cpu_env);
6020 break;
6021 case 0x3c: /* df/4 */
6022 switch(rm) {
6023 case 0:
6024 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
6025 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
6026 gen_op_mov_reg_T0(OT_WORD, R_EAX);
6027 break;
6028 default:
6029 goto illegal_op;
6030 }
6031 break;
6032 case 0x3d: /* fucomip */
6033 if (s->cc_op != CC_OP_DYNAMIC)
6034 gen_op_set_cc_op(s->cc_op);
6035 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6036 gen_helper_fucomi_ST0_FT0(cpu_env);
6037 gen_helper_fpop(cpu_env);
6038 s->cc_op = CC_OP_EFLAGS;
6039 break;
6040 case 0x3e: /* fcomip */
6041 if (s->cc_op != CC_OP_DYNAMIC)
6042 gen_op_set_cc_op(s->cc_op);
6043 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6044 gen_helper_fcomi_ST0_FT0(cpu_env);
6045 gen_helper_fpop(cpu_env);
6046 s->cc_op = CC_OP_EFLAGS;
6047 break;
6048 case 0x10 ... 0x13: /* fcmovxx */
6049 case 0x18 ... 0x1b:
6050 {
6051 int op1, l1;
6052 static const uint8_t fcmov_cc[8] = {
6053 (JCC_B << 1),
6054 (JCC_Z << 1),
6055 (JCC_BE << 1),
6056 (JCC_P << 1),
6057 };
6058 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6059 l1 = gen_new_label();
6060 gen_jcc1(s, s->cc_op, op1, l1);
6061 gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
6062 gen_set_label(l1);
6063 }
6064 break;
6065 default:
6066 goto illegal_op;
6067 }
6068 }
6069 break;
6070 /************************/
6071 /* string ops */
6072
6073 case 0xa4: /* movsS */
6074 case 0xa5:
6075 if ((b & 1) == 0)
6076 ot = OT_BYTE;
6077 else
6078 ot = dflag + OT_WORD;
6079
6080 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6081 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6082 } else {
6083 gen_movs(s, ot);
6084 }
6085 break;
6086
6087 case 0xaa: /* stosS */
6088 case 0xab:
6089 if ((b & 1) == 0)
6090 ot = OT_BYTE;
6091 else
6092 ot = dflag + OT_WORD;
6093
6094 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6095 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6096 } else {
6097 gen_stos(s, ot);
6098 }
6099 break;
6100 case 0xac: /* lodsS */
6101 case 0xad:
6102 if ((b & 1) == 0)
6103 ot = OT_BYTE;
6104 else
6105 ot = dflag + OT_WORD;
6106 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6107 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6108 } else {
6109 gen_lods(s, ot);
6110 }
6111 break;
6112 case 0xae: /* scasS */
6113 case 0xaf:
6114 if ((b & 1) == 0)
6115 ot = OT_BYTE;
6116 else
6117 ot = dflag + OT_WORD;
6118 if (prefixes & PREFIX_REPNZ) {
6119 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6120 } else if (prefixes & PREFIX_REPZ) {
6121 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6122 } else {
6123 gen_scas(s, ot);
6124 s->cc_op = CC_OP_SUBB + ot;
6125 }
6126 break;
6127
6128 case 0xa6: /* cmpsS */
6129 case 0xa7:
6130 if ((b & 1) == 0)
6131 ot = OT_BYTE;
6132 else
6133 ot = dflag + OT_WORD;
6134 if (prefixes & PREFIX_REPNZ) {
6135 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6136 } else if (prefixes & PREFIX_REPZ) {
6137 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6138 } else {
6139 gen_cmps(s, ot);
6140 s->cc_op = CC_OP_SUBB + ot;
6141 }
6142 break;
6143 case 0x6c: /* insS */
6144 case 0x6d:
6145 if ((b & 1) == 0)
6146 ot = OT_BYTE;
6147 else
6148 ot = dflag ? OT_LONG : OT_WORD;
6149 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6150 gen_op_andl_T0_ffff();
6151 gen_check_io(s, ot, pc_start - s->cs_base,
6152 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6153 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6154 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6155 } else {
6156 gen_ins(s, ot);
6157 if (use_icount) {
6158 gen_jmp(s, s->pc - s->cs_base);
6159 }
6160 }
6161 break;
6162 case 0x6e: /* outsS */
6163 case 0x6f:
6164 if ((b & 1) == 0)
6165 ot = OT_BYTE;
6166 else
6167 ot = dflag ? OT_LONG : OT_WORD;
6168 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6169 gen_op_andl_T0_ffff();
6170 gen_check_io(s, ot, pc_start - s->cs_base,
6171 svm_is_rep(prefixes) | 4);
6172 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6173 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6174 } else {
6175 gen_outs(s, ot);
6176 if (use_icount) {
6177 gen_jmp(s, s->pc - s->cs_base);
6178 }
6179 }
6180 break;
6181
6182 /************************/
6183 /* port I/O */
6184
6185 case 0xe4:
6186 case 0xe5:
6187 if ((b & 1) == 0)
6188 ot = OT_BYTE;
6189 else
6190 ot = dflag ? OT_LONG : OT_WORD;
6191 val = ldub_code(s->pc++);
6192 gen_op_movl_T0_im(val);
6193 gen_check_io(s, ot, pc_start - s->cs_base,
6194 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6195 if (use_icount)
6196 gen_io_start();
6197 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6198 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6199 gen_op_mov_reg_T1(ot, R_EAX);
6200 if (use_icount) {
6201 gen_io_end();
6202 gen_jmp(s, s->pc - s->cs_base);
6203 }
6204 break;
6205 case 0xe6:
6206 case 0xe7:
6207 if ((b & 1) == 0)
6208 ot = OT_BYTE;
6209 else
6210 ot = dflag ? OT_LONG : OT_WORD;
6211 val = ldub_code(s->pc++);
6212 gen_op_movl_T0_im(val);
6213 gen_check_io(s, ot, pc_start - s->cs_base,
6214 svm_is_rep(prefixes));
6215 gen_op_mov_TN_reg(ot, 1, R_EAX);
6216
6217 if (use_icount)
6218 gen_io_start();
6219 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6220 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6221 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6222 if (use_icount) {
6223 gen_io_end();
6224 gen_jmp(s, s->pc - s->cs_base);
6225 }
6226 break;
6227 case 0xec:
6228 case 0xed:
6229 if ((b & 1) == 0)
6230 ot = OT_BYTE;
6231 else
6232 ot = dflag ? OT_LONG : OT_WORD;
6233 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6234 gen_op_andl_T0_ffff();
6235 gen_check_io(s, ot, pc_start - s->cs_base,
6236 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6237 if (use_icount)
6238 gen_io_start();
6239 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6240 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6241 gen_op_mov_reg_T1(ot, R_EAX);
6242 if (use_icount) {
6243 gen_io_end();
6244 gen_jmp(s, s->pc - s->cs_base);
6245 }
6246 break;
6247 case 0xee:
6248 case 0xef:
6249 if ((b & 1) == 0)
6250 ot = OT_BYTE;
6251 else
6252 ot = dflag ? OT_LONG : OT_WORD;
6253 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6254 gen_op_andl_T0_ffff();
6255 gen_check_io(s, ot, pc_start - s->cs_base,
6256 svm_is_rep(prefixes));
6257 gen_op_mov_TN_reg(ot, 1, R_EAX);
6258
6259 if (use_icount)
6260 gen_io_start();
6261 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6262 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6263 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6264 if (use_icount) {
6265 gen_io_end();
6266 gen_jmp(s, s->pc - s->cs_base);
6267 }
6268 break;
6269
6270 /************************/
6271 /* control */
6272 case 0xc2: /* ret im */
6273 val = ldsw_code(s->pc);
6274 s->pc += 2;
6275 gen_pop_T0(s);
6276 if (CODE64(s) && s->dflag)
6277 s->dflag = 2;
6278 gen_stack_update(s, val + (2 << s->dflag));
6279 if (s->dflag == 0)
6280 gen_op_andl_T0_ffff();
6281 gen_op_jmp_T0();
6282 gen_eob(s);
6283 break;
6284 case 0xc3: /* ret */
6285 gen_pop_T0(s);
6286 gen_pop_update(s);
6287 if (s->dflag == 0)
6288 gen_op_andl_T0_ffff();
6289 gen_op_jmp_T0();
6290 gen_eob(s);
6291 break;
6292 case 0xca: /* lret im */
6293 val = ldsw_code(s->pc);
6294 s->pc += 2;
6295 do_lret:
6296 if (s->pe && !s->vm86) {
6297 if (s->cc_op != CC_OP_DYNAMIC)
6298 gen_op_set_cc_op(s->cc_op);
6299 gen_jmp_im(pc_start - s->cs_base);
6300 gen_helper_lret_protected(tcg_const_i32(s->dflag),
6301 tcg_const_i32(val));
6302 } else {
6303 gen_stack_A0(s);
6304 /* pop offset */
6305 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6306 if (s->dflag == 0)
6307 gen_op_andl_T0_ffff();
6308 /* NOTE: keeping EIP updated is not a problem in case of
6309 exception */
6310 gen_op_jmp_T0();
6311 /* pop selector */
6312 gen_op_addl_A0_im(2 << s->dflag);
6313 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6314 gen_op_movl_seg_T0_vm(R_CS);
6315 /* add stack offset */
6316 gen_stack_update(s, val + (4 << s->dflag));
6317 }
6318 gen_eob(s);
6319 break;
6320 case 0xcb: /* lret */
6321 val = 0;
6322 goto do_lret;
6323 case 0xcf: /* iret */
6324 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6325 if (!s->pe) {
6326 /* real mode */
6327 gen_helper_iret_real(tcg_const_i32(s->dflag));
6328 s->cc_op = CC_OP_EFLAGS;
6329 } else if (s->vm86) {
6330 if (s->iopl != 3) {
6331 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6332 } else {
6333 gen_helper_iret_real(tcg_const_i32(s->dflag));
6334 s->cc_op = CC_OP_EFLAGS;
6335 }
6336 } else {
6337 if (s->cc_op != CC_OP_DYNAMIC)
6338 gen_op_set_cc_op(s->cc_op);
6339 gen_jmp_im(pc_start - s->cs_base);
6340 gen_helper_iret_protected(tcg_const_i32(s->dflag),
6341 tcg_const_i32(s->pc - s->cs_base));
6342 s->cc_op = CC_OP_EFLAGS;
6343 }
6344 gen_eob(s);
6345 break;
6346 case 0xe8: /* call im */
6347 {
6348 if (dflag)
6349 tval = (int32_t)insn_get(s, OT_LONG);
6350 else
6351 tval = (int16_t)insn_get(s, OT_WORD);
6352 next_eip = s->pc - s->cs_base;
6353 tval += next_eip;
6354 if (s->dflag == 0)
6355 tval &= 0xffff;
6356 else if(!CODE64(s))
6357 tval &= 0xffffffff;
6358 gen_movtl_T0_im(next_eip);
6359 gen_push_T0(s);
6360 gen_jmp(s, tval);
6361 }
6362 break;
6363 case 0x9a: /* lcall im */
6364 {
6365 unsigned int selector, offset;
6366
6367 if (CODE64(s))
6368 goto illegal_op;
6369 ot = dflag ? OT_LONG : OT_WORD;
6370 offset = insn_get(s, ot);
6371 selector = insn_get(s, OT_WORD);
6372
6373 gen_op_movl_T0_im(selector);
6374 gen_op_movl_T1_imu(offset);
6375 }
6376 goto do_lcall;
6377 case 0xe9: /* jmp im */
6378 if (dflag)
6379 tval = (int32_t)insn_get(s, OT_LONG);
6380 else
6381 tval = (int16_t)insn_get(s, OT_WORD);
6382 tval += s->pc - s->cs_base;
6383 if (s->dflag == 0)
6384 tval &= 0xffff;
6385 else if(!CODE64(s))
6386 tval &= 0xffffffff;
6387 gen_jmp(s, tval);
6388 break;
6389 case 0xea: /* ljmp im */
6390 {
6391 unsigned int selector, offset;
6392
6393 if (CODE64(s))
6394 goto illegal_op;
6395 ot = dflag ? OT_LONG : OT_WORD;
6396 offset = insn_get(s, ot);
6397 selector = insn_get(s, OT_WORD);
6398
6399 gen_op_movl_T0_im(selector);
6400 gen_op_movl_T1_imu(offset);
6401 }
6402 goto do_ljmp;
6403 case 0xeb: /* jmp Jb */
6404 tval = (int8_t)insn_get(s, OT_BYTE);
6405 tval += s->pc - s->cs_base;
6406 if (s->dflag == 0)
6407 tval &= 0xffff;
6408 gen_jmp(s, tval);
6409 break;
6410 case 0x70 ... 0x7f: /* jcc Jb */
6411 tval = (int8_t)insn_get(s, OT_BYTE);
6412 goto do_jcc;
6413 case 0x180 ... 0x18f: /* jcc Jv */
6414 if (dflag) {
6415 tval = (int32_t)insn_get(s, OT_LONG);
6416 } else {
6417 tval = (int16_t)insn_get(s, OT_WORD);
6418 }
6419 do_jcc:
6420 next_eip = s->pc - s->cs_base;
6421 tval += next_eip;
6422 if (s->dflag == 0)
6423 tval &= 0xffff;
6424 gen_jcc(s, b, tval, next_eip);
6425 break;
6426
6427 case 0x190 ... 0x19f: /* setcc Gv */
6428 modrm = ldub_code(s->pc++);
6429 gen_setcc(s, b);
6430 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6431 break;
6432 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6433 {
6434 int l1;
6435 TCGv t0;
6436
6437 ot = dflag + OT_WORD;
6438 modrm = ldub_code(s->pc++);
6439 reg = ((modrm >> 3) & 7) | rex_r;
6440 mod = (modrm >> 6) & 3;
6441 t0 = tcg_temp_local_new();
6442 if (mod != 3) {
6443 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6444 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6445 } else {
6446 rm = (modrm & 7) | REX_B(s);
6447 gen_op_mov_v_reg(ot, t0, rm);
6448 }
6449 #ifdef TARGET_X86_64
6450 if (ot == OT_LONG) {
6451 /* XXX: specific Intel behaviour ? */
6452 l1 = gen_new_label();
6453 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6454 tcg_gen_mov_tl(cpu_regs[reg], t0);
6455 gen_set_label(l1);
6456 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
6457 } else
6458 #endif
6459 {
6460 l1 = gen_new_label();
6461 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6462 gen_op_mov_reg_v(ot, reg, t0);
6463 gen_set_label(l1);
6464 }
6465 tcg_temp_free(t0);
6466 }
6467 break;
6468
6469 /************************/
6470 /* flags */
6471 case 0x9c: /* pushf */
6472 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6473 if (s->vm86 && s->iopl != 3) {
6474 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6475 } else {
6476 if (s->cc_op != CC_OP_DYNAMIC)
6477 gen_op_set_cc_op(s->cc_op);
6478 gen_helper_read_eflags(cpu_T[0]);
6479 gen_push_T0(s);
6480 }
6481 break;
6482 case 0x9d: /* popf */
6483 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6484 if (s->vm86 && s->iopl != 3) {
6485 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6486 } else {
6487 gen_pop_T0(s);
6488 if (s->cpl == 0) {
6489 if (s->dflag) {
6490 gen_helper_write_eflags(cpu_T[0],
6491 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6492 } else {
6493 gen_helper_write_eflags(cpu_T[0],
6494 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6495 }
6496 } else {
6497 if (s->cpl <= s->iopl) {
6498 if (s->dflag) {
6499 gen_helper_write_eflags(cpu_T[0],
6500 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6501 } else {
6502 gen_helper_write_eflags(cpu_T[0],
6503 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6504 }
6505 } else {
6506 if (s->dflag) {
6507 gen_helper_write_eflags(cpu_T[0],
6508 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6509 } else {
6510 gen_helper_write_eflags(cpu_T[0],
6511 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6512 }
6513 }
6514 }
6515 gen_pop_update(s);
6516 s->cc_op = CC_OP_EFLAGS;
6517 /* abort translation because TF flag may change */
6518 gen_jmp_im(s->pc - s->cs_base);
6519 gen_eob(s);
6520 }
6521 break;
6522 case 0x9e: /* sahf */
6523 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6524 goto illegal_op;
6525 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6526 if (s->cc_op != CC_OP_DYNAMIC)
6527 gen_op_set_cc_op(s->cc_op);
6528 gen_compute_eflags(cpu_cc_src);
6529 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6530 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6531 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6532 s->cc_op = CC_OP_EFLAGS;
6533 break;
6534 case 0x9f: /* lahf */
6535 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6536 goto illegal_op;
6537 if (s->cc_op != CC_OP_DYNAMIC)
6538 gen_op_set_cc_op(s->cc_op);
6539 gen_compute_eflags(cpu_T[0]);
6540 /* Note: gen_compute_eflags() only gives the condition codes */
6541 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6542 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6543 break;
6544 case 0xf5: /* cmc */
6545 if (s->cc_op != CC_OP_DYNAMIC)
6546 gen_op_set_cc_op(s->cc_op);
6547 gen_compute_eflags(cpu_cc_src);
6548 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6549 s->cc_op = CC_OP_EFLAGS;
6550 break;
6551 case 0xf8: /* clc */
6552 if (s->cc_op != CC_OP_DYNAMIC)
6553 gen_op_set_cc_op(s->cc_op);
6554 gen_compute_eflags(cpu_cc_src);
6555 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6556 s->cc_op = CC_OP_EFLAGS;
6557 break;
6558 case 0xf9: /* stc */
6559 if (s->cc_op != CC_OP_DYNAMIC)
6560 gen_op_set_cc_op(s->cc_op);
6561 gen_compute_eflags(cpu_cc_src);
6562 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6563 s->cc_op = CC_OP_EFLAGS;
6564 break;
6565 case 0xfc: /* cld */
6566 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6567 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6568 break;
6569 case 0xfd: /* std */
6570 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6571 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6572 break;
6573
6574 /************************/
6575 /* bit operations */
6576 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6577 ot = dflag + OT_WORD;
6578 modrm = ldub_code(s->pc++);
6579 op = (modrm >> 3) & 7;
6580 mod = (modrm >> 6) & 3;
6581 rm = (modrm & 7) | REX_B(s);
6582 if (mod != 3) {
6583 s->rip_offset = 1;
6584 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6585 gen_op_ld_T0_A0(ot + s->mem_index);
6586 } else {
6587 gen_op_mov_TN_reg(ot, 0, rm);
6588 }
6589 /* load shift */
6590 val = ldub_code(s->pc++);
6591 gen_op_movl_T1_im(val);
6592 if (op < 4)
6593 goto illegal_op;
6594 op -= 4;
6595 goto bt_op;
6596 case 0x1a3: /* bt Gv, Ev */
6597 op = 0;
6598 goto do_btx;
6599 case 0x1ab: /* bts */
6600 op = 1;
6601 goto do_btx;
6602 case 0x1b3: /* btr */
6603 op = 2;
6604 goto do_btx;
6605 case 0x1bb: /* btc */
6606 op = 3;
6607 do_btx:
6608 ot = dflag + OT_WORD;
6609 modrm = ldub_code(s->pc++);
6610 reg = ((modrm >> 3) & 7) | rex_r;
6611 mod = (modrm >> 6) & 3;
6612 rm = (modrm & 7) | REX_B(s);
6613 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6614 if (mod != 3) {
6615 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6616 /* specific case: we need to add a displacement */
6617 gen_exts(ot, cpu_T[1]);
6618 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6619 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6620 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6621 gen_op_ld_T0_A0(ot + s->mem_index);
6622 } else {
6623 gen_op_mov_TN_reg(ot, 0, rm);
6624 }
6625 bt_op:
6626 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6627 switch(op) {
6628 case 0:
6629 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6630 tcg_gen_movi_tl(cpu_cc_dst, 0);
6631 break;
6632 case 1:
6633 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6634 tcg_gen_movi_tl(cpu_tmp0, 1);
6635 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6636 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6637 break;
6638 case 2:
6639 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6640 tcg_gen_movi_tl(cpu_tmp0, 1);
6641 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6642 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6643 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6644 break;
6645 default:
6646 case 3:
6647 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6648 tcg_gen_movi_tl(cpu_tmp0, 1);
6649 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6650 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6651 break;
6652 }
6653 s->cc_op = CC_OP_SARB + ot;
6654 if (op != 0) {
6655 if (mod != 3)
6656 gen_op_st_T0_A0(ot + s->mem_index);
6657 else
6658 gen_op_mov_reg_T0(ot, rm);
6659 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6660 tcg_gen_movi_tl(cpu_cc_dst, 0);
6661 }
6662 break;
6663 case 0x1bc: /* bsf */
6664 case 0x1bd: /* bsr */
6665 {
6666 int label1;
6667 TCGv t0;
6668
6669 ot = dflag + OT_WORD;
6670 modrm = ldub_code(s->pc++);
6671 reg = ((modrm >> 3) & 7) | rex_r;
6672 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
6673 gen_extu(ot, cpu_T[0]);
6674 t0 = tcg_temp_local_new();
6675 tcg_gen_mov_tl(t0, cpu_T[0]);
6676 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6677 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6678 switch(ot) {
6679 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6680 tcg_const_i32(16)); break;
6681 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6682 tcg_const_i32(32)); break;
6683 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6684 tcg_const_i32(64)); break;
6685 }
6686 gen_op_mov_reg_T0(ot, reg);
6687 } else {
6688 label1 = gen_new_label();
6689 tcg_gen_movi_tl(cpu_cc_dst, 0);
6690 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6691 if (b & 1) {
6692 gen_helper_bsr(cpu_T[0], t0);
6693 } else {
6694 gen_helper_bsf(cpu_T[0], t0);
6695 }
6696 gen_op_mov_reg_T0(ot, reg);
6697 tcg_gen_movi_tl(cpu_cc_dst, 1);
6698 gen_set_label(label1);
6699 tcg_gen_discard_tl(cpu_cc_src);
6700 s->cc_op = CC_OP_LOGICB + ot;
6701 }
6702 tcg_temp_free(t0);
6703 }
6704 break;
6705 /************************/
6706 /* bcd */
6707 case 0x27: /* daa */
6708 if (CODE64(s))
6709 goto illegal_op;
6710 if (s->cc_op != CC_OP_DYNAMIC)
6711 gen_op_set_cc_op(s->cc_op);
6712 gen_helper_daa();
6713 s->cc_op = CC_OP_EFLAGS;
6714 break;
6715 case 0x2f: /* das */
6716 if (CODE64(s))
6717 goto illegal_op;
6718 if (s->cc_op != CC_OP_DYNAMIC)
6719 gen_op_set_cc_op(s->cc_op);
6720 gen_helper_das();
6721 s->cc_op = CC_OP_EFLAGS;
6722 break;
6723 case 0x37: /* aaa */
6724 if (CODE64(s))
6725 goto illegal_op;
6726 if (s->cc_op != CC_OP_DYNAMIC)
6727 gen_op_set_cc_op(s->cc_op);
6728 gen_helper_aaa();
6729 s->cc_op = CC_OP_EFLAGS;
6730 break;
6731 case 0x3f: /* aas */
6732 if (CODE64(s))
6733 goto illegal_op;
6734 if (s->cc_op != CC_OP_DYNAMIC)
6735 gen_op_set_cc_op(s->cc_op);
6736 gen_helper_aas();
6737 s->cc_op = CC_OP_EFLAGS;
6738 break;
6739 case 0xd4: /* aam */
6740 if (CODE64(s))
6741 goto illegal_op;
6742 val = ldub_code(s->pc++);
6743 if (val == 0) {
6744 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6745 } else {
6746 gen_helper_aam(tcg_const_i32(val));
6747 s->cc_op = CC_OP_LOGICB;
6748 }
6749 break;
6750 case 0xd5: /* aad */
6751 if (CODE64(s))
6752 goto illegal_op;
6753 val = ldub_code(s->pc++);
6754 gen_helper_aad(tcg_const_i32(val));
6755 s->cc_op = CC_OP_LOGICB;
6756 break;
6757 /************************/
6758 /* misc */
6759 case 0x90: /* nop */
6760 /* XXX: correct lock test for all insn */
6761 if (prefixes & PREFIX_LOCK) {
6762 goto illegal_op;
6763 }
6764 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6765 if (REX_B(s)) {
6766 goto do_xchg_reg_eax;
6767 }
6768 if (prefixes & PREFIX_REPZ) {
6769 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6770 }
6771 break;
6772 case 0x9b: /* fwait */
6773 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6774 (HF_MP_MASK | HF_TS_MASK)) {
6775 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6776 } else {
6777 if (s->cc_op != CC_OP_DYNAMIC)
6778 gen_op_set_cc_op(s->cc_op);
6779 gen_jmp_im(pc_start - s->cs_base);
6780 gen_helper_fwait(cpu_env);
6781 }
6782 break;
6783 case 0xcc: /* int3 */
6784 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6785 break;
6786 case 0xcd: /* int N */
6787 val = ldub_code(s->pc++);
6788 if (s->vm86 && s->iopl != 3) {
6789 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6790 } else {
6791 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6792 }
6793 break;
6794 case 0xce: /* into */
6795 if (CODE64(s))
6796 goto illegal_op;
6797 if (s->cc_op != CC_OP_DYNAMIC)
6798 gen_op_set_cc_op(s->cc_op);
6799 gen_jmp_im(pc_start - s->cs_base);
6800 gen_helper_into(tcg_const_i32(s->pc - pc_start));
6801 break;
6802 #ifdef WANT_ICEBP
6803 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6804 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6805 #if 1
6806 gen_debug(s, pc_start - s->cs_base);
6807 #else
6808 /* start debug */
6809 tb_flush(cpu_single_env);
6810 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6811 #endif
6812 break;
6813 #endif
6814 case 0xfa: /* cli */
6815 if (!s->vm86) {
6816 if (s->cpl <= s->iopl) {
6817 gen_helper_cli();
6818 } else {
6819 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6820 }
6821 } else {
6822 if (s->iopl == 3) {
6823 gen_helper_cli();
6824 } else {
6825 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6826 }
6827 }
6828 break;
6829 case 0xfb: /* sti */
6830 if (!s->vm86) {
6831 if (s->cpl <= s->iopl) {
6832 gen_sti:
6833 gen_helper_sti();
6834 /* interruptions are enabled only the first insn after sti */
6835 /* If several instructions disable interrupts, only the
6836 _first_ does it */
6837 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6838 gen_helper_set_inhibit_irq();
6839 /* give a chance to handle pending irqs */
6840 gen_jmp_im(s->pc - s->cs_base);
6841 gen_eob(s);
6842 } else {
6843 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6844 }
6845 } else {
6846 if (s->iopl == 3) {
6847 goto gen_sti;
6848 } else {
6849 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6850 }
6851 }
6852 break;
6853 case 0x62: /* bound */
6854 if (CODE64(s))
6855 goto illegal_op;
6856 ot = dflag ? OT_LONG : OT_WORD;
6857 modrm = ldub_code(s->pc++);
6858 reg = (modrm >> 3) & 7;
6859 mod = (modrm >> 6) & 3;
6860 if (mod == 3)
6861 goto illegal_op;
6862 gen_op_mov_TN_reg(ot, 0, reg);
6863 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6864 gen_jmp_im(pc_start - s->cs_base);
6865 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6866 if (ot == OT_WORD)
6867 gen_helper_boundw(cpu_A0, cpu_tmp2_i32);
6868 else
6869 gen_helper_boundl(cpu_A0, cpu_tmp2_i32);
6870 break;
6871 case 0x1c8 ... 0x1cf: /* bswap reg */
6872 reg = (b & 7) | REX_B(s);
6873 #ifdef TARGET_X86_64
6874 if (dflag == 2) {
6875 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6876 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6877 gen_op_mov_reg_T0(OT_QUAD, reg);
6878 } else
6879 #endif
6880 {
6881 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6882 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6883 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6884 gen_op_mov_reg_T0(OT_LONG, reg);
6885 }
6886 break;
6887 case 0xd6: /* salc */
6888 if (CODE64(s))
6889 goto illegal_op;
6890 if (s->cc_op != CC_OP_DYNAMIC)
6891 gen_op_set_cc_op(s->cc_op);
6892 gen_compute_eflags_c(cpu_T[0]);
6893 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6894 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6895 break;
6896 case 0xe0: /* loopnz */
6897 case 0xe1: /* loopz */
6898 case 0xe2: /* loop */
6899 case 0xe3: /* jecxz */
6900 {
6901 int l1, l2, l3;
6902
6903 tval = (int8_t)insn_get(s, OT_BYTE);
6904 next_eip = s->pc - s->cs_base;
6905 tval += next_eip;
6906 if (s->dflag == 0)
6907 tval &= 0xffff;
6908
6909 l1 = gen_new_label();
6910 l2 = gen_new_label();
6911 l3 = gen_new_label();
6912 b &= 3;
6913 switch(b) {
6914 case 0: /* loopnz */
6915 case 1: /* loopz */
6916 if (s->cc_op != CC_OP_DYNAMIC)
6917 gen_op_set_cc_op(s->cc_op);
6918 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6919 gen_op_jz_ecx(s->aflag, l3);
6920 gen_compute_eflags(cpu_tmp0);
6921 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6922 if (b == 0) {
6923 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6924 } else {
6925 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6926 }
6927 break;
6928 case 2: /* loop */
6929 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6930 gen_op_jnz_ecx(s->aflag, l1);
6931 break;
6932 default:
6933 case 3: /* jcxz */
6934 gen_op_jz_ecx(s->aflag, l1);
6935 break;
6936 }
6937
6938 gen_set_label(l3);
6939 gen_jmp_im(next_eip);
6940 tcg_gen_br(l2);
6941
6942 gen_set_label(l1);
6943 gen_jmp_im(tval);
6944 gen_set_label(l2);
6945 gen_eob(s);
6946 }
6947 break;
6948 case 0x130: /* wrmsr */
6949 case 0x132: /* rdmsr */
6950 if (s->cpl != 0) {
6951 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6952 } else {
6953 if (s->cc_op != CC_OP_DYNAMIC)
6954 gen_op_set_cc_op(s->cc_op);
6955 gen_jmp_im(pc_start - s->cs_base);
6956 if (b & 2) {
6957 gen_helper_rdmsr();
6958 } else {
6959 gen_helper_wrmsr();
6960 }
6961 }
6962 break;
6963 case 0x131: /* rdtsc */
6964 if (s->cc_op != CC_OP_DYNAMIC)
6965 gen_op_set_cc_op(s->cc_op);
6966 gen_jmp_im(pc_start - s->cs_base);
6967 if (use_icount)
6968 gen_io_start();
6969 gen_helper_rdtsc();
6970 if (use_icount) {
6971 gen_io_end();
6972 gen_jmp(s, s->pc - s->cs_base);
6973 }
6974 break;
6975 case 0x133: /* rdpmc */
6976 if (s->cc_op != CC_OP_DYNAMIC)
6977 gen_op_set_cc_op(s->cc_op);
6978 gen_jmp_im(pc_start - s->cs_base);
6979 gen_helper_rdpmc();
6980 break;
6981 case 0x134: /* sysenter */
6982 /* For Intel SYSENTER is valid on 64-bit */
6983 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6984 goto illegal_op;
6985 if (!s->pe) {
6986 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6987 } else {
6988 gen_update_cc_op(s);
6989 gen_jmp_im(pc_start - s->cs_base);
6990 gen_helper_sysenter();
6991 gen_eob(s);
6992 }
6993 break;
6994 case 0x135: /* sysexit */
6995 /* For Intel SYSEXIT is valid on 64-bit */
6996 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6997 goto illegal_op;
6998 if (!s->pe) {
6999 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7000 } else {
7001 gen_update_cc_op(s);
7002 gen_jmp_im(pc_start - s->cs_base);
7003 gen_helper_sysexit(tcg_const_i32(dflag));
7004 gen_eob(s);
7005 }
7006 break;
7007 #ifdef TARGET_X86_64
7008 case 0x105: /* syscall */
7009 /* XXX: is it usable in real mode ? */
7010 gen_update_cc_op(s);
7011 gen_jmp_im(pc_start - s->cs_base);
7012 gen_helper_syscall(tcg_const_i32(s->pc - pc_start));
7013 gen_eob(s);
7014 break;
7015 case 0x107: /* sysret */
7016 if (!s->pe) {
7017 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7018 } else {
7019 gen_update_cc_op(s);
7020 gen_jmp_im(pc_start - s->cs_base);
7021 gen_helper_sysret(tcg_const_i32(s->dflag));
7022 /* condition codes are modified only in long mode */
7023 if (s->lma)
7024 s->cc_op = CC_OP_EFLAGS;
7025 gen_eob(s);
7026 }
7027 break;
7028 #endif
7029 case 0x1a2: /* cpuid */
7030 if (s->cc_op != CC_OP_DYNAMIC)
7031 gen_op_set_cc_op(s->cc_op);
7032 gen_jmp_im(pc_start - s->cs_base);
7033 gen_helper_cpuid();
7034 break;
7035 case 0xf4: /* hlt */
7036 if (s->cpl != 0) {
7037 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7038 } else {
7039 if (s->cc_op != CC_OP_DYNAMIC)
7040 gen_op_set_cc_op(s->cc_op);
7041 gen_jmp_im(pc_start - s->cs_base);
7042 gen_helper_hlt(tcg_const_i32(s->pc - pc_start));
7043 s->is_jmp = DISAS_TB_JUMP;
7044 }
7045 break;
7046 case 0x100:
7047 modrm = ldub_code(s->pc++);
7048 mod = (modrm >> 6) & 3;
7049 op = (modrm >> 3) & 7;
7050 switch(op) {
7051 case 0: /* sldt */
7052 if (!s->pe || s->vm86)
7053 goto illegal_op;
7054 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
7055 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7056 ot = OT_WORD;
7057 if (mod == 3)
7058 ot += s->dflag;
7059 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7060 break;
7061 case 2: /* lldt */
7062 if (!s->pe || s->vm86)
7063 goto illegal_op;
7064 if (s->cpl != 0) {
7065 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7066 } else {
7067 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
7068 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7069 gen_jmp_im(pc_start - s->cs_base);
7070 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7071 gen_helper_lldt(cpu_tmp2_i32);
7072 }
7073 break;
7074 case 1: /* str */
7075 if (!s->pe || s->vm86)
7076 goto illegal_op;
7077 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7078 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7079 ot = OT_WORD;
7080 if (mod == 3)
7081 ot += s->dflag;
7082 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7083 break;
7084 case 3: /* ltr */
7085 if (!s->pe || s->vm86)
7086 goto illegal_op;
7087 if (s->cpl != 0) {
7088 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7089 } else {
7090 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7091 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7092 gen_jmp_im(pc_start - s->cs_base);
7093 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7094 gen_helper_ltr(cpu_tmp2_i32);
7095 }
7096 break;
7097 case 4: /* verr */
7098 case 5: /* verw */
7099 if (!s->pe || s->vm86)
7100 goto illegal_op;
7101 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7102 if (s->cc_op != CC_OP_DYNAMIC)
7103 gen_op_set_cc_op(s->cc_op);
7104 if (op == 4)
7105 gen_helper_verr(cpu_T[0]);
7106 else
7107 gen_helper_verw(cpu_T[0]);
7108 s->cc_op = CC_OP_EFLAGS;
7109 break;
7110 default:
7111 goto illegal_op;
7112 }
7113 break;
7114 case 0x101:
7115 modrm = ldub_code(s->pc++);
7116 mod = (modrm >> 6) & 3;
7117 op = (modrm >> 3) & 7;
7118 rm = modrm & 7;
7119 switch(op) {
7120 case 0: /* sgdt */
7121 if (mod == 3)
7122 goto illegal_op;
7123 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7124 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7125 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7126 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7127 gen_add_A0_im(s, 2);
7128 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7129 if (!s->dflag)
7130 gen_op_andl_T0_im(0xffffff);
7131 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7132 break;
7133 case 1:
7134 if (mod == 3) {
7135 switch (rm) {
7136 case 0: /* monitor */
7137 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7138 s->cpl != 0)
7139 goto illegal_op;
7140 if (s->cc_op != CC_OP_DYNAMIC)
7141 gen_op_set_cc_op(s->cc_op);
7142 gen_jmp_im(pc_start - s->cs_base);
7143 #ifdef TARGET_X86_64
7144 if (s->aflag == 2) {
7145 gen_op_movq_A0_reg(R_EAX);
7146 } else
7147 #endif
7148 {
7149 gen_op_movl_A0_reg(R_EAX);
7150 if (s->aflag == 0)
7151 gen_op_andl_A0_ffff();
7152 }
7153 gen_add_A0_ds_seg(s);
7154 gen_helper_monitor(cpu_A0);
7155 break;
7156 case 1: /* mwait */
7157 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7158 s->cpl != 0)
7159 goto illegal_op;
7160 gen_update_cc_op(s);
7161 gen_jmp_im(pc_start - s->cs_base);
7162 gen_helper_mwait(tcg_const_i32(s->pc - pc_start));
7163 gen_eob(s);
7164 break;
7165 default:
7166 goto illegal_op;
7167 }
7168 } else { /* sidt */
7169 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7170 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7171 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7172 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7173 gen_add_A0_im(s, 2);
7174 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7175 if (!s->dflag)
7176 gen_op_andl_T0_im(0xffffff);
7177 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7178 }
7179 break;
7180 case 2: /* lgdt */
7181 case 3: /* lidt */
7182 if (mod == 3) {
7183 if (s->cc_op != CC_OP_DYNAMIC)
7184 gen_op_set_cc_op(s->cc_op);
7185 gen_jmp_im(pc_start - s->cs_base);
7186 switch(rm) {
7187 case 0: /* VMRUN */
7188 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7189 goto illegal_op;
7190 if (s->cpl != 0) {
7191 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7192 break;
7193 } else {
7194 gen_helper_vmrun(tcg_const_i32(s->aflag),
7195 tcg_const_i32(s->pc - pc_start));
7196 tcg_gen_exit_tb(0);
7197 s->is_jmp = DISAS_TB_JUMP;
7198 }
7199 break;
7200 case 1: /* VMMCALL */
7201 if (!(s->flags & HF_SVME_MASK))
7202 goto illegal_op;
7203 gen_helper_vmmcall();
7204 break;
7205 case 2: /* VMLOAD */
7206 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7207 goto illegal_op;
7208 if (s->cpl != 0) {
7209 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7210 break;
7211 } else {
7212 gen_helper_vmload(tcg_const_i32(s->aflag));
7213 }
7214 break;
7215 case 3: /* VMSAVE */
7216 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7217 goto illegal_op;
7218 if (s->cpl != 0) {
7219 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7220 break;
7221 } else {
7222 gen_helper_vmsave(tcg_const_i32(s->aflag));
7223 }
7224 break;
7225 case 4: /* STGI */
7226 if ((!(s->flags & HF_SVME_MASK) &&
7227 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7228 !s->pe)
7229 goto illegal_op;
7230 if (s->cpl != 0) {
7231 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7232 break;
7233 } else {
7234 gen_helper_stgi();
7235 }
7236 break;
7237 case 5: /* CLGI */
7238 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7239 goto illegal_op;
7240 if (s->cpl != 0) {
7241 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7242 break;
7243 } else {
7244 gen_helper_clgi();
7245 }
7246 break;
7247 case 6: /* SKINIT */
7248 if ((!(s->flags & HF_SVME_MASK) &&
7249 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7250 !s->pe)
7251 goto illegal_op;
7252 gen_helper_skinit();
7253 break;
7254 case 7: /* INVLPGA */
7255 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7256 goto illegal_op;
7257 if (s->cpl != 0) {
7258 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7259 break;
7260 } else {
7261 gen_helper_invlpga(tcg_const_i32(s->aflag));
7262 }
7263 break;
7264 default:
7265 goto illegal_op;
7266 }
7267 } else if (s->cpl != 0) {
7268 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7269 } else {
7270 gen_svm_check_intercept(s, pc_start,
7271 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7272 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7273 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7274 gen_add_A0_im(s, 2);
7275 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7276 if (!s->dflag)
7277 gen_op_andl_T0_im(0xffffff);
7278 if (op == 2) {
7279 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7280 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7281 } else {
7282 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7283 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7284 }
7285 }
7286 break;
7287 case 4: /* smsw */
7288 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7289 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7290 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7291 #else
7292 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7293 #endif
7294 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7295 break;
7296 case 6: /* lmsw */
7297 if (s->cpl != 0) {
7298 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7299 } else {
7300 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7301 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7302 gen_helper_lmsw(cpu_T[0]);
7303 gen_jmp_im(s->pc - s->cs_base);
7304 gen_eob(s);
7305 }
7306 break;
7307 case 7:
7308 if (mod != 3) { /* invlpg */
7309 if (s->cpl != 0) {
7310 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7311 } else {
7312 if (s->cc_op != CC_OP_DYNAMIC)
7313 gen_op_set_cc_op(s->cc_op);
7314 gen_jmp_im(pc_start - s->cs_base);
7315 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7316 gen_helper_invlpg(cpu_A0);
7317 gen_jmp_im(s->pc - s->cs_base);
7318 gen_eob(s);
7319 }
7320 } else {
7321 switch (rm) {
7322 case 0: /* swapgs */
7323 #ifdef TARGET_X86_64
7324 if (CODE64(s)) {
7325 if (s->cpl != 0) {
7326 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7327 } else {
7328 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7329 offsetof(CPUX86State,segs[R_GS].base));
7330 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7331 offsetof(CPUX86State,kernelgsbase));
7332 tcg_gen_st_tl(cpu_T[1], cpu_env,
7333 offsetof(CPUX86State,segs[R_GS].base));
7334 tcg_gen_st_tl(cpu_T[0], cpu_env,
7335 offsetof(CPUX86State,kernelgsbase));
7336 }
7337 } else
7338 #endif
7339 {
7340 goto illegal_op;
7341 }
7342 break;
7343 case 1: /* rdtscp */
7344 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7345 goto illegal_op;
7346 if (s->cc_op != CC_OP_DYNAMIC)
7347 gen_op_set_cc_op(s->cc_op);
7348 gen_jmp_im(pc_start - s->cs_base);
7349 if (use_icount)
7350 gen_io_start();
7351 gen_helper_rdtscp();
7352 if (use_icount) {
7353 gen_io_end();
7354 gen_jmp(s, s->pc - s->cs_base);
7355 }
7356 break;
7357 default:
7358 goto illegal_op;
7359 }
7360 }
7361 break;
7362 default:
7363 goto illegal_op;
7364 }
7365 break;
7366 case 0x108: /* invd */
7367 case 0x109: /* wbinvd */
7368 if (s->cpl != 0) {
7369 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7370 } else {
7371 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7372 /* nothing to do */
7373 }
7374 break;
7375 case 0x63: /* arpl or movslS (x86_64) */
7376 #ifdef TARGET_X86_64
7377 if (CODE64(s)) {
7378 int d_ot;
7379 /* d_ot is the size of destination */
7380 d_ot = dflag + OT_WORD;
7381
7382 modrm = ldub_code(s->pc++);
7383 reg = ((modrm >> 3) & 7) | rex_r;
7384 mod = (modrm >> 6) & 3;
7385 rm = (modrm & 7) | REX_B(s);
7386
7387 if (mod == 3) {
7388 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7389 /* sign extend */
7390 if (d_ot == OT_QUAD)
7391 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7392 gen_op_mov_reg_T0(d_ot, reg);
7393 } else {
7394 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7395 if (d_ot == OT_QUAD) {
7396 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7397 } else {
7398 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7399 }
7400 gen_op_mov_reg_T0(d_ot, reg);
7401 }
7402 } else
7403 #endif
7404 {
7405 int label1;
7406 TCGv t0, t1, t2, a0;
7407
7408 if (!s->pe || s->vm86)
7409 goto illegal_op;
7410 t0 = tcg_temp_local_new();
7411 t1 = tcg_temp_local_new();
7412 t2 = tcg_temp_local_new();
7413 ot = OT_WORD;
7414 modrm = ldub_code(s->pc++);
7415 reg = (modrm >> 3) & 7;
7416 mod = (modrm >> 6) & 3;
7417 rm = modrm & 7;
7418 if (mod != 3) {
7419 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7420 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7421 a0 = tcg_temp_local_new();
7422 tcg_gen_mov_tl(a0, cpu_A0);
7423 } else {
7424 gen_op_mov_v_reg(ot, t0, rm);
7425 TCGV_UNUSED(a0);
7426 }
7427 gen_op_mov_v_reg(ot, t1, reg);
7428 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7429 tcg_gen_andi_tl(t1, t1, 3);
7430 tcg_gen_movi_tl(t2, 0);
7431 label1 = gen_new_label();
7432 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7433 tcg_gen_andi_tl(t0, t0, ~3);
7434 tcg_gen_or_tl(t0, t0, t1);
7435 tcg_gen_movi_tl(t2, CC_Z);
7436 gen_set_label(label1);
7437 if (mod != 3) {
7438 gen_op_st_v(ot + s->mem_index, t0, a0);
7439 tcg_temp_free(a0);
7440 } else {
7441 gen_op_mov_reg_v(ot, rm, t0);
7442 }
7443 if (s->cc_op != CC_OP_DYNAMIC)
7444 gen_op_set_cc_op(s->cc_op);
7445 gen_compute_eflags(cpu_cc_src);
7446 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7447 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7448 s->cc_op = CC_OP_EFLAGS;
7449 tcg_temp_free(t0);
7450 tcg_temp_free(t1);
7451 tcg_temp_free(t2);
7452 }
7453 break;
7454 case 0x102: /* lar */
7455 case 0x103: /* lsl */
7456 {
7457 int label1;
7458 TCGv t0;
7459 if (!s->pe || s->vm86)
7460 goto illegal_op;
7461 ot = dflag ? OT_LONG : OT_WORD;
7462 modrm = ldub_code(s->pc++);
7463 reg = ((modrm >> 3) & 7) | rex_r;
7464 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7465 t0 = tcg_temp_local_new();
7466 if (s->cc_op != CC_OP_DYNAMIC)
7467 gen_op_set_cc_op(s->cc_op);
7468 if (b == 0x102)
7469 gen_helper_lar(t0, cpu_T[0]);
7470 else
7471 gen_helper_lsl(t0, cpu_T[0]);
7472 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7473 label1 = gen_new_label();
7474 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7475 gen_op_mov_reg_v(ot, reg, t0);
7476 gen_set_label(label1);
7477 s->cc_op = CC_OP_EFLAGS;
7478 tcg_temp_free(t0);
7479 }
7480 break;
7481 case 0x118:
7482 modrm = ldub_code(s->pc++);
7483 mod = (modrm >> 6) & 3;
7484 op = (modrm >> 3) & 7;
7485 switch(op) {
7486 case 0: /* prefetchnta */
7487 case 1: /* prefetchnt0 */
7488 case 2: /* prefetchnt0 */
7489 case 3: /* prefetchnt0 */
7490 if (mod == 3)
7491 goto illegal_op;
7492 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7493 /* nothing more to do */
7494 break;
7495 default: /* nop (multi byte) */
7496 gen_nop_modrm(s, modrm);
7497 break;
7498 }
7499 break;
7500 case 0x119 ... 0x11f: /* nop (multi byte) */
7501 modrm = ldub_code(s->pc++);
7502 gen_nop_modrm(s, modrm);
7503 break;
7504 case 0x120: /* mov reg, crN */
7505 case 0x122: /* mov crN, reg */
7506 if (s->cpl != 0) {
7507 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7508 } else {
7509 modrm = ldub_code(s->pc++);
7510 if ((modrm & 0xc0) != 0xc0)
7511 goto illegal_op;
7512 rm = (modrm & 7) | REX_B(s);
7513 reg = ((modrm >> 3) & 7) | rex_r;
7514 if (CODE64(s))
7515 ot = OT_QUAD;
7516 else
7517 ot = OT_LONG;
7518 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7519 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7520 reg = 8;
7521 }
7522 switch(reg) {
7523 case 0:
7524 case 2:
7525 case 3:
7526 case 4:
7527 case 8:
7528 if (s->cc_op != CC_OP_DYNAMIC)
7529 gen_op_set_cc_op(s->cc_op);
7530 gen_jmp_im(pc_start - s->cs_base);
7531 if (b & 2) {
7532 gen_op_mov_TN_reg(ot, 0, rm);
7533 gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]);
7534 gen_jmp_im(s->pc - s->cs_base);
7535 gen_eob(s);
7536 } else {
7537 gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg));
7538 gen_op_mov_reg_T0(ot, rm);
7539 }
7540 break;
7541 default:
7542 goto illegal_op;
7543 }
7544 }
7545 break;
7546 case 0x121: /* mov reg, drN */
7547 case 0x123: /* mov drN, reg */
7548 if (s->cpl != 0) {
7549 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7550 } else {
7551 modrm = ldub_code(s->pc++);
7552 if ((modrm & 0xc0) != 0xc0)
7553 goto illegal_op;
7554 rm = (modrm & 7) | REX_B(s);
7555 reg = ((modrm >> 3) & 7) | rex_r;
7556 if (CODE64(s))
7557 ot = OT_QUAD;
7558 else
7559 ot = OT_LONG;
7560 /* XXX: do it dynamically with CR4.DE bit */
7561 if (reg == 4 || reg == 5 || reg >= 8)
7562 goto illegal_op;
7563 if (b & 2) {
7564 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7565 gen_op_mov_TN_reg(ot, 0, rm);
7566 gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]);
7567 gen_jmp_im(s->pc - s->cs_base);
7568 gen_eob(s);
7569 } else {
7570 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7571 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7572 gen_op_mov_reg_T0(ot, rm);
7573 }
7574 }
7575 break;
7576 case 0x106: /* clts */
7577 if (s->cpl != 0) {
7578 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7579 } else {
7580 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7581 gen_helper_clts();
7582 /* abort block because static cpu state changed */
7583 gen_jmp_im(s->pc - s->cs_base);
7584 gen_eob(s);
7585 }
7586 break;
7587 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7588 case 0x1c3: /* MOVNTI reg, mem */
7589 if (!(s->cpuid_features & CPUID_SSE2))
7590 goto illegal_op;
7591 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7592 modrm = ldub_code(s->pc++);
7593 mod = (modrm >> 6) & 3;
7594 if (mod == 3)
7595 goto illegal_op;
7596 reg = ((modrm >> 3) & 7) | rex_r;
7597 /* generate a generic store */
7598 gen_ldst_modrm(s, modrm, ot, reg, 1);
7599 break;
7600 case 0x1ae:
7601 modrm = ldub_code(s->pc++);
7602 mod = (modrm >> 6) & 3;
7603 op = (modrm >> 3) & 7;
7604 switch(op) {
7605 case 0: /* fxsave */
7606 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7607 (s->prefix & PREFIX_LOCK))
7608 goto illegal_op;
7609 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7610 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7611 break;
7612 }
7613 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7614 if (s->cc_op != CC_OP_DYNAMIC)
7615 gen_op_set_cc_op(s->cc_op);
7616 gen_jmp_im(pc_start - s->cs_base);
7617 gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
7618 break;
7619 case 1: /* fxrstor */
7620 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7621 (s->prefix & PREFIX_LOCK))
7622 goto illegal_op;
7623 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7624 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7625 break;
7626 }
7627 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7628 if (s->cc_op != CC_OP_DYNAMIC)
7629 gen_op_set_cc_op(s->cc_op);
7630 gen_jmp_im(pc_start - s->cs_base);
7631 gen_helper_fxrstor(cpu_env, cpu_A0,
7632 tcg_const_i32((s->dflag == 2)));
7633 break;
7634 case 2: /* ldmxcsr */
7635 case 3: /* stmxcsr */
7636 if (s->flags & HF_TS_MASK) {
7637 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7638 break;
7639 }
7640 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7641 mod == 3)
7642 goto illegal_op;
7643 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7644 if (op == 2) {
7645 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7646 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7647 gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
7648 } else {
7649 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7650 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7651 }
7652 break;
7653 case 5: /* lfence */
7654 case 6: /* mfence */
7655 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2))
7656 goto illegal_op;
7657 break;
7658 case 7: /* sfence / clflush */
7659 if ((modrm & 0xc7) == 0xc0) {
7660 /* sfence */
7661 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7662 if (!(s->cpuid_features & CPUID_SSE))
7663 goto illegal_op;
7664 } else {
7665 /* clflush */
7666 if (!(s->cpuid_features & CPUID_CLFLUSH))
7667 goto illegal_op;
7668 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7669 }
7670 break;
7671 default:
7672 goto illegal_op;
7673 }
7674 break;
7675 case 0x10d: /* 3DNow! prefetch(w) */
7676 modrm = ldub_code(s->pc++);
7677 mod = (modrm >> 6) & 3;
7678 if (mod == 3)
7679 goto illegal_op;
7680 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7681 /* ignore for now */
7682 break;
7683 case 0x1aa: /* rsm */
7684 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7685 if (!(s->flags & HF_SMM_MASK))
7686 goto illegal_op;
7687 gen_update_cc_op(s);
7688 gen_jmp_im(s->pc - s->cs_base);
7689 gen_helper_rsm();
7690 gen_eob(s);
7691 break;
7692 case 0x1b8: /* SSE4.2 popcnt */
7693 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7694 PREFIX_REPZ)
7695 goto illegal_op;
7696 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7697 goto illegal_op;
7698
7699 modrm = ldub_code(s->pc++);
7700 reg = ((modrm >> 3) & 7);
7701
7702 if (s->prefix & PREFIX_DATA)
7703 ot = OT_WORD;
7704 else if (s->dflag != 2)
7705 ot = OT_LONG;
7706 else
7707 ot = OT_QUAD;
7708
7709 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7710 gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
7711 gen_op_mov_reg_T0(ot, reg);
7712
7713 s->cc_op = CC_OP_EFLAGS;
7714 break;
7715 case 0x10e ... 0x10f:
7716 /* 3DNow! instructions, ignore prefixes */
7717 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7718 case 0x110 ... 0x117:
7719 case 0x128 ... 0x12f:
7720 case 0x138 ... 0x13a:
7721 case 0x150 ... 0x179:
7722 case 0x17c ... 0x17f:
7723 case 0x1c2:
7724 case 0x1c4 ... 0x1c6:
7725 case 0x1d0 ... 0x1fe:
7726 gen_sse(s, b, pc_start, rex_r);
7727 break;
7728 default:
7729 goto illegal_op;
7730 }
7731 /* lock generation */
7732 if (s->prefix & PREFIX_LOCK)
7733 gen_helper_unlock();
7734 return s->pc;
7735 illegal_op:
7736 if (s->prefix & PREFIX_LOCK)
7737 gen_helper_unlock();
7738 /* XXX: ensure that no lock was generated */
7739 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7740 return s->pc;
7741 }
7742
7743 void optimize_flags_init(void)
7744 {
7745 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7746 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7747 offsetof(CPUX86State, cc_op), "cc_op");
7748 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
7749 "cc_src");
7750 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
7751 "cc_dst");
7752 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_tmp),
7753 "cc_tmp");
7754
7755 #ifdef TARGET_X86_64
7756 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7757 offsetof(CPUX86State, regs[R_EAX]), "rax");
7758 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7759 offsetof(CPUX86State, regs[R_ECX]), "rcx");
7760 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7761 offsetof(CPUX86State, regs[R_EDX]), "rdx");
7762 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7763 offsetof(CPUX86State, regs[R_EBX]), "rbx");
7764 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7765 offsetof(CPUX86State, regs[R_ESP]), "rsp");
7766 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7767 offsetof(CPUX86State, regs[R_EBP]), "rbp");
7768 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7769 offsetof(CPUX86State, regs[R_ESI]), "rsi");
7770 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7771 offsetof(CPUX86State, regs[R_EDI]), "rdi");
7772 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7773 offsetof(CPUX86State, regs[8]), "r8");
7774 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7775 offsetof(CPUX86State, regs[9]), "r9");
7776 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7777 offsetof(CPUX86State, regs[10]), "r10");
7778 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7779 offsetof(CPUX86State, regs[11]), "r11");
7780 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7781 offsetof(CPUX86State, regs[12]), "r12");
7782 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7783 offsetof(CPUX86State, regs[13]), "r13");
7784 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7785 offsetof(CPUX86State, regs[14]), "r14");
7786 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7787 offsetof(CPUX86State, regs[15]), "r15");
7788 #else
7789 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7790 offsetof(CPUX86State, regs[R_EAX]), "eax");
7791 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7792 offsetof(CPUX86State, regs[R_ECX]), "ecx");
7793 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7794 offsetof(CPUX86State, regs[R_EDX]), "edx");
7795 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7796 offsetof(CPUX86State, regs[R_EBX]), "ebx");
7797 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7798 offsetof(CPUX86State, regs[R_ESP]), "esp");
7799 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7800 offsetof(CPUX86State, regs[R_EBP]), "ebp");
7801 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7802 offsetof(CPUX86State, regs[R_ESI]), "esi");
7803 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7804 offsetof(CPUX86State, regs[R_EDI]), "edi");
7805 #endif
7806
7807 /* register helpers */
7808 #define GEN_HELPER 2
7809 #include "helper.h"
7810 }
7811
7812 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7813 basic block 'tb'. If search_pc is TRUE, also generate PC
7814 information for each intermediate instruction. */
7815 static inline void gen_intermediate_code_internal(CPUX86State *env,
7816 TranslationBlock *tb,
7817 int search_pc)
7818 {
7819 DisasContext dc1, *dc = &dc1;
7820 target_ulong pc_ptr;
7821 uint16_t *gen_opc_end;
7822 CPUBreakpoint *bp;
7823 int j, lj;
7824 uint64_t flags;
7825 target_ulong pc_start;
7826 target_ulong cs_base;
7827 int num_insns;
7828 int max_insns;
7829
7830 /* generate intermediate code */
7831 pc_start = tb->pc;
7832 cs_base = tb->cs_base;
7833 flags = tb->flags;
7834
7835 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7836 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7837 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7838 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7839 dc->f_st = 0;
7840 dc->vm86 = (flags >> VM_SHIFT) & 1;
7841 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7842 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7843 dc->tf = (flags >> TF_SHIFT) & 1;
7844 dc->singlestep_enabled = env->singlestep_enabled;
7845 dc->cc_op = CC_OP_DYNAMIC;
7846 dc->cs_base = cs_base;
7847 dc->tb = tb;
7848 dc->popl_esp_hack = 0;
7849 /* select memory access functions */
7850 dc->mem_index = 0;
7851 if (flags & HF_SOFTMMU_MASK) {
7852 if (dc->cpl == 3)
7853 dc->mem_index = 2 * 4;
7854 else
7855 dc->mem_index = 1 * 4;
7856 }
7857 dc->cpuid_features = env->cpuid_features;
7858 dc->cpuid_ext_features = env->cpuid_ext_features;
7859 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7860 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7861 #ifdef TARGET_X86_64
7862 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7863 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7864 #endif
7865 dc->flags = flags;
7866 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7867 (flags & HF_INHIBIT_IRQ_MASK)
7868 #ifndef CONFIG_SOFTMMU
7869 || (flags & HF_SOFTMMU_MASK)
7870 #endif
7871 );
7872 #if 0
7873 /* check addseg logic */
7874 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7875 printf("ERROR addseg\n");
7876 #endif
7877
7878 cpu_T[0] = tcg_temp_new();
7879 cpu_T[1] = tcg_temp_new();
7880 cpu_A0 = tcg_temp_new();
7881 cpu_T3 = tcg_temp_new();
7882
7883 cpu_tmp0 = tcg_temp_new();
7884 cpu_tmp1_i64 = tcg_temp_new_i64();
7885 cpu_tmp2_i32 = tcg_temp_new_i32();
7886 cpu_tmp3_i32 = tcg_temp_new_i32();
7887 cpu_tmp4 = tcg_temp_new();
7888 cpu_tmp5 = tcg_temp_new();
7889 cpu_ptr0 = tcg_temp_new_ptr();
7890 cpu_ptr1 = tcg_temp_new_ptr();
7891
7892 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7893
7894 dc->is_jmp = DISAS_NEXT;
7895 pc_ptr = pc_start;
7896 lj = -1;
7897 num_insns = 0;
7898 max_insns = tb->cflags & CF_COUNT_MASK;
7899 if (max_insns == 0)
7900 max_insns = CF_COUNT_MASK;
7901
7902 gen_icount_start();
7903 for(;;) {
7904 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7905 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7906 if (bp->pc == pc_ptr &&
7907 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7908 gen_debug(dc, pc_ptr - dc->cs_base);
7909 break;
7910 }
7911 }
7912 }
7913 if (search_pc) {
7914 j = gen_opc_ptr - gen_opc_buf;
7915 if (lj < j) {
7916 lj++;
7917 while (lj < j)
7918 gen_opc_instr_start[lj++] = 0;
7919 }
7920 gen_opc_pc[lj] = pc_ptr;
7921 gen_opc_cc_op[lj] = dc->cc_op;
7922 gen_opc_instr_start[lj] = 1;
7923 gen_opc_icount[lj] = num_insns;
7924 }
7925 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7926 gen_io_start();
7927
7928 pc_ptr = disas_insn(dc, pc_ptr);
7929 num_insns++;
7930 /* stop translation if indicated */
7931 if (dc->is_jmp)
7932 break;
7933 /* if single step mode, we generate only one instruction and
7934 generate an exception */
7935 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7936 the flag and abort the translation to give the irqs a
7937 change to be happen */
7938 if (dc->tf || dc->singlestep_enabled ||
7939 (flags & HF_INHIBIT_IRQ_MASK)) {
7940 gen_jmp_im(pc_ptr - dc->cs_base);
7941 gen_eob(dc);
7942 break;
7943 }
7944 /* if too long translation, stop generation too */
7945 if (gen_opc_ptr >= gen_opc_end ||
7946 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7947 num_insns >= max_insns) {
7948 gen_jmp_im(pc_ptr - dc->cs_base);
7949 gen_eob(dc);
7950 break;
7951 }
7952 if (singlestep) {
7953 gen_jmp_im(pc_ptr - dc->cs_base);
7954 gen_eob(dc);
7955 break;
7956 }
7957 }
7958 if (tb->cflags & CF_LAST_IO)
7959 gen_io_end();
7960 gen_icount_end(tb, num_insns);
7961 *gen_opc_ptr = INDEX_op_end;
7962 /* we don't forget to fill the last values */
7963 if (search_pc) {
7964 j = gen_opc_ptr - gen_opc_buf;
7965 lj++;
7966 while (lj <= j)
7967 gen_opc_instr_start[lj++] = 0;
7968 }
7969
7970 #ifdef DEBUG_DISAS
7971 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7972 int disas_flags;
7973 qemu_log("----------------\n");
7974 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7975 #ifdef TARGET_X86_64
7976 if (dc->code64)
7977 disas_flags = 2;
7978 else
7979 #endif
7980 disas_flags = !dc->code32;
7981 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
7982 qemu_log("\n");
7983 }
7984 #endif
7985
7986 if (!search_pc) {
7987 tb->size = pc_ptr - pc_start;
7988 tb->icount = num_insns;
7989 }
7990 }
7991
7992 void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
7993 {
7994 gen_intermediate_code_internal(env, tb, 0);
7995 }
7996
7997 void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
7998 {
7999 gen_intermediate_code_internal(env, tb, 1);
8000 }
8001
8002 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
8003 {
8004 int cc_op;
8005 #ifdef DEBUG_DISAS
8006 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
8007 int i;
8008 qemu_log("RESTORE:\n");
8009 for(i = 0;i <= pc_pos; i++) {
8010 if (gen_opc_instr_start[i]) {
8011 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
8012 }
8013 }
8014 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
8015 pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
8016 (uint32_t)tb->cs_base);
8017 }
8018 #endif
8019 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
8020 cc_op = gen_opc_cc_op[pc_pos];
8021 if (cc_op != CC_OP_DYNAMIC)
8022 env->cc_op = cc_op;
8023 }
AR7 emulation for QEMU