2 * Aspeed SD Host Controller
3 * Eddie James <eajames@linux.ibm.com>
5 * Copyright (C) 2019 IBM Corp
6 * SPDX-License-Identifer: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/error-report.h"
12 #include "hw/sd/aspeed_sdhci.h"
13 #include "qapi/error.h"
15 #include "migration/vmstate.h"
16 #include "hw/qdev-properties.h"
18 #define ASPEED_SDHCI_INFO 0x00
19 #define ASPEED_SDHCI_INFO_RESET 0x00030000
20 #define ASPEED_SDHCI_DEBOUNCE 0x04
21 #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
22 #define ASPEED_SDHCI_BUS 0x08
23 #define ASPEED_SDHCI_SDIO_140 0x10
24 #define ASPEED_SDHCI_SDIO_148 0x18
25 #define ASPEED_SDHCI_SDIO_240 0x20
26 #define ASPEED_SDHCI_SDIO_248 0x28
27 #define ASPEED_SDHCI_WP_POL 0xec
28 #define ASPEED_SDHCI_CARD_DET 0xf0
29 #define ASPEED_SDHCI_IRQ_STAT 0xfc
31 #define TO_REG(addr) ((addr) / sizeof(uint32_t))
33 static uint64_t aspeed_sdhci_read(void *opaque
, hwaddr addr
, unsigned int size
)
36 AspeedSDHCIState
*sdhci
= opaque
;
39 case ASPEED_SDHCI_SDIO_140
:
40 val
= (uint32_t)sdhci
->slots
[0].capareg
;
42 case ASPEED_SDHCI_SDIO_148
:
43 val
= (uint32_t)sdhci
->slots
[0].maxcurr
;
45 case ASPEED_SDHCI_SDIO_240
:
46 val
= (uint32_t)sdhci
->slots
[1].capareg
;
48 case ASPEED_SDHCI_SDIO_248
:
49 val
= (uint32_t)sdhci
->slots
[1].maxcurr
;
52 if (addr
< ASPEED_SDHCI_REG_SIZE
) {
53 val
= sdhci
->regs
[TO_REG(addr
)];
55 qemu_log_mask(LOG_GUEST_ERROR
,
56 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx
"\n",
64 static void aspeed_sdhci_write(void *opaque
, hwaddr addr
, uint64_t val
,
67 AspeedSDHCIState
*sdhci
= opaque
;
70 case ASPEED_SDHCI_SDIO_140
:
71 sdhci
->slots
[0].capareg
= (uint64_t)(uint32_t)val
;
73 case ASPEED_SDHCI_SDIO_148
:
74 sdhci
->slots
[0].maxcurr
= (uint64_t)(uint32_t)val
;
76 case ASPEED_SDHCI_SDIO_240
:
77 sdhci
->slots
[1].capareg
= (uint64_t)(uint32_t)val
;
79 case ASPEED_SDHCI_SDIO_248
:
80 sdhci
->slots
[1].maxcurr
= (uint64_t)(uint32_t)val
;
83 if (addr
< ASPEED_SDHCI_REG_SIZE
) {
84 sdhci
->regs
[TO_REG(addr
)] = (uint32_t)val
;
86 qemu_log_mask(LOG_GUEST_ERROR
,
87 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx
"\n",
93 static const MemoryRegionOps aspeed_sdhci_ops
= {
94 .read
= aspeed_sdhci_read
,
95 .write
= aspeed_sdhci_write
,
96 .endianness
= DEVICE_NATIVE_ENDIAN
,
97 .valid
.min_access_size
= 4,
98 .valid
.max_access_size
= 4,
101 static void aspeed_sdhci_set_irq(void *opaque
, int n
, int level
)
103 AspeedSDHCIState
*sdhci
= opaque
;
106 sdhci
->regs
[TO_REG(ASPEED_SDHCI_IRQ_STAT
)] |= BIT(n
);
108 qemu_irq_raise(sdhci
->irq
);
110 sdhci
->regs
[TO_REG(ASPEED_SDHCI_IRQ_STAT
)] &= ~BIT(n
);
112 qemu_irq_lower(sdhci
->irq
);
116 static void aspeed_sdhci_realize(DeviceState
*dev
, Error
**errp
)
119 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
120 AspeedSDHCIState
*sdhci
= ASPEED_SDHCI(dev
);
122 /* Create input irqs for the slots */
123 qdev_init_gpio_in_named_with_opaque(DEVICE(sbd
), aspeed_sdhci_set_irq
,
124 sdhci
, NULL
, sdhci
->num_slots
);
126 sysbus_init_irq(sbd
, &sdhci
->irq
);
127 memory_region_init_io(&sdhci
->iomem
, OBJECT(sdhci
), &aspeed_sdhci_ops
,
128 sdhci
, TYPE_ASPEED_SDHCI
, 0x1000);
129 sysbus_init_mmio(sbd
, &sdhci
->iomem
);
131 for (int i
= 0; i
< sdhci
->num_slots
; ++i
) {
132 Object
*sdhci_slot
= OBJECT(&sdhci
->slots
[i
]);
133 SysBusDevice
*sbd_slot
= SYS_BUS_DEVICE(&sdhci
->slots
[i
]);
135 object_property_set_int(sdhci_slot
, 2, "sd-spec-version", &err
);
137 error_propagate(errp
, err
);
141 object_property_set_uint(sdhci_slot
, ASPEED_SDHCI_CAPABILITIES
,
144 error_propagate(errp
, err
);
148 object_property_set_bool(sdhci_slot
, true, "realized", &err
);
150 error_propagate(errp
, err
);
154 sysbus_connect_irq(sbd_slot
, 0, qdev_get_gpio_in(DEVICE(sbd
), i
));
155 memory_region_add_subregion(&sdhci
->iomem
, (i
+ 1) * 0x100,
156 &sdhci
->slots
[i
].iomem
);
160 static void aspeed_sdhci_reset(DeviceState
*dev
)
162 AspeedSDHCIState
*sdhci
= ASPEED_SDHCI(dev
);
164 memset(sdhci
->regs
, 0, ASPEED_SDHCI_REG_SIZE
);
165 sdhci
->regs
[TO_REG(ASPEED_SDHCI_INFO
)] = ASPEED_SDHCI_INFO_RESET
;
166 sdhci
->regs
[TO_REG(ASPEED_SDHCI_DEBOUNCE
)] = ASPEED_SDHCI_DEBOUNCE_RESET
;
169 static const VMStateDescription vmstate_aspeed_sdhci
= {
170 .name
= TYPE_ASPEED_SDHCI
,
172 .fields
= (VMStateField
[]) {
173 VMSTATE_UINT32_ARRAY(regs
, AspeedSDHCIState
, ASPEED_SDHCI_NUM_REGS
),
174 VMSTATE_END_OF_LIST(),
178 static Property aspeed_sdhci_properties
[] = {
179 DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState
, num_slots
, 0),
180 DEFINE_PROP_END_OF_LIST(),
183 static void aspeed_sdhci_class_init(ObjectClass
*classp
, void *data
)
185 DeviceClass
*dc
= DEVICE_CLASS(classp
);
187 dc
->realize
= aspeed_sdhci_realize
;
188 dc
->reset
= aspeed_sdhci_reset
;
189 dc
->vmsd
= &vmstate_aspeed_sdhci
;
190 device_class_set_props(dc
, aspeed_sdhci_properties
);
193 static TypeInfo aspeed_sdhci_info
= {
194 .name
= TYPE_ASPEED_SDHCI
,
195 .parent
= TYPE_SYS_BUS_DEVICE
,
196 .instance_size
= sizeof(AspeedSDHCIState
),
197 .class_init
= aspeed_sdhci_class_init
,
200 static void aspeed_sdhci_register_types(void)
202 type_register_static(&aspeed_sdhci_info
);
205 type_init(aspeed_sdhci_register_types
)