target-ppc/mem_helper.c

   1 /*
   2  *  PowerPC memory access emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "qemu/host-utils.h"
  21 #include "exec/helper-proto.h"
  22
  23 #include "helper_regs.h"
  24 #include "exec/cpu_ldst.h"
  25
  26 //#define DEBUG_OP
  27
  28 static inline bool needs_byteswap(const CPUPPCState *env)
  29 {
  30 #if defined(TARGET_WORDS_BIGENDIAN)
  31   return msr_le;
  32 #else
  33   return !msr_le;
  34 #endif
  35 }
  36
  37 /*****************************************************************************/
  38 /* Memory load and stores */
  39
  40 static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
  41                                     target_long arg)
  42 {
  43 #if defined(TARGET_PPC64)
  44     if (!msr_is_64bit(env, env->msr)) {
  45         return (uint32_t)(addr + arg);
  46     } else
  47 #endif
  48     {
  49         return addr + arg;
  50     }
  51 }
  52
  53 void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  54 {
  55     for (; reg < 32; reg++) {
  56         if (needs_byteswap(env)) {
  57             env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
  58         } else {
  59             env->gpr[reg] = cpu_ldl_data(env, addr);
  60         }
  61         addr = addr_add(env, addr, 4);
  62     }
  63 }
  64
  65 void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
  66 {
  67     for (; reg < 32; reg++) {
  68         if (needs_byteswap(env)) {
  69             cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
  70         } else {
  71             cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
  72         }
  73         addr = addr_add(env, addr, 4);
  74     }
  75 }
  76
  77 void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
  78 {
  79     int sh;
  80
  81     for (; nb > 3; nb -= 4) {
  82         env->gpr[reg] = cpu_ldl_data(env, addr);
  83         reg = (reg + 1) % 32;
  84         addr = addr_add(env, addr, 4);
  85     }
  86     if (unlikely(nb > 0)) {
  87         env->gpr[reg] = 0;
  88         for (sh = 24; nb > 0; nb--, sh -= 8) {
  89             env->gpr[reg] |= cpu_ldub_data(env, addr) << sh;
  90             addr = addr_add(env, addr, 1);
  91         }
  92     }
  93 }
  94 /* PPC32 specification says we must generate an exception if
  95  * rA is in the range of registers to be loaded.
  96  * In an other hand, IBM says this is valid, but rA won't be loaded.
  97  * For now, I'll follow the spec...
  98  */
  99 void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 100                  uint32_t ra, uint32_t rb)
 101 {
 102     if (likely(xer_bc != 0)) {
 103         if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
 104                      (reg < rb && (reg + xer_bc) > rb))) {
 105             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 106                                        POWERPC_EXCP_INVAL |
 107                                        POWERPC_EXCP_INVAL_LSWX);
 108         } else {
 109             helper_lsw(env, addr, xer_bc, reg);
 110         }
 111     }
 112 }
 113
 114 void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
 115                  uint32_t reg)
 116 {
 117     int sh;
 118
 119     for (; nb > 3; nb -= 4) {
 120         cpu_stl_data(env, addr, env->gpr[reg]);
 121         reg = (reg + 1) % 32;
 122         addr = addr_add(env, addr, 4);
 123     }
 124     if (unlikely(nb > 0)) {
 125         for (sh = 24; nb > 0; nb--, sh -= 8) {
 126             cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
 127             addr = addr_add(env, addr, 1);
 128         }
 129     }
 130 }
 131
 132 static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
 133 {
 134     int i;
 135
 136     addr &= ~(dcache_line_size - 1);
 137     for (i = 0; i < dcache_line_size; i += 4) {
 138         cpu_stl_data(env, addr + i, 0);
 139     }
 140     if (env->reserve_addr == addr) {
 141         env->reserve_addr = (target_ulong)-1ULL;
 142     }
 143 }
 144
 145 void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
 146 {
 147     int dcbz_size = env->dcache_line_size;
 148
 149 #if defined(TARGET_PPC64)
 150     if (!is_dcbzl &&
 151         (env->excp_model == POWERPC_EXCP_970) &&
 152         ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
 153         dcbz_size = 32;
 154     }
 155 #endif
 156
 157     /* XXX add e500mc support */
 158
 159     do_dcbz(env, addr, dcbz_size);
 160 }
 161
 162 void helper_icbi(CPUPPCState *env, target_ulong addr)
 163 {
 164     addr &= ~(env->dcache_line_size - 1);
 165     /* Invalidate one cache line :
 166      * PowerPC specification says this is to be treated like a load
 167      * (not a fetch) by the MMU. To be sure it will be so,
 168      * do the load "by hand".
 169      */
 170     cpu_ldl_data(env, addr);
 171 }
 172
 173 /* XXX: to be tested */
 174 target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
 175                           uint32_t ra, uint32_t rb)
 176 {
 177     int i, c, d;
 178
 179     d = 24;
 180     for (i = 0; i < xer_bc; i++) {
 181         c = cpu_ldub_data(env, addr);
 182         addr = addr_add(env, addr, 1);
 183         /* ra (if not 0) and rb are never modified */
 184         if (likely(reg != rb && (ra == 0 || reg != ra))) {
 185             env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
 186         }
 187         if (unlikely(c == xer_cmp)) {
 188             break;
 189         }
 190         if (likely(d != 0)) {
 191             d -= 8;
 192         } else {
 193             d = 24;
 194             reg++;
 195             reg = reg & 0x1F;
 196         }
 197     }
 198     return i;
 199 }
 200
 201 /*****************************************************************************/
 202 /* Altivec extension helpers */
 203 #if defined(HOST_WORDS_BIGENDIAN)
 204 #define HI_IDX 0
 205 #define LO_IDX 1
 206 #else
 207 #define HI_IDX 1
 208 #define LO_IDX 0
 209 #endif
 210
 211 /* We use msr_le to determine index ordering in a vector.  However,
 212    byteswapping is not simply controlled by msr_le.  We also need to take
 213    into account endianness of the target.  This is done for the little-endian
 214    PPC64 user-mode target. */
 215
 216 #define LVE(name, access, swap, element)                        \
 217     void helper_##name(CPUPPCState *env, ppc_avr_t *r,          \
 218                        target_ulong addr)                       \
 219     {                                                           \
 220         size_t n_elems = ARRAY_SIZE(r->element);                \
 221         int adjust = HI_IDX*(n_elems - 1);                      \
 222         int sh = sizeof(r->element[0]) >> 1;                    \
 223         int index = (addr & 0xf) >> sh;                         \
 224         if (msr_le) {                                           \
 225             index = n_elems - index - 1;                        \
 226         }                                                       \
 227                                                                 \
 228         if (needs_byteswap(env)) {                              \
 229             r->element[LO_IDX ? index : (adjust - index)] =     \
 230                 swap(access(env, addr));                        \
 231         } else {                                                \
 232             r->element[LO_IDX ? index : (adjust - index)] =     \
 233                 access(env, addr);                              \
 234         }                                                       \
 235     }
 236 #define I(x) (x)
 237 LVE(lvebx, cpu_ldub_data, I, u8)
 238 LVE(lvehx, cpu_lduw_data, bswap16, u16)
 239 LVE(lvewx, cpu_ldl_data, bswap32, u32)
 240 #undef I
 241 #undef LVE
 242
 243 #define STVE(name, access, swap, element)                               \
 244     void helper_##name(CPUPPCState *env, ppc_avr_t *r,                  \
 245                        target_ulong addr)                               \
 246     {                                                                   \
 247         size_t n_elems = ARRAY_SIZE(r->element);                        \
 248         int adjust = HI_IDX * (n_elems - 1);                            \
 249         int sh = sizeof(r->element[0]) >> 1;                            \
 250         int index = (addr & 0xf) >> sh;                                 \
 251         if (msr_le) {                                                   \
 252             index = n_elems - index - 1;                                \
 253         }                                                               \
 254                                                                         \
 255         if (needs_byteswap(env)) {                                      \
 256             access(env, addr, swap(r->element[LO_IDX ? index :          \
 257                                               (adjust - index)]));      \
 258         } else {                                                        \
 259             access(env, addr, r->element[LO_IDX ? index :               \
 260                                          (adjust - index)]);            \
 261         }                                                               \
 262     }
 263 #define I(x) (x)
 264 STVE(stvebx, cpu_stb_data, I, u8)
 265 STVE(stvehx, cpu_stw_data, bswap16, u16)
 266 STVE(stvewx, cpu_stl_data, bswap32, u32)
 267 #undef I
 268 #undef LVE
 269
 270 #undef HI_IDX
 271 #undef LO_IDX
 272
 273 void helper_tbegin(CPUPPCState *env)
 274 {
 275     /* As a degenerate implementation, always fail tbegin.  The reason
 276      * given is "Nesting overflow".  The "persistent" bit is set,
 277      * providing a hint to the error handler to not retry.  The TFIAR
 278      * captures the address of the failure, which is this tbegin
 279      * instruction.  Instruction execution will continue with the
 280      * next instruction in memory, which is precisely what we want.
 281      */
 282
 283     env->spr[SPR_TEXASR] =
 284         (1ULL << TEXASR_FAILURE_PERSISTENT) |
 285         (1ULL << TEXASR_NESTING_OVERFLOW) |
 286         (msr_hv << TEXASR_PRIVILEGE_HV) |
 287         (msr_pr << TEXASR_PRIVILEGE_PR) |
 288         (1ULL << TEXASR_FAILURE_SUMMARY) |
 289         (1ULL << TEXASR_TFIAR_EXACT);
 290     env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
 291     env->spr[SPR_TFHAR] = env->nip + 4;
 292     env->crf[0] = 0xB; /* 0b1010 = transaction failure */
 293 }