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[qemu/ar7.git] / target-ppc / translate.c
blobe3fcb03c2667f4dfd1703f5cc93b97724d6d1478
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Update Cr6 flags (Altivec) */
391 EXTRACT_HELPER(Rc21, 10, 1);
392 /* Destination */
393 EXTRACT_HELPER(rD, 21, 5);
394 /* Source */
395 EXTRACT_HELPER(rS, 21, 5);
396 /* First operand */
397 EXTRACT_HELPER(rA, 16, 5);
398 /* Second operand */
399 EXTRACT_HELPER(rB, 11, 5);
400 /* Third operand */
401 EXTRACT_HELPER(rC, 6, 5);
402 /*** Get CRn ***/
403 EXTRACT_HELPER(crfD, 23, 3);
404 EXTRACT_HELPER(crfS, 18, 3);
405 EXTRACT_HELPER(crbD, 21, 5);
406 EXTRACT_HELPER(crbA, 16, 5);
407 EXTRACT_HELPER(crbB, 11, 5);
408 /* SPR / TBL */
409 EXTRACT_HELPER(_SPR, 11, 10);
410 static inline uint32_t SPR(uint32_t opcode)
411 {
412 uint32_t sprn = _SPR(opcode);
413
414 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
415 }
416 /*** Get constants ***/
417 EXTRACT_HELPER(IMM, 12, 8);
418 /* 16 bits signed immediate value */
419 EXTRACT_SHELPER(SIMM, 0, 16);
420 /* 16 bits unsigned immediate value */
421 EXTRACT_HELPER(UIMM, 0, 16);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(SIMM5, 16, 5);
424 /* 5 bits signed immediate value */
425 EXTRACT_HELPER(UIMM5, 16, 5);
426 /* Bit count */
427 EXTRACT_HELPER(NB, 11, 5);
428 /* Shift count */
429 EXTRACT_HELPER(SH, 11, 5);
430 /* Vector shift count */
431 EXTRACT_HELPER(VSH, 6, 4);
432 /* Mask start */
433 EXTRACT_HELPER(MB, 6, 5);
434 /* Mask end */
435 EXTRACT_HELPER(ME, 1, 5);
436 /* Trap operand */
437 EXTRACT_HELPER(TO, 21, 5);
438
439 EXTRACT_HELPER(CRM, 12, 8);
440 EXTRACT_HELPER(SR, 16, 4);
441
442 /* mtfsf/mtfsfi */
443 EXTRACT_HELPER(FPBF, 23, 3);
444 EXTRACT_HELPER(FPIMM, 12, 4);
445 EXTRACT_HELPER(FPL, 25, 1);
446 EXTRACT_HELPER(FPFLM, 17, 8);
447 EXTRACT_HELPER(FPW, 16, 1);
448
449 /*** Jump target decoding ***/
450 /* Displacement */
451 EXTRACT_SHELPER(d, 0, 16);
452 /* Immediate address */
453 static inline target_ulong LI(uint32_t opcode)
454 {
455 return (opcode >> 0) & 0x03FFFFFC;
456 }
457
458 static inline uint32_t BD(uint32_t opcode)
459 {
460 return (opcode >> 0) & 0xFFFC;
461 }
462
463 EXTRACT_HELPER(BO, 21, 5);
464 EXTRACT_HELPER(BI, 16, 5);
465 /* Absolute/relative address */
466 EXTRACT_HELPER(AA, 1, 1);
467 /* Link */
468 EXTRACT_HELPER(LK, 0, 1);
469
470 /* Create a mask between <start> and <end> bits */
471 static inline target_ulong MASK(uint32_t start, uint32_t end)
472 {
473 target_ulong ret;
474
475 #if defined(TARGET_PPC64)
476 if (likely(start == 0)) {
477 ret = UINT64_MAX << (63 - end);
478 } else if (likely(end == 63)) {
479 ret = UINT64_MAX >> start;
480 }
481 #else
482 if (likely(start == 0)) {
483 ret = UINT32_MAX << (31 - end);
484 } else if (likely(end == 31)) {
485 ret = UINT32_MAX >> start;
486 }
487 #endif
488 else {
489 ret = (((target_ulong)(-1ULL)) >> (start)) ^
490 (((target_ulong)(-1ULL) >> (end)) >> 1);
491 if (unlikely(start > end))
492 return ~ret;
493 }
494
495 return ret;
496 }
497
498 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
499 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
500 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
501 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
502 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
503 EXTRACT_HELPER(DM, 8, 2);
504 EXTRACT_HELPER(UIM, 16, 2);
505 EXTRACT_HELPER(SHW, 8, 2);
506 /*****************************************************************************/
507 /* PowerPC instructions table */
508
509 #if defined(DO_PPC_STATISTICS)
510 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
511 { \
512 .opc1 = op1, \
513 .opc2 = op2, \
514 .opc3 = op3, \
515 .pad = { 0, }, \
516 .handler = { \
517 .inval1 = invl, \
518 .type = _typ, \
519 .type2 = _typ2, \
520 .handler = &gen_##name, \
521 .oname = stringify(name), \
522 }, \
523 .oname = stringify(name), \
524 }
525 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl1, \
533 .inval2 = invl2, \
534 .type = _typ, \
535 .type2 = _typ2, \
536 .handler = &gen_##name, \
537 .oname = stringify(name), \
538 }, \
539 .oname = stringify(name), \
540 }
541 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
542 { \
543 .opc1 = op1, \
544 .opc2 = op2, \
545 .opc3 = op3, \
546 .pad = { 0, }, \
547 .handler = { \
548 .inval1 = invl, \
549 .type = _typ, \
550 .type2 = _typ2, \
551 .handler = &gen_##name, \
552 .oname = onam, \
553 }, \
554 .oname = onam, \
555 }
556 #else
557 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
558 { \
559 .opc1 = op1, \
560 .opc2 = op2, \
561 .opc3 = op3, \
562 .pad = { 0, }, \
563 .handler = { \
564 .inval1 = invl, \
565 .type = _typ, \
566 .type2 = _typ2, \
567 .handler = &gen_##name, \
568 }, \
569 .oname = stringify(name), \
570 }
571 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
572 { \
573 .opc1 = op1, \
574 .opc2 = op2, \
575 .opc3 = op3, \
576 .pad = { 0, }, \
577 .handler = { \
578 .inval1 = invl1, \
579 .inval2 = invl2, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = stringify(name), \
585 }
586 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
587 { \
588 .opc1 = op1, \
589 .opc2 = op2, \
590 .opc3 = op3, \
591 .pad = { 0, }, \
592 .handler = { \
593 .inval1 = invl, \
594 .type = _typ, \
595 .type2 = _typ2, \
596 .handler = &gen_##name, \
597 }, \
598 .oname = onam, \
599 }
600 #endif
601
602 /* SPR load/store helpers */
603 static inline void gen_load_spr(TCGv t, int reg)
604 {
605 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
606 }
607
608 static inline void gen_store_spr(int reg, TCGv t)
609 {
610 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
611 }
612
613 /* Invalid instruction */
614 static void gen_invalid(DisasContext *ctx)
615 {
616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
617 }
618
619 static opc_handler_t invalid_handler = {
620 .inval1 = 0xFFFFFFFF,
621 .inval2 = 0xFFFFFFFF,
622 .type = PPC_NONE,
623 .type2 = PPC_NONE,
624 .handler = gen_invalid,
625 };
626
627 #if defined(TARGET_PPC64)
628 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
629 /* so the function is wrapped in the standard 64-bit ifdef in order to */
630 /* avoid compiler warnings in 32-bit implementations. */
631 static bool is_user_mode(DisasContext *ctx)
632 {
633 #if defined(CONFIG_USER_ONLY)
634 return true;
635 #else
636 return ctx->mem_idx == 0;
637 #endif
638 }
639 #endif
640
641 /*** Integer comparison ***/
642
643 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
644 {
645 TCGv t0 = tcg_temp_new();
646 TCGv_i32 t1 = tcg_temp_new_i32();
647
648 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
649
650 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
651 tcg_gen_trunc_tl_i32(t1, t0);
652 tcg_gen_shli_i32(t1, t1, CRF_LT);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
654
655 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
656 tcg_gen_trunc_tl_i32(t1, t0);
657 tcg_gen_shli_i32(t1, t1, CRF_GT);
658 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
659
660 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
661 tcg_gen_trunc_tl_i32(t1, t0);
662 tcg_gen_shli_i32(t1, t1, CRF_EQ);
663 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
664
665 tcg_temp_free(t0);
666 tcg_temp_free_i32(t1);
667 }
668
669 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
670 {
671 TCGv t0 = tcg_const_tl(arg1);
672 gen_op_cmp(arg0, t0, s, crf);
673 tcg_temp_free(t0);
674 }
675
676 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
677 {
678 TCGv t0, t1;
679 t0 = tcg_temp_new();
680 t1 = tcg_temp_new();
681 if (s) {
682 tcg_gen_ext32s_tl(t0, arg0);
683 tcg_gen_ext32s_tl(t1, arg1);
684 } else {
685 tcg_gen_ext32u_tl(t0, arg0);
686 tcg_gen_ext32u_tl(t1, arg1);
687 }
688 gen_op_cmp(t0, t1, s, crf);
689 tcg_temp_free(t1);
690 tcg_temp_free(t0);
691 }
692
693 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
694 {
695 TCGv t0 = tcg_const_tl(arg1);
696 gen_op_cmp32(arg0, t0, s, crf);
697 tcg_temp_free(t0);
698 }
699
700 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
701 {
702 if (NARROW_MODE(ctx)) {
703 gen_op_cmpi32(reg, 0, 1, 0);
704 } else {
705 gen_op_cmpi(reg, 0, 1, 0);
706 }
707 }
708
709 /* cmp */
710 static void gen_cmp(DisasContext *ctx)
711 {
712 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
713 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
715 } else {
716 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
717 1, crfD(ctx->opcode));
718 }
719 }
720
721 /* cmpi */
722 static void gen_cmpi(DisasContext *ctx)
723 {
724 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
725 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
727 } else {
728 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
729 1, crfD(ctx->opcode));
730 }
731 }
732
733 /* cmpl */
734 static void gen_cmpl(DisasContext *ctx)
735 {
736 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
737 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
739 } else {
740 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
741 0, crfD(ctx->opcode));
742 }
743 }
744
745 /* cmpli */
746 static void gen_cmpli(DisasContext *ctx)
747 {
748 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
749 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
751 } else {
752 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
753 0, crfD(ctx->opcode));
754 }
755 }
756
757 /* isel (PowerPC 2.03 specification) */
758 static void gen_isel(DisasContext *ctx)
759 {
760 int l1, l2;
761 uint32_t bi = rC(ctx->opcode);
762 uint32_t mask;
763 TCGv_i32 t0;
764
765 l1 = gen_new_label();
766 l2 = gen_new_label();
767
768 mask = 1 << (3 - (bi & 0x03));
769 t0 = tcg_temp_new_i32();
770 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
771 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
772 if (rA(ctx->opcode) == 0)
773 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
774 else
775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
776 tcg_gen_br(l2);
777 gen_set_label(l1);
778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
779 gen_set_label(l2);
780 tcg_temp_free_i32(t0);
781 }
782
783 /* cmpb: PowerPC 2.05 specification */
784 static void gen_cmpb(DisasContext *ctx)
785 {
786 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
787 cpu_gpr[rB(ctx->opcode)]);
788 }
789
790 /*** Integer arithmetic ***/
791
792 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
793 TCGv arg1, TCGv arg2, int sub)
794 {
795 TCGv t0 = tcg_temp_new();
796
797 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
798 tcg_gen_xor_tl(t0, arg1, arg2);
799 if (sub) {
800 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
801 } else {
802 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
803 }
804 tcg_temp_free(t0);
805 if (NARROW_MODE(ctx)) {
806 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
807 }
808 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
809 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
810 }
811
812 /* Common add function */
813 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
814 TCGv arg2, bool add_ca, bool compute_ca,
815 bool compute_ov, bool compute_rc0)
816 {
817 TCGv t0 = ret;
818
819 if (compute_ca || compute_ov) {
820 t0 = tcg_temp_new();
821 }
822
823 if (compute_ca) {
824 if (NARROW_MODE(ctx)) {
825 /* Caution: a non-obvious corner case of the spec is that we
826 must produce the *entire* 64-bit addition, but produce the
827 carry into bit 32. */
828 TCGv t1 = tcg_temp_new();
829 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
830 tcg_gen_add_tl(t0, arg1, arg2);
831 if (add_ca) {
832 tcg_gen_add_tl(t0, t0, cpu_ca);
833 }
834 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
835 tcg_temp_free(t1);
836 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
837 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
838 } else {
839 TCGv zero = tcg_const_tl(0);
840 if (add_ca) {
841 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
842 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
843 } else {
844 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
845 }
846 tcg_temp_free(zero);
847 }
848 } else {
849 tcg_gen_add_tl(t0, arg1, arg2);
850 if (add_ca) {
851 tcg_gen_add_tl(t0, t0, cpu_ca);
852 }
853 }
854
855 if (compute_ov) {
856 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
857 }
858 if (unlikely(compute_rc0)) {
859 gen_set_Rc0(ctx, t0);
860 }
861
862 if (!TCGV_EQUAL(t0, ret)) {
863 tcg_gen_mov_tl(ret, t0);
864 tcg_temp_free(t0);
865 }
866 }
867 /* Add functions with two operands */
868 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
869 static void glue(gen_, name)(DisasContext *ctx) \
870 { \
871 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
872 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
873 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
874 }
875 /* Add functions with one operand and one immediate */
876 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
877 add_ca, compute_ca, compute_ov) \
878 static void glue(gen_, name)(DisasContext *ctx) \
879 { \
880 TCGv t0 = tcg_const_tl(const_val); \
881 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
882 cpu_gpr[rA(ctx->opcode)], t0, \
883 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
884 tcg_temp_free(t0); \
885 }
886
887 /* add add. addo addo. */
888 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
889 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
890 /* addc addc. addco addco. */
891 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
892 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
893 /* adde adde. addeo addeo. */
894 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
895 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
896 /* addme addme. addmeo addmeo. */
897 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
898 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
899 /* addze addze. addzeo addzeo.*/
900 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
901 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
902 /* addi */
903 static void gen_addi(DisasContext *ctx)
904 {
905 target_long simm = SIMM(ctx->opcode);
906
907 if (rA(ctx->opcode) == 0) {
908 /* li case */
909 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
910 } else {
911 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
912 cpu_gpr[rA(ctx->opcode)], simm);
913 }
914 }
915 /* addic addic.*/
916 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
917 {
918 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
919 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
920 c, 0, 1, 0, compute_rc0);
921 tcg_temp_free(c);
922 }
923
924 static void gen_addic(DisasContext *ctx)
925 {
926 gen_op_addic(ctx, 0);
927 }
928
929 static void gen_addic_(DisasContext *ctx)
930 {
931 gen_op_addic(ctx, 1);
932 }
933
934 /* addis */
935 static void gen_addis(DisasContext *ctx)
936 {
937 target_long simm = SIMM(ctx->opcode);
938
939 if (rA(ctx->opcode) == 0) {
940 /* lis case */
941 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
942 } else {
943 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
944 cpu_gpr[rA(ctx->opcode)], simm << 16);
945 }
946 }
947
948 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
949 TCGv arg2, int sign, int compute_ov)
950 {
951 int l1 = gen_new_label();
952 int l2 = gen_new_label();
953 TCGv_i32 t0 = tcg_temp_local_new_i32();
954 TCGv_i32 t1 = tcg_temp_local_new_i32();
955
956 tcg_gen_trunc_tl_i32(t0, arg1);
957 tcg_gen_trunc_tl_i32(t1, arg2);
958 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
959 if (sign) {
960 int l3 = gen_new_label();
961 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
962 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
963 gen_set_label(l3);
964 tcg_gen_div_i32(t0, t0, t1);
965 } else {
966 tcg_gen_divu_i32(t0, t0, t1);
967 }
968 if (compute_ov) {
969 tcg_gen_movi_tl(cpu_ov, 0);
970 }
971 tcg_gen_br(l2);
972 gen_set_label(l1);
973 if (sign) {
974 tcg_gen_sari_i32(t0, t0, 31);
975 } else {
976 tcg_gen_movi_i32(t0, 0);
977 }
978 if (compute_ov) {
979 tcg_gen_movi_tl(cpu_ov, 1);
980 tcg_gen_movi_tl(cpu_so, 1);
981 }
982 gen_set_label(l2);
983 tcg_gen_extu_i32_tl(ret, t0);
984 tcg_temp_free_i32(t0);
985 tcg_temp_free_i32(t1);
986 if (unlikely(Rc(ctx->opcode) != 0))
987 gen_set_Rc0(ctx, ret);
988 }
989 /* Div functions */
990 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
991 static void glue(gen_, name)(DisasContext *ctx) \
992 { \
993 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
994 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
995 sign, compute_ov); \
996 }
997 /* divwu divwu. divwuo divwuo. */
998 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
999 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1000 /* divw divw. divwo divwo. */
1001 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1002 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1003
1004 /* div[wd]eu[o][.] */
1005 #define GEN_DIVE(name, hlpr, compute_ov) \
1006 static void gen_##name(DisasContext *ctx) \
1007 { \
1008 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1009 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1010 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1011 tcg_temp_free_i32(t0); \
1012 if (unlikely(Rc(ctx->opcode) != 0)) { \
1013 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1014 } \
1015 }
1016
1017 GEN_DIVE(divweu, divweu, 0);
1018 GEN_DIVE(divweuo, divweu, 1);
1019 GEN_DIVE(divwe, divwe, 0);
1020 GEN_DIVE(divweo, divwe, 1);
1021
1022 #if defined(TARGET_PPC64)
1023 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1024 TCGv arg2, int sign, int compute_ov)
1025 {
1026 int l1 = gen_new_label();
1027 int l2 = gen_new_label();
1028
1029 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1030 if (sign) {
1031 int l3 = gen_new_label();
1032 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1033 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1034 gen_set_label(l3);
1035 tcg_gen_div_i64(ret, arg1, arg2);
1036 } else {
1037 tcg_gen_divu_i64(ret, arg1, arg2);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_movi_tl(cpu_ov, 0);
1041 }
1042 tcg_gen_br(l2);
1043 gen_set_label(l1);
1044 if (sign) {
1045 tcg_gen_sari_i64(ret, arg1, 63);
1046 } else {
1047 tcg_gen_movi_i64(ret, 0);
1048 }
1049 if (compute_ov) {
1050 tcg_gen_movi_tl(cpu_ov, 1);
1051 tcg_gen_movi_tl(cpu_so, 1);
1052 }
1053 gen_set_label(l2);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, ret);
1056 }
1057 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1058 static void glue(gen_, name)(DisasContext *ctx) \
1059 { \
1060 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1061 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1062 sign, compute_ov); \
1063 }
1064 /* divwu divwu. divwuo divwuo. */
1065 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1066 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1067 /* divw divw. divwo divwo. */
1068 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1069 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1070
1071 GEN_DIVE(divdeu, divdeu, 0);
1072 GEN_DIVE(divdeuo, divdeu, 1);
1073 GEN_DIVE(divde, divde, 0);
1074 GEN_DIVE(divdeo, divde, 1);
1075 #endif
1076
1077 /* mulhw mulhw. */
1078 static void gen_mulhw(DisasContext *ctx)
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i32 t1 = tcg_temp_new_i32();
1082
1083 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1085 tcg_gen_muls2_i32(t0, t1, t0, t1);
1086 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1087 tcg_temp_free_i32(t0);
1088 tcg_temp_free_i32(t1);
1089 if (unlikely(Rc(ctx->opcode) != 0))
1090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1091 }
1092
1093 /* mulhwu mulhwu. */
1094 static void gen_mulhwu(DisasContext *ctx)
1095 {
1096 TCGv_i32 t0 = tcg_temp_new_i32();
1097 TCGv_i32 t1 = tcg_temp_new_i32();
1098
1099 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1102 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1107 }
1108
1109 /* mullw mullw. */
1110 static void gen_mullw(DisasContext *ctx)
1111 {
1112 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1113 cpu_gpr[rB(ctx->opcode)]);
1114 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1115 if (unlikely(Rc(ctx->opcode) != 0))
1116 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1117 }
1118
1119 /* mullwo mullwo. */
1120 static void gen_mullwo(DisasContext *ctx)
1121 {
1122 TCGv_i32 t0 = tcg_temp_new_i32();
1123 TCGv_i32 t1 = tcg_temp_new_i32();
1124
1125 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1126 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1127 tcg_gen_muls2_i32(t0, t1, t0, t1);
1128 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1129
1130 tcg_gen_sari_i32(t0, t0, 31);
1131 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1132 tcg_gen_extu_i32_tl(cpu_ov, t0);
1133 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1134
1135 tcg_temp_free_i32(t0);
1136 tcg_temp_free_i32(t1);
1137 if (unlikely(Rc(ctx->opcode) != 0))
1138 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1139 }
1140
1141 /* mulli */
1142 static void gen_mulli(DisasContext *ctx)
1143 {
1144 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1145 SIMM(ctx->opcode));
1146 }
1147
1148 #if defined(TARGET_PPC64)
1149 /* mulhd mulhd. */
1150 static void gen_mulhd(DisasContext *ctx)
1151 {
1152 TCGv lo = tcg_temp_new();
1153 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1154 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1155 tcg_temp_free(lo);
1156 if (unlikely(Rc(ctx->opcode) != 0)) {
1157 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1158 }
1159 }
1160
1161 /* mulhdu mulhdu. */
1162 static void gen_mulhdu(DisasContext *ctx)
1163 {
1164 TCGv lo = tcg_temp_new();
1165 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1167 tcg_temp_free(lo);
1168 if (unlikely(Rc(ctx->opcode) != 0)) {
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1170 }
1171 }
1172
1173 /* mulld mulld. */
1174 static void gen_mulld(DisasContext *ctx)
1175 {
1176 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1177 cpu_gpr[rB(ctx->opcode)]);
1178 if (unlikely(Rc(ctx->opcode) != 0))
1179 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1180 }
1181
1182 /* mulldo mulldo. */
1183 static void gen_mulldo(DisasContext *ctx)
1184 {
1185 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1186 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1187 if (unlikely(Rc(ctx->opcode) != 0)) {
1188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1189 }
1190 }
1191 #endif
1192
1193 /* Common subf function */
1194 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1195 TCGv arg2, bool add_ca, bool compute_ca,
1196 bool compute_ov, bool compute_rc0)
1197 {
1198 TCGv t0 = ret;
1199
1200 if (compute_ca || compute_ov) {
1201 t0 = tcg_temp_new();
1202 }
1203
1204 if (compute_ca) {
1205 /* dest = ~arg1 + arg2 [+ ca]. */
1206 if (NARROW_MODE(ctx)) {
1207 /* Caution: a non-obvious corner case of the spec is that we
1208 must produce the *entire* 64-bit addition, but produce the
1209 carry into bit 32. */
1210 TCGv inv1 = tcg_temp_new();
1211 TCGv t1 = tcg_temp_new();
1212 tcg_gen_not_tl(inv1, arg1);
1213 if (add_ca) {
1214 tcg_gen_add_tl(t0, arg2, cpu_ca);
1215 } else {
1216 tcg_gen_addi_tl(t0, arg2, 1);
1217 }
1218 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1219 tcg_gen_add_tl(t0, t0, inv1);
1220 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1221 tcg_temp_free(t1);
1222 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1223 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1224 } else if (add_ca) {
1225 TCGv zero, inv1 = tcg_temp_new();
1226 tcg_gen_not_tl(inv1, arg1);
1227 zero = tcg_const_tl(0);
1228 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1229 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1230 tcg_temp_free(zero);
1231 tcg_temp_free(inv1);
1232 } else {
1233 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1234 tcg_gen_sub_tl(t0, arg2, arg1);
1235 }
1236 } else if (add_ca) {
1237 /* Since we're ignoring carry-out, we can simplify the
1238 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1239 tcg_gen_sub_tl(t0, arg2, arg1);
1240 tcg_gen_add_tl(t0, t0, cpu_ca);
1241 tcg_gen_subi_tl(t0, t0, 1);
1242 } else {
1243 tcg_gen_sub_tl(t0, arg2, arg1);
1244 }
1245
1246 if (compute_ov) {
1247 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1248 }
1249 if (unlikely(compute_rc0)) {
1250 gen_set_Rc0(ctx, t0);
1251 }
1252
1253 if (!TCGV_EQUAL(t0, ret)) {
1254 tcg_gen_mov_tl(ret, t0);
1255 tcg_temp_free(t0);
1256 }
1257 }
1258 /* Sub functions with Two operands functions */
1259 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1260 static void glue(gen_, name)(DisasContext *ctx) \
1261 { \
1262 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1263 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1264 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1265 }
1266 /* Sub functions with one operand and one immediate */
1267 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1268 add_ca, compute_ca, compute_ov) \
1269 static void glue(gen_, name)(DisasContext *ctx) \
1270 { \
1271 TCGv t0 = tcg_const_tl(const_val); \
1272 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1273 cpu_gpr[rA(ctx->opcode)], t0, \
1274 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1275 tcg_temp_free(t0); \
1276 }
1277 /* subf subf. subfo subfo. */
1278 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1279 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1280 /* subfc subfc. subfco subfco. */
1281 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1282 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1283 /* subfe subfe. subfeo subfo. */
1284 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1285 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1286 /* subfme subfme. subfmeo subfmeo. */
1287 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1288 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1289 /* subfze subfze. subfzeo subfzeo.*/
1290 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1291 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1292
1293 /* subfic */
1294 static void gen_subfic(DisasContext *ctx)
1295 {
1296 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1297 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1298 c, 0, 1, 0, 0);
1299 tcg_temp_free(c);
1300 }
1301
1302 /* neg neg. nego nego. */
1303 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1304 {
1305 TCGv zero = tcg_const_tl(0);
1306 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1307 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1308 tcg_temp_free(zero);
1309 }
1310
1311 static void gen_neg(DisasContext *ctx)
1312 {
1313 gen_op_arith_neg(ctx, 0);
1314 }
1315
1316 static void gen_nego(DisasContext *ctx)
1317 {
1318 gen_op_arith_neg(ctx, 1);
1319 }
1320
1321 /*** Integer logical ***/
1322 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1323 static void glue(gen_, name)(DisasContext *ctx) \
1324 { \
1325 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1326 cpu_gpr[rB(ctx->opcode)]); \
1327 if (unlikely(Rc(ctx->opcode) != 0)) \
1328 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1329 }
1330
1331 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1332 static void glue(gen_, name)(DisasContext *ctx) \
1333 { \
1334 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1335 if (unlikely(Rc(ctx->opcode) != 0)) \
1336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1337 }
1338
1339 /* and & and. */
1340 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1341 /* andc & andc. */
1342 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1343
1344 /* andi. */
1345 static void gen_andi_(DisasContext *ctx)
1346 {
1347 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1348 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1349 }
1350
1351 /* andis. */
1352 static void gen_andis_(DisasContext *ctx)
1353 {
1354 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1355 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1356 }
1357
1358 /* cntlzw */
1359 static void gen_cntlzw(DisasContext *ctx)
1360 {
1361 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1362 if (unlikely(Rc(ctx->opcode) != 0))
1363 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1364 }
1365 /* eqv & eqv. */
1366 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1367 /* extsb & extsb. */
1368 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1369 /* extsh & extsh. */
1370 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1371 /* nand & nand. */
1372 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1373 /* nor & nor. */
1374 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1375
1376 /* or & or. */
1377 static void gen_or(DisasContext *ctx)
1378 {
1379 int rs, ra, rb;
1380
1381 rs = rS(ctx->opcode);
1382 ra = rA(ctx->opcode);
1383 rb = rB(ctx->opcode);
1384 /* Optimisation for mr. ri case */
1385 if (rs != ra || rs != rb) {
1386 if (rs != rb)
1387 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1388 else
1389 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1390 if (unlikely(Rc(ctx->opcode) != 0))
1391 gen_set_Rc0(ctx, cpu_gpr[ra]);
1392 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1393 gen_set_Rc0(ctx, cpu_gpr[rs]);
1394 #if defined(TARGET_PPC64)
1395 } else {
1396 int prio = 0;
1397
1398 switch (rs) {
1399 case 1:
1400 /* Set process priority to low */
1401 prio = 2;
1402 break;
1403 case 6:
1404 /* Set process priority to medium-low */
1405 prio = 3;
1406 break;
1407 case 2:
1408 /* Set process priority to normal */
1409 prio = 4;
1410 break;
1411 #if !defined(CONFIG_USER_ONLY)
1412 case 31:
1413 if (ctx->mem_idx > 0) {
1414 /* Set process priority to very low */
1415 prio = 1;
1416 }
1417 break;
1418 case 5:
1419 if (ctx->mem_idx > 0) {
1420 /* Set process priority to medium-hight */
1421 prio = 5;
1422 }
1423 break;
1424 case 3:
1425 if (ctx->mem_idx > 0) {
1426 /* Set process priority to high */
1427 prio = 6;
1428 }
1429 break;
1430 case 7:
1431 if (ctx->mem_idx > 1) {
1432 /* Set process priority to very high */
1433 prio = 7;
1434 }
1435 break;
1436 #endif
1437 default:
1438 /* nop */
1439 break;
1440 }
1441 if (prio) {
1442 TCGv t0 = tcg_temp_new();
1443 gen_load_spr(t0, SPR_PPR);
1444 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1445 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1446 gen_store_spr(SPR_PPR, t0);
1447 tcg_temp_free(t0);
1448 }
1449 #endif
1450 }
1451 }
1452 /* orc & orc. */
1453 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1454
1455 /* xor & xor. */
1456 static void gen_xor(DisasContext *ctx)
1457 {
1458 /* Optimisation for "set to zero" case */
1459 if (rS(ctx->opcode) != rB(ctx->opcode))
1460 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1461 else
1462 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1463 if (unlikely(Rc(ctx->opcode) != 0))
1464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1465 }
1466
1467 /* ori */
1468 static void gen_ori(DisasContext *ctx)
1469 {
1470 target_ulong uimm = UIMM(ctx->opcode);
1471
1472 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1473 /* NOP */
1474 /* XXX: should handle special NOPs for POWER series */
1475 return;
1476 }
1477 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1478 }
1479
1480 /* oris */
1481 static void gen_oris(DisasContext *ctx)
1482 {
1483 target_ulong uimm = UIMM(ctx->opcode);
1484
1485 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1486 /* NOP */
1487 return;
1488 }
1489 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1490 }
1491
1492 /* xori */
1493 static void gen_xori(DisasContext *ctx)
1494 {
1495 target_ulong uimm = UIMM(ctx->opcode);
1496
1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
1499 return;
1500 }
1501 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1502 }
1503
1504 /* xoris */
1505 static void gen_xoris(DisasContext *ctx)
1506 {
1507 target_ulong uimm = UIMM(ctx->opcode);
1508
1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1510 /* NOP */
1511 return;
1512 }
1513 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1514 }
1515
1516 /* popcntb : PowerPC 2.03 specification */
1517 static void gen_popcntb(DisasContext *ctx)
1518 {
1519 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1520 }
1521
1522 static void gen_popcntw(DisasContext *ctx)
1523 {
1524 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1525 }
1526
1527 #if defined(TARGET_PPC64)
1528 /* popcntd: PowerPC 2.06 specification */
1529 static void gen_popcntd(DisasContext *ctx)
1530 {
1531 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1532 }
1533 #endif
1534
1535 /* prtyw: PowerPC 2.05 specification */
1536 static void gen_prtyw(DisasContext *ctx)
1537 {
1538 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1539 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1540 TCGv t0 = tcg_temp_new();
1541 tcg_gen_shri_tl(t0, rs, 16);
1542 tcg_gen_xor_tl(ra, rs, t0);
1543 tcg_gen_shri_tl(t0, ra, 8);
1544 tcg_gen_xor_tl(ra, ra, t0);
1545 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1546 tcg_temp_free(t0);
1547 }
1548
1549 #if defined(TARGET_PPC64)
1550 /* prtyd: PowerPC 2.05 specification */
1551 static void gen_prtyd(DisasContext *ctx)
1552 {
1553 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1554 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1555 TCGv t0 = tcg_temp_new();
1556 tcg_gen_shri_tl(t0, rs, 32);
1557 tcg_gen_xor_tl(ra, rs, t0);
1558 tcg_gen_shri_tl(t0, ra, 16);
1559 tcg_gen_xor_tl(ra, ra, t0);
1560 tcg_gen_shri_tl(t0, ra, 8);
1561 tcg_gen_xor_tl(ra, ra, t0);
1562 tcg_gen_andi_tl(ra, ra, 1);
1563 tcg_temp_free(t0);
1564 }
1565 #endif
1566
1567 #if defined(TARGET_PPC64)
1568 /* bpermd */
1569 static void gen_bpermd(DisasContext *ctx)
1570 {
1571 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1572 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1573 }
1574 #endif
1575
1576 #if defined(TARGET_PPC64)
1577 /* extsw & extsw. */
1578 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1579
1580 /* cntlzd */
1581 static void gen_cntlzd(DisasContext *ctx)
1582 {
1583 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1584 if (unlikely(Rc(ctx->opcode) != 0))
1585 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1586 }
1587 #endif
1588
1589 /*** Integer rotate ***/
1590
1591 /* rlwimi & rlwimi. */
1592 static void gen_rlwimi(DisasContext *ctx)
1593 {
1594 uint32_t mb, me, sh;
1595
1596 mb = MB(ctx->opcode);
1597 me = ME(ctx->opcode);
1598 sh = SH(ctx->opcode);
1599 if (likely(sh == 0 && mb == 0 && me == 31)) {
1600 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1601 } else {
1602 target_ulong mask;
1603 TCGv t1;
1604 TCGv t0 = tcg_temp_new();
1605 #if defined(TARGET_PPC64)
1606 TCGv_i32 t2 = tcg_temp_new_i32();
1607 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1608 tcg_gen_rotli_i32(t2, t2, sh);
1609 tcg_gen_extu_i32_i64(t0, t2);
1610 tcg_temp_free_i32(t2);
1611 #else
1612 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1613 #endif
1614 #if defined(TARGET_PPC64)
1615 mb += 32;
1616 me += 32;
1617 #endif
1618 mask = MASK(mb, me);
1619 t1 = tcg_temp_new();
1620 tcg_gen_andi_tl(t0, t0, mask);
1621 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1622 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1623 tcg_temp_free(t0);
1624 tcg_temp_free(t1);
1625 }
1626 if (unlikely(Rc(ctx->opcode) != 0))
1627 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1628 }
1629
1630 /* rlwinm & rlwinm. */
1631 static void gen_rlwinm(DisasContext *ctx)
1632 {
1633 uint32_t mb, me, sh;
1634
1635 sh = SH(ctx->opcode);
1636 mb = MB(ctx->opcode);
1637 me = ME(ctx->opcode);
1638
1639 if (likely(mb == 0 && me == (31 - sh))) {
1640 if (likely(sh == 0)) {
1641 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1642 } else {
1643 TCGv t0 = tcg_temp_new();
1644 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1645 tcg_gen_shli_tl(t0, t0, sh);
1646 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1647 tcg_temp_free(t0);
1648 }
1649 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1650 TCGv t0 = tcg_temp_new();
1651 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1652 tcg_gen_shri_tl(t0, t0, mb);
1653 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1654 tcg_temp_free(t0);
1655 } else {
1656 TCGv t0 = tcg_temp_new();
1657 #if defined(TARGET_PPC64)
1658 TCGv_i32 t1 = tcg_temp_new_i32();
1659 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1660 tcg_gen_rotli_i32(t1, t1, sh);
1661 tcg_gen_extu_i32_i64(t0, t1);
1662 tcg_temp_free_i32(t1);
1663 #else
1664 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1665 #endif
1666 #if defined(TARGET_PPC64)
1667 mb += 32;
1668 me += 32;
1669 #endif
1670 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1671 tcg_temp_free(t0);
1672 }
1673 if (unlikely(Rc(ctx->opcode) != 0))
1674 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1675 }
1676
1677 /* rlwnm & rlwnm. */
1678 static void gen_rlwnm(DisasContext *ctx)
1679 {
1680 uint32_t mb, me;
1681 TCGv t0;
1682 #if defined(TARGET_PPC64)
1683 TCGv_i32 t1, t2;
1684 #endif
1685
1686 mb = MB(ctx->opcode);
1687 me = ME(ctx->opcode);
1688 t0 = tcg_temp_new();
1689 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1690 #if defined(TARGET_PPC64)
1691 t1 = tcg_temp_new_i32();
1692 t2 = tcg_temp_new_i32();
1693 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1694 tcg_gen_trunc_i64_i32(t2, t0);
1695 tcg_gen_rotl_i32(t1, t1, t2);
1696 tcg_gen_extu_i32_i64(t0, t1);
1697 tcg_temp_free_i32(t1);
1698 tcg_temp_free_i32(t2);
1699 #else
1700 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1701 #endif
1702 if (unlikely(mb != 0 || me != 31)) {
1703 #if defined(TARGET_PPC64)
1704 mb += 32;
1705 me += 32;
1706 #endif
1707 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1708 } else {
1709 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1710 }
1711 tcg_temp_free(t0);
1712 if (unlikely(Rc(ctx->opcode) != 0))
1713 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1714 }
1715
1716 #if defined(TARGET_PPC64)
1717 #define GEN_PPC64_R2(name, opc1, opc2) \
1718 static void glue(gen_, name##0)(DisasContext *ctx) \
1719 { \
1720 gen_##name(ctx, 0); \
1721 } \
1722 \
1723 static void glue(gen_, name##1)(DisasContext *ctx) \
1724 { \
1725 gen_##name(ctx, 1); \
1726 }
1727 #define GEN_PPC64_R4(name, opc1, opc2) \
1728 static void glue(gen_, name##0)(DisasContext *ctx) \
1729 { \
1730 gen_##name(ctx, 0, 0); \
1731 } \
1732 \
1733 static void glue(gen_, name##1)(DisasContext *ctx) \
1734 { \
1735 gen_##name(ctx, 0, 1); \
1736 } \
1737 \
1738 static void glue(gen_, name##2)(DisasContext *ctx) \
1739 { \
1740 gen_##name(ctx, 1, 0); \
1741 } \
1742 \
1743 static void glue(gen_, name##3)(DisasContext *ctx) \
1744 { \
1745 gen_##name(ctx, 1, 1); \
1746 }
1747
1748 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1749 uint32_t sh)
1750 {
1751 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1752 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1753 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1754 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1755 } else {
1756 TCGv t0 = tcg_temp_new();
1757 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1758 if (likely(mb == 0 && me == 63)) {
1759 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1760 } else {
1761 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1762 }
1763 tcg_temp_free(t0);
1764 }
1765 if (unlikely(Rc(ctx->opcode) != 0))
1766 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1767 }
1768 /* rldicl - rldicl. */
1769 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1770 {
1771 uint32_t sh, mb;
1772
1773 sh = SH(ctx->opcode) | (shn << 5);
1774 mb = MB(ctx->opcode) | (mbn << 5);
1775 gen_rldinm(ctx, mb, 63, sh);
1776 }
1777 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1778 /* rldicr - rldicr. */
1779 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1780 {
1781 uint32_t sh, me;
1782
1783 sh = SH(ctx->opcode) | (shn << 5);
1784 me = MB(ctx->opcode) | (men << 5);
1785 gen_rldinm(ctx, 0, me, sh);
1786 }
1787 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1788 /* rldic - rldic. */
1789 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1790 {
1791 uint32_t sh, mb;
1792
1793 sh = SH(ctx->opcode) | (shn << 5);
1794 mb = MB(ctx->opcode) | (mbn << 5);
1795 gen_rldinm(ctx, mb, 63 - sh, sh);
1796 }
1797 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1798
1799 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1800 {
1801 TCGv t0;
1802
1803 t0 = tcg_temp_new();
1804 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1805 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1806 if (unlikely(mb != 0 || me != 63)) {
1807 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1808 } else {
1809 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1810 }
1811 tcg_temp_free(t0);
1812 if (unlikely(Rc(ctx->opcode) != 0))
1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1814 }
1815
1816 /* rldcl - rldcl. */
1817 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1818 {
1819 uint32_t mb;
1820
1821 mb = MB(ctx->opcode) | (mbn << 5);
1822 gen_rldnm(ctx, mb, 63);
1823 }
1824 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1825 /* rldcr - rldcr. */
1826 static inline void gen_rldcr(DisasContext *ctx, int men)
1827 {
1828 uint32_t me;
1829
1830 me = MB(ctx->opcode) | (men << 5);
1831 gen_rldnm(ctx, 0, me);
1832 }
1833 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1834 /* rldimi - rldimi. */
1835 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1836 {
1837 uint32_t sh, mb, me;
1838
1839 sh = SH(ctx->opcode) | (shn << 5);
1840 mb = MB(ctx->opcode) | (mbn << 5);
1841 me = 63 - sh;
1842 if (unlikely(sh == 0 && mb == 0)) {
1843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1844 } else {
1845 TCGv t0, t1;
1846 target_ulong mask;
1847
1848 t0 = tcg_temp_new();
1849 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1850 t1 = tcg_temp_new();
1851 mask = MASK(mb, me);
1852 tcg_gen_andi_tl(t0, t0, mask);
1853 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1854 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1855 tcg_temp_free(t0);
1856 tcg_temp_free(t1);
1857 }
1858 if (unlikely(Rc(ctx->opcode) != 0))
1859 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1860 }
1861 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1862 #endif
1863
1864 /*** Integer shift ***/
1865
1866 /* slw & slw. */
1867 static void gen_slw(DisasContext *ctx)
1868 {
1869 TCGv t0, t1;
1870
1871 t0 = tcg_temp_new();
1872 /* AND rS with a mask that is 0 when rB >= 0x20 */
1873 #if defined(TARGET_PPC64)
1874 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1875 tcg_gen_sari_tl(t0, t0, 0x3f);
1876 #else
1877 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1878 tcg_gen_sari_tl(t0, t0, 0x1f);
1879 #endif
1880 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1881 t1 = tcg_temp_new();
1882 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1883 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1884 tcg_temp_free(t1);
1885 tcg_temp_free(t0);
1886 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1887 if (unlikely(Rc(ctx->opcode) != 0))
1888 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1889 }
1890
1891 /* sraw & sraw. */
1892 static void gen_sraw(DisasContext *ctx)
1893 {
1894 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1895 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1896 if (unlikely(Rc(ctx->opcode) != 0))
1897 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1898 }
1899
1900 /* srawi & srawi. */
1901 static void gen_srawi(DisasContext *ctx)
1902 {
1903 int sh = SH(ctx->opcode);
1904 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1905 TCGv src = cpu_gpr[rS(ctx->opcode)];
1906 if (sh == 0) {
1907 tcg_gen_mov_tl(dst, src);
1908 tcg_gen_movi_tl(cpu_ca, 0);
1909 } else {
1910 TCGv t0;
1911 tcg_gen_ext32s_tl(dst, src);
1912 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1913 t0 = tcg_temp_new();
1914 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1915 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1916 tcg_temp_free(t0);
1917 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1918 tcg_gen_sari_tl(dst, dst, sh);
1919 }
1920 if (unlikely(Rc(ctx->opcode) != 0)) {
1921 gen_set_Rc0(ctx, dst);
1922 }
1923 }
1924
1925 /* srw & srw. */
1926 static void gen_srw(DisasContext *ctx)
1927 {
1928 TCGv t0, t1;
1929
1930 t0 = tcg_temp_new();
1931 /* AND rS with a mask that is 0 when rB >= 0x20 */
1932 #if defined(TARGET_PPC64)
1933 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1934 tcg_gen_sari_tl(t0, t0, 0x3f);
1935 #else
1936 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1937 tcg_gen_sari_tl(t0, t0, 0x1f);
1938 #endif
1939 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1940 tcg_gen_ext32u_tl(t0, t0);
1941 t1 = tcg_temp_new();
1942 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1943 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1944 tcg_temp_free(t1);
1945 tcg_temp_free(t0);
1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948 }
1949
1950 #if defined(TARGET_PPC64)
1951 /* sld & sld. */
1952 static void gen_sld(DisasContext *ctx)
1953 {
1954 TCGv t0, t1;
1955
1956 t0 = tcg_temp_new();
1957 /* AND rS with a mask that is 0 when rB >= 0x40 */
1958 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1959 tcg_gen_sari_tl(t0, t0, 0x3f);
1960 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1961 t1 = tcg_temp_new();
1962 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1963 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1964 tcg_temp_free(t1);
1965 tcg_temp_free(t0);
1966 if (unlikely(Rc(ctx->opcode) != 0))
1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1968 }
1969
1970 /* srad & srad. */
1971 static void gen_srad(DisasContext *ctx)
1972 {
1973 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1974 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1975 if (unlikely(Rc(ctx->opcode) != 0))
1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1977 }
1978 /* sradi & sradi. */
1979 static inline void gen_sradi(DisasContext *ctx, int n)
1980 {
1981 int sh = SH(ctx->opcode) + (n << 5);
1982 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1983 TCGv src = cpu_gpr[rS(ctx->opcode)];
1984 if (sh == 0) {
1985 tcg_gen_mov_tl(dst, src);
1986 tcg_gen_movi_tl(cpu_ca, 0);
1987 } else {
1988 TCGv t0;
1989 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1990 t0 = tcg_temp_new();
1991 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1992 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1993 tcg_temp_free(t0);
1994 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1995 tcg_gen_sari_tl(dst, src, sh);
1996 }
1997 if (unlikely(Rc(ctx->opcode) != 0)) {
1998 gen_set_Rc0(ctx, dst);
1999 }
2000 }
2001
2002 static void gen_sradi0(DisasContext *ctx)
2003 {
2004 gen_sradi(ctx, 0);
2005 }
2006
2007 static void gen_sradi1(DisasContext *ctx)
2008 {
2009 gen_sradi(ctx, 1);
2010 }
2011
2012 /* srd & srd. */
2013 static void gen_srd(DisasContext *ctx)
2014 {
2015 TCGv t0, t1;
2016
2017 t0 = tcg_temp_new();
2018 /* AND rS with a mask that is 0 when rB >= 0x40 */
2019 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2020 tcg_gen_sari_tl(t0, t0, 0x3f);
2021 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2022 t1 = tcg_temp_new();
2023 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2024 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2025 tcg_temp_free(t1);
2026 tcg_temp_free(t0);
2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029 }
2030 #endif
2031
2032 /*** Floating-Point arithmetic ***/
2033 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2034 static void gen_f##name(DisasContext *ctx) \
2035 { \
2036 if (unlikely(!ctx->fpu_enabled)) { \
2037 gen_exception(ctx, POWERPC_EXCP_FPU); \
2038 return; \
2039 } \
2040 /* NIP cannot be restored if the memory exception comes from an helper */ \
2041 gen_update_nip(ctx, ctx->nip - 4); \
2042 gen_reset_fpstatus(); \
2043 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2044 cpu_fpr[rA(ctx->opcode)], \
2045 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2046 if (isfloat) { \
2047 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2048 cpu_fpr[rD(ctx->opcode)]); \
2049 } \
2050 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2051 Rc(ctx->opcode) != 0); \
2052 }
2053
2054 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2055 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2056 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2057
2058 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2059 static void gen_f##name(DisasContext *ctx) \
2060 { \
2061 if (unlikely(!ctx->fpu_enabled)) { \
2062 gen_exception(ctx, POWERPC_EXCP_FPU); \
2063 return; \
2064 } \
2065 /* NIP cannot be restored if the memory exception comes from an helper */ \
2066 gen_update_nip(ctx, ctx->nip - 4); \
2067 gen_reset_fpstatus(); \
2068 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2069 cpu_fpr[rA(ctx->opcode)], \
2070 cpu_fpr[rB(ctx->opcode)]); \
2071 if (isfloat) { \
2072 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2073 cpu_fpr[rD(ctx->opcode)]); \
2074 } \
2075 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2076 set_fprf, Rc(ctx->opcode) != 0); \
2077 }
2078 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2079 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2080 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2081
2082 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2083 static void gen_f##name(DisasContext *ctx) \
2084 { \
2085 if (unlikely(!ctx->fpu_enabled)) { \
2086 gen_exception(ctx, POWERPC_EXCP_FPU); \
2087 return; \
2088 } \
2089 /* NIP cannot be restored if the memory exception comes from an helper */ \
2090 gen_update_nip(ctx, ctx->nip - 4); \
2091 gen_reset_fpstatus(); \
2092 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2093 cpu_fpr[rA(ctx->opcode)], \
2094 cpu_fpr[rC(ctx->opcode)]); \
2095 if (isfloat) { \
2096 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2097 cpu_fpr[rD(ctx->opcode)]); \
2098 } \
2099 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2100 set_fprf, Rc(ctx->opcode) != 0); \
2101 }
2102 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2103 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2104 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2105
2106 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2107 static void gen_f##name(DisasContext *ctx) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rB(ctx->opcode)]); \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121
2122 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2123 static void gen_f##name(DisasContext *ctx) \
2124 { \
2125 if (unlikely(!ctx->fpu_enabled)) { \
2126 gen_exception(ctx, POWERPC_EXCP_FPU); \
2127 return; \
2128 } \
2129 /* NIP cannot be restored if the memory exception comes from an helper */ \
2130 gen_update_nip(ctx, ctx->nip - 4); \
2131 gen_reset_fpstatus(); \
2132 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2133 cpu_fpr[rB(ctx->opcode)]); \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2135 set_fprf, Rc(ctx->opcode) != 0); \
2136 }
2137
2138 /* fadd - fadds */
2139 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2140 /* fdiv - fdivs */
2141 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2142 /* fmul - fmuls */
2143 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2144
2145 /* fre */
2146 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2147
2148 /* fres */
2149 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2150
2151 /* frsqrte */
2152 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2153
2154 /* frsqrtes */
2155 static void gen_frsqrtes(DisasContext *ctx)
2156 {
2157 if (unlikely(!ctx->fpu_enabled)) {
2158 gen_exception(ctx, POWERPC_EXCP_FPU);
2159 return;
2160 }
2161 /* NIP cannot be restored if the memory exception comes from an helper */
2162 gen_update_nip(ctx, ctx->nip - 4);
2163 gen_reset_fpstatus();
2164 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2165 cpu_fpr[rB(ctx->opcode)]);
2166 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2167 cpu_fpr[rD(ctx->opcode)]);
2168 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2169 }
2170
2171 /* fsel */
2172 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2173 /* fsub - fsubs */
2174 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2175 /* Optional: */
2176
2177 /* fsqrt */
2178 static void gen_fsqrt(DisasContext *ctx)
2179 {
2180 if (unlikely(!ctx->fpu_enabled)) {
2181 gen_exception(ctx, POWERPC_EXCP_FPU);
2182 return;
2183 }
2184 /* NIP cannot be restored if the memory exception comes from an helper */
2185 gen_update_nip(ctx, ctx->nip - 4);
2186 gen_reset_fpstatus();
2187 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2188 cpu_fpr[rB(ctx->opcode)]);
2189 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2190 }
2191
2192 static void gen_fsqrts(DisasContext *ctx)
2193 {
2194 if (unlikely(!ctx->fpu_enabled)) {
2195 gen_exception(ctx, POWERPC_EXCP_FPU);
2196 return;
2197 }
2198 /* NIP cannot be restored if the memory exception comes from an helper */
2199 gen_update_nip(ctx, ctx->nip - 4);
2200 gen_reset_fpstatus();
2201 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2202 cpu_fpr[rB(ctx->opcode)]);
2203 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2204 cpu_fpr[rD(ctx->opcode)]);
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2206 }
2207
2208 /*** Floating-Point multiply-and-add ***/
2209 /* fmadd - fmadds */
2210 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2211 /* fmsub - fmsubs */
2212 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2213 /* fnmadd - fnmadds */
2214 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2215 /* fnmsub - fnmsubs */
2216 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2217
2218 /*** Floating-Point round & convert ***/
2219 /* fctiw */
2220 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2221 /* fctiwu */
2222 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2223 /* fctiwz */
2224 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2225 /* fctiwuz */
2226 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2227 /* frsp */
2228 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2229 #if defined(TARGET_PPC64)
2230 /* fcfid */
2231 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2232 /* fcfids */
2233 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2234 /* fcfidu */
2235 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2236 /* fcfidus */
2237 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2238 /* fctid */
2239 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2240 /* fctidu */
2241 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2242 /* fctidz */
2243 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2244 /* fctidu */
2245 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2246 #endif
2247
2248 /* frin */
2249 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2250 /* friz */
2251 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2252 /* frip */
2253 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2254 /* frim */
2255 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2256
2257 static void gen_ftdiv(DisasContext *ctx)
2258 {
2259 if (unlikely(!ctx->fpu_enabled)) {
2260 gen_exception(ctx, POWERPC_EXCP_FPU);
2261 return;
2262 }
2263 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2264 cpu_fpr[rB(ctx->opcode)]);
2265 }
2266
2267 static void gen_ftsqrt(DisasContext *ctx)
2268 {
2269 if (unlikely(!ctx->fpu_enabled)) {
2270 gen_exception(ctx, POWERPC_EXCP_FPU);
2271 return;
2272 }
2273 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2274 }
2275
2276
2277
2278 /*** Floating-Point compare ***/
2279
2280 /* fcmpo */
2281 static void gen_fcmpo(DisasContext *ctx)
2282 {
2283 TCGv_i32 crf;
2284 if (unlikely(!ctx->fpu_enabled)) {
2285 gen_exception(ctx, POWERPC_EXCP_FPU);
2286 return;
2287 }
2288 /* NIP cannot be restored if the memory exception comes from an helper */
2289 gen_update_nip(ctx, ctx->nip - 4);
2290 gen_reset_fpstatus();
2291 crf = tcg_const_i32(crfD(ctx->opcode));
2292 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2293 cpu_fpr[rB(ctx->opcode)], crf);
2294 tcg_temp_free_i32(crf);
2295 gen_helper_float_check_status(cpu_env);
2296 }
2297
2298 /* fcmpu */
2299 static void gen_fcmpu(DisasContext *ctx)
2300 {
2301 TCGv_i32 crf;
2302 if (unlikely(!ctx->fpu_enabled)) {
2303 gen_exception(ctx, POWERPC_EXCP_FPU);
2304 return;
2305 }
2306 /* NIP cannot be restored if the memory exception comes from an helper */
2307 gen_update_nip(ctx, ctx->nip - 4);
2308 gen_reset_fpstatus();
2309 crf = tcg_const_i32(crfD(ctx->opcode));
2310 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2311 cpu_fpr[rB(ctx->opcode)], crf);
2312 tcg_temp_free_i32(crf);
2313 gen_helper_float_check_status(cpu_env);
2314 }
2315
2316 /*** Floating-point move ***/
2317 /* fabs */
2318 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2319 static void gen_fabs(DisasContext *ctx)
2320 {
2321 if (unlikely(!ctx->fpu_enabled)) {
2322 gen_exception(ctx, POWERPC_EXCP_FPU);
2323 return;
2324 }
2325 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2326 ~(1ULL << 63));
2327 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2328 }
2329
2330 /* fmr - fmr. */
2331 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2332 static void gen_fmr(DisasContext *ctx)
2333 {
2334 if (unlikely(!ctx->fpu_enabled)) {
2335 gen_exception(ctx, POWERPC_EXCP_FPU);
2336 return;
2337 }
2338 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2339 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2340 }
2341
2342 /* fnabs */
2343 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2344 static void gen_fnabs(DisasContext *ctx)
2345 {
2346 if (unlikely(!ctx->fpu_enabled)) {
2347 gen_exception(ctx, POWERPC_EXCP_FPU);
2348 return;
2349 }
2350 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2351 1ULL << 63);
2352 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2353 }
2354
2355 /* fneg */
2356 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2357 static void gen_fneg(DisasContext *ctx)
2358 {
2359 if (unlikely(!ctx->fpu_enabled)) {
2360 gen_exception(ctx, POWERPC_EXCP_FPU);
2361 return;
2362 }
2363 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2364 1ULL << 63);
2365 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2366 }
2367
2368 /* fcpsgn: PowerPC 2.05 specification */
2369 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2370 static void gen_fcpsgn(DisasContext *ctx)
2371 {
2372 if (unlikely(!ctx->fpu_enabled)) {
2373 gen_exception(ctx, POWERPC_EXCP_FPU);
2374 return;
2375 }
2376 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2377 cpu_fpr[rB(ctx->opcode)], 0, 63);
2378 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2379 }
2380
2381 static void gen_fmrgew(DisasContext *ctx)
2382 {
2383 TCGv_i64 b0;
2384 if (unlikely(!ctx->fpu_enabled)) {
2385 gen_exception(ctx, POWERPC_EXCP_FPU);
2386 return;
2387 }
2388 b0 = tcg_temp_new_i64();
2389 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2390 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2391 b0, 0, 32);
2392 tcg_temp_free_i64(b0);
2393 }
2394
2395 static void gen_fmrgow(DisasContext *ctx)
2396 {
2397 if (unlikely(!ctx->fpu_enabled)) {
2398 gen_exception(ctx, POWERPC_EXCP_FPU);
2399 return;
2400 }
2401 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2402 cpu_fpr[rB(ctx->opcode)],
2403 cpu_fpr[rA(ctx->opcode)],
2404 32, 32);
2405 }
2406
2407 /*** Floating-Point status & ctrl register ***/
2408
2409 /* mcrfs */
2410 static void gen_mcrfs(DisasContext *ctx)
2411 {
2412 TCGv tmp = tcg_temp_new();
2413 int bfa;
2414
2415 if (unlikely(!ctx->fpu_enabled)) {
2416 gen_exception(ctx, POWERPC_EXCP_FPU);
2417 return;
2418 }
2419 bfa = 4 * (7 - crfS(ctx->opcode));
2420 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2421 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2422 tcg_temp_free(tmp);
2423 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2424 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2425 }
2426
2427 /* mffs */
2428 static void gen_mffs(DisasContext *ctx)
2429 {
2430 if (unlikely(!ctx->fpu_enabled)) {
2431 gen_exception(ctx, POWERPC_EXCP_FPU);
2432 return;
2433 }
2434 gen_reset_fpstatus();
2435 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2436 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2437 }
2438
2439 /* mtfsb0 */
2440 static void gen_mtfsb0(DisasContext *ctx)
2441 {
2442 uint8_t crb;
2443
2444 if (unlikely(!ctx->fpu_enabled)) {
2445 gen_exception(ctx, POWERPC_EXCP_FPU);
2446 return;
2447 }
2448 crb = 31 - crbD(ctx->opcode);
2449 gen_reset_fpstatus();
2450 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2451 TCGv_i32 t0;
2452 /* NIP cannot be restored if the memory exception comes from an helper */
2453 gen_update_nip(ctx, ctx->nip - 4);
2454 t0 = tcg_const_i32(crb);
2455 gen_helper_fpscr_clrbit(cpu_env, t0);
2456 tcg_temp_free_i32(t0);
2457 }
2458 if (unlikely(Rc(ctx->opcode) != 0)) {
2459 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2460 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2461 }
2462 }
2463
2464 /* mtfsb1 */
2465 static void gen_mtfsb1(DisasContext *ctx)
2466 {
2467 uint8_t crb;
2468
2469 if (unlikely(!ctx->fpu_enabled)) {
2470 gen_exception(ctx, POWERPC_EXCP_FPU);
2471 return;
2472 }
2473 crb = 31 - crbD(ctx->opcode);
2474 gen_reset_fpstatus();
2475 /* XXX: we pretend we can only do IEEE floating-point computations */
2476 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2477 TCGv_i32 t0;
2478 /* NIP cannot be restored if the memory exception comes from an helper */
2479 gen_update_nip(ctx, ctx->nip - 4);
2480 t0 = tcg_const_i32(crb);
2481 gen_helper_fpscr_setbit(cpu_env, t0);
2482 tcg_temp_free_i32(t0);
2483 }
2484 if (unlikely(Rc(ctx->opcode) != 0)) {
2485 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2486 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2487 }
2488 /* We can raise a differed exception */
2489 gen_helper_float_check_status(cpu_env);
2490 }
2491
2492 /* mtfsf */
2493 static void gen_mtfsf(DisasContext *ctx)
2494 {
2495 TCGv_i32 t0;
2496 int flm, l, w;
2497
2498 if (unlikely(!ctx->fpu_enabled)) {
2499 gen_exception(ctx, POWERPC_EXCP_FPU);
2500 return;
2501 }
2502 flm = FPFLM(ctx->opcode);
2503 l = FPL(ctx->opcode);
2504 w = FPW(ctx->opcode);
2505 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2507 return;
2508 }
2509 /* NIP cannot be restored if the memory exception comes from an helper */
2510 gen_update_nip(ctx, ctx->nip - 4);
2511 gen_reset_fpstatus();
2512 if (l) {
2513 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2514 } else {
2515 t0 = tcg_const_i32(flm << (w * 8));
2516 }
2517 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2518 tcg_temp_free_i32(t0);
2519 if (unlikely(Rc(ctx->opcode) != 0)) {
2520 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2521 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2522 }
2523 /* We can raise a differed exception */
2524 gen_helper_float_check_status(cpu_env);
2525 }
2526
2527 /* mtfsfi */
2528 static void gen_mtfsfi(DisasContext *ctx)
2529 {
2530 int bf, sh, w;
2531 TCGv_i64 t0;
2532 TCGv_i32 t1;
2533
2534 if (unlikely(!ctx->fpu_enabled)) {
2535 gen_exception(ctx, POWERPC_EXCP_FPU);
2536 return;
2537 }
2538 w = FPW(ctx->opcode);
2539 bf = FPBF(ctx->opcode);
2540 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2541 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2542 return;
2543 }
2544 sh = (8 * w) + 7 - bf;
2545 /* NIP cannot be restored if the memory exception comes from an helper */
2546 gen_update_nip(ctx, ctx->nip - 4);
2547 gen_reset_fpstatus();
2548 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2549 t1 = tcg_const_i32(1 << sh);
2550 gen_helper_store_fpscr(cpu_env, t0, t1);
2551 tcg_temp_free_i64(t0);
2552 tcg_temp_free_i32(t1);
2553 if (unlikely(Rc(ctx->opcode) != 0)) {
2554 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2555 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2556 }
2557 /* We can raise a differed exception */
2558 gen_helper_float_check_status(cpu_env);
2559 }
2560
2561 /*** Addressing modes ***/
2562 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2563 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2564 target_long maskl)
2565 {
2566 target_long simm = SIMM(ctx->opcode);
2567
2568 simm &= ~maskl;
2569 if (rA(ctx->opcode) == 0) {
2570 if (NARROW_MODE(ctx)) {
2571 simm = (uint32_t)simm;
2572 }
2573 tcg_gen_movi_tl(EA, simm);
2574 } else if (likely(simm != 0)) {
2575 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2576 if (NARROW_MODE(ctx)) {
2577 tcg_gen_ext32u_tl(EA, EA);
2578 }
2579 } else {
2580 if (NARROW_MODE(ctx)) {
2581 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2582 } else {
2583 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2584 }
2585 }
2586 }
2587
2588 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2589 {
2590 if (rA(ctx->opcode) == 0) {
2591 if (NARROW_MODE(ctx)) {
2592 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2593 } else {
2594 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2595 }
2596 } else {
2597 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2598 if (NARROW_MODE(ctx)) {
2599 tcg_gen_ext32u_tl(EA, EA);
2600 }
2601 }
2602 }
2603
2604 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2605 {
2606 if (rA(ctx->opcode) == 0) {
2607 tcg_gen_movi_tl(EA, 0);
2608 } else if (NARROW_MODE(ctx)) {
2609 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2610 } else {
2611 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2612 }
2613 }
2614
2615 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2616 target_long val)
2617 {
2618 tcg_gen_addi_tl(ret, arg1, val);
2619 if (NARROW_MODE(ctx)) {
2620 tcg_gen_ext32u_tl(ret, ret);
2621 }
2622 }
2623
2624 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2625 {
2626 int l1 = gen_new_label();
2627 TCGv t0 = tcg_temp_new();
2628 TCGv_i32 t1, t2;
2629 /* NIP cannot be restored if the memory exception comes from an helper */
2630 gen_update_nip(ctx, ctx->nip - 4);
2631 tcg_gen_andi_tl(t0, EA, mask);
2632 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2633 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2634 t2 = tcg_const_i32(0);
2635 gen_helper_raise_exception_err(cpu_env, t1, t2);
2636 tcg_temp_free_i32(t1);
2637 tcg_temp_free_i32(t2);
2638 gen_set_label(l1);
2639 tcg_temp_free(t0);
2640 }
2641
2642 /*** Integer load ***/
2643 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2644 {
2645 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2646 }
2647
2648 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2649 {
2650 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2651 }
2652
2653 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2654 {
2655 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2656 if (unlikely(ctx->le_mode)) {
2657 tcg_gen_bswap16_tl(arg1, arg1);
2658 }
2659 }
2660
2661 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2662 {
2663 if (unlikely(ctx->le_mode)) {
2664 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2665 tcg_gen_bswap16_tl(arg1, arg1);
2666 tcg_gen_ext16s_tl(arg1, arg1);
2667 } else {
2668 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2669 }
2670 }
2671
2672 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2673 {
2674 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2675 if (unlikely(ctx->le_mode)) {
2676 tcg_gen_bswap32_tl(arg1, arg1);
2677 }
2678 }
2679
2680 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2681 {
2682 TCGv tmp = tcg_temp_new();
2683 gen_qemu_ld32u(ctx, tmp, addr);
2684 tcg_gen_extu_tl_i64(val, tmp);
2685 tcg_temp_free(tmp);
2686 }
2687
2688 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2689 {
2690 if (unlikely(ctx->le_mode)) {
2691 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2692 tcg_gen_bswap32_tl(arg1, arg1);
2693 tcg_gen_ext32s_tl(arg1, arg1);
2694 } else
2695 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2696 }
2697
2698 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2699 {
2700 TCGv tmp = tcg_temp_new();
2701 gen_qemu_ld32s(ctx, tmp, addr);
2702 tcg_gen_ext_tl_i64(val, tmp);
2703 tcg_temp_free(tmp);
2704 }
2705
2706 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2707 {
2708 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2709 if (unlikely(ctx->le_mode)) {
2710 tcg_gen_bswap64_i64(arg1, arg1);
2711 }
2712 }
2713
2714 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2715 {
2716 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2717 }
2718
2719 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2720 {
2721 if (unlikely(ctx->le_mode)) {
2722 TCGv t0 = tcg_temp_new();
2723 tcg_gen_ext16u_tl(t0, arg1);
2724 tcg_gen_bswap16_tl(t0, t0);
2725 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2726 tcg_temp_free(t0);
2727 } else {
2728 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2729 }
2730 }
2731
2732 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2733 {
2734 if (unlikely(ctx->le_mode)) {
2735 TCGv t0 = tcg_temp_new();
2736 tcg_gen_ext32u_tl(t0, arg1);
2737 tcg_gen_bswap32_tl(t0, t0);
2738 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2739 tcg_temp_free(t0);
2740 } else {
2741 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2742 }
2743 }
2744
2745 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2746 {
2747 TCGv tmp = tcg_temp_new();
2748 tcg_gen_trunc_i64_tl(tmp, val);
2749 gen_qemu_st32(ctx, tmp, addr);
2750 tcg_temp_free(tmp);
2751 }
2752
2753 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2754 {
2755 if (unlikely(ctx->le_mode)) {
2756 TCGv_i64 t0 = tcg_temp_new_i64();
2757 tcg_gen_bswap64_i64(t0, arg1);
2758 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2759 tcg_temp_free_i64(t0);
2760 } else
2761 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2762 }
2763
2764 #define GEN_LD(name, ldop, opc, type) \
2765 static void glue(gen_, name)(DisasContext *ctx) \
2766 { \
2767 TCGv EA; \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 gen_addr_imm_index(ctx, EA, 0); \
2771 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2772 tcg_temp_free(EA); \
2773 }
2774
2775 #define GEN_LDU(name, ldop, opc, type) \
2776 static void glue(gen_, name##u)(DisasContext *ctx) \
2777 { \
2778 TCGv EA; \
2779 if (unlikely(rA(ctx->opcode) == 0 || \
2780 rA(ctx->opcode) == rD(ctx->opcode))) { \
2781 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2782 return; \
2783 } \
2784 gen_set_access_type(ctx, ACCESS_INT); \
2785 EA = tcg_temp_new(); \
2786 if (type == PPC_64B) \
2787 gen_addr_imm_index(ctx, EA, 0x03); \
2788 else \
2789 gen_addr_imm_index(ctx, EA, 0); \
2790 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2791 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2792 tcg_temp_free(EA); \
2793 }
2794
2795 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2796 static void glue(gen_, name##ux)(DisasContext *ctx) \
2797 { \
2798 TCGv EA; \
2799 if (unlikely(rA(ctx->opcode) == 0 || \
2800 rA(ctx->opcode) == rD(ctx->opcode))) { \
2801 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2802 return; \
2803 } \
2804 gen_set_access_type(ctx, ACCESS_INT); \
2805 EA = tcg_temp_new(); \
2806 gen_addr_reg_index(ctx, EA); \
2807 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2808 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2809 tcg_temp_free(EA); \
2810 }
2811
2812 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2813 static void glue(gen_, name##x)(DisasContext *ctx) \
2814 { \
2815 TCGv EA; \
2816 gen_set_access_type(ctx, ACCESS_INT); \
2817 EA = tcg_temp_new(); \
2818 gen_addr_reg_index(ctx, EA); \
2819 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2820 tcg_temp_free(EA); \
2821 }
2822 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2823 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2824
2825 #define GEN_LDS(name, ldop, op, type) \
2826 GEN_LD(name, ldop, op | 0x20, type); \
2827 GEN_LDU(name, ldop, op | 0x21, type); \
2828 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2829 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2830
2831 /* lbz lbzu lbzux lbzx */
2832 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2833 /* lha lhau lhaux lhax */
2834 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2835 /* lhz lhzu lhzux lhzx */
2836 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2837 /* lwz lwzu lwzux lwzx */
2838 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2839 #if defined(TARGET_PPC64)
2840 /* lwaux */
2841 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2842 /* lwax */
2843 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2844 /* ldux */
2845 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2846 /* ldx */
2847 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2848
2849 static void gen_ld(DisasContext *ctx)
2850 {
2851 TCGv EA;
2852 if (Rc(ctx->opcode)) {
2853 if (unlikely(rA(ctx->opcode) == 0 ||
2854 rA(ctx->opcode) == rD(ctx->opcode))) {
2855 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2856 return;
2857 }
2858 }
2859 gen_set_access_type(ctx, ACCESS_INT);
2860 EA = tcg_temp_new();
2861 gen_addr_imm_index(ctx, EA, 0x03);
2862 if (ctx->opcode & 0x02) {
2863 /* lwa (lwau is undefined) */
2864 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2865 } else {
2866 /* ld - ldu */
2867 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2868 }
2869 if (Rc(ctx->opcode))
2870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2871 tcg_temp_free(EA);
2872 }
2873
2874 /* lq */
2875 static void gen_lq(DisasContext *ctx)
2876 {
2877 int ra, rd;
2878 TCGv EA;
2879
2880 /* lq is a legal user mode instruction starting in ISA 2.07 */
2881 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2882 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2883
2884 if (!legal_in_user_mode && is_user_mode(ctx)) {
2885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2886 return;
2887 }
2888
2889 if (!le_is_supported && ctx->le_mode) {
2890 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2891 return;
2892 }
2893
2894 ra = rA(ctx->opcode);
2895 rd = rD(ctx->opcode);
2896 if (unlikely((rd & 1) || rd == ra)) {
2897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2898 return;
2899 }
2900
2901 gen_set_access_type(ctx, ACCESS_INT);
2902 EA = tcg_temp_new();
2903 gen_addr_imm_index(ctx, EA, 0x0F);
2904
2905 if (unlikely(ctx->le_mode)) {
2906 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2907 gen_addr_add(ctx, EA, EA, 8);
2908 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2909 } else {
2910 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2911 gen_addr_add(ctx, EA, EA, 8);
2912 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2913 }
2914 tcg_temp_free(EA);
2915 }
2916 #endif
2917
2918 /*** Integer store ***/
2919 #define GEN_ST(name, stop, opc, type) \
2920 static void glue(gen_, name)(DisasContext *ctx) \
2921 { \
2922 TCGv EA; \
2923 gen_set_access_type(ctx, ACCESS_INT); \
2924 EA = tcg_temp_new(); \
2925 gen_addr_imm_index(ctx, EA, 0); \
2926 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2927 tcg_temp_free(EA); \
2928 }
2929
2930 #define GEN_STU(name, stop, opc, type) \
2931 static void glue(gen_, stop##u)(DisasContext *ctx) \
2932 { \
2933 TCGv EA; \
2934 if (unlikely(rA(ctx->opcode) == 0)) { \
2935 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2936 return; \
2937 } \
2938 gen_set_access_type(ctx, ACCESS_INT); \
2939 EA = tcg_temp_new(); \
2940 if (type == PPC_64B) \
2941 gen_addr_imm_index(ctx, EA, 0x03); \
2942 else \
2943 gen_addr_imm_index(ctx, EA, 0); \
2944 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2945 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2946 tcg_temp_free(EA); \
2947 }
2948
2949 #define GEN_STUX(name, stop, opc2, opc3, type) \
2950 static void glue(gen_, name##ux)(DisasContext *ctx) \
2951 { \
2952 TCGv EA; \
2953 if (unlikely(rA(ctx->opcode) == 0)) { \
2954 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2955 return; \
2956 } \
2957 gen_set_access_type(ctx, ACCESS_INT); \
2958 EA = tcg_temp_new(); \
2959 gen_addr_reg_index(ctx, EA); \
2960 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2961 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2962 tcg_temp_free(EA); \
2963 }
2964
2965 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2966 static void glue(gen_, name##x)(DisasContext *ctx) \
2967 { \
2968 TCGv EA; \
2969 gen_set_access_type(ctx, ACCESS_INT); \
2970 EA = tcg_temp_new(); \
2971 gen_addr_reg_index(ctx, EA); \
2972 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2973 tcg_temp_free(EA); \
2974 }
2975 #define GEN_STX(name, stop, opc2, opc3, type) \
2976 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2977
2978 #define GEN_STS(name, stop, op, type) \
2979 GEN_ST(name, stop, op | 0x20, type); \
2980 GEN_STU(name, stop, op | 0x21, type); \
2981 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2982 GEN_STX(name, stop, 0x17, op | 0x00, type)
2983
2984 /* stb stbu stbux stbx */
2985 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2986 /* sth sthu sthux sthx */
2987 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2988 /* stw stwu stwux stwx */
2989 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2990 #if defined(TARGET_PPC64)
2991 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2992 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2993
2994 static void gen_std(DisasContext *ctx)
2995 {
2996 int rs;
2997 TCGv EA;
2998
2999 rs = rS(ctx->opcode);
3000 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3001
3002 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3003 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3004
3005 if (!legal_in_user_mode && is_user_mode(ctx)) {
3006 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3007 return;
3008 }
3009
3010 if (!le_is_supported && ctx->le_mode) {
3011 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3012 return;
3013 }
3014
3015 if (unlikely(rs & 1)) {
3016 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3017 return;
3018 }
3019 gen_set_access_type(ctx, ACCESS_INT);
3020 EA = tcg_temp_new();
3021 gen_addr_imm_index(ctx, EA, 0x03);
3022
3023 if (unlikely(ctx->le_mode)) {
3024 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3025 gen_addr_add(ctx, EA, EA, 8);
3026 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3027 } else {
3028 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3029 gen_addr_add(ctx, EA, EA, 8);
3030 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3031 }
3032 tcg_temp_free(EA);
3033 } else {
3034 /* std / stdu*/
3035 if (Rc(ctx->opcode)) {
3036 if (unlikely(rA(ctx->opcode) == 0)) {
3037 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3038 return;
3039 }
3040 }
3041 gen_set_access_type(ctx, ACCESS_INT);
3042 EA = tcg_temp_new();
3043 gen_addr_imm_index(ctx, EA, 0x03);
3044 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3045 if (Rc(ctx->opcode))
3046 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3047 tcg_temp_free(EA);
3048 }
3049 }
3050 #endif
3051 /*** Integer load and store with byte reverse ***/
3052 /* lhbrx */
3053 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3054 {
3055 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3056 if (likely(!ctx->le_mode)) {
3057 tcg_gen_bswap16_tl(arg1, arg1);
3058 }
3059 }
3060 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3061
3062 /* lwbrx */
3063 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3064 {
3065 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3066 if (likely(!ctx->le_mode)) {
3067 tcg_gen_bswap32_tl(arg1, arg1);
3068 }
3069 }
3070 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3071
3072 #if defined(TARGET_PPC64)
3073 /* ldbrx */
3074 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3075 {
3076 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3077 if (likely(!ctx->le_mode)) {
3078 tcg_gen_bswap64_tl(arg1, arg1);
3079 }
3080 }
3081 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3082 #endif /* TARGET_PPC64 */
3083
3084 /* sthbrx */
3085 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3086 {
3087 if (likely(!ctx->le_mode)) {
3088 TCGv t0 = tcg_temp_new();
3089 tcg_gen_ext16u_tl(t0, arg1);
3090 tcg_gen_bswap16_tl(t0, t0);
3091 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3092 tcg_temp_free(t0);
3093 } else {
3094 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3095 }
3096 }
3097 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3098
3099 /* stwbrx */
3100 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3101 {
3102 if (likely(!ctx->le_mode)) {
3103 TCGv t0 = tcg_temp_new();
3104 tcg_gen_ext32u_tl(t0, arg1);
3105 tcg_gen_bswap32_tl(t0, t0);
3106 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3107 tcg_temp_free(t0);
3108 } else {
3109 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3110 }
3111 }
3112 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3113
3114 #if defined(TARGET_PPC64)
3115 /* stdbrx */
3116 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3117 {
3118 if (likely(!ctx->le_mode)) {
3119 TCGv t0 = tcg_temp_new();
3120 tcg_gen_bswap64_tl(t0, arg1);
3121 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3122 tcg_temp_free(t0);
3123 } else {
3124 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3125 }
3126 }
3127 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3128 #endif /* TARGET_PPC64 */
3129
3130 /*** Integer load and store multiple ***/
3131
3132 /* lmw */
3133 static void gen_lmw(DisasContext *ctx)
3134 {
3135 TCGv t0;
3136 TCGv_i32 t1;
3137 gen_set_access_type(ctx, ACCESS_INT);
3138 /* NIP cannot be restored if the memory exception comes from an helper */
3139 gen_update_nip(ctx, ctx->nip - 4);
3140 t0 = tcg_temp_new();
3141 t1 = tcg_const_i32(rD(ctx->opcode));
3142 gen_addr_imm_index(ctx, t0, 0);
3143 gen_helper_lmw(cpu_env, t0, t1);
3144 tcg_temp_free(t0);
3145 tcg_temp_free_i32(t1);
3146 }
3147
3148 /* stmw */
3149 static void gen_stmw(DisasContext *ctx)
3150 {
3151 TCGv t0;
3152 TCGv_i32 t1;
3153 gen_set_access_type(ctx, ACCESS_INT);
3154 /* NIP cannot be restored if the memory exception comes from an helper */
3155 gen_update_nip(ctx, ctx->nip - 4);
3156 t0 = tcg_temp_new();
3157 t1 = tcg_const_i32(rS(ctx->opcode));
3158 gen_addr_imm_index(ctx, t0, 0);
3159 gen_helper_stmw(cpu_env, t0, t1);
3160 tcg_temp_free(t0);
3161 tcg_temp_free_i32(t1);
3162 }
3163
3164 /*** Integer load and store strings ***/
3165
3166 /* lswi */
3167 /* PowerPC32 specification says we must generate an exception if
3168 * rA is in the range of registers to be loaded.
3169 * In an other hand, IBM says this is valid, but rA won't be loaded.
3170 * For now, I'll follow the spec...
3171 */
3172 static void gen_lswi(DisasContext *ctx)
3173 {
3174 TCGv t0;
3175 TCGv_i32 t1, t2;
3176 int nb = NB(ctx->opcode);
3177 int start = rD(ctx->opcode);
3178 int ra = rA(ctx->opcode);
3179 int nr;
3180
3181 if (nb == 0)
3182 nb = 32;
3183 nr = nb / 4;
3184 if (unlikely(((start + nr) > 32 &&
3185 start <= ra && (start + nr - 32) > ra) ||
3186 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3187 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3188 return;
3189 }
3190 gen_set_access_type(ctx, ACCESS_INT);
3191 /* NIP cannot be restored if the memory exception comes from an helper */
3192 gen_update_nip(ctx, ctx->nip - 4);
3193 t0 = tcg_temp_new();
3194 gen_addr_register(ctx, t0);
3195 t1 = tcg_const_i32(nb);
3196 t2 = tcg_const_i32(start);
3197 gen_helper_lsw(cpu_env, t0, t1, t2);
3198 tcg_temp_free(t0);
3199 tcg_temp_free_i32(t1);
3200 tcg_temp_free_i32(t2);
3201 }
3202
3203 /* lswx */
3204 static void gen_lswx(DisasContext *ctx)
3205 {
3206 TCGv t0;
3207 TCGv_i32 t1, t2, t3;
3208 gen_set_access_type(ctx, ACCESS_INT);
3209 /* NIP cannot be restored if the memory exception comes from an helper */
3210 gen_update_nip(ctx, ctx->nip - 4);
3211 t0 = tcg_temp_new();
3212 gen_addr_reg_index(ctx, t0);
3213 t1 = tcg_const_i32(rD(ctx->opcode));
3214 t2 = tcg_const_i32(rA(ctx->opcode));
3215 t3 = tcg_const_i32(rB(ctx->opcode));
3216 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3217 tcg_temp_free(t0);
3218 tcg_temp_free_i32(t1);
3219 tcg_temp_free_i32(t2);
3220 tcg_temp_free_i32(t3);
3221 }
3222
3223 /* stswi */
3224 static void gen_stswi(DisasContext *ctx)
3225 {
3226 TCGv t0;
3227 TCGv_i32 t1, t2;
3228 int nb = NB(ctx->opcode);
3229 gen_set_access_type(ctx, ACCESS_INT);
3230 /* NIP cannot be restored if the memory exception comes from an helper */
3231 gen_update_nip(ctx, ctx->nip - 4);
3232 t0 = tcg_temp_new();
3233 gen_addr_register(ctx, t0);
3234 if (nb == 0)
3235 nb = 32;
3236 t1 = tcg_const_i32(nb);
3237 t2 = tcg_const_i32(rS(ctx->opcode));
3238 gen_helper_stsw(cpu_env, t0, t1, t2);
3239 tcg_temp_free(t0);
3240 tcg_temp_free_i32(t1);
3241 tcg_temp_free_i32(t2);
3242 }
3243
3244 /* stswx */
3245 static void gen_stswx(DisasContext *ctx)
3246 {
3247 TCGv t0;
3248 TCGv_i32 t1, t2;
3249 gen_set_access_type(ctx, ACCESS_INT);
3250 /* NIP cannot be restored if the memory exception comes from an helper */
3251 gen_update_nip(ctx, ctx->nip - 4);
3252 t0 = tcg_temp_new();
3253 gen_addr_reg_index(ctx, t0);
3254 t1 = tcg_temp_new_i32();
3255 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3256 tcg_gen_andi_i32(t1, t1, 0x7F);
3257 t2 = tcg_const_i32(rS(ctx->opcode));
3258 gen_helper_stsw(cpu_env, t0, t1, t2);
3259 tcg_temp_free(t0);
3260 tcg_temp_free_i32(t1);
3261 tcg_temp_free_i32(t2);
3262 }
3263
3264 /*** Memory synchronisation ***/
3265 /* eieio */
3266 static void gen_eieio(DisasContext *ctx)
3267 {
3268 }
3269
3270 /* isync */
3271 static void gen_isync(DisasContext *ctx)
3272 {
3273 gen_stop_exception(ctx);
3274 }
3275
3276 #define LARX(name, len, loadop) \
3277 static void gen_##name(DisasContext *ctx) \
3278 { \
3279 TCGv t0; \
3280 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3281 gen_set_access_type(ctx, ACCESS_RES); \
3282 t0 = tcg_temp_local_new(); \
3283 gen_addr_reg_index(ctx, t0); \
3284 if ((len) > 1) { \
3285 gen_check_align(ctx, t0, (len)-1); \
3286 } \
3287 gen_qemu_##loadop(ctx, gpr, t0); \
3288 tcg_gen_mov_tl(cpu_reserve, t0); \
3289 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3290 tcg_temp_free(t0); \
3291 }
3292
3293 /* lwarx */
3294 LARX(lbarx, 1, ld8u);
3295 LARX(lharx, 2, ld16u);
3296 LARX(lwarx, 4, ld32u);
3297
3298
3299 #if defined(CONFIG_USER_ONLY)
3300 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3301 int reg, int size)
3302 {
3303 TCGv t0 = tcg_temp_new();
3304 uint32_t save_exception = ctx->exception;
3305
3306 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3307 tcg_gen_movi_tl(t0, (size << 5) | reg);
3308 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3309 tcg_temp_free(t0);
3310 gen_update_nip(ctx, ctx->nip-4);
3311 ctx->exception = POWERPC_EXCP_BRANCH;
3312 gen_exception(ctx, POWERPC_EXCP_STCX);
3313 ctx->exception = save_exception;
3314 }
3315 #else
3316 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3317 int reg, int size)
3318 {
3319 int l1;
3320
3321 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3322 l1 = gen_new_label();
3323 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3324 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3325 #if defined(TARGET_PPC64)
3326 if (size == 8) {
3327 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3328 } else
3329 #endif
3330 if (size == 4) {
3331 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3332 } else if (size == 2) {
3333 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3334 #if defined(TARGET_PPC64)
3335 } else if (size == 16) {
3336 TCGv gpr1, gpr2 , EA8;
3337 if (unlikely(ctx->le_mode)) {
3338 gpr1 = cpu_gpr[reg+1];
3339 gpr2 = cpu_gpr[reg];
3340 } else {
3341 gpr1 = cpu_gpr[reg];
3342 gpr2 = cpu_gpr[reg+1];
3343 }
3344 gen_qemu_st64(ctx, gpr1, EA);
3345 EA8 = tcg_temp_local_new();
3346 gen_addr_add(ctx, EA8, EA, 8);
3347 gen_qemu_st64(ctx, gpr2, EA8);
3348 tcg_temp_free(EA8);
3349 #endif
3350 } else {
3351 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3352 }
3353 gen_set_label(l1);
3354 tcg_gen_movi_tl(cpu_reserve, -1);
3355 }
3356 #endif
3357
3358 #define STCX(name, len) \
3359 static void gen_##name(DisasContext *ctx) \
3360 { \
3361 TCGv t0; \
3362 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3363 gen_inval_exception(ctx, \
3364 POWERPC_EXCP_INVAL_INVAL); \
3365 return; \
3366 } \
3367 gen_set_access_type(ctx, ACCESS_RES); \
3368 t0 = tcg_temp_local_new(); \
3369 gen_addr_reg_index(ctx, t0); \
3370 if (len > 1) { \
3371 gen_check_align(ctx, t0, (len)-1); \
3372 } \
3373 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3374 tcg_temp_free(t0); \
3375 }
3376
3377 STCX(stbcx_, 1);
3378 STCX(sthcx_, 2);
3379 STCX(stwcx_, 4);
3380
3381 #if defined(TARGET_PPC64)
3382 /* ldarx */
3383 LARX(ldarx, 8, ld64);
3384
3385 /* lqarx */
3386 static void gen_lqarx(DisasContext *ctx)
3387 {
3388 TCGv EA;
3389 int rd = rD(ctx->opcode);
3390 TCGv gpr1, gpr2;
3391
3392 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3393 (rd == rB(ctx->opcode)))) {
3394 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3395 return;
3396 }
3397
3398 gen_set_access_type(ctx, ACCESS_RES);
3399 EA = tcg_temp_local_new();
3400 gen_addr_reg_index(ctx, EA);
3401 gen_check_align(ctx, EA, 15);
3402 if (unlikely(ctx->le_mode)) {
3403 gpr1 = cpu_gpr[rd+1];
3404 gpr2 = cpu_gpr[rd];
3405 } else {
3406 gpr1 = cpu_gpr[rd];
3407 gpr2 = cpu_gpr[rd+1];
3408 }
3409 gen_qemu_ld64(ctx, gpr1, EA);
3410 tcg_gen_mov_tl(cpu_reserve, EA);
3411
3412 gen_addr_add(ctx, EA, EA, 8);
3413 gen_qemu_ld64(ctx, gpr2, EA);
3414
3415 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3416 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3417
3418 tcg_temp_free(EA);
3419 }
3420
3421 /* stdcx. */
3422 STCX(stdcx_, 8);
3423 STCX(stqcx_, 16);
3424 #endif /* defined(TARGET_PPC64) */
3425
3426 /* sync */
3427 static void gen_sync(DisasContext *ctx)
3428 {
3429 }
3430
3431 /* wait */
3432 static void gen_wait(DisasContext *ctx)
3433 {
3434 TCGv_i32 t0 = tcg_temp_new_i32();
3435 tcg_gen_st_i32(t0, cpu_env,
3436 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3437 tcg_temp_free_i32(t0);
3438 /* Stop translation, as the CPU is supposed to sleep from now */
3439 gen_exception_err(ctx, EXCP_HLT, 1);
3440 }
3441
3442 /*** Floating-point load ***/
3443 #define GEN_LDF(name, ldop, opc, type) \
3444 static void glue(gen_, name)(DisasContext *ctx) \
3445 { \
3446 TCGv EA; \
3447 if (unlikely(!ctx->fpu_enabled)) { \
3448 gen_exception(ctx, POWERPC_EXCP_FPU); \
3449 return; \
3450 } \
3451 gen_set_access_type(ctx, ACCESS_FLOAT); \
3452 EA = tcg_temp_new(); \
3453 gen_addr_imm_index(ctx, EA, 0); \
3454 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3455 tcg_temp_free(EA); \
3456 }
3457
3458 #define GEN_LDUF(name, ldop, opc, type) \
3459 static void glue(gen_, name##u)(DisasContext *ctx) \
3460 { \
3461 TCGv EA; \
3462 if (unlikely(!ctx->fpu_enabled)) { \
3463 gen_exception(ctx, POWERPC_EXCP_FPU); \
3464 return; \
3465 } \
3466 if (unlikely(rA(ctx->opcode) == 0)) { \
3467 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3468 return; \
3469 } \
3470 gen_set_access_type(ctx, ACCESS_FLOAT); \
3471 EA = tcg_temp_new(); \
3472 gen_addr_imm_index(ctx, EA, 0); \
3473 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3474 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3475 tcg_temp_free(EA); \
3476 }
3477
3478 #define GEN_LDUXF(name, ldop, opc, type) \
3479 static void glue(gen_, name##ux)(DisasContext *ctx) \
3480 { \
3481 TCGv EA; \
3482 if (unlikely(!ctx->fpu_enabled)) { \
3483 gen_exception(ctx, POWERPC_EXCP_FPU); \
3484 return; \
3485 } \
3486 if (unlikely(rA(ctx->opcode) == 0)) { \
3487 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3488 return; \
3489 } \
3490 gen_set_access_type(ctx, ACCESS_FLOAT); \
3491 EA = tcg_temp_new(); \
3492 gen_addr_reg_index(ctx, EA); \
3493 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3494 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3495 tcg_temp_free(EA); \
3496 }
3497
3498 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3499 static void glue(gen_, name##x)(DisasContext *ctx) \
3500 { \
3501 TCGv EA; \
3502 if (unlikely(!ctx->fpu_enabled)) { \
3503 gen_exception(ctx, POWERPC_EXCP_FPU); \
3504 return; \
3505 } \
3506 gen_set_access_type(ctx, ACCESS_FLOAT); \
3507 EA = tcg_temp_new(); \
3508 gen_addr_reg_index(ctx, EA); \
3509 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3510 tcg_temp_free(EA); \
3511 }
3512
3513 #define GEN_LDFS(name, ldop, op, type) \
3514 GEN_LDF(name, ldop, op | 0x20, type); \
3515 GEN_LDUF(name, ldop, op | 0x21, type); \
3516 GEN_LDUXF(name, ldop, op | 0x01, type); \
3517 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3518
3519 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3520 {
3521 TCGv t0 = tcg_temp_new();
3522 TCGv_i32 t1 = tcg_temp_new_i32();
3523 gen_qemu_ld32u(ctx, t0, arg2);
3524 tcg_gen_trunc_tl_i32(t1, t0);
3525 tcg_temp_free(t0);
3526 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3527 tcg_temp_free_i32(t1);
3528 }
3529
3530 /* lfd lfdu lfdux lfdx */
3531 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3532 /* lfs lfsu lfsux lfsx */
3533 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3534
3535 /* lfdp */
3536 static void gen_lfdp(DisasContext *ctx)
3537 {
3538 TCGv EA;
3539 if (unlikely(!ctx->fpu_enabled)) {
3540 gen_exception(ctx, POWERPC_EXCP_FPU);
3541 return;
3542 }
3543 gen_set_access_type(ctx, ACCESS_FLOAT);
3544 EA = tcg_temp_new();
3545 gen_addr_imm_index(ctx, EA, 0); \
3546 if (unlikely(ctx->le_mode)) {
3547 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3548 tcg_gen_addi_tl(EA, EA, 8);
3549 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3550 } else {
3551 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3552 tcg_gen_addi_tl(EA, EA, 8);
3553 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3554 }
3555 tcg_temp_free(EA);
3556 }
3557
3558 /* lfdpx */
3559 static void gen_lfdpx(DisasContext *ctx)
3560 {
3561 TCGv EA;
3562 if (unlikely(!ctx->fpu_enabled)) {
3563 gen_exception(ctx, POWERPC_EXCP_FPU);
3564 return;
3565 }
3566 gen_set_access_type(ctx, ACCESS_FLOAT);
3567 EA = tcg_temp_new();
3568 gen_addr_reg_index(ctx, EA);
3569 if (unlikely(ctx->le_mode)) {
3570 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3571 tcg_gen_addi_tl(EA, EA, 8);
3572 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3573 } else {
3574 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3575 tcg_gen_addi_tl(EA, EA, 8);
3576 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3577 }
3578 tcg_temp_free(EA);
3579 }
3580
3581 /* lfiwax */
3582 static void gen_lfiwax(DisasContext *ctx)
3583 {
3584 TCGv EA;
3585 TCGv t0;
3586 if (unlikely(!ctx->fpu_enabled)) {
3587 gen_exception(ctx, POWERPC_EXCP_FPU);
3588 return;
3589 }
3590 gen_set_access_type(ctx, ACCESS_FLOAT);
3591 EA = tcg_temp_new();
3592 t0 = tcg_temp_new();
3593 gen_addr_reg_index(ctx, EA);
3594 gen_qemu_ld32s(ctx, t0, EA);
3595 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3596 tcg_temp_free(EA);
3597 tcg_temp_free(t0);
3598 }
3599
3600 /* lfiwzx */
3601 static void gen_lfiwzx(DisasContext *ctx)
3602 {
3603 TCGv EA;
3604 if (unlikely(!ctx->fpu_enabled)) {
3605 gen_exception(ctx, POWERPC_EXCP_FPU);
3606 return;
3607 }
3608 gen_set_access_type(ctx, ACCESS_FLOAT);
3609 EA = tcg_temp_new();
3610 gen_addr_reg_index(ctx, EA);
3611 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3612 tcg_temp_free(EA);
3613 }
3614 /*** Floating-point store ***/
3615 #define GEN_STF(name, stop, opc, type) \
3616 static void glue(gen_, name)(DisasContext *ctx) \
3617 { \
3618 TCGv EA; \
3619 if (unlikely(!ctx->fpu_enabled)) { \
3620 gen_exception(ctx, POWERPC_EXCP_FPU); \
3621 return; \
3622 } \
3623 gen_set_access_type(ctx, ACCESS_FLOAT); \
3624 EA = tcg_temp_new(); \
3625 gen_addr_imm_index(ctx, EA, 0); \
3626 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3627 tcg_temp_free(EA); \
3628 }
3629
3630 #define GEN_STUF(name, stop, opc, type) \
3631 static void glue(gen_, name##u)(DisasContext *ctx) \
3632 { \
3633 TCGv EA; \
3634 if (unlikely(!ctx->fpu_enabled)) { \
3635 gen_exception(ctx, POWERPC_EXCP_FPU); \
3636 return; \
3637 } \
3638 if (unlikely(rA(ctx->opcode) == 0)) { \
3639 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3640 return; \
3641 } \
3642 gen_set_access_type(ctx, ACCESS_FLOAT); \
3643 EA = tcg_temp_new(); \
3644 gen_addr_imm_index(ctx, EA, 0); \
3645 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3646 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3647 tcg_temp_free(EA); \
3648 }
3649
3650 #define GEN_STUXF(name, stop, opc, type) \
3651 static void glue(gen_, name##ux)(DisasContext *ctx) \
3652 { \
3653 TCGv EA; \
3654 if (unlikely(!ctx->fpu_enabled)) { \
3655 gen_exception(ctx, POWERPC_EXCP_FPU); \
3656 return; \
3657 } \
3658 if (unlikely(rA(ctx->opcode) == 0)) { \
3659 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3660 return; \
3661 } \
3662 gen_set_access_type(ctx, ACCESS_FLOAT); \
3663 EA = tcg_temp_new(); \
3664 gen_addr_reg_index(ctx, EA); \
3665 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3666 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3667 tcg_temp_free(EA); \
3668 }
3669
3670 #define GEN_STXF(name, stop, opc2, opc3, type) \
3671 static void glue(gen_, name##x)(DisasContext *ctx) \
3672 { \
3673 TCGv EA; \
3674 if (unlikely(!ctx->fpu_enabled)) { \
3675 gen_exception(ctx, POWERPC_EXCP_FPU); \
3676 return; \
3677 } \
3678 gen_set_access_type(ctx, ACCESS_FLOAT); \
3679 EA = tcg_temp_new(); \
3680 gen_addr_reg_index(ctx, EA); \
3681 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3682 tcg_temp_free(EA); \
3683 }
3684
3685 #define GEN_STFS(name, stop, op, type) \
3686 GEN_STF(name, stop, op | 0x20, type); \
3687 GEN_STUF(name, stop, op | 0x21, type); \
3688 GEN_STUXF(name, stop, op | 0x01, type); \
3689 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3690
3691 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3692 {
3693 TCGv_i32 t0 = tcg_temp_new_i32();
3694 TCGv t1 = tcg_temp_new();
3695 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3696 tcg_gen_extu_i32_tl(t1, t0);
3697 tcg_temp_free_i32(t0);
3698 gen_qemu_st32(ctx, t1, arg2);
3699 tcg_temp_free(t1);
3700 }
3701
3702 /* stfd stfdu stfdux stfdx */
3703 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3704 /* stfs stfsu stfsux stfsx */
3705 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3706
3707 /* stfdp */
3708 static void gen_stfdp(DisasContext *ctx)
3709 {
3710 TCGv EA;
3711 if (unlikely(!ctx->fpu_enabled)) {
3712 gen_exception(ctx, POWERPC_EXCP_FPU);
3713 return;
3714 }
3715 gen_set_access_type(ctx, ACCESS_FLOAT);
3716 EA = tcg_temp_new();
3717 gen_addr_imm_index(ctx, EA, 0); \
3718 if (unlikely(ctx->le_mode)) {
3719 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3720 tcg_gen_addi_tl(EA, EA, 8);
3721 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3722 } else {
3723 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3724 tcg_gen_addi_tl(EA, EA, 8);
3725 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3726 }
3727 tcg_temp_free(EA);
3728 }
3729
3730 /* stfdpx */
3731 static void gen_stfdpx(DisasContext *ctx)
3732 {
3733 TCGv EA;
3734 if (unlikely(!ctx->fpu_enabled)) {
3735 gen_exception(ctx, POWERPC_EXCP_FPU);
3736 return;
3737 }
3738 gen_set_access_type(ctx, ACCESS_FLOAT);
3739 EA = tcg_temp_new();
3740 gen_addr_reg_index(ctx, EA);
3741 if (unlikely(ctx->le_mode)) {
3742 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3743 tcg_gen_addi_tl(EA, EA, 8);
3744 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3745 } else {
3746 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3747 tcg_gen_addi_tl(EA, EA, 8);
3748 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3749 }
3750 tcg_temp_free(EA);
3751 }
3752
3753 /* Optional: */
3754 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3755 {
3756 TCGv t0 = tcg_temp_new();
3757 tcg_gen_trunc_i64_tl(t0, arg1),
3758 gen_qemu_st32(ctx, t0, arg2);
3759 tcg_temp_free(t0);
3760 }
3761 /* stfiwx */
3762 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3763
3764 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3765 {
3766 #if defined(TARGET_PPC64)
3767 if (ctx->has_cfar)
3768 tcg_gen_movi_tl(cpu_cfar, nip);
3769 #endif
3770 }
3771
3772 /*** Branch ***/
3773 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3774 {
3775 TranslationBlock *tb;
3776 tb = ctx->tb;
3777 if (NARROW_MODE(ctx)) {
3778 dest = (uint32_t) dest;
3779 }
3780 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3781 likely(!ctx->singlestep_enabled)) {
3782 tcg_gen_goto_tb(n);
3783 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3784 tcg_gen_exit_tb((uintptr_t)tb + n);
3785 } else {
3786 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3787 if (unlikely(ctx->singlestep_enabled)) {
3788 if ((ctx->singlestep_enabled &
3789 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3790 (ctx->exception == POWERPC_EXCP_BRANCH ||
3791 ctx->exception == POWERPC_EXCP_TRACE)) {
3792 target_ulong tmp = ctx->nip;
3793 ctx->nip = dest;
3794 gen_exception(ctx, POWERPC_EXCP_TRACE);
3795 ctx->nip = tmp;
3796 }
3797 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3798 gen_debug_exception(ctx);
3799 }
3800 }
3801 tcg_gen_exit_tb(0);
3802 }
3803 }
3804
3805 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3806 {
3807 if (NARROW_MODE(ctx)) {
3808 nip = (uint32_t)nip;
3809 }
3810 tcg_gen_movi_tl(cpu_lr, nip);
3811 }
3812
3813 /* b ba bl bla */
3814 static void gen_b(DisasContext *ctx)
3815 {
3816 target_ulong li, target;
3817
3818 ctx->exception = POWERPC_EXCP_BRANCH;
3819 /* sign extend LI */
3820 li = LI(ctx->opcode);
3821 li = (li ^ 0x02000000) - 0x02000000;
3822 if (likely(AA(ctx->opcode) == 0)) {
3823 target = ctx->nip + li - 4;
3824 } else {
3825 target = li;
3826 }
3827 if (LK(ctx->opcode)) {
3828 gen_setlr(ctx, ctx->nip);
3829 }
3830 gen_update_cfar(ctx, ctx->nip);
3831 gen_goto_tb(ctx, 0, target);
3832 }
3833
3834 #define BCOND_IM 0
3835 #define BCOND_LR 1
3836 #define BCOND_CTR 2
3837 #define BCOND_TAR 3
3838
3839 static inline void gen_bcond(DisasContext *ctx, int type)
3840 {
3841 uint32_t bo = BO(ctx->opcode);
3842 int l1;
3843 TCGv target;
3844
3845 ctx->exception = POWERPC_EXCP_BRANCH;
3846 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3847 target = tcg_temp_local_new();
3848 if (type == BCOND_CTR)
3849 tcg_gen_mov_tl(target, cpu_ctr);
3850 else if (type == BCOND_TAR)
3851 gen_load_spr(target, SPR_TAR);
3852 else
3853 tcg_gen_mov_tl(target, cpu_lr);
3854 } else {
3855 TCGV_UNUSED(target);
3856 }
3857 if (LK(ctx->opcode))
3858 gen_setlr(ctx, ctx->nip);
3859 l1 = gen_new_label();
3860 if ((bo & 0x4) == 0) {
3861 /* Decrement and test CTR */
3862 TCGv temp = tcg_temp_new();
3863 if (unlikely(type == BCOND_CTR)) {
3864 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3865 return;
3866 }
3867 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3868 if (NARROW_MODE(ctx)) {
3869 tcg_gen_ext32u_tl(temp, cpu_ctr);
3870 } else {
3871 tcg_gen_mov_tl(temp, cpu_ctr);
3872 }
3873 if (bo & 0x2) {
3874 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3875 } else {
3876 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3877 }
3878 tcg_temp_free(temp);
3879 }
3880 if ((bo & 0x10) == 0) {
3881 /* Test CR */
3882 uint32_t bi = BI(ctx->opcode);
3883 uint32_t mask = 1 << (3 - (bi & 0x03));
3884 TCGv_i32 temp = tcg_temp_new_i32();
3885
3886 if (bo & 0x8) {
3887 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3888 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3889 } else {
3890 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3891 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3892 }
3893 tcg_temp_free_i32(temp);
3894 }
3895 gen_update_cfar(ctx, ctx->nip);
3896 if (type == BCOND_IM) {
3897 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3898 if (likely(AA(ctx->opcode) == 0)) {
3899 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3900 } else {
3901 gen_goto_tb(ctx, 0, li);
3902 }
3903 gen_set_label(l1);
3904 gen_goto_tb(ctx, 1, ctx->nip);
3905 } else {
3906 if (NARROW_MODE(ctx)) {
3907 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3908 } else {
3909 tcg_gen_andi_tl(cpu_nip, target, ~3);
3910 }
3911 tcg_gen_exit_tb(0);
3912 gen_set_label(l1);
3913 gen_update_nip(ctx, ctx->nip);
3914 tcg_gen_exit_tb(0);
3915 }
3916 }
3917
3918 static void gen_bc(DisasContext *ctx)
3919 {
3920 gen_bcond(ctx, BCOND_IM);
3921 }
3922
3923 static void gen_bcctr(DisasContext *ctx)
3924 {
3925 gen_bcond(ctx, BCOND_CTR);
3926 }
3927
3928 static void gen_bclr(DisasContext *ctx)
3929 {
3930 gen_bcond(ctx, BCOND_LR);
3931 }
3932
3933 static void gen_bctar(DisasContext *ctx)
3934 {
3935 gen_bcond(ctx, BCOND_TAR);
3936 }
3937
3938 /*** Condition register logical ***/
3939 #define GEN_CRLOGIC(name, tcg_op, opc) \
3940 static void glue(gen_, name)(DisasContext *ctx) \
3941 { \
3942 uint8_t bitmask; \
3943 int sh; \
3944 TCGv_i32 t0, t1; \
3945 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3946 t0 = tcg_temp_new_i32(); \
3947 if (sh > 0) \
3948 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3949 else if (sh < 0) \
3950 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3951 else \
3952 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3953 t1 = tcg_temp_new_i32(); \
3954 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3955 if (sh > 0) \
3956 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3957 else if (sh < 0) \
3958 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3959 else \
3960 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3961 tcg_op(t0, t0, t1); \
3962 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3963 tcg_gen_andi_i32(t0, t0, bitmask); \
3964 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3965 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3966 tcg_temp_free_i32(t0); \
3967 tcg_temp_free_i32(t1); \
3968 }
3969
3970 /* crand */
3971 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3972 /* crandc */
3973 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3974 /* creqv */
3975 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3976 /* crnand */
3977 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3978 /* crnor */
3979 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3980 /* cror */
3981 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3982 /* crorc */
3983 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3984 /* crxor */
3985 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3986
3987 /* mcrf */
3988 static void gen_mcrf(DisasContext *ctx)
3989 {
3990 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3991 }
3992
3993 /*** System linkage ***/
3994
3995 /* rfi (mem_idx only) */
3996 static void gen_rfi(DisasContext *ctx)
3997 {
3998 #if defined(CONFIG_USER_ONLY)
3999 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4000 #else
4001 /* Restore CPU state */
4002 if (unlikely(!ctx->mem_idx)) {
4003 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4004 return;
4005 }
4006 gen_update_cfar(ctx, ctx->nip);
4007 gen_helper_rfi(cpu_env);
4008 gen_sync_exception(ctx);
4009 #endif
4010 }
4011
4012 #if defined(TARGET_PPC64)
4013 static void gen_rfid(DisasContext *ctx)
4014 {
4015 #if defined(CONFIG_USER_ONLY)
4016 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4017 #else
4018 /* Restore CPU state */
4019 if (unlikely(!ctx->mem_idx)) {
4020 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4021 return;
4022 }
4023 gen_update_cfar(ctx, ctx->nip);
4024 gen_helper_rfid(cpu_env);
4025 gen_sync_exception(ctx);
4026 #endif
4027 }
4028
4029 static void gen_hrfid(DisasContext *ctx)
4030 {
4031 #if defined(CONFIG_USER_ONLY)
4032 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4033 #else
4034 /* Restore CPU state */
4035 if (unlikely(ctx->mem_idx <= 1)) {
4036 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4037 return;
4038 }
4039 gen_helper_hrfid(cpu_env);
4040 gen_sync_exception(ctx);
4041 #endif
4042 }
4043 #endif
4044
4045 /* sc */
4046 #if defined(CONFIG_USER_ONLY)
4047 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4048 #else
4049 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4050 #endif
4051 static void gen_sc(DisasContext *ctx)
4052 {
4053 uint32_t lev;
4054
4055 lev = (ctx->opcode >> 5) & 0x7F;
4056 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4057 }
4058
4059 /*** Trap ***/
4060
4061 /* tw */
4062 static void gen_tw(DisasContext *ctx)
4063 {
4064 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4065 /* Update the nip since this might generate a trap exception */
4066 gen_update_nip(ctx, ctx->nip);
4067 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4068 t0);
4069 tcg_temp_free_i32(t0);
4070 }
4071
4072 /* twi */
4073 static void gen_twi(DisasContext *ctx)
4074 {
4075 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4076 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4077 /* Update the nip since this might generate a trap exception */
4078 gen_update_nip(ctx, ctx->nip);
4079 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4080 tcg_temp_free(t0);
4081 tcg_temp_free_i32(t1);
4082 }
4083
4084 #if defined(TARGET_PPC64)
4085 /* td */
4086 static void gen_td(DisasContext *ctx)
4087 {
4088 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4089 /* Update the nip since this might generate a trap exception */
4090 gen_update_nip(ctx, ctx->nip);
4091 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4092 t0);
4093 tcg_temp_free_i32(t0);
4094 }
4095
4096 /* tdi */
4097 static void gen_tdi(DisasContext *ctx)
4098 {
4099 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4100 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4101 /* Update the nip since this might generate a trap exception */
4102 gen_update_nip(ctx, ctx->nip);
4103 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4104 tcg_temp_free(t0);
4105 tcg_temp_free_i32(t1);
4106 }
4107 #endif
4108
4109 /*** Processor control ***/
4110
4111 static void gen_read_xer(TCGv dst)
4112 {
4113 TCGv t0 = tcg_temp_new();
4114 TCGv t1 = tcg_temp_new();
4115 TCGv t2 = tcg_temp_new();
4116 tcg_gen_mov_tl(dst, cpu_xer);
4117 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4118 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4119 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4120 tcg_gen_or_tl(t0, t0, t1);
4121 tcg_gen_or_tl(dst, dst, t2);
4122 tcg_gen_or_tl(dst, dst, t0);
4123 tcg_temp_free(t0);
4124 tcg_temp_free(t1);
4125 tcg_temp_free(t2);
4126 }
4127
4128 static void gen_write_xer(TCGv src)
4129 {
4130 tcg_gen_andi_tl(cpu_xer, src,
4131 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4132 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4133 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4134 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4135 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4136 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4137 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4138 }
4139
4140 /* mcrxr */
4141 static void gen_mcrxr(DisasContext *ctx)
4142 {
4143 TCGv_i32 t0 = tcg_temp_new_i32();
4144 TCGv_i32 t1 = tcg_temp_new_i32();
4145 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4146
4147 tcg_gen_trunc_tl_i32(t0, cpu_so);
4148 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4149 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4150 tcg_gen_shri_i32(t0, t0, 2);
4151 tcg_gen_shri_i32(t1, t1, 1);
4152 tcg_gen_or_i32(dst, dst, t0);
4153 tcg_gen_or_i32(dst, dst, t1);
4154 tcg_temp_free_i32(t0);
4155 tcg_temp_free_i32(t1);
4156
4157 tcg_gen_movi_tl(cpu_so, 0);
4158 tcg_gen_movi_tl(cpu_ov, 0);
4159 tcg_gen_movi_tl(cpu_ca, 0);
4160 }
4161
4162 /* mfcr mfocrf */
4163 static void gen_mfcr(DisasContext *ctx)
4164 {
4165 uint32_t crm, crn;
4166
4167 if (likely(ctx->opcode & 0x00100000)) {
4168 crm = CRM(ctx->opcode);
4169 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4170 crn = ctz32 (crm);
4171 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4172 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4173 cpu_gpr[rD(ctx->opcode)], crn * 4);
4174 }
4175 } else {
4176 TCGv_i32 t0 = tcg_temp_new_i32();
4177 tcg_gen_mov_i32(t0, cpu_crf[0]);
4178 tcg_gen_shli_i32(t0, t0, 4);
4179 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4180 tcg_gen_shli_i32(t0, t0, 4);
4181 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4182 tcg_gen_shli_i32(t0, t0, 4);
4183 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4184 tcg_gen_shli_i32(t0, t0, 4);
4185 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4186 tcg_gen_shli_i32(t0, t0, 4);
4187 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4188 tcg_gen_shli_i32(t0, t0, 4);
4189 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4190 tcg_gen_shli_i32(t0, t0, 4);
4191 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4192 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4193 tcg_temp_free_i32(t0);
4194 }
4195 }
4196
4197 /* mfmsr */
4198 static void gen_mfmsr(DisasContext *ctx)
4199 {
4200 #if defined(CONFIG_USER_ONLY)
4201 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4202 #else
4203 if (unlikely(!ctx->mem_idx)) {
4204 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4205 return;
4206 }
4207 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4208 #endif
4209 }
4210
4211 static void spr_noaccess(void *opaque, int gprn, int sprn)
4212 {
4213 #if 0
4214 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4215 printf("ERROR: try to access SPR %d !\n", sprn);
4216 #endif
4217 }
4218 #define SPR_NOACCESS (&spr_noaccess)
4219
4220 /* mfspr */
4221 static inline void gen_op_mfspr(DisasContext *ctx)
4222 {
4223 void (*read_cb)(void *opaque, int gprn, int sprn);
4224 uint32_t sprn = SPR(ctx->opcode);
4225
4226 #if !defined(CONFIG_USER_ONLY)
4227 if (ctx->mem_idx == 2)
4228 read_cb = ctx->spr_cb[sprn].hea_read;
4229 else if (ctx->mem_idx)
4230 read_cb = ctx->spr_cb[sprn].oea_read;
4231 else
4232 #endif
4233 read_cb = ctx->spr_cb[sprn].uea_read;
4234 if (likely(read_cb != NULL)) {
4235 if (likely(read_cb != SPR_NOACCESS)) {
4236 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4237 } else {
4238 /* Privilege exception */
4239 /* This is a hack to avoid warnings when running Linux:
4240 * this OS breaks the PowerPC virtualisation model,
4241 * allowing userland application to read the PVR
4242 */
4243 if (sprn != SPR_PVR) {
4244 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4245 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4246 printf("Trying to read privileged spr %d (0x%03x) at "
4247 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4248 }
4249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4250 }
4251 } else {
4252 /* Not defined */
4253 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4254 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4255 printf("Trying to read invalid spr %d (0x%03x) at "
4256 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4257 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4258 }
4259 }
4260
4261 static void gen_mfspr(DisasContext *ctx)
4262 {
4263 gen_op_mfspr(ctx);
4264 }
4265
4266 /* mftb */
4267 static void gen_mftb(DisasContext *ctx)
4268 {
4269 gen_op_mfspr(ctx);
4270 }
4271
4272 /* mtcrf mtocrf*/
4273 static void gen_mtcrf(DisasContext *ctx)
4274 {
4275 uint32_t crm, crn;
4276
4277 crm = CRM(ctx->opcode);
4278 if (likely((ctx->opcode & 0x00100000))) {
4279 if (crm && ((crm & (crm - 1)) == 0)) {
4280 TCGv_i32 temp = tcg_temp_new_i32();
4281 crn = ctz32 (crm);
4282 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4283 tcg_gen_shri_i32(temp, temp, crn * 4);
4284 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4285 tcg_temp_free_i32(temp);
4286 }
4287 } else {
4288 TCGv_i32 temp = tcg_temp_new_i32();
4289 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4290 for (crn = 0 ; crn < 8 ; crn++) {
4291 if (crm & (1 << crn)) {
4292 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4293 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4294 }
4295 }
4296 tcg_temp_free_i32(temp);
4297 }
4298 }
4299
4300 /* mtmsr */
4301 #if defined(TARGET_PPC64)
4302 static void gen_mtmsrd(DisasContext *ctx)
4303 {
4304 #if defined(CONFIG_USER_ONLY)
4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4306 #else
4307 if (unlikely(!ctx->mem_idx)) {
4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4309 return;
4310 }
4311 if (ctx->opcode & 0x00010000) {
4312 /* Special form that does not need any synchronisation */
4313 TCGv t0 = tcg_temp_new();
4314 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4315 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4316 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4317 tcg_temp_free(t0);
4318 } else {
4319 /* XXX: we need to update nip before the store
4320 * if we enter power saving mode, we will exit the loop
4321 * directly from ppc_store_msr
4322 */
4323 gen_update_nip(ctx, ctx->nip);
4324 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4325 /* Must stop the translation as machine state (may have) changed */
4326 /* Note that mtmsr is not always defined as context-synchronizing */
4327 gen_stop_exception(ctx);
4328 }
4329 #endif
4330 }
4331 #endif
4332
4333 static void gen_mtmsr(DisasContext *ctx)
4334 {
4335 #if defined(CONFIG_USER_ONLY)
4336 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4337 #else
4338 if (unlikely(!ctx->mem_idx)) {
4339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4340 return;
4341 }
4342 if (ctx->opcode & 0x00010000) {
4343 /* Special form that does not need any synchronisation */
4344 TCGv t0 = tcg_temp_new();
4345 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4346 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4347 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4348 tcg_temp_free(t0);
4349 } else {
4350 TCGv msr = tcg_temp_new();
4351
4352 /* XXX: we need to update nip before the store
4353 * if we enter power saving mode, we will exit the loop
4354 * directly from ppc_store_msr
4355 */
4356 gen_update_nip(ctx, ctx->nip);
4357 #if defined(TARGET_PPC64)
4358 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4359 #else
4360 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4361 #endif
4362 gen_helper_store_msr(cpu_env, msr);
4363 /* Must stop the translation as machine state (may have) changed */
4364 /* Note that mtmsr is not always defined as context-synchronizing */
4365 gen_stop_exception(ctx);
4366 }
4367 #endif
4368 }
4369
4370 /* mtspr */
4371 static void gen_mtspr(DisasContext *ctx)
4372 {
4373 void (*write_cb)(void *opaque, int sprn, int gprn);
4374 uint32_t sprn = SPR(ctx->opcode);
4375
4376 #if !defined(CONFIG_USER_ONLY)
4377 if (ctx->mem_idx == 2)
4378 write_cb = ctx->spr_cb[sprn].hea_write;
4379 else if (ctx->mem_idx)
4380 write_cb = ctx->spr_cb[sprn].oea_write;
4381 else
4382 #endif
4383 write_cb = ctx->spr_cb[sprn].uea_write;
4384 if (likely(write_cb != NULL)) {
4385 if (likely(write_cb != SPR_NOACCESS)) {
4386 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4387 } else {
4388 /* Privilege exception */
4389 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4390 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4391 printf("Trying to write privileged spr %d (0x%03x) at "
4392 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4394 }
4395 } else {
4396 /* Not defined */
4397 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4398 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4399 printf("Trying to write invalid spr %d (0x%03x) at "
4400 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4401 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4402 }
4403 }
4404
4405 /*** Cache management ***/
4406
4407 /* dcbf */
4408 static void gen_dcbf(DisasContext *ctx)
4409 {
4410 /* XXX: specification says this is treated as a load by the MMU */
4411 TCGv t0;
4412 gen_set_access_type(ctx, ACCESS_CACHE);
4413 t0 = tcg_temp_new();
4414 gen_addr_reg_index(ctx, t0);
4415 gen_qemu_ld8u(ctx, t0, t0);
4416 tcg_temp_free(t0);
4417 }
4418
4419 /* dcbi (Supervisor only) */
4420 static void gen_dcbi(DisasContext *ctx)
4421 {
4422 #if defined(CONFIG_USER_ONLY)
4423 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4424 #else
4425 TCGv EA, val;
4426 if (unlikely(!ctx->mem_idx)) {
4427 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4428 return;
4429 }
4430 EA = tcg_temp_new();
4431 gen_set_access_type(ctx, ACCESS_CACHE);
4432 gen_addr_reg_index(ctx, EA);
4433 val = tcg_temp_new();
4434 /* XXX: specification says this should be treated as a store by the MMU */
4435 gen_qemu_ld8u(ctx, val, EA);
4436 gen_qemu_st8(ctx, val, EA);
4437 tcg_temp_free(val);
4438 tcg_temp_free(EA);
4439 #endif
4440 }
4441
4442 /* dcdst */
4443 static void gen_dcbst(DisasContext *ctx)
4444 {
4445 /* XXX: specification say this is treated as a load by the MMU */
4446 TCGv t0;
4447 gen_set_access_type(ctx, ACCESS_CACHE);
4448 t0 = tcg_temp_new();
4449 gen_addr_reg_index(ctx, t0);
4450 gen_qemu_ld8u(ctx, t0, t0);
4451 tcg_temp_free(t0);
4452 }
4453
4454 /* dcbt */
4455 static void gen_dcbt(DisasContext *ctx)
4456 {
4457 /* interpreted as no-op */
4458 /* XXX: specification say this is treated as a load by the MMU
4459 * but does not generate any exception
4460 */
4461 }
4462
4463 /* dcbtst */
4464 static void gen_dcbtst(DisasContext *ctx)
4465 {
4466 /* interpreted as no-op */
4467 /* XXX: specification say this is treated as a load by the MMU
4468 * but does not generate any exception
4469 */
4470 }
4471
4472 /* dcbz */
4473 static void gen_dcbz(DisasContext *ctx)
4474 {
4475 TCGv tcgv_addr;
4476 TCGv_i32 tcgv_is_dcbzl;
4477 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4478
4479 gen_set_access_type(ctx, ACCESS_CACHE);
4480 /* NIP cannot be restored if the memory exception comes from an helper */
4481 gen_update_nip(ctx, ctx->nip - 4);
4482 tcgv_addr = tcg_temp_new();
4483 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4484
4485 gen_addr_reg_index(ctx, tcgv_addr);
4486 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4487
4488 tcg_temp_free(tcgv_addr);
4489 tcg_temp_free_i32(tcgv_is_dcbzl);
4490 }
4491
4492 /* dst / dstt */
4493 static void gen_dst(DisasContext *ctx)
4494 {
4495 if (rA(ctx->opcode) == 0) {
4496 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4497 } else {
4498 /* interpreted as no-op */
4499 }
4500 }
4501
4502 /* dstst /dststt */
4503 static void gen_dstst(DisasContext *ctx)
4504 {
4505 if (rA(ctx->opcode) == 0) {
4506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4507 } else {
4508 /* interpreted as no-op */
4509 }
4510
4511 }
4512
4513 /* dss / dssall */
4514 static void gen_dss(DisasContext *ctx)
4515 {
4516 /* interpreted as no-op */
4517 }
4518
4519 /* icbi */
4520 static void gen_icbi(DisasContext *ctx)
4521 {
4522 TCGv t0;
4523 gen_set_access_type(ctx, ACCESS_CACHE);
4524 /* NIP cannot be restored if the memory exception comes from an helper */
4525 gen_update_nip(ctx, ctx->nip - 4);
4526 t0 = tcg_temp_new();
4527 gen_addr_reg_index(ctx, t0);
4528 gen_helper_icbi(cpu_env, t0);
4529 tcg_temp_free(t0);
4530 }
4531
4532 /* Optional: */
4533 /* dcba */
4534 static void gen_dcba(DisasContext *ctx)
4535 {
4536 /* interpreted as no-op */
4537 /* XXX: specification say this is treated as a store by the MMU
4538 * but does not generate any exception
4539 */
4540 }
4541
4542 /*** Segment register manipulation ***/
4543 /* Supervisor only: */
4544
4545 /* mfsr */
4546 static void gen_mfsr(DisasContext *ctx)
4547 {
4548 #if defined(CONFIG_USER_ONLY)
4549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4550 #else
4551 TCGv t0;
4552 if (unlikely(!ctx->mem_idx)) {
4553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4554 return;
4555 }
4556 t0 = tcg_const_tl(SR(ctx->opcode));
4557 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4558 tcg_temp_free(t0);
4559 #endif
4560 }
4561
4562 /* mfsrin */
4563 static void gen_mfsrin(DisasContext *ctx)
4564 {
4565 #if defined(CONFIG_USER_ONLY)
4566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4567 #else
4568 TCGv t0;
4569 if (unlikely(!ctx->mem_idx)) {
4570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4571 return;
4572 }
4573 t0 = tcg_temp_new();
4574 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4575 tcg_gen_andi_tl(t0, t0, 0xF);
4576 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4577 tcg_temp_free(t0);
4578 #endif
4579 }
4580
4581 /* mtsr */
4582 static void gen_mtsr(DisasContext *ctx)
4583 {
4584 #if defined(CONFIG_USER_ONLY)
4585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4586 #else
4587 TCGv t0;
4588 if (unlikely(!ctx->mem_idx)) {
4589 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4590 return;
4591 }
4592 t0 = tcg_const_tl(SR(ctx->opcode));
4593 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4594 tcg_temp_free(t0);
4595 #endif
4596 }
4597
4598 /* mtsrin */
4599 static void gen_mtsrin(DisasContext *ctx)
4600 {
4601 #if defined(CONFIG_USER_ONLY)
4602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4603 #else
4604 TCGv t0;
4605 if (unlikely(!ctx->mem_idx)) {
4606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4607 return;
4608 }
4609 t0 = tcg_temp_new();
4610 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4611 tcg_gen_andi_tl(t0, t0, 0xF);
4612 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4613 tcg_temp_free(t0);
4614 #endif
4615 }
4616
4617 #if defined(TARGET_PPC64)
4618 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4619
4620 /* mfsr */
4621 static void gen_mfsr_64b(DisasContext *ctx)
4622 {
4623 #if defined(CONFIG_USER_ONLY)
4624 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4625 #else
4626 TCGv t0;
4627 if (unlikely(!ctx->mem_idx)) {
4628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4629 return;
4630 }
4631 t0 = tcg_const_tl(SR(ctx->opcode));
4632 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4633 tcg_temp_free(t0);
4634 #endif
4635 }
4636
4637 /* mfsrin */
4638 static void gen_mfsrin_64b(DisasContext *ctx)
4639 {
4640 #if defined(CONFIG_USER_ONLY)
4641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4642 #else
4643 TCGv t0;
4644 if (unlikely(!ctx->mem_idx)) {
4645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4646 return;
4647 }
4648 t0 = tcg_temp_new();
4649 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4650 tcg_gen_andi_tl(t0, t0, 0xF);
4651 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4652 tcg_temp_free(t0);
4653 #endif
4654 }
4655
4656 /* mtsr */
4657 static void gen_mtsr_64b(DisasContext *ctx)
4658 {
4659 #if defined(CONFIG_USER_ONLY)
4660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4661 #else
4662 TCGv t0;
4663 if (unlikely(!ctx->mem_idx)) {
4664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4665 return;
4666 }
4667 t0 = tcg_const_tl(SR(ctx->opcode));
4668 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4669 tcg_temp_free(t0);
4670 #endif
4671 }
4672
4673 /* mtsrin */
4674 static void gen_mtsrin_64b(DisasContext *ctx)
4675 {
4676 #if defined(CONFIG_USER_ONLY)
4677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4678 #else
4679 TCGv t0;
4680 if (unlikely(!ctx->mem_idx)) {
4681 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4682 return;
4683 }
4684 t0 = tcg_temp_new();
4685 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4686 tcg_gen_andi_tl(t0, t0, 0xF);
4687 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4688 tcg_temp_free(t0);
4689 #endif
4690 }
4691
4692 /* slbmte */
4693 static void gen_slbmte(DisasContext *ctx)
4694 {
4695 #if defined(CONFIG_USER_ONLY)
4696 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4697 #else
4698 if (unlikely(!ctx->mem_idx)) {
4699 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4700 return;
4701 }
4702 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4703 cpu_gpr[rS(ctx->opcode)]);
4704 #endif
4705 }
4706
4707 static void gen_slbmfee(DisasContext *ctx)
4708 {
4709 #if defined(CONFIG_USER_ONLY)
4710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4711 #else
4712 if (unlikely(!ctx->mem_idx)) {
4713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4714 return;
4715 }
4716 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4717 cpu_gpr[rB(ctx->opcode)]);
4718 #endif
4719 }
4720
4721 static void gen_slbmfev(DisasContext *ctx)
4722 {
4723 #if defined(CONFIG_USER_ONLY)
4724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4725 #else
4726 if (unlikely(!ctx->mem_idx)) {
4727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4728 return;
4729 }
4730 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4731 cpu_gpr[rB(ctx->opcode)]);
4732 #endif
4733 }
4734 #endif /* defined(TARGET_PPC64) */
4735
4736 /*** Lookaside buffer management ***/
4737 /* Optional & mem_idx only: */
4738
4739 /* tlbia */
4740 static void gen_tlbia(DisasContext *ctx)
4741 {
4742 #if defined(CONFIG_USER_ONLY)
4743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4744 #else
4745 if (unlikely(!ctx->mem_idx)) {
4746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4747 return;
4748 }
4749 gen_helper_tlbia(cpu_env);
4750 #endif
4751 }
4752
4753 /* tlbiel */
4754 static void gen_tlbiel(DisasContext *ctx)
4755 {
4756 #if defined(CONFIG_USER_ONLY)
4757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4758 #else
4759 if (unlikely(!ctx->mem_idx)) {
4760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4761 return;
4762 }
4763 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4764 #endif
4765 }
4766
4767 /* tlbie */
4768 static void gen_tlbie(DisasContext *ctx)
4769 {
4770 #if defined(CONFIG_USER_ONLY)
4771 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4772 #else
4773 if (unlikely(!ctx->mem_idx)) {
4774 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4775 return;
4776 }
4777 if (NARROW_MODE(ctx)) {
4778 TCGv t0 = tcg_temp_new();
4779 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4780 gen_helper_tlbie(cpu_env, t0);
4781 tcg_temp_free(t0);
4782 } else {
4783 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4784 }
4785 #endif
4786 }
4787
4788 /* tlbsync */
4789 static void gen_tlbsync(DisasContext *ctx)
4790 {
4791 #if defined(CONFIG_USER_ONLY)
4792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4793 #else
4794 if (unlikely(!ctx->mem_idx)) {
4795 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4796 return;
4797 }
4798 /* This has no effect: it should ensure that all previous
4799 * tlbie have completed
4800 */
4801 gen_stop_exception(ctx);
4802 #endif
4803 }
4804
4805 #if defined(TARGET_PPC64)
4806 /* slbia */
4807 static void gen_slbia(DisasContext *ctx)
4808 {
4809 #if defined(CONFIG_USER_ONLY)
4810 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4811 #else
4812 if (unlikely(!ctx->mem_idx)) {
4813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4814 return;
4815 }
4816 gen_helper_slbia(cpu_env);
4817 #endif
4818 }
4819
4820 /* slbie */
4821 static void gen_slbie(DisasContext *ctx)
4822 {
4823 #if defined(CONFIG_USER_ONLY)
4824 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4825 #else
4826 if (unlikely(!ctx->mem_idx)) {
4827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4828 return;
4829 }
4830 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4831 #endif
4832 }
4833 #endif
4834
4835 /*** External control ***/
4836 /* Optional: */
4837
4838 /* eciwx */
4839 static void gen_eciwx(DisasContext *ctx)
4840 {
4841 TCGv t0;
4842 /* Should check EAR[E] ! */
4843 gen_set_access_type(ctx, ACCESS_EXT);
4844 t0 = tcg_temp_new();
4845 gen_addr_reg_index(ctx, t0);
4846 gen_check_align(ctx, t0, 0x03);
4847 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4848 tcg_temp_free(t0);
4849 }
4850
4851 /* ecowx */
4852 static void gen_ecowx(DisasContext *ctx)
4853 {
4854 TCGv t0;
4855 /* Should check EAR[E] ! */
4856 gen_set_access_type(ctx, ACCESS_EXT);
4857 t0 = tcg_temp_new();
4858 gen_addr_reg_index(ctx, t0);
4859 gen_check_align(ctx, t0, 0x03);
4860 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4861 tcg_temp_free(t0);
4862 }
4863
4864 /* PowerPC 601 specific instructions */
4865
4866 /* abs - abs. */
4867 static void gen_abs(DisasContext *ctx)
4868 {
4869 int l1 = gen_new_label();
4870 int l2 = gen_new_label();
4871 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4872 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4873 tcg_gen_br(l2);
4874 gen_set_label(l1);
4875 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4876 gen_set_label(l2);
4877 if (unlikely(Rc(ctx->opcode) != 0))
4878 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4879 }
4880
4881 /* abso - abso. */
4882 static void gen_abso(DisasContext *ctx)
4883 {
4884 int l1 = gen_new_label();
4885 int l2 = gen_new_label();
4886 int l3 = gen_new_label();
4887 /* Start with XER OV disabled, the most likely case */
4888 tcg_gen_movi_tl(cpu_ov, 0);
4889 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4890 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4891 tcg_gen_movi_tl(cpu_ov, 1);
4892 tcg_gen_movi_tl(cpu_so, 1);
4893 tcg_gen_br(l2);
4894 gen_set_label(l1);
4895 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4896 tcg_gen_br(l3);
4897 gen_set_label(l2);
4898 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4899 gen_set_label(l3);
4900 if (unlikely(Rc(ctx->opcode) != 0))
4901 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4902 }
4903
4904 /* clcs */
4905 static void gen_clcs(DisasContext *ctx)
4906 {
4907 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4908 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4909 tcg_temp_free_i32(t0);
4910 /* Rc=1 sets CR0 to an undefined state */
4911 }
4912
4913 /* div - div. */
4914 static void gen_div(DisasContext *ctx)
4915 {
4916 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4917 cpu_gpr[rB(ctx->opcode)]);
4918 if (unlikely(Rc(ctx->opcode) != 0))
4919 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4920 }
4921
4922 /* divo - divo. */
4923 static void gen_divo(DisasContext *ctx)
4924 {
4925 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4926 cpu_gpr[rB(ctx->opcode)]);
4927 if (unlikely(Rc(ctx->opcode) != 0))
4928 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4929 }
4930
4931 /* divs - divs. */
4932 static void gen_divs(DisasContext *ctx)
4933 {
4934 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4935 cpu_gpr[rB(ctx->opcode)]);
4936 if (unlikely(Rc(ctx->opcode) != 0))
4937 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4938 }
4939
4940 /* divso - divso. */
4941 static void gen_divso(DisasContext *ctx)
4942 {
4943 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4944 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4945 if (unlikely(Rc(ctx->opcode) != 0))
4946 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4947 }
4948
4949 /* doz - doz. */
4950 static void gen_doz(DisasContext *ctx)
4951 {
4952 int l1 = gen_new_label();
4953 int l2 = gen_new_label();
4954 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4955 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4956 tcg_gen_br(l2);
4957 gen_set_label(l1);
4958 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4959 gen_set_label(l2);
4960 if (unlikely(Rc(ctx->opcode) != 0))
4961 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4962 }
4963
4964 /* dozo - dozo. */
4965 static void gen_dozo(DisasContext *ctx)
4966 {
4967 int l1 = gen_new_label();
4968 int l2 = gen_new_label();
4969 TCGv t0 = tcg_temp_new();
4970 TCGv t1 = tcg_temp_new();
4971 TCGv t2 = tcg_temp_new();
4972 /* Start with XER OV disabled, the most likely case */
4973 tcg_gen_movi_tl(cpu_ov, 0);
4974 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4975 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4976 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4977 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4978 tcg_gen_andc_tl(t1, t1, t2);
4979 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4980 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4981 tcg_gen_movi_tl(cpu_ov, 1);
4982 tcg_gen_movi_tl(cpu_so, 1);
4983 tcg_gen_br(l2);
4984 gen_set_label(l1);
4985 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4986 gen_set_label(l2);
4987 tcg_temp_free(t0);
4988 tcg_temp_free(t1);
4989 tcg_temp_free(t2);
4990 if (unlikely(Rc(ctx->opcode) != 0))
4991 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4992 }
4993
4994 /* dozi */
4995 static void gen_dozi(DisasContext *ctx)
4996 {
4997 target_long simm = SIMM(ctx->opcode);
4998 int l1 = gen_new_label();
4999 int l2 = gen_new_label();
5000 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5001 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5002 tcg_gen_br(l2);
5003 gen_set_label(l1);
5004 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5005 gen_set_label(l2);
5006 if (unlikely(Rc(ctx->opcode) != 0))
5007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5008 }
5009
5010 /* lscbx - lscbx. */
5011 static void gen_lscbx(DisasContext *ctx)
5012 {
5013 TCGv t0 = tcg_temp_new();
5014 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5015 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5016 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5017
5018 gen_addr_reg_index(ctx, t0);
5019 /* NIP cannot be restored if the memory exception comes from an helper */
5020 gen_update_nip(ctx, ctx->nip - 4);
5021 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5022 tcg_temp_free_i32(t1);
5023 tcg_temp_free_i32(t2);
5024 tcg_temp_free_i32(t3);
5025 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5026 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5027 if (unlikely(Rc(ctx->opcode) != 0))
5028 gen_set_Rc0(ctx, t0);
5029 tcg_temp_free(t0);
5030 }
5031
5032 /* maskg - maskg. */
5033 static void gen_maskg(DisasContext *ctx)
5034 {
5035 int l1 = gen_new_label();
5036 TCGv t0 = tcg_temp_new();
5037 TCGv t1 = tcg_temp_new();
5038 TCGv t2 = tcg_temp_new();
5039 TCGv t3 = tcg_temp_new();
5040 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5041 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5042 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5043 tcg_gen_addi_tl(t2, t0, 1);
5044 tcg_gen_shr_tl(t2, t3, t2);
5045 tcg_gen_shr_tl(t3, t3, t1);
5046 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5047 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5048 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5049 gen_set_label(l1);
5050 tcg_temp_free(t0);
5051 tcg_temp_free(t1);
5052 tcg_temp_free(t2);
5053 tcg_temp_free(t3);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5056 }
5057
5058 /* maskir - maskir. */
5059 static void gen_maskir(DisasContext *ctx)
5060 {
5061 TCGv t0 = tcg_temp_new();
5062 TCGv t1 = tcg_temp_new();
5063 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5064 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5065 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5066 tcg_temp_free(t0);
5067 tcg_temp_free(t1);
5068 if (unlikely(Rc(ctx->opcode) != 0))
5069 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5070 }
5071
5072 /* mul - mul. */
5073 static void gen_mul(DisasContext *ctx)
5074 {
5075 TCGv_i64 t0 = tcg_temp_new_i64();
5076 TCGv_i64 t1 = tcg_temp_new_i64();
5077 TCGv t2 = tcg_temp_new();
5078 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5079 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5080 tcg_gen_mul_i64(t0, t0, t1);
5081 tcg_gen_trunc_i64_tl(t2, t0);
5082 gen_store_spr(SPR_MQ, t2);
5083 tcg_gen_shri_i64(t1, t0, 32);
5084 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5085 tcg_temp_free_i64(t0);
5086 tcg_temp_free_i64(t1);
5087 tcg_temp_free(t2);
5088 if (unlikely(Rc(ctx->opcode) != 0))
5089 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5090 }
5091
5092 /* mulo - mulo. */
5093 static void gen_mulo(DisasContext *ctx)
5094 {
5095 int l1 = gen_new_label();
5096 TCGv_i64 t0 = tcg_temp_new_i64();
5097 TCGv_i64 t1 = tcg_temp_new_i64();
5098 TCGv t2 = tcg_temp_new();
5099 /* Start with XER OV disabled, the most likely case */
5100 tcg_gen_movi_tl(cpu_ov, 0);
5101 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5102 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5103 tcg_gen_mul_i64(t0, t0, t1);
5104 tcg_gen_trunc_i64_tl(t2, t0);
5105 gen_store_spr(SPR_MQ, t2);
5106 tcg_gen_shri_i64(t1, t0, 32);
5107 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5108 tcg_gen_ext32s_i64(t1, t0);
5109 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5110 tcg_gen_movi_tl(cpu_ov, 1);
5111 tcg_gen_movi_tl(cpu_so, 1);
5112 gen_set_label(l1);
5113 tcg_temp_free_i64(t0);
5114 tcg_temp_free_i64(t1);
5115 tcg_temp_free(t2);
5116 if (unlikely(Rc(ctx->opcode) != 0))
5117 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5118 }
5119
5120 /* nabs - nabs. */
5121 static void gen_nabs(DisasContext *ctx)
5122 {
5123 int l1 = gen_new_label();
5124 int l2 = gen_new_label();
5125 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5126 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5127 tcg_gen_br(l2);
5128 gen_set_label(l1);
5129 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5130 gen_set_label(l2);
5131 if (unlikely(Rc(ctx->opcode) != 0))
5132 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5133 }
5134
5135 /* nabso - nabso. */
5136 static void gen_nabso(DisasContext *ctx)
5137 {
5138 int l1 = gen_new_label();
5139 int l2 = gen_new_label();
5140 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5141 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5142 tcg_gen_br(l2);
5143 gen_set_label(l1);
5144 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5145 gen_set_label(l2);
5146 /* nabs never overflows */
5147 tcg_gen_movi_tl(cpu_ov, 0);
5148 if (unlikely(Rc(ctx->opcode) != 0))
5149 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5150 }
5151
5152 /* rlmi - rlmi. */
5153 static void gen_rlmi(DisasContext *ctx)
5154 {
5155 uint32_t mb = MB(ctx->opcode);
5156 uint32_t me = ME(ctx->opcode);
5157 TCGv t0 = tcg_temp_new();
5158 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5159 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5160 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5161 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5162 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5163 tcg_temp_free(t0);
5164 if (unlikely(Rc(ctx->opcode) != 0))
5165 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5166 }
5167
5168 /* rrib - rrib. */
5169 static void gen_rrib(DisasContext *ctx)
5170 {
5171 TCGv t0 = tcg_temp_new();
5172 TCGv t1 = tcg_temp_new();
5173 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5174 tcg_gen_movi_tl(t1, 0x80000000);
5175 tcg_gen_shr_tl(t1, t1, t0);
5176 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5177 tcg_gen_and_tl(t0, t0, t1);
5178 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5179 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5180 tcg_temp_free(t0);
5181 tcg_temp_free(t1);
5182 if (unlikely(Rc(ctx->opcode) != 0))
5183 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5184 }
5185
5186 /* sle - sle. */
5187 static void gen_sle(DisasContext *ctx)
5188 {
5189 TCGv t0 = tcg_temp_new();
5190 TCGv t1 = tcg_temp_new();
5191 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5192 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5193 tcg_gen_subfi_tl(t1, 32, t1);
5194 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5195 tcg_gen_or_tl(t1, t0, t1);
5196 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5197 gen_store_spr(SPR_MQ, t1);
5198 tcg_temp_free(t0);
5199 tcg_temp_free(t1);
5200 if (unlikely(Rc(ctx->opcode) != 0))
5201 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5202 }
5203
5204 /* sleq - sleq. */
5205 static void gen_sleq(DisasContext *ctx)
5206 {
5207 TCGv t0 = tcg_temp_new();
5208 TCGv t1 = tcg_temp_new();
5209 TCGv t2 = tcg_temp_new();
5210 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5211 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5212 tcg_gen_shl_tl(t2, t2, t0);
5213 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5214 gen_load_spr(t1, SPR_MQ);
5215 gen_store_spr(SPR_MQ, t0);
5216 tcg_gen_and_tl(t0, t0, t2);
5217 tcg_gen_andc_tl(t1, t1, t2);
5218 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5219 tcg_temp_free(t0);
5220 tcg_temp_free(t1);
5221 tcg_temp_free(t2);
5222 if (unlikely(Rc(ctx->opcode) != 0))
5223 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5224 }
5225
5226 /* sliq - sliq. */
5227 static void gen_sliq(DisasContext *ctx)
5228 {
5229 int sh = SH(ctx->opcode);
5230 TCGv t0 = tcg_temp_new();
5231 TCGv t1 = tcg_temp_new();
5232 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5233 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5234 tcg_gen_or_tl(t1, t0, t1);
5235 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5236 gen_store_spr(SPR_MQ, t1);
5237 tcg_temp_free(t0);
5238 tcg_temp_free(t1);
5239 if (unlikely(Rc(ctx->opcode) != 0))
5240 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5241 }
5242
5243 /* slliq - slliq. */
5244 static void gen_slliq(DisasContext *ctx)
5245 {
5246 int sh = SH(ctx->opcode);
5247 TCGv t0 = tcg_temp_new();
5248 TCGv t1 = tcg_temp_new();
5249 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5250 gen_load_spr(t1, SPR_MQ);
5251 gen_store_spr(SPR_MQ, t0);
5252 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5253 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5254 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5255 tcg_temp_free(t0);
5256 tcg_temp_free(t1);
5257 if (unlikely(Rc(ctx->opcode) != 0))
5258 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5259 }
5260
5261 /* sllq - sllq. */
5262 static void gen_sllq(DisasContext *ctx)
5263 {
5264 int l1 = gen_new_label();
5265 int l2 = gen_new_label();
5266 TCGv t0 = tcg_temp_local_new();
5267 TCGv t1 = tcg_temp_local_new();
5268 TCGv t2 = tcg_temp_local_new();
5269 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5270 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5271 tcg_gen_shl_tl(t1, t1, t2);
5272 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5273 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5274 gen_load_spr(t0, SPR_MQ);
5275 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5276 tcg_gen_br(l2);
5277 gen_set_label(l1);
5278 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5279 gen_load_spr(t2, SPR_MQ);
5280 tcg_gen_andc_tl(t1, t2, t1);
5281 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5282 gen_set_label(l2);
5283 tcg_temp_free(t0);
5284 tcg_temp_free(t1);
5285 tcg_temp_free(t2);
5286 if (unlikely(Rc(ctx->opcode) != 0))
5287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5288 }
5289
5290 /* slq - slq. */
5291 static void gen_slq(DisasContext *ctx)
5292 {
5293 int l1 = gen_new_label();
5294 TCGv t0 = tcg_temp_new();
5295 TCGv t1 = tcg_temp_new();
5296 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5297 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5298 tcg_gen_subfi_tl(t1, 32, t1);
5299 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5300 tcg_gen_or_tl(t1, t0, t1);
5301 gen_store_spr(SPR_MQ, t1);
5302 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5303 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5304 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5305 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5306 gen_set_label(l1);
5307 tcg_temp_free(t0);
5308 tcg_temp_free(t1);
5309 if (unlikely(Rc(ctx->opcode) != 0))
5310 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5311 }
5312
5313 /* sraiq - sraiq. */
5314 static void gen_sraiq(DisasContext *ctx)
5315 {
5316 int sh = SH(ctx->opcode);
5317 int l1 = gen_new_label();
5318 TCGv t0 = tcg_temp_new();
5319 TCGv t1 = tcg_temp_new();
5320 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5321 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5322 tcg_gen_or_tl(t0, t0, t1);
5323 gen_store_spr(SPR_MQ, t0);
5324 tcg_gen_movi_tl(cpu_ca, 0);
5325 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5326 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5327 tcg_gen_movi_tl(cpu_ca, 1);
5328 gen_set_label(l1);
5329 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5330 tcg_temp_free(t0);
5331 tcg_temp_free(t1);
5332 if (unlikely(Rc(ctx->opcode) != 0))
5333 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5334 }
5335
5336 /* sraq - sraq. */
5337 static void gen_sraq(DisasContext *ctx)
5338 {
5339 int l1 = gen_new_label();
5340 int l2 = gen_new_label();
5341 TCGv t0 = tcg_temp_new();
5342 TCGv t1 = tcg_temp_local_new();
5343 TCGv t2 = tcg_temp_local_new();
5344 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5345 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5346 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5347 tcg_gen_subfi_tl(t2, 32, t2);
5348 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5349 tcg_gen_or_tl(t0, t0, t2);
5350 gen_store_spr(SPR_MQ, t0);
5351 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5352 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5353 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5354 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5355 gen_set_label(l1);
5356 tcg_temp_free(t0);
5357 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5358 tcg_gen_movi_tl(cpu_ca, 0);
5359 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5360 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5361 tcg_gen_movi_tl(cpu_ca, 1);
5362 gen_set_label(l2);
5363 tcg_temp_free(t1);
5364 tcg_temp_free(t2);
5365 if (unlikely(Rc(ctx->opcode) != 0))
5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5367 }
5368
5369 /* sre - sre. */
5370 static void gen_sre(DisasContext *ctx)
5371 {
5372 TCGv t0 = tcg_temp_new();
5373 TCGv t1 = tcg_temp_new();
5374 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5375 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5376 tcg_gen_subfi_tl(t1, 32, t1);
5377 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5378 tcg_gen_or_tl(t1, t0, t1);
5379 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5380 gen_store_spr(SPR_MQ, t1);
5381 tcg_temp_free(t0);
5382 tcg_temp_free(t1);
5383 if (unlikely(Rc(ctx->opcode) != 0))
5384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5385 }
5386
5387 /* srea - srea. */
5388 static void gen_srea(DisasContext *ctx)
5389 {
5390 TCGv t0 = tcg_temp_new();
5391 TCGv t1 = tcg_temp_new();
5392 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5393 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5394 gen_store_spr(SPR_MQ, t0);
5395 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5396 tcg_temp_free(t0);
5397 tcg_temp_free(t1);
5398 if (unlikely(Rc(ctx->opcode) != 0))
5399 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5400 }
5401
5402 /* sreq */
5403 static void gen_sreq(DisasContext *ctx)
5404 {
5405 TCGv t0 = tcg_temp_new();
5406 TCGv t1 = tcg_temp_new();
5407 TCGv t2 = tcg_temp_new();
5408 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5409 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5410 tcg_gen_shr_tl(t1, t1, t0);
5411 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5412 gen_load_spr(t2, SPR_MQ);
5413 gen_store_spr(SPR_MQ, t0);
5414 tcg_gen_and_tl(t0, t0, t1);
5415 tcg_gen_andc_tl(t2, t2, t1);
5416 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5417 tcg_temp_free(t0);
5418 tcg_temp_free(t1);
5419 tcg_temp_free(t2);
5420 if (unlikely(Rc(ctx->opcode) != 0))
5421 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5422 }
5423
5424 /* sriq */
5425 static void gen_sriq(DisasContext *ctx)
5426 {
5427 int sh = SH(ctx->opcode);
5428 TCGv t0 = tcg_temp_new();
5429 TCGv t1 = tcg_temp_new();
5430 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5431 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5432 tcg_gen_or_tl(t1, t0, t1);
5433 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5434 gen_store_spr(SPR_MQ, t1);
5435 tcg_temp_free(t0);
5436 tcg_temp_free(t1);
5437 if (unlikely(Rc(ctx->opcode) != 0))
5438 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5439 }
5440
5441 /* srliq */
5442 static void gen_srliq(DisasContext *ctx)
5443 {
5444 int sh = SH(ctx->opcode);
5445 TCGv t0 = tcg_temp_new();
5446 TCGv t1 = tcg_temp_new();
5447 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5448 gen_load_spr(t1, SPR_MQ);
5449 gen_store_spr(SPR_MQ, t0);
5450 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5451 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5452 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5453 tcg_temp_free(t0);
5454 tcg_temp_free(t1);
5455 if (unlikely(Rc(ctx->opcode) != 0))
5456 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5457 }
5458
5459 /* srlq */
5460 static void gen_srlq(DisasContext *ctx)
5461 {
5462 int l1 = gen_new_label();
5463 int l2 = gen_new_label();
5464 TCGv t0 = tcg_temp_local_new();
5465 TCGv t1 = tcg_temp_local_new();
5466 TCGv t2 = tcg_temp_local_new();
5467 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5468 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5469 tcg_gen_shr_tl(t2, t1, t2);
5470 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5471 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5472 gen_load_spr(t0, SPR_MQ);
5473 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5474 tcg_gen_br(l2);
5475 gen_set_label(l1);
5476 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5477 tcg_gen_and_tl(t0, t0, t2);
5478 gen_load_spr(t1, SPR_MQ);
5479 tcg_gen_andc_tl(t1, t1, t2);
5480 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5481 gen_set_label(l2);
5482 tcg_temp_free(t0);
5483 tcg_temp_free(t1);
5484 tcg_temp_free(t2);
5485 if (unlikely(Rc(ctx->opcode) != 0))
5486 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5487 }
5488
5489 /* srq */
5490 static void gen_srq(DisasContext *ctx)
5491 {
5492 int l1 = gen_new_label();
5493 TCGv t0 = tcg_temp_new();
5494 TCGv t1 = tcg_temp_new();
5495 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5496 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5497 tcg_gen_subfi_tl(t1, 32, t1);
5498 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5499 tcg_gen_or_tl(t1, t0, t1);
5500 gen_store_spr(SPR_MQ, t1);
5501 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5502 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5503 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5504 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5505 gen_set_label(l1);
5506 tcg_temp_free(t0);
5507 tcg_temp_free(t1);
5508 if (unlikely(Rc(ctx->opcode) != 0))
5509 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5510 }
5511
5512 /* PowerPC 602 specific instructions */
5513
5514 /* dsa */
5515 static void gen_dsa(DisasContext *ctx)
5516 {
5517 /* XXX: TODO */
5518 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5519 }
5520
5521 /* esa */
5522 static void gen_esa(DisasContext *ctx)
5523 {
5524 /* XXX: TODO */
5525 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5526 }
5527
5528 /* mfrom */
5529 static void gen_mfrom(DisasContext *ctx)
5530 {
5531 #if defined(CONFIG_USER_ONLY)
5532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5533 #else
5534 if (unlikely(!ctx->mem_idx)) {
5535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5536 return;
5537 }
5538 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5539 #endif
5540 }
5541
5542 /* 602 - 603 - G2 TLB management */
5543
5544 /* tlbld */
5545 static void gen_tlbld_6xx(DisasContext *ctx)
5546 {
5547 #if defined(CONFIG_USER_ONLY)
5548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5549 #else
5550 if (unlikely(!ctx->mem_idx)) {
5551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5552 return;
5553 }
5554 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5555 #endif
5556 }
5557
5558 /* tlbli */
5559 static void gen_tlbli_6xx(DisasContext *ctx)
5560 {
5561 #if defined(CONFIG_USER_ONLY)
5562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5563 #else
5564 if (unlikely(!ctx->mem_idx)) {
5565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5566 return;
5567 }
5568 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5569 #endif
5570 }
5571
5572 /* 74xx TLB management */
5573
5574 /* tlbld */
5575 static void gen_tlbld_74xx(DisasContext *ctx)
5576 {
5577 #if defined(CONFIG_USER_ONLY)
5578 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5579 #else
5580 if (unlikely(!ctx->mem_idx)) {
5581 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5582 return;
5583 }
5584 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5585 #endif
5586 }
5587
5588 /* tlbli */
5589 static void gen_tlbli_74xx(DisasContext *ctx)
5590 {
5591 #if defined(CONFIG_USER_ONLY)
5592 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5593 #else
5594 if (unlikely(!ctx->mem_idx)) {
5595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5596 return;
5597 }
5598 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5599 #endif
5600 }
5601
5602 /* POWER instructions not in PowerPC 601 */
5603
5604 /* clf */
5605 static void gen_clf(DisasContext *ctx)
5606 {
5607 /* Cache line flush: implemented as no-op */
5608 }
5609
5610 /* cli */
5611 static void gen_cli(DisasContext *ctx)
5612 {
5613 /* Cache line invalidate: privileged and treated as no-op */
5614 #if defined(CONFIG_USER_ONLY)
5615 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5616 #else
5617 if (unlikely(!ctx->mem_idx)) {
5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5619 return;
5620 }
5621 #endif
5622 }
5623
5624 /* dclst */
5625 static void gen_dclst(DisasContext *ctx)
5626 {
5627 /* Data cache line store: treated as no-op */
5628 }
5629
5630 static void gen_mfsri(DisasContext *ctx)
5631 {
5632 #if defined(CONFIG_USER_ONLY)
5633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5634 #else
5635 int ra = rA(ctx->opcode);
5636 int rd = rD(ctx->opcode);
5637 TCGv t0;
5638 if (unlikely(!ctx->mem_idx)) {
5639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5640 return;
5641 }
5642 t0 = tcg_temp_new();
5643 gen_addr_reg_index(ctx, t0);
5644 tcg_gen_shri_tl(t0, t0, 28);
5645 tcg_gen_andi_tl(t0, t0, 0xF);
5646 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5647 tcg_temp_free(t0);
5648 if (ra != 0 && ra != rd)
5649 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5650 #endif
5651 }
5652
5653 static void gen_rac(DisasContext *ctx)
5654 {
5655 #if defined(CONFIG_USER_ONLY)
5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5657 #else
5658 TCGv t0;
5659 if (unlikely(!ctx->mem_idx)) {
5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5661 return;
5662 }
5663 t0 = tcg_temp_new();
5664 gen_addr_reg_index(ctx, t0);
5665 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5666 tcg_temp_free(t0);
5667 #endif
5668 }
5669
5670 static void gen_rfsvc(DisasContext *ctx)
5671 {
5672 #if defined(CONFIG_USER_ONLY)
5673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5674 #else
5675 if (unlikely(!ctx->mem_idx)) {
5676 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5677 return;
5678 }
5679 gen_helper_rfsvc(cpu_env);
5680 gen_sync_exception(ctx);
5681 #endif
5682 }
5683
5684 /* svc is not implemented for now */
5685
5686 /* POWER2 specific instructions */
5687 /* Quad manipulation (load/store two floats at a time) */
5688
5689 /* lfq */
5690 static void gen_lfq(DisasContext *ctx)
5691 {
5692 int rd = rD(ctx->opcode);
5693 TCGv t0;
5694 gen_set_access_type(ctx, ACCESS_FLOAT);
5695 t0 = tcg_temp_new();
5696 gen_addr_imm_index(ctx, t0, 0);
5697 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5698 gen_addr_add(ctx, t0, t0, 8);
5699 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5700 tcg_temp_free(t0);
5701 }
5702
5703 /* lfqu */
5704 static void gen_lfqu(DisasContext *ctx)
5705 {
5706 int ra = rA(ctx->opcode);
5707 int rd = rD(ctx->opcode);
5708 TCGv t0, t1;
5709 gen_set_access_type(ctx, ACCESS_FLOAT);
5710 t0 = tcg_temp_new();
5711 t1 = tcg_temp_new();
5712 gen_addr_imm_index(ctx, t0, 0);
5713 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5714 gen_addr_add(ctx, t1, t0, 8);
5715 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5716 if (ra != 0)
5717 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5718 tcg_temp_free(t0);
5719 tcg_temp_free(t1);
5720 }
5721
5722 /* lfqux */
5723 static void gen_lfqux(DisasContext *ctx)
5724 {
5725 int ra = rA(ctx->opcode);
5726 int rd = rD(ctx->opcode);
5727 gen_set_access_type(ctx, ACCESS_FLOAT);
5728 TCGv t0, t1;
5729 t0 = tcg_temp_new();
5730 gen_addr_reg_index(ctx, t0);
5731 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5732 t1 = tcg_temp_new();
5733 gen_addr_add(ctx, t1, t0, 8);
5734 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5735 tcg_temp_free(t1);
5736 if (ra != 0)
5737 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5738 tcg_temp_free(t0);
5739 }
5740
5741 /* lfqx */
5742 static void gen_lfqx(DisasContext *ctx)
5743 {
5744 int rd = rD(ctx->opcode);
5745 TCGv t0;
5746 gen_set_access_type(ctx, ACCESS_FLOAT);
5747 t0 = tcg_temp_new();
5748 gen_addr_reg_index(ctx, t0);
5749 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5750 gen_addr_add(ctx, t0, t0, 8);
5751 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5752 tcg_temp_free(t0);
5753 }
5754
5755 /* stfq */
5756 static void gen_stfq(DisasContext *ctx)
5757 {
5758 int rd = rD(ctx->opcode);
5759 TCGv t0;
5760 gen_set_access_type(ctx, ACCESS_FLOAT);
5761 t0 = tcg_temp_new();
5762 gen_addr_imm_index(ctx, t0, 0);
5763 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5764 gen_addr_add(ctx, t0, t0, 8);
5765 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5766 tcg_temp_free(t0);
5767 }
5768
5769 /* stfqu */
5770 static void gen_stfqu(DisasContext *ctx)
5771 {
5772 int ra = rA(ctx->opcode);
5773 int rd = rD(ctx->opcode);
5774 TCGv t0, t1;
5775 gen_set_access_type(ctx, ACCESS_FLOAT);
5776 t0 = tcg_temp_new();
5777 gen_addr_imm_index(ctx, t0, 0);
5778 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5779 t1 = tcg_temp_new();
5780 gen_addr_add(ctx, t1, t0, 8);
5781 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5782 tcg_temp_free(t1);
5783 if (ra != 0)
5784 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5785 tcg_temp_free(t0);
5786 }
5787
5788 /* stfqux */
5789 static void gen_stfqux(DisasContext *ctx)
5790 {
5791 int ra = rA(ctx->opcode);
5792 int rd = rD(ctx->opcode);
5793 TCGv t0, t1;
5794 gen_set_access_type(ctx, ACCESS_FLOAT);
5795 t0 = tcg_temp_new();
5796 gen_addr_reg_index(ctx, t0);
5797 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5798 t1 = tcg_temp_new();
5799 gen_addr_add(ctx, t1, t0, 8);
5800 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5801 tcg_temp_free(t1);
5802 if (ra != 0)
5803 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5804 tcg_temp_free(t0);
5805 }
5806
5807 /* stfqx */
5808 static void gen_stfqx(DisasContext *ctx)
5809 {
5810 int rd = rD(ctx->opcode);
5811 TCGv t0;
5812 gen_set_access_type(ctx, ACCESS_FLOAT);
5813 t0 = tcg_temp_new();
5814 gen_addr_reg_index(ctx, t0);
5815 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5816 gen_addr_add(ctx, t0, t0, 8);
5817 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5818 tcg_temp_free(t0);
5819 }
5820
5821 /* BookE specific instructions */
5822
5823 /* XXX: not implemented on 440 ? */
5824 static void gen_mfapidi(DisasContext *ctx)
5825 {
5826 /* XXX: TODO */
5827 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5828 }
5829
5830 /* XXX: not implemented on 440 ? */
5831 static void gen_tlbiva(DisasContext *ctx)
5832 {
5833 #if defined(CONFIG_USER_ONLY)
5834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5835 #else
5836 TCGv t0;
5837 if (unlikely(!ctx->mem_idx)) {
5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5839 return;
5840 }
5841 t0 = tcg_temp_new();
5842 gen_addr_reg_index(ctx, t0);
5843 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5844 tcg_temp_free(t0);
5845 #endif
5846 }
5847
5848 /* All 405 MAC instructions are translated here */
5849 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5850 int ra, int rb, int rt, int Rc)
5851 {
5852 TCGv t0, t1;
5853
5854 t0 = tcg_temp_local_new();
5855 t1 = tcg_temp_local_new();
5856
5857 switch (opc3 & 0x0D) {
5858 case 0x05:
5859 /* macchw - macchw. - macchwo - macchwo. */
5860 /* macchws - macchws. - macchwso - macchwso. */
5861 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5862 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5863 /* mulchw - mulchw. */
5864 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5865 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5866 tcg_gen_ext16s_tl(t1, t1);
5867 break;
5868 case 0x04:
5869 /* macchwu - macchwu. - macchwuo - macchwuo. */
5870 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5871 /* mulchwu - mulchwu. */
5872 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5873 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5874 tcg_gen_ext16u_tl(t1, t1);
5875 break;
5876 case 0x01:
5877 /* machhw - machhw. - machhwo - machhwo. */
5878 /* machhws - machhws. - machhwso - machhwso. */
5879 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5880 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5881 /* mulhhw - mulhhw. */
5882 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5883 tcg_gen_ext16s_tl(t0, t0);
5884 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5885 tcg_gen_ext16s_tl(t1, t1);
5886 break;
5887 case 0x00:
5888 /* machhwu - machhwu. - machhwuo - machhwuo. */
5889 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5890 /* mulhhwu - mulhhwu. */
5891 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5892 tcg_gen_ext16u_tl(t0, t0);
5893 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5894 tcg_gen_ext16u_tl(t1, t1);
5895 break;
5896 case 0x0D:
5897 /* maclhw - maclhw. - maclhwo - maclhwo. */
5898 /* maclhws - maclhws. - maclhwso - maclhwso. */
5899 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5900 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5901 /* mullhw - mullhw. */
5902 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5903 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5904 break;
5905 case 0x0C:
5906 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5907 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5908 /* mullhwu - mullhwu. */
5909 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5910 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5911 break;
5912 }
5913 if (opc2 & 0x04) {
5914 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5915 tcg_gen_mul_tl(t1, t0, t1);
5916 if (opc2 & 0x02) {
5917 /* nmultiply-and-accumulate (0x0E) */
5918 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5919 } else {
5920 /* multiply-and-accumulate (0x0C) */
5921 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5922 }
5923
5924 if (opc3 & 0x12) {
5925 /* Check overflow and/or saturate */
5926 int l1 = gen_new_label();
5927
5928 if (opc3 & 0x10) {
5929 /* Start with XER OV disabled, the most likely case */
5930 tcg_gen_movi_tl(cpu_ov, 0);
5931 }
5932 if (opc3 & 0x01) {
5933 /* Signed */
5934 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5935 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5936 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5937 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5938 if (opc3 & 0x02) {
5939 /* Saturate */
5940 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5941 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5942 }
5943 } else {
5944 /* Unsigned */
5945 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5946 if (opc3 & 0x02) {
5947 /* Saturate */
5948 tcg_gen_movi_tl(t0, UINT32_MAX);
5949 }
5950 }
5951 if (opc3 & 0x10) {
5952 /* Check overflow */
5953 tcg_gen_movi_tl(cpu_ov, 1);
5954 tcg_gen_movi_tl(cpu_so, 1);
5955 }
5956 gen_set_label(l1);
5957 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5958 }
5959 } else {
5960 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5961 }
5962 tcg_temp_free(t0);
5963 tcg_temp_free(t1);
5964 if (unlikely(Rc) != 0) {
5965 /* Update Rc0 */
5966 gen_set_Rc0(ctx, cpu_gpr[rt]);
5967 }
5968 }
5969
5970 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5971 static void glue(gen_, name)(DisasContext *ctx) \
5972 { \
5973 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5974 rD(ctx->opcode), Rc(ctx->opcode)); \
5975 }
5976
5977 /* macchw - macchw. */
5978 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5979 /* macchwo - macchwo. */
5980 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5981 /* macchws - macchws. */
5982 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5983 /* macchwso - macchwso. */
5984 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5985 /* macchwsu - macchwsu. */
5986 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5987 /* macchwsuo - macchwsuo. */
5988 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5989 /* macchwu - macchwu. */
5990 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5991 /* macchwuo - macchwuo. */
5992 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5993 /* machhw - machhw. */
5994 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5995 /* machhwo - machhwo. */
5996 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5997 /* machhws - machhws. */
5998 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5999 /* machhwso - machhwso. */
6000 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6001 /* machhwsu - machhwsu. */
6002 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6003 /* machhwsuo - machhwsuo. */
6004 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6005 /* machhwu - machhwu. */
6006 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6007 /* machhwuo - machhwuo. */
6008 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6009 /* maclhw - maclhw. */
6010 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6011 /* maclhwo - maclhwo. */
6012 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6013 /* maclhws - maclhws. */
6014 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6015 /* maclhwso - maclhwso. */
6016 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6017 /* maclhwu - maclhwu. */
6018 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6019 /* maclhwuo - maclhwuo. */
6020 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6021 /* maclhwsu - maclhwsu. */
6022 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6023 /* maclhwsuo - maclhwsuo. */
6024 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6025 /* nmacchw - nmacchw. */
6026 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6027 /* nmacchwo - nmacchwo. */
6028 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6029 /* nmacchws - nmacchws. */
6030 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6031 /* nmacchwso - nmacchwso. */
6032 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6033 /* nmachhw - nmachhw. */
6034 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6035 /* nmachhwo - nmachhwo. */
6036 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6037 /* nmachhws - nmachhws. */
6038 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6039 /* nmachhwso - nmachhwso. */
6040 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6041 /* nmaclhw - nmaclhw. */
6042 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6043 /* nmaclhwo - nmaclhwo. */
6044 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6045 /* nmaclhws - nmaclhws. */
6046 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6047 /* nmaclhwso - nmaclhwso. */
6048 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6049
6050 /* mulchw - mulchw. */
6051 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6052 /* mulchwu - mulchwu. */
6053 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6054 /* mulhhw - mulhhw. */
6055 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6056 /* mulhhwu - mulhhwu. */
6057 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6058 /* mullhw - mullhw. */
6059 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6060 /* mullhwu - mullhwu. */
6061 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6062
6063 /* mfdcr */
6064 static void gen_mfdcr(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6068 #else
6069 TCGv dcrn;
6070 if (unlikely(!ctx->mem_idx)) {
6071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6072 return;
6073 }
6074 /* NIP cannot be restored if the memory exception comes from an helper */
6075 gen_update_nip(ctx, ctx->nip - 4);
6076 dcrn = tcg_const_tl(SPR(ctx->opcode));
6077 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6078 tcg_temp_free(dcrn);
6079 #endif
6080 }
6081
6082 /* mtdcr */
6083 static void gen_mtdcr(DisasContext *ctx)
6084 {
6085 #if defined(CONFIG_USER_ONLY)
6086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6087 #else
6088 TCGv dcrn;
6089 if (unlikely(!ctx->mem_idx)) {
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6091 return;
6092 }
6093 /* NIP cannot be restored if the memory exception comes from an helper */
6094 gen_update_nip(ctx, ctx->nip - 4);
6095 dcrn = tcg_const_tl(SPR(ctx->opcode));
6096 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6097 tcg_temp_free(dcrn);
6098 #endif
6099 }
6100
6101 /* mfdcrx */
6102 /* XXX: not implemented on 440 ? */
6103 static void gen_mfdcrx(DisasContext *ctx)
6104 {
6105 #if defined(CONFIG_USER_ONLY)
6106 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6107 #else
6108 if (unlikely(!ctx->mem_idx)) {
6109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6110 return;
6111 }
6112 /* NIP cannot be restored if the memory exception comes from an helper */
6113 gen_update_nip(ctx, ctx->nip - 4);
6114 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6115 cpu_gpr[rA(ctx->opcode)]);
6116 /* Note: Rc update flag set leads to undefined state of Rc0 */
6117 #endif
6118 }
6119
6120 /* mtdcrx */
6121 /* XXX: not implemented on 440 ? */
6122 static void gen_mtdcrx(DisasContext *ctx)
6123 {
6124 #if defined(CONFIG_USER_ONLY)
6125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6126 #else
6127 if (unlikely(!ctx->mem_idx)) {
6128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6129 return;
6130 }
6131 /* NIP cannot be restored if the memory exception comes from an helper */
6132 gen_update_nip(ctx, ctx->nip - 4);
6133 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6134 cpu_gpr[rS(ctx->opcode)]);
6135 /* Note: Rc update flag set leads to undefined state of Rc0 */
6136 #endif
6137 }
6138
6139 /* mfdcrux (PPC 460) : user-mode access to DCR */
6140 static void gen_mfdcrux(DisasContext *ctx)
6141 {
6142 /* NIP cannot be restored if the memory exception comes from an helper */
6143 gen_update_nip(ctx, ctx->nip - 4);
6144 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6145 cpu_gpr[rA(ctx->opcode)]);
6146 /* Note: Rc update flag set leads to undefined state of Rc0 */
6147 }
6148
6149 /* mtdcrux (PPC 460) : user-mode access to DCR */
6150 static void gen_mtdcrux(DisasContext *ctx)
6151 {
6152 /* NIP cannot be restored if the memory exception comes from an helper */
6153 gen_update_nip(ctx, ctx->nip - 4);
6154 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6155 cpu_gpr[rS(ctx->opcode)]);
6156 /* Note: Rc update flag set leads to undefined state of Rc0 */
6157 }
6158
6159 /* dccci */
6160 static void gen_dccci(DisasContext *ctx)
6161 {
6162 #if defined(CONFIG_USER_ONLY)
6163 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6164 #else
6165 if (unlikely(!ctx->mem_idx)) {
6166 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6167 return;
6168 }
6169 /* interpreted as no-op */
6170 #endif
6171 }
6172
6173 /* dcread */
6174 static void gen_dcread(DisasContext *ctx)
6175 {
6176 #if defined(CONFIG_USER_ONLY)
6177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6178 #else
6179 TCGv EA, val;
6180 if (unlikely(!ctx->mem_idx)) {
6181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6182 return;
6183 }
6184 gen_set_access_type(ctx, ACCESS_CACHE);
6185 EA = tcg_temp_new();
6186 gen_addr_reg_index(ctx, EA);
6187 val = tcg_temp_new();
6188 gen_qemu_ld32u(ctx, val, EA);
6189 tcg_temp_free(val);
6190 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6191 tcg_temp_free(EA);
6192 #endif
6193 }
6194
6195 /* icbt */
6196 static void gen_icbt_40x(DisasContext *ctx)
6197 {
6198 /* interpreted as no-op */
6199 /* XXX: specification say this is treated as a load by the MMU
6200 * but does not generate any exception
6201 */
6202 }
6203
6204 /* iccci */
6205 static void gen_iccci(DisasContext *ctx)
6206 {
6207 #if defined(CONFIG_USER_ONLY)
6208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6209 #else
6210 if (unlikely(!ctx->mem_idx)) {
6211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6212 return;
6213 }
6214 /* interpreted as no-op */
6215 #endif
6216 }
6217
6218 /* icread */
6219 static void gen_icread(DisasContext *ctx)
6220 {
6221 #if defined(CONFIG_USER_ONLY)
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6223 #else
6224 if (unlikely(!ctx->mem_idx)) {
6225 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6226 return;
6227 }
6228 /* interpreted as no-op */
6229 #endif
6230 }
6231
6232 /* rfci (mem_idx only) */
6233 static void gen_rfci_40x(DisasContext *ctx)
6234 {
6235 #if defined(CONFIG_USER_ONLY)
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 #else
6238 if (unlikely(!ctx->mem_idx)) {
6239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6240 return;
6241 }
6242 /* Restore CPU state */
6243 gen_helper_40x_rfci(cpu_env);
6244 gen_sync_exception(ctx);
6245 #endif
6246 }
6247
6248 static void gen_rfci(DisasContext *ctx)
6249 {
6250 #if defined(CONFIG_USER_ONLY)
6251 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6252 #else
6253 if (unlikely(!ctx->mem_idx)) {
6254 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6255 return;
6256 }
6257 /* Restore CPU state */
6258 gen_helper_rfci(cpu_env);
6259 gen_sync_exception(ctx);
6260 #endif
6261 }
6262
6263 /* BookE specific */
6264
6265 /* XXX: not implemented on 440 ? */
6266 static void gen_rfdi(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6270 #else
6271 if (unlikely(!ctx->mem_idx)) {
6272 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6273 return;
6274 }
6275 /* Restore CPU state */
6276 gen_helper_rfdi(cpu_env);
6277 gen_sync_exception(ctx);
6278 #endif
6279 }
6280
6281 /* XXX: not implemented on 440 ? */
6282 static void gen_rfmci(DisasContext *ctx)
6283 {
6284 #if defined(CONFIG_USER_ONLY)
6285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6286 #else
6287 if (unlikely(!ctx->mem_idx)) {
6288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6289 return;
6290 }
6291 /* Restore CPU state */
6292 gen_helper_rfmci(cpu_env);
6293 gen_sync_exception(ctx);
6294 #endif
6295 }
6296
6297 /* TLB management - PowerPC 405 implementation */
6298
6299 /* tlbre */
6300 static void gen_tlbre_40x(DisasContext *ctx)
6301 {
6302 #if defined(CONFIG_USER_ONLY)
6303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6304 #else
6305 if (unlikely(!ctx->mem_idx)) {
6306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6307 return;
6308 }
6309 switch (rB(ctx->opcode)) {
6310 case 0:
6311 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6312 cpu_gpr[rA(ctx->opcode)]);
6313 break;
6314 case 1:
6315 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6316 cpu_gpr[rA(ctx->opcode)]);
6317 break;
6318 default:
6319 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6320 break;
6321 }
6322 #endif
6323 }
6324
6325 /* tlbsx - tlbsx. */
6326 static void gen_tlbsx_40x(DisasContext *ctx)
6327 {
6328 #if defined(CONFIG_USER_ONLY)
6329 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6330 #else
6331 TCGv t0;
6332 if (unlikely(!ctx->mem_idx)) {
6333 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6334 return;
6335 }
6336 t0 = tcg_temp_new();
6337 gen_addr_reg_index(ctx, t0);
6338 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6339 tcg_temp_free(t0);
6340 if (Rc(ctx->opcode)) {
6341 int l1 = gen_new_label();
6342 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6343 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6344 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6345 gen_set_label(l1);
6346 }
6347 #endif
6348 }
6349
6350 /* tlbwe */
6351 static void gen_tlbwe_40x(DisasContext *ctx)
6352 {
6353 #if defined(CONFIG_USER_ONLY)
6354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6355 #else
6356 if (unlikely(!ctx->mem_idx)) {
6357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6358 return;
6359 }
6360 switch (rB(ctx->opcode)) {
6361 case 0:
6362 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6363 cpu_gpr[rS(ctx->opcode)]);
6364 break;
6365 case 1:
6366 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6367 cpu_gpr[rS(ctx->opcode)]);
6368 break;
6369 default:
6370 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6371 break;
6372 }
6373 #endif
6374 }
6375
6376 /* TLB management - PowerPC 440 implementation */
6377
6378 /* tlbre */
6379 static void gen_tlbre_440(DisasContext *ctx)
6380 {
6381 #if defined(CONFIG_USER_ONLY)
6382 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6383 #else
6384 if (unlikely(!ctx->mem_idx)) {
6385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6386 return;
6387 }
6388 switch (rB(ctx->opcode)) {
6389 case 0:
6390 case 1:
6391 case 2:
6392 {
6393 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6394 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6395 t0, cpu_gpr[rA(ctx->opcode)]);
6396 tcg_temp_free_i32(t0);
6397 }
6398 break;
6399 default:
6400 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6401 break;
6402 }
6403 #endif
6404 }
6405
6406 /* tlbsx - tlbsx. */
6407 static void gen_tlbsx_440(DisasContext *ctx)
6408 {
6409 #if defined(CONFIG_USER_ONLY)
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 #else
6412 TCGv t0;
6413 if (unlikely(!ctx->mem_idx)) {
6414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6415 return;
6416 }
6417 t0 = tcg_temp_new();
6418 gen_addr_reg_index(ctx, t0);
6419 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6420 tcg_temp_free(t0);
6421 if (Rc(ctx->opcode)) {
6422 int l1 = gen_new_label();
6423 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6424 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6425 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6426 gen_set_label(l1);
6427 }
6428 #endif
6429 }
6430
6431 /* tlbwe */
6432 static void gen_tlbwe_440(DisasContext *ctx)
6433 {
6434 #if defined(CONFIG_USER_ONLY)
6435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6436 #else
6437 if (unlikely(!ctx->mem_idx)) {
6438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6439 return;
6440 }
6441 switch (rB(ctx->opcode)) {
6442 case 0:
6443 case 1:
6444 case 2:
6445 {
6446 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6447 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6448 cpu_gpr[rS(ctx->opcode)]);
6449 tcg_temp_free_i32(t0);
6450 }
6451 break;
6452 default:
6453 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6454 break;
6455 }
6456 #endif
6457 }
6458
6459 /* TLB management - PowerPC BookE 2.06 implementation */
6460
6461 /* tlbre */
6462 static void gen_tlbre_booke206(DisasContext *ctx)
6463 {
6464 #if defined(CONFIG_USER_ONLY)
6465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6466 #else
6467 if (unlikely(!ctx->mem_idx)) {
6468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6469 return;
6470 }
6471
6472 gen_helper_booke206_tlbre(cpu_env);
6473 #endif
6474 }
6475
6476 /* tlbsx - tlbsx. */
6477 static void gen_tlbsx_booke206(DisasContext *ctx)
6478 {
6479 #if defined(CONFIG_USER_ONLY)
6480 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6481 #else
6482 TCGv t0;
6483 if (unlikely(!ctx->mem_idx)) {
6484 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6485 return;
6486 }
6487
6488 if (rA(ctx->opcode)) {
6489 t0 = tcg_temp_new();
6490 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6491 } else {
6492 t0 = tcg_const_tl(0);
6493 }
6494
6495 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6496 gen_helper_booke206_tlbsx(cpu_env, t0);
6497 #endif
6498 }
6499
6500 /* tlbwe */
6501 static void gen_tlbwe_booke206(DisasContext *ctx)
6502 {
6503 #if defined(CONFIG_USER_ONLY)
6504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6505 #else
6506 if (unlikely(!ctx->mem_idx)) {
6507 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6508 return;
6509 }
6510 gen_update_nip(ctx, ctx->nip - 4);
6511 gen_helper_booke206_tlbwe(cpu_env);
6512 #endif
6513 }
6514
6515 static void gen_tlbivax_booke206(DisasContext *ctx)
6516 {
6517 #if defined(CONFIG_USER_ONLY)
6518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6519 #else
6520 TCGv t0;
6521 if (unlikely(!ctx->mem_idx)) {
6522 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6523 return;
6524 }
6525
6526 t0 = tcg_temp_new();
6527 gen_addr_reg_index(ctx, t0);
6528
6529 gen_helper_booke206_tlbivax(cpu_env, t0);
6530 #endif
6531 }
6532
6533 static void gen_tlbilx_booke206(DisasContext *ctx)
6534 {
6535 #if defined(CONFIG_USER_ONLY)
6536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6537 #else
6538 TCGv t0;
6539 if (unlikely(!ctx->mem_idx)) {
6540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6541 return;
6542 }
6543
6544 t0 = tcg_temp_new();
6545 gen_addr_reg_index(ctx, t0);
6546
6547 switch((ctx->opcode >> 21) & 0x3) {
6548 case 0:
6549 gen_helper_booke206_tlbilx0(cpu_env, t0);
6550 break;
6551 case 1:
6552 gen_helper_booke206_tlbilx1(cpu_env, t0);
6553 break;
6554 case 3:
6555 gen_helper_booke206_tlbilx3(cpu_env, t0);
6556 break;
6557 default:
6558 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6559 break;
6560 }
6561
6562 tcg_temp_free(t0);
6563 #endif
6564 }
6565
6566
6567 /* wrtee */
6568 static void gen_wrtee(DisasContext *ctx)
6569 {
6570 #if defined(CONFIG_USER_ONLY)
6571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6572 #else
6573 TCGv t0;
6574 if (unlikely(!ctx->mem_idx)) {
6575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6576 return;
6577 }
6578 t0 = tcg_temp_new();
6579 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6580 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6581 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6582 tcg_temp_free(t0);
6583 /* Stop translation to have a chance to raise an exception
6584 * if we just set msr_ee to 1
6585 */
6586 gen_stop_exception(ctx);
6587 #endif
6588 }
6589
6590 /* wrteei */
6591 static void gen_wrteei(DisasContext *ctx)
6592 {
6593 #if defined(CONFIG_USER_ONLY)
6594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6595 #else
6596 if (unlikely(!ctx->mem_idx)) {
6597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6598 return;
6599 }
6600 if (ctx->opcode & 0x00008000) {
6601 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6602 /* Stop translation to have a chance to raise an exception */
6603 gen_stop_exception(ctx);
6604 } else {
6605 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6606 }
6607 #endif
6608 }
6609
6610 /* PowerPC 440 specific instructions */
6611
6612 /* dlmzb */
6613 static void gen_dlmzb(DisasContext *ctx)
6614 {
6615 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6616 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6617 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6618 tcg_temp_free_i32(t0);
6619 }
6620
6621 /* mbar replaces eieio on 440 */
6622 static void gen_mbar(DisasContext *ctx)
6623 {
6624 /* interpreted as no-op */
6625 }
6626
6627 /* msync replaces sync on 440 */
6628 static void gen_msync_4xx(DisasContext *ctx)
6629 {
6630 /* interpreted as no-op */
6631 }
6632
6633 /* icbt */
6634 static void gen_icbt_440(DisasContext *ctx)
6635 {
6636 /* interpreted as no-op */
6637 /* XXX: specification say this is treated as a load by the MMU
6638 * but does not generate any exception
6639 */
6640 }
6641
6642 /* Embedded.Processor Control */
6643
6644 static void gen_msgclr(DisasContext *ctx)
6645 {
6646 #if defined(CONFIG_USER_ONLY)
6647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6648 #else
6649 if (unlikely(ctx->mem_idx == 0)) {
6650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6651 return;
6652 }
6653
6654 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6655 #endif
6656 }
6657
6658 static void gen_msgsnd(DisasContext *ctx)
6659 {
6660 #if defined(CONFIG_USER_ONLY)
6661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6662 #else
6663 if (unlikely(ctx->mem_idx == 0)) {
6664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6665 return;
6666 }
6667
6668 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6669 #endif
6670 }
6671
6672 /*** Altivec vector extension ***/
6673 /* Altivec registers moves */
6674
6675 static inline TCGv_ptr gen_avr_ptr(int reg)
6676 {
6677 TCGv_ptr r = tcg_temp_new_ptr();
6678 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6679 return r;
6680 }
6681
6682 #define GEN_VR_LDX(name, opc2, opc3) \
6683 static void glue(gen_, name)(DisasContext *ctx) \
6684 { \
6685 TCGv EA; \
6686 if (unlikely(!ctx->altivec_enabled)) { \
6687 gen_exception(ctx, POWERPC_EXCP_VPU); \
6688 return; \
6689 } \
6690 gen_set_access_type(ctx, ACCESS_INT); \
6691 EA = tcg_temp_new(); \
6692 gen_addr_reg_index(ctx, EA); \
6693 tcg_gen_andi_tl(EA, EA, ~0xf); \
6694 if (ctx->le_mode) { \
6695 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6696 tcg_gen_addi_tl(EA, EA, 8); \
6697 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6698 } else { \
6699 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6700 tcg_gen_addi_tl(EA, EA, 8); \
6701 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6702 } \
6703 tcg_temp_free(EA); \
6704 }
6705
6706 #define GEN_VR_STX(name, opc2, opc3) \
6707 static void gen_st##name(DisasContext *ctx) \
6708 { \
6709 TCGv EA; \
6710 if (unlikely(!ctx->altivec_enabled)) { \
6711 gen_exception(ctx, POWERPC_EXCP_VPU); \
6712 return; \
6713 } \
6714 gen_set_access_type(ctx, ACCESS_INT); \
6715 EA = tcg_temp_new(); \
6716 gen_addr_reg_index(ctx, EA); \
6717 tcg_gen_andi_tl(EA, EA, ~0xf); \
6718 if (ctx->le_mode) { \
6719 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6720 tcg_gen_addi_tl(EA, EA, 8); \
6721 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6722 } else { \
6723 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6724 tcg_gen_addi_tl(EA, EA, 8); \
6725 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6726 } \
6727 tcg_temp_free(EA); \
6728 }
6729
6730 #define GEN_VR_LVE(name, opc2, opc3) \
6731 static void gen_lve##name(DisasContext *ctx) \
6732 { \
6733 TCGv EA; \
6734 TCGv_ptr rs; \
6735 if (unlikely(!ctx->altivec_enabled)) { \
6736 gen_exception(ctx, POWERPC_EXCP_VPU); \
6737 return; \
6738 } \
6739 gen_set_access_type(ctx, ACCESS_INT); \
6740 EA = tcg_temp_new(); \
6741 gen_addr_reg_index(ctx, EA); \
6742 rs = gen_avr_ptr(rS(ctx->opcode)); \
6743 gen_helper_lve##name(cpu_env, rs, EA); \
6744 tcg_temp_free(EA); \
6745 tcg_temp_free_ptr(rs); \
6746 }
6747
6748 #define GEN_VR_STVE(name, opc2, opc3) \
6749 static void gen_stve##name(DisasContext *ctx) \
6750 { \
6751 TCGv EA; \
6752 TCGv_ptr rs; \
6753 if (unlikely(!ctx->altivec_enabled)) { \
6754 gen_exception(ctx, POWERPC_EXCP_VPU); \
6755 return; \
6756 } \
6757 gen_set_access_type(ctx, ACCESS_INT); \
6758 EA = tcg_temp_new(); \
6759 gen_addr_reg_index(ctx, EA); \
6760 rs = gen_avr_ptr(rS(ctx->opcode)); \
6761 gen_helper_stve##name(cpu_env, rs, EA); \
6762 tcg_temp_free(EA); \
6763 tcg_temp_free_ptr(rs); \
6764 }
6765
6766 GEN_VR_LDX(lvx, 0x07, 0x03);
6767 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6768 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6769
6770 GEN_VR_LVE(bx, 0x07, 0x00);
6771 GEN_VR_LVE(hx, 0x07, 0x01);
6772 GEN_VR_LVE(wx, 0x07, 0x02);
6773
6774 GEN_VR_STX(svx, 0x07, 0x07);
6775 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6776 GEN_VR_STX(svxl, 0x07, 0x0F);
6777
6778 GEN_VR_STVE(bx, 0x07, 0x04);
6779 GEN_VR_STVE(hx, 0x07, 0x05);
6780 GEN_VR_STVE(wx, 0x07, 0x06);
6781
6782 static void gen_lvsl(DisasContext *ctx)
6783 {
6784 TCGv_ptr rd;
6785 TCGv EA;
6786 if (unlikely(!ctx->altivec_enabled)) {
6787 gen_exception(ctx, POWERPC_EXCP_VPU);
6788 return;
6789 }
6790 EA = tcg_temp_new();
6791 gen_addr_reg_index(ctx, EA);
6792 rd = gen_avr_ptr(rD(ctx->opcode));
6793 gen_helper_lvsl(rd, EA);
6794 tcg_temp_free(EA);
6795 tcg_temp_free_ptr(rd);
6796 }
6797
6798 static void gen_lvsr(DisasContext *ctx)
6799 {
6800 TCGv_ptr rd;
6801 TCGv EA;
6802 if (unlikely(!ctx->altivec_enabled)) {
6803 gen_exception(ctx, POWERPC_EXCP_VPU);
6804 return;
6805 }
6806 EA = tcg_temp_new();
6807 gen_addr_reg_index(ctx, EA);
6808 rd = gen_avr_ptr(rD(ctx->opcode));
6809 gen_helper_lvsr(rd, EA);
6810 tcg_temp_free(EA);
6811 tcg_temp_free_ptr(rd);
6812 }
6813
6814 static void gen_mfvscr(DisasContext *ctx)
6815 {
6816 TCGv_i32 t;
6817 if (unlikely(!ctx->altivec_enabled)) {
6818 gen_exception(ctx, POWERPC_EXCP_VPU);
6819 return;
6820 }
6821 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6822 t = tcg_temp_new_i32();
6823 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6824 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6825 tcg_temp_free_i32(t);
6826 }
6827
6828 static void gen_mtvscr(DisasContext *ctx)
6829 {
6830 TCGv_ptr p;
6831 if (unlikely(!ctx->altivec_enabled)) {
6832 gen_exception(ctx, POWERPC_EXCP_VPU);
6833 return;
6834 }
6835 p = gen_avr_ptr(rD(ctx->opcode));
6836 gen_helper_mtvscr(cpu_env, p);
6837 tcg_temp_free_ptr(p);
6838 }
6839
6840 /* Logical operations */
6841 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6842 static void glue(gen_, name)(DisasContext *ctx) \
6843 { \
6844 if (unlikely(!ctx->altivec_enabled)) { \
6845 gen_exception(ctx, POWERPC_EXCP_VPU); \
6846 return; \
6847 } \
6848 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6849 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6850 }
6851
6852 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6853 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6854 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6855 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6856 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6857 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6858 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6859 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6860
6861 #define GEN_VXFORM(name, opc2, opc3) \
6862 static void glue(gen_, name)(DisasContext *ctx) \
6863 { \
6864 TCGv_ptr ra, rb, rd; \
6865 if (unlikely(!ctx->altivec_enabled)) { \
6866 gen_exception(ctx, POWERPC_EXCP_VPU); \
6867 return; \
6868 } \
6869 ra = gen_avr_ptr(rA(ctx->opcode)); \
6870 rb = gen_avr_ptr(rB(ctx->opcode)); \
6871 rd = gen_avr_ptr(rD(ctx->opcode)); \
6872 gen_helper_##name (rd, ra, rb); \
6873 tcg_temp_free_ptr(ra); \
6874 tcg_temp_free_ptr(rb); \
6875 tcg_temp_free_ptr(rd); \
6876 }
6877
6878 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6879 static void glue(gen_, name)(DisasContext *ctx) \
6880 { \
6881 TCGv_ptr ra, rb, rd; \
6882 if (unlikely(!ctx->altivec_enabled)) { \
6883 gen_exception(ctx, POWERPC_EXCP_VPU); \
6884 return; \
6885 } \
6886 ra = gen_avr_ptr(rA(ctx->opcode)); \
6887 rb = gen_avr_ptr(rB(ctx->opcode)); \
6888 rd = gen_avr_ptr(rD(ctx->opcode)); \
6889 gen_helper_##name(cpu_env, rd, ra, rb); \
6890 tcg_temp_free_ptr(ra); \
6891 tcg_temp_free_ptr(rb); \
6892 tcg_temp_free_ptr(rd); \
6893 }
6894
6895 #define GEN_VXFORM3(name, opc2, opc3) \
6896 static void glue(gen_, name)(DisasContext *ctx) \
6897 { \
6898 TCGv_ptr ra, rb, rc, rd; \
6899 if (unlikely(!ctx->altivec_enabled)) { \
6900 gen_exception(ctx, POWERPC_EXCP_VPU); \
6901 return; \
6902 } \
6903 ra = gen_avr_ptr(rA(ctx->opcode)); \
6904 rb = gen_avr_ptr(rB(ctx->opcode)); \
6905 rc = gen_avr_ptr(rC(ctx->opcode)); \
6906 rd = gen_avr_ptr(rD(ctx->opcode)); \
6907 gen_helper_##name(rd, ra, rb, rc); \
6908 tcg_temp_free_ptr(ra); \
6909 tcg_temp_free_ptr(rb); \
6910 tcg_temp_free_ptr(rc); \
6911 tcg_temp_free_ptr(rd); \
6912 }
6913
6914 /*
6915 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6916 * an opcode bit. In general, these pairs come from different
6917 * versions of the ISA, so we must also support a pair of flags for
6918 * each instruction.
6919 */
6920 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6921 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6922 { \
6923 if ((Rc(ctx->opcode) == 0) && \
6924 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6925 gen_##name0(ctx); \
6926 } else if ((Rc(ctx->opcode) == 1) && \
6927 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6928 gen_##name1(ctx); \
6929 } else { \
6930 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6931 } \
6932 }
6933
6934 GEN_VXFORM(vaddubm, 0, 0);
6935 GEN_VXFORM(vadduhm, 0, 1);
6936 GEN_VXFORM(vadduwm, 0, 2);
6937 GEN_VXFORM(vaddudm, 0, 3);
6938 GEN_VXFORM(vsububm, 0, 16);
6939 GEN_VXFORM(vsubuhm, 0, 17);
6940 GEN_VXFORM(vsubuwm, 0, 18);
6941 GEN_VXFORM(vsubudm, 0, 19);
6942 GEN_VXFORM(vmaxub, 1, 0);
6943 GEN_VXFORM(vmaxuh, 1, 1);
6944 GEN_VXFORM(vmaxuw, 1, 2);
6945 GEN_VXFORM(vmaxud, 1, 3);
6946 GEN_VXFORM(vmaxsb, 1, 4);
6947 GEN_VXFORM(vmaxsh, 1, 5);
6948 GEN_VXFORM(vmaxsw, 1, 6);
6949 GEN_VXFORM(vmaxsd, 1, 7);
6950 GEN_VXFORM(vminub, 1, 8);
6951 GEN_VXFORM(vminuh, 1, 9);
6952 GEN_VXFORM(vminuw, 1, 10);
6953 GEN_VXFORM(vminud, 1, 11);
6954 GEN_VXFORM(vminsb, 1, 12);
6955 GEN_VXFORM(vminsh, 1, 13);
6956 GEN_VXFORM(vminsw, 1, 14);
6957 GEN_VXFORM(vminsd, 1, 15);
6958 GEN_VXFORM(vavgub, 1, 16);
6959 GEN_VXFORM(vavguh, 1, 17);
6960 GEN_VXFORM(vavguw, 1, 18);
6961 GEN_VXFORM(vavgsb, 1, 20);
6962 GEN_VXFORM(vavgsh, 1, 21);
6963 GEN_VXFORM(vavgsw, 1, 22);
6964 GEN_VXFORM(vmrghb, 6, 0);
6965 GEN_VXFORM(vmrghh, 6, 1);
6966 GEN_VXFORM(vmrghw, 6, 2);
6967 GEN_VXFORM(vmrglb, 6, 4);
6968 GEN_VXFORM(vmrglh, 6, 5);
6969 GEN_VXFORM(vmrglw, 6, 6);
6970
6971 static void gen_vmrgew(DisasContext *ctx)
6972 {
6973 TCGv_i64 tmp;
6974 int VT, VA, VB;
6975 if (unlikely(!ctx->altivec_enabled)) {
6976 gen_exception(ctx, POWERPC_EXCP_VPU);
6977 return;
6978 }
6979 VT = rD(ctx->opcode);
6980 VA = rA(ctx->opcode);
6981 VB = rB(ctx->opcode);
6982 tmp = tcg_temp_new_i64();
6983 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
6984 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
6985 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
6986 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
6987 tcg_temp_free_i64(tmp);
6988 }
6989
6990 static void gen_vmrgow(DisasContext *ctx)
6991 {
6992 int VT, VA, VB;
6993 if (unlikely(!ctx->altivec_enabled)) {
6994 gen_exception(ctx, POWERPC_EXCP_VPU);
6995 return;
6996 }
6997 VT = rD(ctx->opcode);
6998 VA = rA(ctx->opcode);
6999 VB = rB(ctx->opcode);
7000
7001 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7002 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7003 }
7004
7005 GEN_VXFORM(vmuloub, 4, 0);
7006 GEN_VXFORM(vmulouh, 4, 1);
7007 GEN_VXFORM(vmulouw, 4, 2);
7008 GEN_VXFORM(vmuluwm, 4, 2);
7009 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7010 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7011 GEN_VXFORM(vmulosb, 4, 4);
7012 GEN_VXFORM(vmulosh, 4, 5);
7013 GEN_VXFORM(vmulosw, 4, 6);
7014 GEN_VXFORM(vmuleub, 4, 8);
7015 GEN_VXFORM(vmuleuh, 4, 9);
7016 GEN_VXFORM(vmuleuw, 4, 10);
7017 GEN_VXFORM(vmulesb, 4, 12);
7018 GEN_VXFORM(vmulesh, 4, 13);
7019 GEN_VXFORM(vmulesw, 4, 14);
7020 GEN_VXFORM(vslb, 2, 4);
7021 GEN_VXFORM(vslh, 2, 5);
7022 GEN_VXFORM(vslw, 2, 6);
7023 GEN_VXFORM(vsld, 2, 23);
7024 GEN_VXFORM(vsrb, 2, 8);
7025 GEN_VXFORM(vsrh, 2, 9);
7026 GEN_VXFORM(vsrw, 2, 10);
7027 GEN_VXFORM(vsrd, 2, 27);
7028 GEN_VXFORM(vsrab, 2, 12);
7029 GEN_VXFORM(vsrah, 2, 13);
7030 GEN_VXFORM(vsraw, 2, 14);
7031 GEN_VXFORM(vsrad, 2, 15);
7032 GEN_VXFORM(vslo, 6, 16);
7033 GEN_VXFORM(vsro, 6, 17);
7034 GEN_VXFORM(vaddcuw, 0, 6);
7035 GEN_VXFORM(vsubcuw, 0, 22);
7036 GEN_VXFORM_ENV(vaddubs, 0, 8);
7037 GEN_VXFORM_ENV(vadduhs, 0, 9);
7038 GEN_VXFORM_ENV(vadduws, 0, 10);
7039 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7040 GEN_VXFORM_ENV(vaddshs, 0, 13);
7041 GEN_VXFORM_ENV(vaddsws, 0, 14);
7042 GEN_VXFORM_ENV(vsububs, 0, 24);
7043 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7044 GEN_VXFORM_ENV(vsubuws, 0, 26);
7045 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7046 GEN_VXFORM_ENV(vsubshs, 0, 29);
7047 GEN_VXFORM_ENV(vsubsws, 0, 30);
7048 GEN_VXFORM(vadduqm, 0, 4);
7049 GEN_VXFORM(vaddcuq, 0, 5);
7050 GEN_VXFORM3(vaddeuqm, 30, 0);
7051 GEN_VXFORM3(vaddecuq, 30, 0);
7052 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7053 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7054 GEN_VXFORM(vsubuqm, 0, 20);
7055 GEN_VXFORM(vsubcuq, 0, 21);
7056 GEN_VXFORM3(vsubeuqm, 31, 0);
7057 GEN_VXFORM3(vsubecuq, 31, 0);
7058 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7059 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7060 GEN_VXFORM(vrlb, 2, 0);
7061 GEN_VXFORM(vrlh, 2, 1);
7062 GEN_VXFORM(vrlw, 2, 2);
7063 GEN_VXFORM(vrld, 2, 3);
7064 GEN_VXFORM(vsl, 2, 7);
7065 GEN_VXFORM(vsr, 2, 11);
7066 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7067 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7068 GEN_VXFORM_ENV(vpkudum, 7, 17);
7069 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7070 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7071 GEN_VXFORM_ENV(vpkudus, 7, 19);
7072 GEN_VXFORM_ENV(vpkshus, 7, 4);
7073 GEN_VXFORM_ENV(vpkswus, 7, 5);
7074 GEN_VXFORM_ENV(vpksdus, 7, 21);
7075 GEN_VXFORM_ENV(vpkshss, 7, 6);
7076 GEN_VXFORM_ENV(vpkswss, 7, 7);
7077 GEN_VXFORM_ENV(vpksdss, 7, 23);
7078 GEN_VXFORM(vpkpx, 7, 12);
7079 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7080 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7081 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7082 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7083 GEN_VXFORM_ENV(vsumsws, 4, 30);
7084 GEN_VXFORM_ENV(vaddfp, 5, 0);
7085 GEN_VXFORM_ENV(vsubfp, 5, 1);
7086 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7087 GEN_VXFORM_ENV(vminfp, 5, 17);
7088
7089 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7090 static void glue(gen_, name)(DisasContext *ctx) \
7091 { \
7092 TCGv_ptr ra, rb, rd; \
7093 if (unlikely(!ctx->altivec_enabled)) { \
7094 gen_exception(ctx, POWERPC_EXCP_VPU); \
7095 return; \
7096 } \
7097 ra = gen_avr_ptr(rA(ctx->opcode)); \
7098 rb = gen_avr_ptr(rB(ctx->opcode)); \
7099 rd = gen_avr_ptr(rD(ctx->opcode)); \
7100 gen_helper_##opname(cpu_env, rd, ra, rb); \
7101 tcg_temp_free_ptr(ra); \
7102 tcg_temp_free_ptr(rb); \
7103 tcg_temp_free_ptr(rd); \
7104 }
7105
7106 #define GEN_VXRFORM(name, opc2, opc3) \
7107 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7108 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7109
7110 /*
7111 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7112 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7113 * come from different versions of the ISA, so we must also support a
7114 * pair of flags for each instruction.
7115 */
7116 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7117 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7118 { \
7119 if ((Rc(ctx->opcode) == 0) && \
7120 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7121 if (Rc21(ctx->opcode) == 0) { \
7122 gen_##name0(ctx); \
7123 } else { \
7124 gen_##name0##_(ctx); \
7125 } \
7126 } else if ((Rc(ctx->opcode) == 1) && \
7127 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7128 if (Rc21(ctx->opcode) == 0) { \
7129 gen_##name1(ctx); \
7130 } else { \
7131 gen_##name1##_(ctx); \
7132 } \
7133 } else { \
7134 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7135 } \
7136 }
7137
7138 GEN_VXRFORM(vcmpequb, 3, 0)
7139 GEN_VXRFORM(vcmpequh, 3, 1)
7140 GEN_VXRFORM(vcmpequw, 3, 2)
7141 GEN_VXRFORM(vcmpequd, 3, 3)
7142 GEN_VXRFORM(vcmpgtsb, 3, 12)
7143 GEN_VXRFORM(vcmpgtsh, 3, 13)
7144 GEN_VXRFORM(vcmpgtsw, 3, 14)
7145 GEN_VXRFORM(vcmpgtsd, 3, 15)
7146 GEN_VXRFORM(vcmpgtub, 3, 8)
7147 GEN_VXRFORM(vcmpgtuh, 3, 9)
7148 GEN_VXRFORM(vcmpgtuw, 3, 10)
7149 GEN_VXRFORM(vcmpgtud, 3, 11)
7150 GEN_VXRFORM(vcmpeqfp, 3, 3)
7151 GEN_VXRFORM(vcmpgefp, 3, 7)
7152 GEN_VXRFORM(vcmpgtfp, 3, 11)
7153 GEN_VXRFORM(vcmpbfp, 3, 15)
7154
7155 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7156 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7157 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7158 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7159 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7160 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7161
7162 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7163 static void glue(gen_, name)(DisasContext *ctx) \
7164 { \
7165 TCGv_ptr rd; \
7166 TCGv_i32 simm; \
7167 if (unlikely(!ctx->altivec_enabled)) { \
7168 gen_exception(ctx, POWERPC_EXCP_VPU); \
7169 return; \
7170 } \
7171 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7172 rd = gen_avr_ptr(rD(ctx->opcode)); \
7173 gen_helper_##name (rd, simm); \
7174 tcg_temp_free_i32(simm); \
7175 tcg_temp_free_ptr(rd); \
7176 }
7177
7178 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7179 GEN_VXFORM_SIMM(vspltish, 6, 13);
7180 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7181
7182 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7183 static void glue(gen_, name)(DisasContext *ctx) \
7184 { \
7185 TCGv_ptr rb, rd; \
7186 if (unlikely(!ctx->altivec_enabled)) { \
7187 gen_exception(ctx, POWERPC_EXCP_VPU); \
7188 return; \
7189 } \
7190 rb = gen_avr_ptr(rB(ctx->opcode)); \
7191 rd = gen_avr_ptr(rD(ctx->opcode)); \
7192 gen_helper_##name (rd, rb); \
7193 tcg_temp_free_ptr(rb); \
7194 tcg_temp_free_ptr(rd); \
7195 }
7196
7197 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7198 static void glue(gen_, name)(DisasContext *ctx) \
7199 { \
7200 TCGv_ptr rb, rd; \
7201 \
7202 if (unlikely(!ctx->altivec_enabled)) { \
7203 gen_exception(ctx, POWERPC_EXCP_VPU); \
7204 return; \
7205 } \
7206 rb = gen_avr_ptr(rB(ctx->opcode)); \
7207 rd = gen_avr_ptr(rD(ctx->opcode)); \
7208 gen_helper_##name(cpu_env, rd, rb); \
7209 tcg_temp_free_ptr(rb); \
7210 tcg_temp_free_ptr(rd); \
7211 }
7212
7213 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7214 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7215 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7216 GEN_VXFORM_NOA(vupklsb, 7, 10);
7217 GEN_VXFORM_NOA(vupklsh, 7, 11);
7218 GEN_VXFORM_NOA(vupklsw, 7, 27);
7219 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7220 GEN_VXFORM_NOA(vupklpx, 7, 15);
7221 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7222 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7223 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7224 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7225 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7226 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7227 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7228 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7229
7230 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7231 static void glue(gen_, name)(DisasContext *ctx) \
7232 { \
7233 TCGv_ptr rd; \
7234 TCGv_i32 simm; \
7235 if (unlikely(!ctx->altivec_enabled)) { \
7236 gen_exception(ctx, POWERPC_EXCP_VPU); \
7237 return; \
7238 } \
7239 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7240 rd = gen_avr_ptr(rD(ctx->opcode)); \
7241 gen_helper_##name (rd, simm); \
7242 tcg_temp_free_i32(simm); \
7243 tcg_temp_free_ptr(rd); \
7244 }
7245
7246 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7247 static void glue(gen_, name)(DisasContext *ctx) \
7248 { \
7249 TCGv_ptr rb, rd; \
7250 TCGv_i32 uimm; \
7251 if (unlikely(!ctx->altivec_enabled)) { \
7252 gen_exception(ctx, POWERPC_EXCP_VPU); \
7253 return; \
7254 } \
7255 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7256 rb = gen_avr_ptr(rB(ctx->opcode)); \
7257 rd = gen_avr_ptr(rD(ctx->opcode)); \
7258 gen_helper_##name (rd, rb, uimm); \
7259 tcg_temp_free_i32(uimm); \
7260 tcg_temp_free_ptr(rb); \
7261 tcg_temp_free_ptr(rd); \
7262 }
7263
7264 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7265 static void glue(gen_, name)(DisasContext *ctx) \
7266 { \
7267 TCGv_ptr rb, rd; \
7268 TCGv_i32 uimm; \
7269 \
7270 if (unlikely(!ctx->altivec_enabled)) { \
7271 gen_exception(ctx, POWERPC_EXCP_VPU); \
7272 return; \
7273 } \
7274 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7275 rb = gen_avr_ptr(rB(ctx->opcode)); \
7276 rd = gen_avr_ptr(rD(ctx->opcode)); \
7277 gen_helper_##name(cpu_env, rd, rb, uimm); \
7278 tcg_temp_free_i32(uimm); \
7279 tcg_temp_free_ptr(rb); \
7280 tcg_temp_free_ptr(rd); \
7281 }
7282
7283 GEN_VXFORM_UIMM(vspltb, 6, 8);
7284 GEN_VXFORM_UIMM(vsplth, 6, 9);
7285 GEN_VXFORM_UIMM(vspltw, 6, 10);
7286 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7287 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7288 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7289 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7290
7291 static void gen_vsldoi(DisasContext *ctx)
7292 {
7293 TCGv_ptr ra, rb, rd;
7294 TCGv_i32 sh;
7295 if (unlikely(!ctx->altivec_enabled)) {
7296 gen_exception(ctx, POWERPC_EXCP_VPU);
7297 return;
7298 }
7299 ra = gen_avr_ptr(rA(ctx->opcode));
7300 rb = gen_avr_ptr(rB(ctx->opcode));
7301 rd = gen_avr_ptr(rD(ctx->opcode));
7302 sh = tcg_const_i32(VSH(ctx->opcode));
7303 gen_helper_vsldoi (rd, ra, rb, sh);
7304 tcg_temp_free_ptr(ra);
7305 tcg_temp_free_ptr(rb);
7306 tcg_temp_free_ptr(rd);
7307 tcg_temp_free_i32(sh);
7308 }
7309
7310 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7311 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7312 { \
7313 TCGv_ptr ra, rb, rc, rd; \
7314 if (unlikely(!ctx->altivec_enabled)) { \
7315 gen_exception(ctx, POWERPC_EXCP_VPU); \
7316 return; \
7317 } \
7318 ra = gen_avr_ptr(rA(ctx->opcode)); \
7319 rb = gen_avr_ptr(rB(ctx->opcode)); \
7320 rc = gen_avr_ptr(rC(ctx->opcode)); \
7321 rd = gen_avr_ptr(rD(ctx->opcode)); \
7322 if (Rc(ctx->opcode)) { \
7323 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7324 } else { \
7325 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7326 } \
7327 tcg_temp_free_ptr(ra); \
7328 tcg_temp_free_ptr(rb); \
7329 tcg_temp_free_ptr(rc); \
7330 tcg_temp_free_ptr(rd); \
7331 }
7332
7333 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7334
7335 static void gen_vmladduhm(DisasContext *ctx)
7336 {
7337 TCGv_ptr ra, rb, rc, rd;
7338 if (unlikely(!ctx->altivec_enabled)) {
7339 gen_exception(ctx, POWERPC_EXCP_VPU);
7340 return;
7341 }
7342 ra = gen_avr_ptr(rA(ctx->opcode));
7343 rb = gen_avr_ptr(rB(ctx->opcode));
7344 rc = gen_avr_ptr(rC(ctx->opcode));
7345 rd = gen_avr_ptr(rD(ctx->opcode));
7346 gen_helper_vmladduhm(rd, ra, rb, rc);
7347 tcg_temp_free_ptr(ra);
7348 tcg_temp_free_ptr(rb);
7349 tcg_temp_free_ptr(rc);
7350 tcg_temp_free_ptr(rd);
7351 }
7352
7353 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7354 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7355 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7356 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7357 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7358
7359 GEN_VXFORM_NOA(vclzb, 1, 28)
7360 GEN_VXFORM_NOA(vclzh, 1, 29)
7361 GEN_VXFORM_NOA(vclzw, 1, 30)
7362 GEN_VXFORM_NOA(vclzd, 1, 31)
7363 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7364 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7365 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7366 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7367 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7368 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7369 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7370 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7371 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7372 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7373 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7374 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7375 GEN_VXFORM(vbpermq, 6, 21);
7376 GEN_VXFORM_NOA(vgbbd, 6, 20);
7377 GEN_VXFORM(vpmsumb, 4, 16)
7378 GEN_VXFORM(vpmsumh, 4, 17)
7379 GEN_VXFORM(vpmsumw, 4, 18)
7380 GEN_VXFORM(vpmsumd, 4, 19)
7381
7382 #define GEN_BCD(op) \
7383 static void gen_##op(DisasContext *ctx) \
7384 { \
7385 TCGv_ptr ra, rb, rd; \
7386 TCGv_i32 ps; \
7387 \
7388 if (unlikely(!ctx->altivec_enabled)) { \
7389 gen_exception(ctx, POWERPC_EXCP_VPU); \
7390 return; \
7391 } \
7392 \
7393 ra = gen_avr_ptr(rA(ctx->opcode)); \
7394 rb = gen_avr_ptr(rB(ctx->opcode)); \
7395 rd = gen_avr_ptr(rD(ctx->opcode)); \
7396 \
7397 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7398 \
7399 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7400 \
7401 tcg_temp_free_ptr(ra); \
7402 tcg_temp_free_ptr(rb); \
7403 tcg_temp_free_ptr(rd); \
7404 tcg_temp_free_i32(ps); \
7405 }
7406
7407 GEN_BCD(bcdadd)
7408 GEN_BCD(bcdsub)
7409
7410 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7411 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7412 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7413 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7414 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7415 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7416 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7417 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7418
7419 static void gen_vsbox(DisasContext *ctx)
7420 {
7421 TCGv_ptr ra, rd;
7422 if (unlikely(!ctx->altivec_enabled)) {
7423 gen_exception(ctx, POWERPC_EXCP_VPU);
7424 return;
7425 }
7426 ra = gen_avr_ptr(rA(ctx->opcode));
7427 rd = gen_avr_ptr(rD(ctx->opcode));
7428 gen_helper_vsbox(rd, ra);
7429 tcg_temp_free_ptr(ra);
7430 tcg_temp_free_ptr(rd);
7431 }
7432
7433 GEN_VXFORM(vcipher, 4, 20)
7434 GEN_VXFORM(vcipherlast, 4, 20)
7435 GEN_VXFORM(vncipher, 4, 21)
7436 GEN_VXFORM(vncipherlast, 4, 21)
7437
7438 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7439 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7440 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7441 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7442
7443 #define VSHASIGMA(op) \
7444 static void gen_##op(DisasContext *ctx) \
7445 { \
7446 TCGv_ptr ra, rd; \
7447 TCGv_i32 st_six; \
7448 if (unlikely(!ctx->altivec_enabled)) { \
7449 gen_exception(ctx, POWERPC_EXCP_VPU); \
7450 return; \
7451 } \
7452 ra = gen_avr_ptr(rA(ctx->opcode)); \
7453 rd = gen_avr_ptr(rD(ctx->opcode)); \
7454 st_six = tcg_const_i32(rB(ctx->opcode)); \
7455 gen_helper_##op(rd, ra, st_six); \
7456 tcg_temp_free_ptr(ra); \
7457 tcg_temp_free_ptr(rd); \
7458 tcg_temp_free_i32(st_six); \
7459 }
7460
7461 VSHASIGMA(vshasigmaw)
7462 VSHASIGMA(vshasigmad)
7463
7464 GEN_VXFORM3(vpermxor, 22, 0xFF)
7465 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7466 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7467
7468 /*** VSX extension ***/
7469
7470 static inline TCGv_i64 cpu_vsrh(int n)
7471 {
7472 if (n < 32) {
7473 return cpu_fpr[n];
7474 } else {
7475 return cpu_avrh[n-32];
7476 }
7477 }
7478
7479 static inline TCGv_i64 cpu_vsrl(int n)
7480 {
7481 if (n < 32) {
7482 return cpu_vsr[n];
7483 } else {
7484 return cpu_avrl[n-32];
7485 }
7486 }
7487
7488 #define VSX_LOAD_SCALAR(name, operation) \
7489 static void gen_##name(DisasContext *ctx) \
7490 { \
7491 TCGv EA; \
7492 if (unlikely(!ctx->vsx_enabled)) { \
7493 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7494 return; \
7495 } \
7496 gen_set_access_type(ctx, ACCESS_INT); \
7497 EA = tcg_temp_new(); \
7498 gen_addr_reg_index(ctx, EA); \
7499 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7500 /* NOTE: cpu_vsrl is undefined */ \
7501 tcg_temp_free(EA); \
7502 }
7503
7504 VSX_LOAD_SCALAR(lxsdx, ld64)
7505 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7506 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7507 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7508
7509 static void gen_lxvd2x(DisasContext *ctx)
7510 {
7511 TCGv EA;
7512 if (unlikely(!ctx->vsx_enabled)) {
7513 gen_exception(ctx, POWERPC_EXCP_VSXU);
7514 return;
7515 }
7516 gen_set_access_type(ctx, ACCESS_INT);
7517 EA = tcg_temp_new();
7518 gen_addr_reg_index(ctx, EA);
7519 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7520 tcg_gen_addi_tl(EA, EA, 8);
7521 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7522 tcg_temp_free(EA);
7523 }
7524
7525 static void gen_lxvdsx(DisasContext *ctx)
7526 {
7527 TCGv EA;
7528 if (unlikely(!ctx->vsx_enabled)) {
7529 gen_exception(ctx, POWERPC_EXCP_VSXU);
7530 return;
7531 }
7532 gen_set_access_type(ctx, ACCESS_INT);
7533 EA = tcg_temp_new();
7534 gen_addr_reg_index(ctx, EA);
7535 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7536 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7537 tcg_temp_free(EA);
7538 }
7539
7540 static void gen_lxvw4x(DisasContext *ctx)
7541 {
7542 TCGv EA;
7543 TCGv_i64 tmp;
7544 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7545 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7546 if (unlikely(!ctx->vsx_enabled)) {
7547 gen_exception(ctx, POWERPC_EXCP_VSXU);
7548 return;
7549 }
7550 gen_set_access_type(ctx, ACCESS_INT);
7551 EA = tcg_temp_new();
7552 tmp = tcg_temp_new_i64();
7553
7554 gen_addr_reg_index(ctx, EA);
7555 gen_qemu_ld32u_i64(ctx, tmp, EA);
7556 tcg_gen_addi_tl(EA, EA, 4);
7557 gen_qemu_ld32u_i64(ctx, xth, EA);
7558 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7559
7560 tcg_gen_addi_tl(EA, EA, 4);
7561 gen_qemu_ld32u_i64(ctx, tmp, EA);
7562 tcg_gen_addi_tl(EA, EA, 4);
7563 gen_qemu_ld32u_i64(ctx, xtl, EA);
7564 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7565
7566 tcg_temp_free(EA);
7567 tcg_temp_free_i64(tmp);
7568 }
7569
7570 #define VSX_STORE_SCALAR(name, operation) \
7571 static void gen_##name(DisasContext *ctx) \
7572 { \
7573 TCGv EA; \
7574 if (unlikely(!ctx->vsx_enabled)) { \
7575 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7576 return; \
7577 } \
7578 gen_set_access_type(ctx, ACCESS_INT); \
7579 EA = tcg_temp_new(); \
7580 gen_addr_reg_index(ctx, EA); \
7581 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7582 tcg_temp_free(EA); \
7583 }
7584
7585 VSX_STORE_SCALAR(stxsdx, st64)
7586 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7587 VSX_STORE_SCALAR(stxsspx, st32fs)
7588
7589 static void gen_stxvd2x(DisasContext *ctx)
7590 {
7591 TCGv EA;
7592 if (unlikely(!ctx->vsx_enabled)) {
7593 gen_exception(ctx, POWERPC_EXCP_VSXU);
7594 return;
7595 }
7596 gen_set_access_type(ctx, ACCESS_INT);
7597 EA = tcg_temp_new();
7598 gen_addr_reg_index(ctx, EA);
7599 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7600 tcg_gen_addi_tl(EA, EA, 8);
7601 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7602 tcg_temp_free(EA);
7603 }
7604
7605 static void gen_stxvw4x(DisasContext *ctx)
7606 {
7607 TCGv_i64 tmp;
7608 TCGv EA;
7609 if (unlikely(!ctx->vsx_enabled)) {
7610 gen_exception(ctx, POWERPC_EXCP_VSXU);
7611 return;
7612 }
7613 gen_set_access_type(ctx, ACCESS_INT);
7614 EA = tcg_temp_new();
7615 gen_addr_reg_index(ctx, EA);
7616 tmp = tcg_temp_new_i64();
7617
7618 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7619 gen_qemu_st32_i64(ctx, tmp, EA);
7620 tcg_gen_addi_tl(EA, EA, 4);
7621 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7622
7623 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7624 tcg_gen_addi_tl(EA, EA, 4);
7625 gen_qemu_st32_i64(ctx, tmp, EA);
7626 tcg_gen_addi_tl(EA, EA, 4);
7627 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7628
7629 tcg_temp_free(EA);
7630 tcg_temp_free_i64(tmp);
7631 }
7632
7633 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7634 static void gen_##name(DisasContext *ctx) \
7635 { \
7636 if (xS(ctx->opcode) < 32) { \
7637 if (unlikely(!ctx->fpu_enabled)) { \
7638 gen_exception(ctx, POWERPC_EXCP_FPU); \
7639 return; \
7640 } \
7641 } else { \
7642 if (unlikely(!ctx->altivec_enabled)) { \
7643 gen_exception(ctx, POWERPC_EXCP_VPU); \
7644 return; \
7645 } \
7646 } \
7647 TCGv_i64 tmp = tcg_temp_new_i64(); \
7648 tcg_gen_##tcgop1(tmp, source); \
7649 tcg_gen_##tcgop2(target, tmp); \
7650 tcg_temp_free_i64(tmp); \
7651 }
7652
7653
7654 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7655 cpu_vsrh(xS(ctx->opcode)))
7656 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7657 cpu_gpr[rA(ctx->opcode)])
7658 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7659 cpu_gpr[rA(ctx->opcode)])
7660
7661 #if defined(TARGET_PPC64)
7662 #define MV_VSRD(name, target, source) \
7663 static void gen_##name(DisasContext *ctx) \
7664 { \
7665 if (xS(ctx->opcode) < 32) { \
7666 if (unlikely(!ctx->fpu_enabled)) { \
7667 gen_exception(ctx, POWERPC_EXCP_FPU); \
7668 return; \
7669 } \
7670 } else { \
7671 if (unlikely(!ctx->altivec_enabled)) { \
7672 gen_exception(ctx, POWERPC_EXCP_VPU); \
7673 return; \
7674 } \
7675 } \
7676 tcg_gen_mov_i64(target, source); \
7677 }
7678
7679 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7680 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7681
7682 #endif
7683
7684 static void gen_xxpermdi(DisasContext *ctx)
7685 {
7686 if (unlikely(!ctx->vsx_enabled)) {
7687 gen_exception(ctx, POWERPC_EXCP_VSXU);
7688 return;
7689 }
7690
7691 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7692 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7693 TCGv_i64 xh, xl;
7694
7695 xh = tcg_temp_new_i64();
7696 xl = tcg_temp_new_i64();
7697
7698 if ((DM(ctx->opcode) & 2) == 0) {
7699 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7700 } else {
7701 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7702 }
7703 if ((DM(ctx->opcode) & 1) == 0) {
7704 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7705 } else {
7706 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7707 }
7708
7709 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7710 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7711
7712 tcg_temp_free_i64(xh);
7713 tcg_temp_free_i64(xl);
7714 } else {
7715 if ((DM(ctx->opcode) & 2) == 0) {
7716 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7717 } else {
7718 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7719 }
7720 if ((DM(ctx->opcode) & 1) == 0) {
7721 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7722 } else {
7723 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7724 }
7725 }
7726 }
7727
7728 #define OP_ABS 1
7729 #define OP_NABS 2
7730 #define OP_NEG 3
7731 #define OP_CPSGN 4
7732 #define SGN_MASK_DP 0x8000000000000000ull
7733 #define SGN_MASK_SP 0x8000000080000000ull
7734
7735 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7736 static void glue(gen_, name)(DisasContext * ctx) \
7737 { \
7738 TCGv_i64 xb, sgm; \
7739 if (unlikely(!ctx->vsx_enabled)) { \
7740 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7741 return; \
7742 } \
7743 xb = tcg_temp_new_i64(); \
7744 sgm = tcg_temp_new_i64(); \
7745 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7746 tcg_gen_movi_i64(sgm, sgn_mask); \
7747 switch (op) { \
7748 case OP_ABS: { \
7749 tcg_gen_andc_i64(xb, xb, sgm); \
7750 break; \
7751 } \
7752 case OP_NABS: { \
7753 tcg_gen_or_i64(xb, xb, sgm); \
7754 break; \
7755 } \
7756 case OP_NEG: { \
7757 tcg_gen_xor_i64(xb, xb, sgm); \
7758 break; \
7759 } \
7760 case OP_CPSGN: { \
7761 TCGv_i64 xa = tcg_temp_new_i64(); \
7762 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7763 tcg_gen_and_i64(xa, xa, sgm); \
7764 tcg_gen_andc_i64(xb, xb, sgm); \
7765 tcg_gen_or_i64(xb, xb, xa); \
7766 tcg_temp_free_i64(xa); \
7767 break; \
7768 } \
7769 } \
7770 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7771 tcg_temp_free_i64(xb); \
7772 tcg_temp_free_i64(sgm); \
7773 }
7774
7775 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7776 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7777 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7778 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7779
7780 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7781 static void glue(gen_, name)(DisasContext * ctx) \
7782 { \
7783 TCGv_i64 xbh, xbl, sgm; \
7784 if (unlikely(!ctx->vsx_enabled)) { \
7785 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7786 return; \
7787 } \
7788 xbh = tcg_temp_new_i64(); \
7789 xbl = tcg_temp_new_i64(); \
7790 sgm = tcg_temp_new_i64(); \
7791 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7792 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7793 tcg_gen_movi_i64(sgm, sgn_mask); \
7794 switch (op) { \
7795 case OP_ABS: { \
7796 tcg_gen_andc_i64(xbh, xbh, sgm); \
7797 tcg_gen_andc_i64(xbl, xbl, sgm); \
7798 break; \
7799 } \
7800 case OP_NABS: { \
7801 tcg_gen_or_i64(xbh, xbh, sgm); \
7802 tcg_gen_or_i64(xbl, xbl, sgm); \
7803 break; \
7804 } \
7805 case OP_NEG: { \
7806 tcg_gen_xor_i64(xbh, xbh, sgm); \
7807 tcg_gen_xor_i64(xbl, xbl, sgm); \
7808 break; \
7809 } \
7810 case OP_CPSGN: { \
7811 TCGv_i64 xah = tcg_temp_new_i64(); \
7812 TCGv_i64 xal = tcg_temp_new_i64(); \
7813 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7814 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7815 tcg_gen_and_i64(xah, xah, sgm); \
7816 tcg_gen_and_i64(xal, xal, sgm); \
7817 tcg_gen_andc_i64(xbh, xbh, sgm); \
7818 tcg_gen_andc_i64(xbl, xbl, sgm); \
7819 tcg_gen_or_i64(xbh, xbh, xah); \
7820 tcg_gen_or_i64(xbl, xbl, xal); \
7821 tcg_temp_free_i64(xah); \
7822 tcg_temp_free_i64(xal); \
7823 break; \
7824 } \
7825 } \
7826 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7827 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7828 tcg_temp_free_i64(xbh); \
7829 tcg_temp_free_i64(xbl); \
7830 tcg_temp_free_i64(sgm); \
7831 }
7832
7833 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7834 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7835 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7836 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7837 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7838 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7839 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7840 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7841
7842 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7843 static void gen_##name(DisasContext * ctx) \
7844 { \
7845 TCGv_i32 opc; \
7846 if (unlikely(!ctx->vsx_enabled)) { \
7847 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7848 return; \
7849 } \
7850 /* NIP cannot be restored if the memory exception comes from an helper */ \
7851 gen_update_nip(ctx, ctx->nip - 4); \
7852 opc = tcg_const_i32(ctx->opcode); \
7853 gen_helper_##name(cpu_env, opc); \
7854 tcg_temp_free_i32(opc); \
7855 }
7856
7857 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7858 static void gen_##name(DisasContext * ctx) \
7859 { \
7860 if (unlikely(!ctx->vsx_enabled)) { \
7861 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7862 return; \
7863 } \
7864 /* NIP cannot be restored if the exception comes */ \
7865 /* from a helper. */ \
7866 gen_update_nip(ctx, ctx->nip - 4); \
7867 \
7868 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7869 cpu_vsrh(xB(ctx->opcode))); \
7870 }
7871
7872 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7873 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7874 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7875 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7876 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7877 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7878 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7879 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7880 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7881 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7882 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7883 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7884 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7885 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7886 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7887 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7888 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7889 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7891 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7895 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7896 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7897 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7898 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7899 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7900 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7901 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7902 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7903 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7904 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7905 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7906 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7907 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7908 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7909
7910 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7911 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7912 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7913 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7914 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7915 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7916 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7917 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7918 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7919 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7920 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7921 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7922 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7923 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7924 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7925 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7926 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7927
7928 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7929 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7930 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7931 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7932 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7933 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7934 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7935 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7964
7965 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8001
8002 #define VSX_LOGICAL(name, tcg_op) \
8003 static void glue(gen_, name)(DisasContext * ctx) \
8004 { \
8005 if (unlikely(!ctx->vsx_enabled)) { \
8006 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8007 return; \
8008 } \
8009 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8010 cpu_vsrh(xB(ctx->opcode))); \
8011 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8012 cpu_vsrl(xB(ctx->opcode))); \
8013 }
8014
8015 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8016 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8017 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8018 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8019 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8020 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8021 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8022 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8023
8024 #define VSX_XXMRG(name, high) \
8025 static void glue(gen_, name)(DisasContext * ctx) \
8026 { \
8027 TCGv_i64 a0, a1, b0, b1; \
8028 if (unlikely(!ctx->vsx_enabled)) { \
8029 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8030 return; \
8031 } \
8032 a0 = tcg_temp_new_i64(); \
8033 a1 = tcg_temp_new_i64(); \
8034 b0 = tcg_temp_new_i64(); \
8035 b1 = tcg_temp_new_i64(); \
8036 if (high) { \
8037 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8038 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8039 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8040 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8041 } else { \
8042 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8043 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8044 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8045 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8046 } \
8047 tcg_gen_shri_i64(a0, a0, 32); \
8048 tcg_gen_shri_i64(b0, b0, 32); \
8049 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8050 b0, a0, 32, 32); \
8051 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8052 b1, a1, 32, 32); \
8053 tcg_temp_free_i64(a0); \
8054 tcg_temp_free_i64(a1); \
8055 tcg_temp_free_i64(b0); \
8056 tcg_temp_free_i64(b1); \
8057 }
8058
8059 VSX_XXMRG(xxmrghw, 1)
8060 VSX_XXMRG(xxmrglw, 0)
8061
8062 static void gen_xxsel(DisasContext * ctx)
8063 {
8064 TCGv_i64 a, b, c;
8065 if (unlikely(!ctx->vsx_enabled)) {
8066 gen_exception(ctx, POWERPC_EXCP_VSXU);
8067 return;
8068 }
8069 a = tcg_temp_new_i64();
8070 b = tcg_temp_new_i64();
8071 c = tcg_temp_new_i64();
8072
8073 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8074 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8075 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8076
8077 tcg_gen_and_i64(b, b, c);
8078 tcg_gen_andc_i64(a, a, c);
8079 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8080
8081 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8082 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8083 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8084
8085 tcg_gen_and_i64(b, b, c);
8086 tcg_gen_andc_i64(a, a, c);
8087 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8088
8089 tcg_temp_free_i64(a);
8090 tcg_temp_free_i64(b);
8091 tcg_temp_free_i64(c);
8092 }
8093
8094 static void gen_xxspltw(DisasContext *ctx)
8095 {
8096 TCGv_i64 b, b2;
8097 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8098 cpu_vsrl(xB(ctx->opcode)) :
8099 cpu_vsrh(xB(ctx->opcode));
8100
8101 if (unlikely(!ctx->vsx_enabled)) {
8102 gen_exception(ctx, POWERPC_EXCP_VSXU);
8103 return;
8104 }
8105
8106 b = tcg_temp_new_i64();
8107 b2 = tcg_temp_new_i64();
8108
8109 if (UIM(ctx->opcode) & 1) {
8110 tcg_gen_ext32u_i64(b, vsr);
8111 } else {
8112 tcg_gen_shri_i64(b, vsr, 32);
8113 }
8114
8115 tcg_gen_shli_i64(b2, b, 32);
8116 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8117 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8118
8119 tcg_temp_free_i64(b);
8120 tcg_temp_free_i64(b2);
8121 }
8122
8123 static void gen_xxsldwi(DisasContext *ctx)
8124 {
8125 TCGv_i64 xth, xtl;
8126 if (unlikely(!ctx->vsx_enabled)) {
8127 gen_exception(ctx, POWERPC_EXCP_VSXU);
8128 return;
8129 }
8130 xth = tcg_temp_new_i64();
8131 xtl = tcg_temp_new_i64();
8132
8133 switch (SHW(ctx->opcode)) {
8134 case 0: {
8135 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8136 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8137 break;
8138 }
8139 case 1: {
8140 TCGv_i64 t0 = tcg_temp_new_i64();
8141 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8142 tcg_gen_shli_i64(xth, xth, 32);
8143 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8144 tcg_gen_shri_i64(t0, t0, 32);
8145 tcg_gen_or_i64(xth, xth, t0);
8146 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8147 tcg_gen_shli_i64(xtl, xtl, 32);
8148 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8149 tcg_gen_shri_i64(t0, t0, 32);
8150 tcg_gen_or_i64(xtl, xtl, t0);
8151 tcg_temp_free_i64(t0);
8152 break;
8153 }
8154 case 2: {
8155 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8156 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8157 break;
8158 }
8159 case 3: {
8160 TCGv_i64 t0 = tcg_temp_new_i64();
8161 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8162 tcg_gen_shli_i64(xth, xth, 32);
8163 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8164 tcg_gen_shri_i64(t0, t0, 32);
8165 tcg_gen_or_i64(xth, xth, t0);
8166 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8167 tcg_gen_shli_i64(xtl, xtl, 32);
8168 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8169 tcg_gen_shri_i64(t0, t0, 32);
8170 tcg_gen_or_i64(xtl, xtl, t0);
8171 tcg_temp_free_i64(t0);
8172 break;
8173 }
8174 }
8175
8176 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8177 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8178
8179 tcg_temp_free_i64(xth);
8180 tcg_temp_free_i64(xtl);
8181 }
8182
8183
8184 /*** SPE extension ***/
8185 /* Register moves */
8186
8187 static inline void gen_evmra(DisasContext *ctx)
8188 {
8189
8190 if (unlikely(!ctx->spe_enabled)) {
8191 gen_exception(ctx, POWERPC_EXCP_SPEU);
8192 return;
8193 }
8194
8195 #if defined(TARGET_PPC64)
8196 /* rD := rA */
8197 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8198
8199 /* spe_acc := rA */
8200 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
8201 cpu_env,
8202 offsetof(CPUPPCState, spe_acc));
8203 #else
8204 TCGv_i64 tmp = tcg_temp_new_i64();
8205
8206 /* tmp := rA_lo + rA_hi << 32 */
8207 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8208
8209 /* spe_acc := tmp */
8210 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8211 tcg_temp_free_i64(tmp);
8212
8213 /* rD := rA */
8214 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8215 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8216 #endif
8217 }
8218
8219 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8220 {
8221 #if defined(TARGET_PPC64)
8222 tcg_gen_mov_i64(t, cpu_gpr[reg]);
8223 #else
8224 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8225 #endif
8226 }
8227
8228 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8229 {
8230 #if defined(TARGET_PPC64)
8231 tcg_gen_mov_i64(cpu_gpr[reg], t);
8232 #else
8233 TCGv_i64 tmp = tcg_temp_new_i64();
8234 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
8235 tcg_gen_shri_i64(tmp, t, 32);
8236 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
8237 tcg_temp_free_i64(tmp);
8238 #endif
8239 }
8240
8241 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8242 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8243 { \
8244 if (Rc(ctx->opcode)) \
8245 gen_##name1(ctx); \
8246 else \
8247 gen_##name0(ctx); \
8248 }
8249
8250 /* Handler for undefined SPE opcodes */
8251 static inline void gen_speundef(DisasContext *ctx)
8252 {
8253 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8254 }
8255
8256 /* SPE logic */
8257 #if defined(TARGET_PPC64)
8258 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8259 static inline void gen_##name(DisasContext *ctx) \
8260 { \
8261 if (unlikely(!ctx->spe_enabled)) { \
8262 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8263 return; \
8264 } \
8265 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8266 cpu_gpr[rB(ctx->opcode)]); \
8267 }
8268 #else
8269 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8270 static inline void gen_##name(DisasContext *ctx) \
8271 { \
8272 if (unlikely(!ctx->spe_enabled)) { \
8273 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8274 return; \
8275 } \
8276 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8277 cpu_gpr[rB(ctx->opcode)]); \
8278 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8279 cpu_gprh[rB(ctx->opcode)]); \
8280 }
8281 #endif
8282
8283 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8284 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8285 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8286 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8287 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8288 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8289 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8290 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8291
8292 /* SPE logic immediate */
8293 #if defined(TARGET_PPC64)
8294 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8295 static inline void gen_##name(DisasContext *ctx) \
8296 { \
8297 if (unlikely(!ctx->spe_enabled)) { \
8298 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8299 return; \
8300 } \
8301 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8302 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8303 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8304 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8305 tcg_opi(t0, t0, rB(ctx->opcode)); \
8306 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8307 tcg_gen_trunc_i64_i32(t1, t2); \
8308 tcg_temp_free_i64(t2); \
8309 tcg_opi(t1, t1, rB(ctx->opcode)); \
8310 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8311 tcg_temp_free_i32(t0); \
8312 tcg_temp_free_i32(t1); \
8313 }
8314 #else
8315 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8316 static inline void gen_##name(DisasContext *ctx) \
8317 { \
8318 if (unlikely(!ctx->spe_enabled)) { \
8319 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8320 return; \
8321 } \
8322 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8323 rB(ctx->opcode)); \
8324 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8325 rB(ctx->opcode)); \
8326 }
8327 #endif
8328 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8329 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8330 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8331 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8332
8333 /* SPE arithmetic */
8334 #if defined(TARGET_PPC64)
8335 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8336 static inline void gen_##name(DisasContext *ctx) \
8337 { \
8338 if (unlikely(!ctx->spe_enabled)) { \
8339 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8340 return; \
8341 } \
8342 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8343 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8344 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8345 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8346 tcg_op(t0, t0); \
8347 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8348 tcg_gen_trunc_i64_i32(t1, t2); \
8349 tcg_temp_free_i64(t2); \
8350 tcg_op(t1, t1); \
8351 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8352 tcg_temp_free_i32(t0); \
8353 tcg_temp_free_i32(t1); \
8354 }
8355 #else
8356 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8357 static inline void gen_##name(DisasContext *ctx) \
8358 { \
8359 if (unlikely(!ctx->spe_enabled)) { \
8360 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8361 return; \
8362 } \
8363 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8364 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8365 }
8366 #endif
8367
8368 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8369 {
8370 int l1 = gen_new_label();
8371 int l2 = gen_new_label();
8372
8373 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8374 tcg_gen_neg_i32(ret, arg1);
8375 tcg_gen_br(l2);
8376 gen_set_label(l1);
8377 tcg_gen_mov_i32(ret, arg1);
8378 gen_set_label(l2);
8379 }
8380 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8381 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8382 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8383 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8384 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8385 {
8386 tcg_gen_addi_i32(ret, arg1, 0x8000);
8387 tcg_gen_ext16u_i32(ret, ret);
8388 }
8389 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8390 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8391 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8392
8393 #if defined(TARGET_PPC64)
8394 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8395 static inline void gen_##name(DisasContext *ctx) \
8396 { \
8397 if (unlikely(!ctx->spe_enabled)) { \
8398 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8399 return; \
8400 } \
8401 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8402 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8403 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
8404 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
8405 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8406 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8407 tcg_op(t0, t0, t2); \
8408 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8409 tcg_gen_trunc_i64_i32(t1, t3); \
8410 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8411 tcg_gen_trunc_i64_i32(t2, t3); \
8412 tcg_temp_free_i64(t3); \
8413 tcg_op(t1, t1, t2); \
8414 tcg_temp_free_i32(t2); \
8415 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8416 tcg_temp_free_i32(t0); \
8417 tcg_temp_free_i32(t1); \
8418 }
8419 #else
8420 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8421 static inline void gen_##name(DisasContext *ctx) \
8422 { \
8423 if (unlikely(!ctx->spe_enabled)) { \
8424 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8425 return; \
8426 } \
8427 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8428 cpu_gpr[rB(ctx->opcode)]); \
8429 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8430 cpu_gprh[rB(ctx->opcode)]); \
8431 }
8432 #endif
8433
8434 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8435 {
8436 TCGv_i32 t0;
8437 int l1, l2;
8438
8439 l1 = gen_new_label();
8440 l2 = gen_new_label();
8441 t0 = tcg_temp_local_new_i32();
8442 /* No error here: 6 bits are used */
8443 tcg_gen_andi_i32(t0, arg2, 0x3F);
8444 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8445 tcg_gen_shr_i32(ret, arg1, t0);
8446 tcg_gen_br(l2);
8447 gen_set_label(l1);
8448 tcg_gen_movi_i32(ret, 0);
8449 gen_set_label(l2);
8450 tcg_temp_free_i32(t0);
8451 }
8452 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8453 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8454 {
8455 TCGv_i32 t0;
8456 int l1, l2;
8457
8458 l1 = gen_new_label();
8459 l2 = gen_new_label();
8460 t0 = tcg_temp_local_new_i32();
8461 /* No error here: 6 bits are used */
8462 tcg_gen_andi_i32(t0, arg2, 0x3F);
8463 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8464 tcg_gen_sar_i32(ret, arg1, t0);
8465 tcg_gen_br(l2);
8466 gen_set_label(l1);
8467 tcg_gen_movi_i32(ret, 0);
8468 gen_set_label(l2);
8469 tcg_temp_free_i32(t0);
8470 }
8471 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8472 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8473 {
8474 TCGv_i32 t0;
8475 int l1, l2;
8476
8477 l1 = gen_new_label();
8478 l2 = gen_new_label();
8479 t0 = tcg_temp_local_new_i32();
8480 /* No error here: 6 bits are used */
8481 tcg_gen_andi_i32(t0, arg2, 0x3F);
8482 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8483 tcg_gen_shl_i32(ret, arg1, t0);
8484 tcg_gen_br(l2);
8485 gen_set_label(l1);
8486 tcg_gen_movi_i32(ret, 0);
8487 gen_set_label(l2);
8488 tcg_temp_free_i32(t0);
8489 }
8490 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8491 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8492 {
8493 TCGv_i32 t0 = tcg_temp_new_i32();
8494 tcg_gen_andi_i32(t0, arg2, 0x1F);
8495 tcg_gen_rotl_i32(ret, arg1, t0);
8496 tcg_temp_free_i32(t0);
8497 }
8498 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8499 static inline void gen_evmergehi(DisasContext *ctx)
8500 {
8501 if (unlikely(!ctx->spe_enabled)) {
8502 gen_exception(ctx, POWERPC_EXCP_SPEU);
8503 return;
8504 }
8505 #if defined(TARGET_PPC64)
8506 TCGv t0 = tcg_temp_new();
8507 TCGv t1 = tcg_temp_new();
8508 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8509 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8510 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8511 tcg_temp_free(t0);
8512 tcg_temp_free(t1);
8513 #else
8514 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8515 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8516 #endif
8517 }
8518 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8519 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8520 {
8521 tcg_gen_sub_i32(ret, arg2, arg1);
8522 }
8523 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8524
8525 /* SPE arithmetic immediate */
8526 #if defined(TARGET_PPC64)
8527 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8528 static inline void gen_##name(DisasContext *ctx) \
8529 { \
8530 if (unlikely(!ctx->spe_enabled)) { \
8531 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8532 return; \
8533 } \
8534 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8535 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8536 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8537 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8538 tcg_op(t0, t0, rA(ctx->opcode)); \
8539 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8540 tcg_gen_trunc_i64_i32(t1, t2); \
8541 tcg_temp_free_i64(t2); \
8542 tcg_op(t1, t1, rA(ctx->opcode)); \
8543 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8544 tcg_temp_free_i32(t0); \
8545 tcg_temp_free_i32(t1); \
8546 }
8547 #else
8548 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8549 static inline void gen_##name(DisasContext *ctx) \
8550 { \
8551 if (unlikely(!ctx->spe_enabled)) { \
8552 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8553 return; \
8554 } \
8555 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8556 rA(ctx->opcode)); \
8557 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8558 rA(ctx->opcode)); \
8559 }
8560 #endif
8561 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8562 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8563
8564 /* SPE comparison */
8565 #if defined(TARGET_PPC64)
8566 #define GEN_SPEOP_COMP(name, tcg_cond) \
8567 static inline void gen_##name(DisasContext *ctx) \
8568 { \
8569 if (unlikely(!ctx->spe_enabled)) { \
8570 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8571 return; \
8572 } \
8573 int l1 = gen_new_label(); \
8574 int l2 = gen_new_label(); \
8575 int l3 = gen_new_label(); \
8576 int l4 = gen_new_label(); \
8577 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8578 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8579 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8580 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8581 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8582 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8583 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8584 tcg_gen_br(l2); \
8585 gen_set_label(l1); \
8586 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8587 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8588 gen_set_label(l2); \
8589 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8590 tcg_gen_trunc_i64_i32(t0, t2); \
8591 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8592 tcg_gen_trunc_i64_i32(t1, t2); \
8593 tcg_temp_free_i64(t2); \
8594 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8595 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8596 ~(CRF_CH | CRF_CH_AND_CL)); \
8597 tcg_gen_br(l4); \
8598 gen_set_label(l3); \
8599 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8600 CRF_CH | CRF_CH_OR_CL); \
8601 gen_set_label(l4); \
8602 tcg_temp_free_i32(t0); \
8603 tcg_temp_free_i32(t1); \
8604 }
8605 #else
8606 #define GEN_SPEOP_COMP(name, tcg_cond) \
8607 static inline void gen_##name(DisasContext *ctx) \
8608 { \
8609 if (unlikely(!ctx->spe_enabled)) { \
8610 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8611 return; \
8612 } \
8613 int l1 = gen_new_label(); \
8614 int l2 = gen_new_label(); \
8615 int l3 = gen_new_label(); \
8616 int l4 = gen_new_label(); \
8617 \
8618 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8619 cpu_gpr[rB(ctx->opcode)], l1); \
8620 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8621 tcg_gen_br(l2); \
8622 gen_set_label(l1); \
8623 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8624 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8625 gen_set_label(l2); \
8626 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8627 cpu_gprh[rB(ctx->opcode)], l3); \
8628 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8629 ~(CRF_CH | CRF_CH_AND_CL)); \
8630 tcg_gen_br(l4); \
8631 gen_set_label(l3); \
8632 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8633 CRF_CH | CRF_CH_OR_CL); \
8634 gen_set_label(l4); \
8635 }
8636 #endif
8637 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8638 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8639 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8640 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8641 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8642
8643 /* SPE misc */
8644 static inline void gen_brinc(DisasContext *ctx)
8645 {
8646 /* Note: brinc is usable even if SPE is disabled */
8647 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8648 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8649 }
8650 static inline void gen_evmergelo(DisasContext *ctx)
8651 {
8652 if (unlikely(!ctx->spe_enabled)) {
8653 gen_exception(ctx, POWERPC_EXCP_SPEU);
8654 return;
8655 }
8656 #if defined(TARGET_PPC64)
8657 TCGv t0 = tcg_temp_new();
8658 TCGv t1 = tcg_temp_new();
8659 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8660 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8661 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8662 tcg_temp_free(t0);
8663 tcg_temp_free(t1);
8664 #else
8665 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8666 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8667 #endif
8668 }
8669 static inline void gen_evmergehilo(DisasContext *ctx)
8670 {
8671 if (unlikely(!ctx->spe_enabled)) {
8672 gen_exception(ctx, POWERPC_EXCP_SPEU);
8673 return;
8674 }
8675 #if defined(TARGET_PPC64)
8676 TCGv t0 = tcg_temp_new();
8677 TCGv t1 = tcg_temp_new();
8678 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8679 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8680 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8681 tcg_temp_free(t0);
8682 tcg_temp_free(t1);
8683 #else
8684 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8685 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8686 #endif
8687 }
8688 static inline void gen_evmergelohi(DisasContext *ctx)
8689 {
8690 if (unlikely(!ctx->spe_enabled)) {
8691 gen_exception(ctx, POWERPC_EXCP_SPEU);
8692 return;
8693 }
8694 #if defined(TARGET_PPC64)
8695 TCGv t0 = tcg_temp_new();
8696 TCGv t1 = tcg_temp_new();
8697 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8698 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8699 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8700 tcg_temp_free(t0);
8701 tcg_temp_free(t1);
8702 #else
8703 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8704 TCGv_i32 tmp = tcg_temp_new_i32();
8705 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8706 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8707 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8708 tcg_temp_free_i32(tmp);
8709 } else {
8710 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8711 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8712 }
8713 #endif
8714 }
8715 static inline void gen_evsplati(DisasContext *ctx)
8716 {
8717 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8718
8719 #if defined(TARGET_PPC64)
8720 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8721 #else
8722 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8723 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8724 #endif
8725 }
8726 static inline void gen_evsplatfi(DisasContext *ctx)
8727 {
8728 uint64_t imm = rA(ctx->opcode) << 27;
8729
8730 #if defined(TARGET_PPC64)
8731 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8732 #else
8733 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8734 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8735 #endif
8736 }
8737
8738 static inline void gen_evsel(DisasContext *ctx)
8739 {
8740 int l1 = gen_new_label();
8741 int l2 = gen_new_label();
8742 int l3 = gen_new_label();
8743 int l4 = gen_new_label();
8744 TCGv_i32 t0 = tcg_temp_local_new_i32();
8745 #if defined(TARGET_PPC64)
8746 TCGv t1 = tcg_temp_local_new();
8747 TCGv t2 = tcg_temp_local_new();
8748 #endif
8749 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8750 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8751 #if defined(TARGET_PPC64)
8752 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8753 #else
8754 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8755 #endif
8756 tcg_gen_br(l2);
8757 gen_set_label(l1);
8758 #if defined(TARGET_PPC64)
8759 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8760 #else
8761 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8762 #endif
8763 gen_set_label(l2);
8764 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8765 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8766 #if defined(TARGET_PPC64)
8767 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8768 #else
8769 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8770 #endif
8771 tcg_gen_br(l4);
8772 gen_set_label(l3);
8773 #if defined(TARGET_PPC64)
8774 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8775 #else
8776 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8777 #endif
8778 gen_set_label(l4);
8779 tcg_temp_free_i32(t0);
8780 #if defined(TARGET_PPC64)
8781 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8782 tcg_temp_free(t1);
8783 tcg_temp_free(t2);
8784 #endif
8785 }
8786
8787 static void gen_evsel0(DisasContext *ctx)
8788 {
8789 gen_evsel(ctx);
8790 }
8791
8792 static void gen_evsel1(DisasContext *ctx)
8793 {
8794 gen_evsel(ctx);
8795 }
8796
8797 static void gen_evsel2(DisasContext *ctx)
8798 {
8799 gen_evsel(ctx);
8800 }
8801
8802 static void gen_evsel3(DisasContext *ctx)
8803 {
8804 gen_evsel(ctx);
8805 }
8806
8807 /* Multiply */
8808
8809 static inline void gen_evmwumi(DisasContext *ctx)
8810 {
8811 TCGv_i64 t0, t1;
8812
8813 if (unlikely(!ctx->spe_enabled)) {
8814 gen_exception(ctx, POWERPC_EXCP_SPEU);
8815 return;
8816 }
8817
8818 t0 = tcg_temp_new_i64();
8819 t1 = tcg_temp_new_i64();
8820
8821 /* t0 := rA; t1 := rB */
8822 #if defined(TARGET_PPC64)
8823 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8824 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8825 #else
8826 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8827 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8828 #endif
8829
8830 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8831
8832 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8833
8834 tcg_temp_free_i64(t0);
8835 tcg_temp_free_i64(t1);
8836 }
8837
8838 static inline void gen_evmwumia(DisasContext *ctx)
8839 {
8840 TCGv_i64 tmp;
8841
8842 if (unlikely(!ctx->spe_enabled)) {
8843 gen_exception(ctx, POWERPC_EXCP_SPEU);
8844 return;
8845 }
8846
8847 gen_evmwumi(ctx); /* rD := rA * rB */
8848
8849 tmp = tcg_temp_new_i64();
8850
8851 /* acc := rD */
8852 gen_load_gpr64(tmp, rD(ctx->opcode));
8853 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8854 tcg_temp_free_i64(tmp);
8855 }
8856
8857 static inline void gen_evmwumiaa(DisasContext *ctx)
8858 {
8859 TCGv_i64 acc;
8860 TCGv_i64 tmp;
8861
8862 if (unlikely(!ctx->spe_enabled)) {
8863 gen_exception(ctx, POWERPC_EXCP_SPEU);
8864 return;
8865 }
8866
8867 gen_evmwumi(ctx); /* rD := rA * rB */
8868
8869 acc = tcg_temp_new_i64();
8870 tmp = tcg_temp_new_i64();
8871
8872 /* tmp := rD */
8873 gen_load_gpr64(tmp, rD(ctx->opcode));
8874
8875 /* Load acc */
8876 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8877
8878 /* acc := tmp + acc */
8879 tcg_gen_add_i64(acc, acc, tmp);
8880
8881 /* Store acc */
8882 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8883
8884 /* rD := acc */
8885 gen_store_gpr64(rD(ctx->opcode), acc);
8886
8887 tcg_temp_free_i64(acc);
8888 tcg_temp_free_i64(tmp);
8889 }
8890
8891 static inline void gen_evmwsmi(DisasContext *ctx)
8892 {
8893 TCGv_i64 t0, t1;
8894
8895 if (unlikely(!ctx->spe_enabled)) {
8896 gen_exception(ctx, POWERPC_EXCP_SPEU);
8897 return;
8898 }
8899
8900 t0 = tcg_temp_new_i64();
8901 t1 = tcg_temp_new_i64();
8902
8903 /* t0 := rA; t1 := rB */
8904 #if defined(TARGET_PPC64)
8905 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8906 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8907 #else
8908 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8909 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8910 #endif
8911
8912 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8913
8914 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8915
8916 tcg_temp_free_i64(t0);
8917 tcg_temp_free_i64(t1);
8918 }
8919
8920 static inline void gen_evmwsmia(DisasContext *ctx)
8921 {
8922 TCGv_i64 tmp;
8923
8924 gen_evmwsmi(ctx); /* rD := rA * rB */
8925
8926 tmp = tcg_temp_new_i64();
8927
8928 /* acc := rD */
8929 gen_load_gpr64(tmp, rD(ctx->opcode));
8930 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8931
8932 tcg_temp_free_i64(tmp);
8933 }
8934
8935 static inline void gen_evmwsmiaa(DisasContext *ctx)
8936 {
8937 TCGv_i64 acc = tcg_temp_new_i64();
8938 TCGv_i64 tmp = tcg_temp_new_i64();
8939
8940 gen_evmwsmi(ctx); /* rD := rA * rB */
8941
8942 acc = tcg_temp_new_i64();
8943 tmp = tcg_temp_new_i64();
8944
8945 /* tmp := rD */
8946 gen_load_gpr64(tmp, rD(ctx->opcode));
8947
8948 /* Load acc */
8949 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8950
8951 /* acc := tmp + acc */
8952 tcg_gen_add_i64(acc, acc, tmp);
8953
8954 /* Store acc */
8955 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8956
8957 /* rD := acc */
8958 gen_store_gpr64(rD(ctx->opcode), acc);
8959
8960 tcg_temp_free_i64(acc);
8961 tcg_temp_free_i64(tmp);
8962 }
8963
8964 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8965 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8966 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8967 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8968 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8969 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8970 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8971 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8972 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8973 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8974 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8975 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8976 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8977 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8978 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8979 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8980 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8981 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8982 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8983 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8984 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8985 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8986 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8987 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8988 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8989 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8990 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8991 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8992 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8993
8994 /* SPE load and stores */
8995 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8996 {
8997 target_ulong uimm = rB(ctx->opcode);
8998
8999 if (rA(ctx->opcode) == 0) {
9000 tcg_gen_movi_tl(EA, uimm << sh);
9001 } else {
9002 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9003 if (NARROW_MODE(ctx)) {
9004 tcg_gen_ext32u_tl(EA, EA);
9005 }
9006 }
9007 }
9008
9009 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9010 {
9011 #if defined(TARGET_PPC64)
9012 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9013 #else
9014 TCGv_i64 t0 = tcg_temp_new_i64();
9015 gen_qemu_ld64(ctx, t0, addr);
9016 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
9017 tcg_gen_shri_i64(t0, t0, 32);
9018 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
9019 tcg_temp_free_i64(t0);
9020 #endif
9021 }
9022
9023 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9024 {
9025 #if defined(TARGET_PPC64)
9026 TCGv t0 = tcg_temp_new();
9027 gen_qemu_ld32u(ctx, t0, addr);
9028 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9029 gen_addr_add(ctx, addr, addr, 4);
9030 gen_qemu_ld32u(ctx, t0, addr);
9031 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9032 tcg_temp_free(t0);
9033 #else
9034 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9035 gen_addr_add(ctx, addr, addr, 4);
9036 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9037 #endif
9038 }
9039
9040 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9041 {
9042 TCGv t0 = tcg_temp_new();
9043 #if defined(TARGET_PPC64)
9044 gen_qemu_ld16u(ctx, t0, addr);
9045 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9046 gen_addr_add(ctx, addr, addr, 2);
9047 gen_qemu_ld16u(ctx, t0, addr);
9048 tcg_gen_shli_tl(t0, t0, 32);
9049 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9050 gen_addr_add(ctx, addr, addr, 2);
9051 gen_qemu_ld16u(ctx, t0, addr);
9052 tcg_gen_shli_tl(t0, t0, 16);
9053 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9054 gen_addr_add(ctx, addr, addr, 2);
9055 gen_qemu_ld16u(ctx, t0, addr);
9056 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9057 #else
9058 gen_qemu_ld16u(ctx, t0, addr);
9059 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9060 gen_addr_add(ctx, addr, addr, 2);
9061 gen_qemu_ld16u(ctx, t0, addr);
9062 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9063 gen_addr_add(ctx, addr, addr, 2);
9064 gen_qemu_ld16u(ctx, t0, addr);
9065 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9066 gen_addr_add(ctx, addr, addr, 2);
9067 gen_qemu_ld16u(ctx, t0, addr);
9068 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9069 #endif
9070 tcg_temp_free(t0);
9071 }
9072
9073 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9074 {
9075 TCGv t0 = tcg_temp_new();
9076 gen_qemu_ld16u(ctx, t0, addr);
9077 #if defined(TARGET_PPC64)
9078 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9079 tcg_gen_shli_tl(t0, t0, 16);
9080 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9081 #else
9082 tcg_gen_shli_tl(t0, t0, 16);
9083 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9084 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9085 #endif
9086 tcg_temp_free(t0);
9087 }
9088
9089 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9090 {
9091 TCGv t0 = tcg_temp_new();
9092 gen_qemu_ld16u(ctx, t0, addr);
9093 #if defined(TARGET_PPC64)
9094 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9095 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9096 #else
9097 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9098 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9099 #endif
9100 tcg_temp_free(t0);
9101 }
9102
9103 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9104 {
9105 TCGv t0 = tcg_temp_new();
9106 gen_qemu_ld16s(ctx, t0, addr);
9107 #if defined(TARGET_PPC64)
9108 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9109 tcg_gen_ext32u_tl(t0, t0);
9110 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9111 #else
9112 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9114 #endif
9115 tcg_temp_free(t0);
9116 }
9117
9118 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9119 {
9120 TCGv t0 = tcg_temp_new();
9121 #if defined(TARGET_PPC64)
9122 gen_qemu_ld16u(ctx, t0, addr);
9123 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9124 gen_addr_add(ctx, addr, addr, 2);
9125 gen_qemu_ld16u(ctx, t0, addr);
9126 tcg_gen_shli_tl(t0, t0, 16);
9127 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9128 #else
9129 gen_qemu_ld16u(ctx, t0, addr);
9130 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9131 gen_addr_add(ctx, addr, addr, 2);
9132 gen_qemu_ld16u(ctx, t0, addr);
9133 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9134 #endif
9135 tcg_temp_free(t0);
9136 }
9137
9138 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9139 {
9140 #if defined(TARGET_PPC64)
9141 TCGv t0 = tcg_temp_new();
9142 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9143 gen_addr_add(ctx, addr, addr, 2);
9144 gen_qemu_ld16u(ctx, t0, addr);
9145 tcg_gen_shli_tl(t0, t0, 32);
9146 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9147 tcg_temp_free(t0);
9148 #else
9149 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9150 gen_addr_add(ctx, addr, addr, 2);
9151 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9152 #endif
9153 }
9154
9155 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9156 {
9157 #if defined(TARGET_PPC64)
9158 TCGv t0 = tcg_temp_new();
9159 gen_qemu_ld16s(ctx, t0, addr);
9160 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
9161 gen_addr_add(ctx, addr, addr, 2);
9162 gen_qemu_ld16s(ctx, t0, addr);
9163 tcg_gen_shli_tl(t0, t0, 32);
9164 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9165 tcg_temp_free(t0);
9166 #else
9167 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9168 gen_addr_add(ctx, addr, addr, 2);
9169 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9170 #endif
9171 }
9172
9173 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9174 {
9175 TCGv t0 = tcg_temp_new();
9176 gen_qemu_ld32u(ctx, t0, addr);
9177 #if defined(TARGET_PPC64)
9178 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
9179 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9180 #else
9181 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9182 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9183 #endif
9184 tcg_temp_free(t0);
9185 }
9186
9187 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9188 {
9189 TCGv t0 = tcg_temp_new();
9190 #if defined(TARGET_PPC64)
9191 gen_qemu_ld16u(ctx, t0, addr);
9192 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
9193 tcg_gen_shli_tl(t0, t0, 32);
9194 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9195 gen_addr_add(ctx, addr, addr, 2);
9196 gen_qemu_ld16u(ctx, t0, addr);
9197 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9198 tcg_gen_shli_tl(t0, t0, 16);
9199 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9200 #else
9201 gen_qemu_ld16u(ctx, t0, addr);
9202 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9203 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9204 gen_addr_add(ctx, addr, addr, 2);
9205 gen_qemu_ld16u(ctx, t0, addr);
9206 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9207 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9208 #endif
9209 tcg_temp_free(t0);
9210 }
9211
9212 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9213 {
9214 #if defined(TARGET_PPC64)
9215 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9216 #else
9217 TCGv_i64 t0 = tcg_temp_new_i64();
9218 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
9219 gen_qemu_st64(ctx, t0, addr);
9220 tcg_temp_free_i64(t0);
9221 #endif
9222 }
9223
9224 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9225 {
9226 #if defined(TARGET_PPC64)
9227 TCGv t0 = tcg_temp_new();
9228 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9229 gen_qemu_st32(ctx, t0, addr);
9230 tcg_temp_free(t0);
9231 #else
9232 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9233 #endif
9234 gen_addr_add(ctx, addr, addr, 4);
9235 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9236 }
9237
9238 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9239 {
9240 TCGv t0 = tcg_temp_new();
9241 #if defined(TARGET_PPC64)
9242 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9243 #else
9244 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9245 #endif
9246 gen_qemu_st16(ctx, t0, addr);
9247 gen_addr_add(ctx, addr, addr, 2);
9248 #if defined(TARGET_PPC64)
9249 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9250 gen_qemu_st16(ctx, t0, addr);
9251 #else
9252 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9253 #endif
9254 gen_addr_add(ctx, addr, addr, 2);
9255 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9256 gen_qemu_st16(ctx, t0, addr);
9257 tcg_temp_free(t0);
9258 gen_addr_add(ctx, addr, addr, 2);
9259 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9260 }
9261
9262 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9263 {
9264 TCGv t0 = tcg_temp_new();
9265 #if defined(TARGET_PPC64)
9266 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
9267 #else
9268 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9269 #endif
9270 gen_qemu_st16(ctx, t0, addr);
9271 gen_addr_add(ctx, addr, addr, 2);
9272 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9273 gen_qemu_st16(ctx, t0, addr);
9274 tcg_temp_free(t0);
9275 }
9276
9277 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9278 {
9279 #if defined(TARGET_PPC64)
9280 TCGv t0 = tcg_temp_new();
9281 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9282 gen_qemu_st16(ctx, t0, addr);
9283 tcg_temp_free(t0);
9284 #else
9285 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9286 #endif
9287 gen_addr_add(ctx, addr, addr, 2);
9288 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9289 }
9290
9291 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9292 {
9293 #if defined(TARGET_PPC64)
9294 TCGv t0 = tcg_temp_new();
9295 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
9296 gen_qemu_st32(ctx, t0, addr);
9297 tcg_temp_free(t0);
9298 #else
9299 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9300 #endif
9301 }
9302
9303 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9304 {
9305 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9306 }
9307
9308 #define GEN_SPEOP_LDST(name, opc2, sh) \
9309 static void glue(gen_, name)(DisasContext *ctx) \
9310 { \
9311 TCGv t0; \
9312 if (unlikely(!ctx->spe_enabled)) { \
9313 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9314 return; \
9315 } \
9316 gen_set_access_type(ctx, ACCESS_INT); \
9317 t0 = tcg_temp_new(); \
9318 if (Rc(ctx->opcode)) { \
9319 gen_addr_spe_imm_index(ctx, t0, sh); \
9320 } else { \
9321 gen_addr_reg_index(ctx, t0); \
9322 } \
9323 gen_op_##name(ctx, t0); \
9324 tcg_temp_free(t0); \
9325 }
9326
9327 GEN_SPEOP_LDST(evldd, 0x00, 3);
9328 GEN_SPEOP_LDST(evldw, 0x01, 3);
9329 GEN_SPEOP_LDST(evldh, 0x02, 3);
9330 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9331 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9332 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9333 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9334 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9335 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9336 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9337 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9338
9339 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9340 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9341 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9342 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9343 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9344 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9345 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9346
9347 /* Multiply and add - TODO */
9348 #if 0
9349 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9350 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9351 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9352 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9353 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9354 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9355 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9356 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9357 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9358 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9359 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9360 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9361
9362 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9363 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9364 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9365 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9366 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9367 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9368 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9369 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9370 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9371 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9372 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9373 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9374
9375 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9376 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9377 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9378 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9379 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9380
9381 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9382 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9383 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9384 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9385 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9386 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9387 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9388 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9389 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9390 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9391 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9392 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9393
9394 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9395 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9396 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9397 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9398
9399 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9400 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9402 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9403 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9404 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9405 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9406 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9408 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9409 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9410 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9411
9412 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9413 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9414 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9415 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9416 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9417 #endif
9418
9419 /*** SPE floating-point extension ***/
9420 #if defined(TARGET_PPC64)
9421 #define GEN_SPEFPUOP_CONV_32_32(name) \
9422 static inline void gen_##name(DisasContext *ctx) \
9423 { \
9424 TCGv_i32 t0; \
9425 TCGv t1; \
9426 t0 = tcg_temp_new_i32(); \
9427 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9428 gen_helper_##name(t0, cpu_env, t0); \
9429 t1 = tcg_temp_new(); \
9430 tcg_gen_extu_i32_tl(t1, t0); \
9431 tcg_temp_free_i32(t0); \
9432 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9433 0xFFFFFFFF00000000ULL); \
9434 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9435 tcg_temp_free(t1); \
9436 }
9437 #define GEN_SPEFPUOP_CONV_32_64(name) \
9438 static inline void gen_##name(DisasContext *ctx) \
9439 { \
9440 TCGv_i32 t0; \
9441 TCGv t1; \
9442 t0 = tcg_temp_new_i32(); \
9443 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9444 t1 = tcg_temp_new(); \
9445 tcg_gen_extu_i32_tl(t1, t0); \
9446 tcg_temp_free_i32(t0); \
9447 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9448 0xFFFFFFFF00000000ULL); \
9449 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9450 tcg_temp_free(t1); \
9451 }
9452 #define GEN_SPEFPUOP_CONV_64_32(name) \
9453 static inline void gen_##name(DisasContext *ctx) \
9454 { \
9455 TCGv_i32 t0 = tcg_temp_new_i32(); \
9456 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9457 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9458 tcg_temp_free_i32(t0); \
9459 }
9460 #define GEN_SPEFPUOP_CONV_64_64(name) \
9461 static inline void gen_##name(DisasContext *ctx) \
9462 { \
9463 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9464 cpu_gpr[rB(ctx->opcode)]); \
9465 }
9466 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9467 static inline void gen_##name(DisasContext *ctx) \
9468 { \
9469 TCGv_i32 t0, t1; \
9470 TCGv_i64 t2; \
9471 if (unlikely(!ctx->spe_enabled)) { \
9472 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9473 return; \
9474 } \
9475 t0 = tcg_temp_new_i32(); \
9476 t1 = tcg_temp_new_i32(); \
9477 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9478 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9479 gen_helper_##name(t0, cpu_env, t0, t1); \
9480 tcg_temp_free_i32(t1); \
9481 t2 = tcg_temp_new(); \
9482 tcg_gen_extu_i32_tl(t2, t0); \
9483 tcg_temp_free_i32(t0); \
9484 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9485 0xFFFFFFFF00000000ULL); \
9486 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9487 tcg_temp_free(t2); \
9488 }
9489 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9490 static inline void gen_##name(DisasContext *ctx) \
9491 { \
9492 if (unlikely(!ctx->spe_enabled)) { \
9493 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9494 return; \
9495 } \
9496 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9497 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9498 }
9499 #define GEN_SPEFPUOP_COMP_32(name) \
9500 static inline void gen_##name(DisasContext *ctx) \
9501 { \
9502 TCGv_i32 t0, t1; \
9503 if (unlikely(!ctx->spe_enabled)) { \
9504 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9505 return; \
9506 } \
9507 t0 = tcg_temp_new_i32(); \
9508 t1 = tcg_temp_new_i32(); \
9509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9510 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9511 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9512 tcg_temp_free_i32(t0); \
9513 tcg_temp_free_i32(t1); \
9514 }
9515 #define GEN_SPEFPUOP_COMP_64(name) \
9516 static inline void gen_##name(DisasContext *ctx) \
9517 { \
9518 if (unlikely(!ctx->spe_enabled)) { \
9519 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9520 return; \
9521 } \
9522 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9523 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9524 }
9525 #else
9526 #define GEN_SPEFPUOP_CONV_32_32(name) \
9527 static inline void gen_##name(DisasContext *ctx) \
9528 { \
9529 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9530 cpu_gpr[rB(ctx->opcode)]); \
9531 }
9532 #define GEN_SPEFPUOP_CONV_32_64(name) \
9533 static inline void gen_##name(DisasContext *ctx) \
9534 { \
9535 TCGv_i64 t0 = tcg_temp_new_i64(); \
9536 gen_load_gpr64(t0, rB(ctx->opcode)); \
9537 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9538 tcg_temp_free_i64(t0); \
9539 }
9540 #define GEN_SPEFPUOP_CONV_64_32(name) \
9541 static inline void gen_##name(DisasContext *ctx) \
9542 { \
9543 TCGv_i64 t0 = tcg_temp_new_i64(); \
9544 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9545 gen_store_gpr64(rD(ctx->opcode), t0); \
9546 tcg_temp_free_i64(t0); \
9547 }
9548 #define GEN_SPEFPUOP_CONV_64_64(name) \
9549 static inline void gen_##name(DisasContext *ctx) \
9550 { \
9551 TCGv_i64 t0 = tcg_temp_new_i64(); \
9552 gen_load_gpr64(t0, rB(ctx->opcode)); \
9553 gen_helper_##name(t0, cpu_env, t0); \
9554 gen_store_gpr64(rD(ctx->opcode), t0); \
9555 tcg_temp_free_i64(t0); \
9556 }
9557 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9558 static inline void gen_##name(DisasContext *ctx) \
9559 { \
9560 if (unlikely(!ctx->spe_enabled)) { \
9561 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9562 return; \
9563 } \
9564 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9565 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9566 }
9567 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9568 static inline void gen_##name(DisasContext *ctx) \
9569 { \
9570 TCGv_i64 t0, t1; \
9571 if (unlikely(!ctx->spe_enabled)) { \
9572 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9573 return; \
9574 } \
9575 t0 = tcg_temp_new_i64(); \
9576 t1 = tcg_temp_new_i64(); \
9577 gen_load_gpr64(t0, rA(ctx->opcode)); \
9578 gen_load_gpr64(t1, rB(ctx->opcode)); \
9579 gen_helper_##name(t0, cpu_env, t0, t1); \
9580 gen_store_gpr64(rD(ctx->opcode), t0); \
9581 tcg_temp_free_i64(t0); \
9582 tcg_temp_free_i64(t1); \
9583 }
9584 #define GEN_SPEFPUOP_COMP_32(name) \
9585 static inline void gen_##name(DisasContext *ctx) \
9586 { \
9587 if (unlikely(!ctx->spe_enabled)) { \
9588 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9589 return; \
9590 } \
9591 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9592 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9593 }
9594 #define GEN_SPEFPUOP_COMP_64(name) \
9595 static inline void gen_##name(DisasContext *ctx) \
9596 { \
9597 TCGv_i64 t0, t1; \
9598 if (unlikely(!ctx->spe_enabled)) { \
9599 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9600 return; \
9601 } \
9602 t0 = tcg_temp_new_i64(); \
9603 t1 = tcg_temp_new_i64(); \
9604 gen_load_gpr64(t0, rA(ctx->opcode)); \
9605 gen_load_gpr64(t1, rB(ctx->opcode)); \
9606 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9607 tcg_temp_free_i64(t0); \
9608 tcg_temp_free_i64(t1); \
9609 }
9610 #endif
9611
9612 /* Single precision floating-point vectors operations */
9613 /* Arithmetic */
9614 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9615 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9616 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9617 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9618 static inline void gen_evfsabs(DisasContext *ctx)
9619 {
9620 if (unlikely(!ctx->spe_enabled)) {
9621 gen_exception(ctx, POWERPC_EXCP_SPEU);
9622 return;
9623 }
9624 #if defined(TARGET_PPC64)
9625 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9626 #else
9627 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9628 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9629 #endif
9630 }
9631 static inline void gen_evfsnabs(DisasContext *ctx)
9632 {
9633 if (unlikely(!ctx->spe_enabled)) {
9634 gen_exception(ctx, POWERPC_EXCP_SPEU);
9635 return;
9636 }
9637 #if defined(TARGET_PPC64)
9638 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9639 #else
9640 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9641 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9642 #endif
9643 }
9644 static inline void gen_evfsneg(DisasContext *ctx)
9645 {
9646 if (unlikely(!ctx->spe_enabled)) {
9647 gen_exception(ctx, POWERPC_EXCP_SPEU);
9648 return;
9649 }
9650 #if defined(TARGET_PPC64)
9651 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9652 #else
9653 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9654 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9655 #endif
9656 }
9657
9658 /* Conversion */
9659 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9660 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9661 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9662 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9663 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9664 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9665 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9666 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9667 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9668 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9669
9670 /* Comparison */
9671 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9672 GEN_SPEFPUOP_COMP_64(evfscmplt);
9673 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9674 GEN_SPEFPUOP_COMP_64(evfststgt);
9675 GEN_SPEFPUOP_COMP_64(evfststlt);
9676 GEN_SPEFPUOP_COMP_64(evfststeq);
9677
9678 /* Opcodes definitions */
9679 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9680 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9681 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9682 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9683 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9684 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9685 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9686 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9687 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9688 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9689 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9690 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9691 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9692 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9693
9694 /* Single precision floating-point operations */
9695 /* Arithmetic */
9696 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9697 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9698 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9699 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9700 static inline void gen_efsabs(DisasContext *ctx)
9701 {
9702 if (unlikely(!ctx->spe_enabled)) {
9703 gen_exception(ctx, POWERPC_EXCP_SPEU);
9704 return;
9705 }
9706 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9707 }
9708 static inline void gen_efsnabs(DisasContext *ctx)
9709 {
9710 if (unlikely(!ctx->spe_enabled)) {
9711 gen_exception(ctx, POWERPC_EXCP_SPEU);
9712 return;
9713 }
9714 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9715 }
9716 static inline void gen_efsneg(DisasContext *ctx)
9717 {
9718 if (unlikely(!ctx->spe_enabled)) {
9719 gen_exception(ctx, POWERPC_EXCP_SPEU);
9720 return;
9721 }
9722 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9723 }
9724
9725 /* Conversion */
9726 GEN_SPEFPUOP_CONV_32_32(efscfui);
9727 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9728 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9729 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9730 GEN_SPEFPUOP_CONV_32_32(efsctui);
9731 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9732 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9733 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9734 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9735 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9736 GEN_SPEFPUOP_CONV_32_64(efscfd);
9737
9738 /* Comparison */
9739 GEN_SPEFPUOP_COMP_32(efscmpgt);
9740 GEN_SPEFPUOP_COMP_32(efscmplt);
9741 GEN_SPEFPUOP_COMP_32(efscmpeq);
9742 GEN_SPEFPUOP_COMP_32(efststgt);
9743 GEN_SPEFPUOP_COMP_32(efststlt);
9744 GEN_SPEFPUOP_COMP_32(efststeq);
9745
9746 /* Opcodes definitions */
9747 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9748 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9749 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9750 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9751 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9752 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9753 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9754 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9755 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9756 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9757 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9758 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9759 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9760 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9761
9762 /* Double precision floating-point operations */
9763 /* Arithmetic */
9764 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9765 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9766 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9767 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9768 static inline void gen_efdabs(DisasContext *ctx)
9769 {
9770 if (unlikely(!ctx->spe_enabled)) {
9771 gen_exception(ctx, POWERPC_EXCP_SPEU);
9772 return;
9773 }
9774 #if defined(TARGET_PPC64)
9775 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9776 #else
9777 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9778 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9779 #endif
9780 }
9781 static inline void gen_efdnabs(DisasContext *ctx)
9782 {
9783 if (unlikely(!ctx->spe_enabled)) {
9784 gen_exception(ctx, POWERPC_EXCP_SPEU);
9785 return;
9786 }
9787 #if defined(TARGET_PPC64)
9788 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9789 #else
9790 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9791 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9792 #endif
9793 }
9794 static inline void gen_efdneg(DisasContext *ctx)
9795 {
9796 if (unlikely(!ctx->spe_enabled)) {
9797 gen_exception(ctx, POWERPC_EXCP_SPEU);
9798 return;
9799 }
9800 #if defined(TARGET_PPC64)
9801 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9802 #else
9803 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9804 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9805 #endif
9806 }
9807
9808 /* Conversion */
9809 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9810 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9811 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9812 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9813 GEN_SPEFPUOP_CONV_32_64(efdctui);
9814 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9815 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9816 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9817 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9818 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9819 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9820 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9821 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9822 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9823 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9824
9825 /* Comparison */
9826 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9827 GEN_SPEFPUOP_COMP_64(efdcmplt);
9828 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9829 GEN_SPEFPUOP_COMP_64(efdtstgt);
9830 GEN_SPEFPUOP_COMP_64(efdtstlt);
9831 GEN_SPEFPUOP_COMP_64(efdtsteq);
9832
9833 /* Opcodes definitions */
9834 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9835 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9836 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9837 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9838 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9839 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9840 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9841 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9842 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9843 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9844 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9845 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9846 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9847 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9848 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9849 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9850
9851 static opcode_t opcodes[] = {
9852 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9853 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9854 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9855 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9856 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9857 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9858 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9859 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9860 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9861 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9862 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9863 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9864 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9865 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9866 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9867 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9868 #if defined(TARGET_PPC64)
9869 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9870 #endif
9871 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9872 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9873 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9874 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9875 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9876 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9877 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9878 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9879 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9880 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9881 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9882 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9883 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9884 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9885 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9886 #if defined(TARGET_PPC64)
9887 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9888 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9889 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9890 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9891 #endif
9892 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9893 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9894 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9895 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9896 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9897 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9898 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9899 #if defined(TARGET_PPC64)
9900 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9901 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9902 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9903 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9904 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9905 #endif
9906 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9907 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9908 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9909 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9910 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9911 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9912 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9913 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9914 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9915 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9916 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9917 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9918 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9919 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9920 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9921 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9922 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9923 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9924 #if defined(TARGET_PPC64)
9925 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9926 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9927 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9928 #endif
9929 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9930 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9931 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9932 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9933 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9934 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9935 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9936 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9937 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9938 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9939 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9940 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9941 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9942 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9943 #if defined(TARGET_PPC64)
9944 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9945 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9946 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9947 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9948 #endif
9949 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9950 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9951 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9952 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9953 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9954 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9955 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9956 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9957 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9958 #if defined(TARGET_PPC64)
9959 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9960 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9961 #endif
9962 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9963 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9964 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9965 #if defined(TARGET_PPC64)
9966 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9967 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9968 #endif
9969 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9970 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9971 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9972 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9973 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9974 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9975 #if defined(TARGET_PPC64)
9976 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9977 #endif
9978 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9979 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9980 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9981 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9982 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9983 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9984 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9985 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9986 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9987 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9988 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9989 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9990 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9991 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9992 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9993 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9994 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9995 #if defined(TARGET_PPC64)
9996 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9997 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9998 PPC_SEGMENT_64B),
9999 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10000 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10001 PPC_SEGMENT_64B),
10002 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10003 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10004 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10005 #endif
10006 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10007 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
10008 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
10009 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10010 #if defined(TARGET_PPC64)
10011 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
10012 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10013 #endif
10014 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10015 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10016 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10017 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10018 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10019 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10020 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10021 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10022 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10023 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10024 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10025 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10026 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10027 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10028 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10029 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10030 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10031 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10032 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10033 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10034 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10035 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10036 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10037 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10038 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10039 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10040 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10041 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10042 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10043 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10044 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10045 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10046 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10047 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10048 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10049 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10050 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10051 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10052 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10053 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10054 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10055 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10056 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10057 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10058 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10059 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10060 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10061 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10062 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10063 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10064 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10065 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10066 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10067 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10068 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10069 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10070 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10071 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10072 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10073 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10074 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10075 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10076 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10077 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10078 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10079 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10080 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10081 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10082 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10083 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10084 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10085 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10086 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10087 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10088 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10089 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10090 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10091 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10092 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10093 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10094 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10095 PPC_NONE, PPC2_BOOKE206),
10096 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10097 PPC_NONE, PPC2_BOOKE206),
10098 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10099 PPC_NONE, PPC2_BOOKE206),
10100 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10101 PPC_NONE, PPC2_BOOKE206),
10102 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10103 PPC_NONE, PPC2_BOOKE206),
10104 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10105 PPC_NONE, PPC2_PRCNTL),
10106 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10107 PPC_NONE, PPC2_PRCNTL),
10108 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10109 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10110 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10111 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10112 PPC_BOOKE, PPC2_BOOKE206),
10113 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10114 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10115 PPC_BOOKE, PPC2_BOOKE206),
10116 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10117 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10118 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10119 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10120 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10121 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10122 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10123 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10124 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10125
10126 #undef GEN_INT_ARITH_ADD
10127 #undef GEN_INT_ARITH_ADD_CONST
10128 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10129 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10130 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10131 add_ca, compute_ca, compute_ov) \
10132 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10133 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10134 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10135 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10136 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10137 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10138 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10139 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10140 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10141 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10142 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10143
10144 #undef GEN_INT_ARITH_DIVW
10145 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10146 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10147 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10148 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10149 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10150 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10151 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10152 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10153 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10154 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10155
10156 #if defined(TARGET_PPC64)
10157 #undef GEN_INT_ARITH_DIVD
10158 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10159 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10160 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10161 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10162 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10163 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10164
10165 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10166 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10167 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10168 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10169
10170 #undef GEN_INT_ARITH_MUL_HELPER
10171 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10172 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10173 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10174 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10175 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10176 #endif
10177
10178 #undef GEN_INT_ARITH_SUBF
10179 #undef GEN_INT_ARITH_SUBF_CONST
10180 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10181 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10182 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10183 add_ca, compute_ca, compute_ov) \
10184 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10185 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10186 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10187 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10188 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10189 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10190 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10191 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10192 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10193 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10194 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10195
10196 #undef GEN_LOGICAL1
10197 #undef GEN_LOGICAL2
10198 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10199 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10200 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10201 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10202 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10203 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10204 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10205 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10206 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10207 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10208 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10209 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10210 #if defined(TARGET_PPC64)
10211 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10212 #endif
10213
10214 #if defined(TARGET_PPC64)
10215 #undef GEN_PPC64_R2
10216 #undef GEN_PPC64_R4
10217 #define GEN_PPC64_R2(name, opc1, opc2) \
10218 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10219 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10220 PPC_64B)
10221 #define GEN_PPC64_R4(name, opc1, opc2) \
10222 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10223 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10224 PPC_64B), \
10225 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10226 PPC_64B), \
10227 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10228 PPC_64B)
10229 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10230 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10231 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10232 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10233 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10234 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10235 #endif
10236
10237 #undef _GEN_FLOAT_ACB
10238 #undef GEN_FLOAT_ACB
10239 #undef _GEN_FLOAT_AB
10240 #undef GEN_FLOAT_AB
10241 #undef _GEN_FLOAT_AC
10242 #undef GEN_FLOAT_AC
10243 #undef GEN_FLOAT_B
10244 #undef GEN_FLOAT_BS
10245 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10246 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10247 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10248 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10249 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10250 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10251 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10252 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10253 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10254 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10255 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10256 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10257 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10258 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10259 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10260 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10261 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10262 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10263 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10264
10265 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10266 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10267 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10268 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10269 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10270 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10271 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10272 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10273 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10274 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10275 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10276 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10277 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10278 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10279 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10280 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10281 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10282 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10283 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10284 #if defined(TARGET_PPC64)
10285 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10286 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10287 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10288 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10289 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10290 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10291 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10292 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10293 #endif
10294 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10295 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10296 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10297 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10298
10299 #undef GEN_LD
10300 #undef GEN_LDU
10301 #undef GEN_LDUX
10302 #undef GEN_LDX_E
10303 #undef GEN_LDS
10304 #define GEN_LD(name, ldop, opc, type) \
10305 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10306 #define GEN_LDU(name, ldop, opc, type) \
10307 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10308 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10309 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10310 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10311 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10312 #define GEN_LDS(name, ldop, op, type) \
10313 GEN_LD(name, ldop, op | 0x20, type) \
10314 GEN_LDU(name, ldop, op | 0x21, type) \
10315 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10316 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10317
10318 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10319 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10320 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10321 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10322 #if defined(TARGET_PPC64)
10323 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10324 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10325 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10326 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10327 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10328 #endif
10329 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10330 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10331
10332 #undef GEN_ST
10333 #undef GEN_STU
10334 #undef GEN_STUX
10335 #undef GEN_STX_E
10336 #undef GEN_STS
10337 #define GEN_ST(name, stop, opc, type) \
10338 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10339 #define GEN_STU(name, stop, opc, type) \
10340 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10341 #define GEN_STUX(name, stop, opc2, opc3, type) \
10342 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10343 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10344 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10345 #define GEN_STS(name, stop, op, type) \
10346 GEN_ST(name, stop, op | 0x20, type) \
10347 GEN_STU(name, stop, op | 0x21, type) \
10348 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10349 GEN_STX(name, stop, 0x17, op | 0x00, type)
10350
10351 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10352 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10353 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10354 #if defined(TARGET_PPC64)
10355 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10356 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10357 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10358 #endif
10359 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10360 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10361
10362 #undef GEN_LDF
10363 #undef GEN_LDUF
10364 #undef GEN_LDUXF
10365 #undef GEN_LDXF
10366 #undef GEN_LDFS
10367 #define GEN_LDF(name, ldop, opc, type) \
10368 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10369 #define GEN_LDUF(name, ldop, opc, type) \
10370 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10371 #define GEN_LDUXF(name, ldop, opc, type) \
10372 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10373 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10374 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10375 #define GEN_LDFS(name, ldop, op, type) \
10376 GEN_LDF(name, ldop, op | 0x20, type) \
10377 GEN_LDUF(name, ldop, op | 0x21, type) \
10378 GEN_LDUXF(name, ldop, op | 0x01, type) \
10379 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10380
10381 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10382 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10383 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10384 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10385 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10386 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10387
10388 #undef GEN_STF
10389 #undef GEN_STUF
10390 #undef GEN_STUXF
10391 #undef GEN_STXF
10392 #undef GEN_STFS
10393 #define GEN_STF(name, stop, opc, type) \
10394 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10395 #define GEN_STUF(name, stop, opc, type) \
10396 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10397 #define GEN_STUXF(name, stop, opc, type) \
10398 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10399 #define GEN_STXF(name, stop, opc2, opc3, type) \
10400 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10401 #define GEN_STFS(name, stop, op, type) \
10402 GEN_STF(name, stop, op | 0x20, type) \
10403 GEN_STUF(name, stop, op | 0x21, type) \
10404 GEN_STUXF(name, stop, op | 0x01, type) \
10405 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10406
10407 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10408 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10409 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10410 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10411 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10412
10413 #undef GEN_CRLOGIC
10414 #define GEN_CRLOGIC(name, tcg_op, opc) \
10415 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10416 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10417 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10418 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10419 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10420 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10421 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10422 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10423 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10424
10425 #undef GEN_MAC_HANDLER
10426 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10427 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10428 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10429 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10430 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10431 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10432 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10433 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10434 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10435 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10436 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10437 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10438 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10439 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10440 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10441 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10442 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10443 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10444 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10445 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10446 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10447 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10448 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10449 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10450 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10451 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10452 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10453 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10454 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10455 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10456 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10457 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10458 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10459 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10460 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10461 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10462 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10463 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10464 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10465 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10466 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10467 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10468 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10469 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10470
10471 #undef GEN_VR_LDX
10472 #undef GEN_VR_STX
10473 #undef GEN_VR_LVE
10474 #undef GEN_VR_STVE
10475 #define GEN_VR_LDX(name, opc2, opc3) \
10476 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10477 #define GEN_VR_STX(name, opc2, opc3) \
10478 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10479 #define GEN_VR_LVE(name, opc2, opc3) \
10480 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10481 #define GEN_VR_STVE(name, opc2, opc3) \
10482 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10483 GEN_VR_LDX(lvx, 0x07, 0x03),
10484 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10485 GEN_VR_LVE(bx, 0x07, 0x00),
10486 GEN_VR_LVE(hx, 0x07, 0x01),
10487 GEN_VR_LVE(wx, 0x07, 0x02),
10488 GEN_VR_STX(svx, 0x07, 0x07),
10489 GEN_VR_STX(svxl, 0x07, 0x0F),
10490 GEN_VR_STVE(bx, 0x07, 0x04),
10491 GEN_VR_STVE(hx, 0x07, 0x05),
10492 GEN_VR_STVE(wx, 0x07, 0x06),
10493
10494 #undef GEN_VX_LOGICAL
10495 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10496 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10497
10498 #undef GEN_VX_LOGICAL_207
10499 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10500 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10501
10502 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10503 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10504 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10505 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10506 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10507 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10508 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10509 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10510
10511 #undef GEN_VXFORM
10512 #define GEN_VXFORM(name, opc2, opc3) \
10513 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10514
10515 #undef GEN_VXFORM_207
10516 #define GEN_VXFORM_207(name, opc2, opc3) \
10517 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10518
10519 #undef GEN_VXFORM_DUAL
10520 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10521 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10522
10523 #undef GEN_VXRFORM_DUAL
10524 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10525 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10526 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10527
10528 GEN_VXFORM(vaddubm, 0, 0),
10529 GEN_VXFORM(vadduhm, 0, 1),
10530 GEN_VXFORM(vadduwm, 0, 2),
10531 GEN_VXFORM_207(vaddudm, 0, 3),
10532 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10533 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10534 GEN_VXFORM(vsubuwm, 0, 18),
10535 GEN_VXFORM_207(vsubudm, 0, 19),
10536 GEN_VXFORM(vmaxub, 1, 0),
10537 GEN_VXFORM(vmaxuh, 1, 1),
10538 GEN_VXFORM(vmaxuw, 1, 2),
10539 GEN_VXFORM_207(vmaxud, 1, 3),
10540 GEN_VXFORM(vmaxsb, 1, 4),
10541 GEN_VXFORM(vmaxsh, 1, 5),
10542 GEN_VXFORM(vmaxsw, 1, 6),
10543 GEN_VXFORM_207(vmaxsd, 1, 7),
10544 GEN_VXFORM(vminub, 1, 8),
10545 GEN_VXFORM(vminuh, 1, 9),
10546 GEN_VXFORM(vminuw, 1, 10),
10547 GEN_VXFORM_207(vminud, 1, 11),
10548 GEN_VXFORM(vminsb, 1, 12),
10549 GEN_VXFORM(vminsh, 1, 13),
10550 GEN_VXFORM(vminsw, 1, 14),
10551 GEN_VXFORM_207(vminsd, 1, 15),
10552 GEN_VXFORM(vavgub, 1, 16),
10553 GEN_VXFORM(vavguh, 1, 17),
10554 GEN_VXFORM(vavguw, 1, 18),
10555 GEN_VXFORM(vavgsb, 1, 20),
10556 GEN_VXFORM(vavgsh, 1, 21),
10557 GEN_VXFORM(vavgsw, 1, 22),
10558 GEN_VXFORM(vmrghb, 6, 0),
10559 GEN_VXFORM(vmrghh, 6, 1),
10560 GEN_VXFORM(vmrghw, 6, 2),
10561 GEN_VXFORM(vmrglb, 6, 4),
10562 GEN_VXFORM(vmrglh, 6, 5),
10563 GEN_VXFORM(vmrglw, 6, 6),
10564 GEN_VXFORM_207(vmrgew, 6, 30),
10565 GEN_VXFORM_207(vmrgow, 6, 26),
10566 GEN_VXFORM(vmuloub, 4, 0),
10567 GEN_VXFORM(vmulouh, 4, 1),
10568 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10569 GEN_VXFORM(vmulosb, 4, 4),
10570 GEN_VXFORM(vmulosh, 4, 5),
10571 GEN_VXFORM_207(vmulosw, 4, 6),
10572 GEN_VXFORM(vmuleub, 4, 8),
10573 GEN_VXFORM(vmuleuh, 4, 9),
10574 GEN_VXFORM_207(vmuleuw, 4, 10),
10575 GEN_VXFORM(vmulesb, 4, 12),
10576 GEN_VXFORM(vmulesh, 4, 13),
10577 GEN_VXFORM_207(vmulesw, 4, 14),
10578 GEN_VXFORM(vslb, 2, 4),
10579 GEN_VXFORM(vslh, 2, 5),
10580 GEN_VXFORM(vslw, 2, 6),
10581 GEN_VXFORM_207(vsld, 2, 23),
10582 GEN_VXFORM(vsrb, 2, 8),
10583 GEN_VXFORM(vsrh, 2, 9),
10584 GEN_VXFORM(vsrw, 2, 10),
10585 GEN_VXFORM_207(vsrd, 2, 27),
10586 GEN_VXFORM(vsrab, 2, 12),
10587 GEN_VXFORM(vsrah, 2, 13),
10588 GEN_VXFORM(vsraw, 2, 14),
10589 GEN_VXFORM_207(vsrad, 2, 15),
10590 GEN_VXFORM(vslo, 6, 16),
10591 GEN_VXFORM(vsro, 6, 17),
10592 GEN_VXFORM(vaddcuw, 0, 6),
10593 GEN_VXFORM(vsubcuw, 0, 22),
10594 GEN_VXFORM(vaddubs, 0, 8),
10595 GEN_VXFORM(vadduhs, 0, 9),
10596 GEN_VXFORM(vadduws, 0, 10),
10597 GEN_VXFORM(vaddsbs, 0, 12),
10598 GEN_VXFORM(vaddshs, 0, 13),
10599 GEN_VXFORM(vaddsws, 0, 14),
10600 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10601 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10602 GEN_VXFORM(vsubuws, 0, 26),
10603 GEN_VXFORM(vsubsbs, 0, 28),
10604 GEN_VXFORM(vsubshs, 0, 29),
10605 GEN_VXFORM(vsubsws, 0, 30),
10606 GEN_VXFORM_207(vadduqm, 0, 4),
10607 GEN_VXFORM_207(vaddcuq, 0, 5),
10608 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10609 GEN_VXFORM_207(vsubuqm, 0, 20),
10610 GEN_VXFORM_207(vsubcuq, 0, 21),
10611 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10612 GEN_VXFORM(vrlb, 2, 0),
10613 GEN_VXFORM(vrlh, 2, 1),
10614 GEN_VXFORM(vrlw, 2, 2),
10615 GEN_VXFORM_207(vrld, 2, 3),
10616 GEN_VXFORM(vsl, 2, 7),
10617 GEN_VXFORM(vsr, 2, 11),
10618 GEN_VXFORM(vpkuhum, 7, 0),
10619 GEN_VXFORM(vpkuwum, 7, 1),
10620 GEN_VXFORM_207(vpkudum, 7, 17),
10621 GEN_VXFORM(vpkuhus, 7, 2),
10622 GEN_VXFORM(vpkuwus, 7, 3),
10623 GEN_VXFORM_207(vpkudus, 7, 19),
10624 GEN_VXFORM(vpkshus, 7, 4),
10625 GEN_VXFORM(vpkswus, 7, 5),
10626 GEN_VXFORM_207(vpksdus, 7, 21),
10627 GEN_VXFORM(vpkshss, 7, 6),
10628 GEN_VXFORM(vpkswss, 7, 7),
10629 GEN_VXFORM_207(vpksdss, 7, 23),
10630 GEN_VXFORM(vpkpx, 7, 12),
10631 GEN_VXFORM(vsum4ubs, 4, 24),
10632 GEN_VXFORM(vsum4sbs, 4, 28),
10633 GEN_VXFORM(vsum4shs, 4, 25),
10634 GEN_VXFORM(vsum2sws, 4, 26),
10635 GEN_VXFORM(vsumsws, 4, 30),
10636 GEN_VXFORM(vaddfp, 5, 0),
10637 GEN_VXFORM(vsubfp, 5, 1),
10638 GEN_VXFORM(vmaxfp, 5, 16),
10639 GEN_VXFORM(vminfp, 5, 17),
10640
10641 #undef GEN_VXRFORM1
10642 #undef GEN_VXRFORM
10643 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10644 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10645 #define GEN_VXRFORM(name, opc2, opc3) \
10646 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10647 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10648 GEN_VXRFORM(vcmpequb, 3, 0)
10649 GEN_VXRFORM(vcmpequh, 3, 1)
10650 GEN_VXRFORM(vcmpequw, 3, 2)
10651 GEN_VXRFORM(vcmpgtsb, 3, 12)
10652 GEN_VXRFORM(vcmpgtsh, 3, 13)
10653 GEN_VXRFORM(vcmpgtsw, 3, 14)
10654 GEN_VXRFORM(vcmpgtub, 3, 8)
10655 GEN_VXRFORM(vcmpgtuh, 3, 9)
10656 GEN_VXRFORM(vcmpgtuw, 3, 10)
10657 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10658 GEN_VXRFORM(vcmpgefp, 3, 7)
10659 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10660 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10661
10662 #undef GEN_VXFORM_SIMM
10663 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10664 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10665 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10666 GEN_VXFORM_SIMM(vspltish, 6, 13),
10667 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10668
10669 #undef GEN_VXFORM_NOA
10670 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10671 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10672 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10673 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10674 GEN_VXFORM_207(vupkhsw, 7, 25),
10675 GEN_VXFORM_NOA(vupklsb, 7, 10),
10676 GEN_VXFORM_NOA(vupklsh, 7, 11),
10677 GEN_VXFORM_207(vupklsw, 7, 27),
10678 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10679 GEN_VXFORM_NOA(vupklpx, 7, 15),
10680 GEN_VXFORM_NOA(vrefp, 5, 4),
10681 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10682 GEN_VXFORM_NOA(vexptefp, 5, 6),
10683 GEN_VXFORM_NOA(vlogefp, 5, 7),
10684 GEN_VXFORM_NOA(vrfim, 5, 8),
10685 GEN_VXFORM_NOA(vrfin, 5, 9),
10686 GEN_VXFORM_NOA(vrfip, 5, 10),
10687 GEN_VXFORM_NOA(vrfiz, 5, 11),
10688
10689 #undef GEN_VXFORM_UIMM
10690 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10691 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10692 GEN_VXFORM_UIMM(vspltb, 6, 8),
10693 GEN_VXFORM_UIMM(vsplth, 6, 9),
10694 GEN_VXFORM_UIMM(vspltw, 6, 10),
10695 GEN_VXFORM_UIMM(vcfux, 5, 12),
10696 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10697 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10698 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10699
10700 #undef GEN_VAFORM_PAIRED
10701 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10702 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10703 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10704 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10705 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10706 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10707 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10708 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10709
10710 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10711 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10712 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10713 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10714
10715 GEN_VXFORM_207(vbpermq, 6, 21),
10716 GEN_VXFORM_207(vgbbd, 6, 20),
10717 GEN_VXFORM_207(vpmsumb, 4, 16),
10718 GEN_VXFORM_207(vpmsumh, 4, 17),
10719 GEN_VXFORM_207(vpmsumw, 4, 18),
10720 GEN_VXFORM_207(vpmsumd, 4, 19),
10721
10722 GEN_VXFORM_207(vsbox, 4, 23),
10723
10724 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10725 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10726
10727 GEN_VXFORM_207(vshasigmaw, 1, 26),
10728 GEN_VXFORM_207(vshasigmad, 1, 27),
10729
10730 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10731
10732 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10733 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10734 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10735 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10736 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10737 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10738 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10739
10740 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10741 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10742 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10743 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10744 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10745
10746 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10747 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10748 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10749 #if defined(TARGET_PPC64)
10750 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10751 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10752 #endif
10753
10754 #undef GEN_XX2FORM
10755 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10756 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10757 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10758
10759 #undef GEN_XX3FORM
10760 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10761 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10762 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10763 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10764 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10765
10766 #undef GEN_XX3_RC_FORM
10767 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10768 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10769 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10770 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10771 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10772 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10773 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10774 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10775 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10776
10777 #undef GEN_XX3FORM_DM
10778 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10779 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10780 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10781 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10782 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10783 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10784 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10785 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10786 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10787 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10788 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10789 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10790 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10791 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10792 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10793 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10794 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10795
10796 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10797 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10798 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10799 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10800
10801 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10802 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10803 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10804 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10805 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10806 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10807 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10808 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10809
10810 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10811 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10812 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10813 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10814 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10815 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10816 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10817 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10818 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10819 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10820 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10821 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10822 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10823 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10824 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10825 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10826 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10827 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10828 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10829 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10830 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10831 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10832 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10833 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10834 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10835 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10836 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10837 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10838 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10839 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10840 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10841 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10842 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10843 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10844 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10845 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10846
10847 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10848 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10849 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10850 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10851 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10852 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10853 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10854 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10855 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10856 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10857 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10858 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10859 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10860 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10861 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10862 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10863 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10864 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10865
10866 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10867 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10868 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10869 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10870 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10871 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10872 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10873 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10874 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10875 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10876 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10877 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10878 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10879 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10880 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10881 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10882 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10883 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10884 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10885 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10886 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10887 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10888 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10889 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10890 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10891 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10892 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10893 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10894 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10895 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10896 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10897 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10898 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10899 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10900 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10901 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10902
10903 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10904 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10905 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10906 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10907 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10908 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10909 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10910 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10911 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10912 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10913 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10914 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10915 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10916 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10917 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10918 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10919 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10920 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10921 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10922 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10923 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10924 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10925 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10926 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10927 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10928 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10929 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10930 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10931 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10932 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10933 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10934 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10935 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10936 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10937 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10938 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10939
10940 #undef VSX_LOGICAL
10941 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10942 GEN_XX3FORM(name, opc2, opc3, fl2)
10943
10944 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10945 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10946 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10947 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10948 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10949 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10950 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10951 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10952 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10953 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10954 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10955 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10956
10957 #define GEN_XXSEL_ROW(opc3) \
10958 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10959 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10960 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10961 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10962 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10963 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10964 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10965 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10966
10967 GEN_XXSEL_ROW(0x00)
10968 GEN_XXSEL_ROW(0x01)
10969 GEN_XXSEL_ROW(0x02)
10970 GEN_XXSEL_ROW(0x03)
10971 GEN_XXSEL_ROW(0x04)
10972 GEN_XXSEL_ROW(0x05)
10973 GEN_XXSEL_ROW(0x06)
10974 GEN_XXSEL_ROW(0x07)
10975 GEN_XXSEL_ROW(0x08)
10976 GEN_XXSEL_ROW(0x09)
10977 GEN_XXSEL_ROW(0x0A)
10978 GEN_XXSEL_ROW(0x0B)
10979 GEN_XXSEL_ROW(0x0C)
10980 GEN_XXSEL_ROW(0x0D)
10981 GEN_XXSEL_ROW(0x0E)
10982 GEN_XXSEL_ROW(0x0F)
10983 GEN_XXSEL_ROW(0x10)
10984 GEN_XXSEL_ROW(0x11)
10985 GEN_XXSEL_ROW(0x12)
10986 GEN_XXSEL_ROW(0x13)
10987 GEN_XXSEL_ROW(0x14)
10988 GEN_XXSEL_ROW(0x15)
10989 GEN_XXSEL_ROW(0x16)
10990 GEN_XXSEL_ROW(0x17)
10991 GEN_XXSEL_ROW(0x18)
10992 GEN_XXSEL_ROW(0x19)
10993 GEN_XXSEL_ROW(0x1A)
10994 GEN_XXSEL_ROW(0x1B)
10995 GEN_XXSEL_ROW(0x1C)
10996 GEN_XXSEL_ROW(0x1D)
10997 GEN_XXSEL_ROW(0x1E)
10998 GEN_XXSEL_ROW(0x1F)
10999
11000 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11001
11002 #undef GEN_SPE
11003 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11004 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11005 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11006 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11007 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11008 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11009 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11010 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11011 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11012 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11013 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11014 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11015 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11016 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11017 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11018 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11019 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11020 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11021 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11022 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11023 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11024 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11025 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11026 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11027 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11028 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11029 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11030 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11031 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11032 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11033 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11034
11035 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11036 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11037 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11038 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11039 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11040 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11041 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11042 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11043 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11044 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11045 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11046 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11047 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11048 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11049
11050 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11051 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11052 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11053 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11054 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11055 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11056 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11057 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11058 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11059 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11060 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11061 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11062 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11063 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11064
11065 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11066 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11067 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11068 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11069 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11070 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11071 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11072 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11073 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11074 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11075 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11076 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11077 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11078 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11079 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11080 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11081
11082 #undef GEN_SPEOP_LDST
11083 #define GEN_SPEOP_LDST(name, opc2, sh) \
11084 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11085 GEN_SPEOP_LDST(evldd, 0x00, 3),
11086 GEN_SPEOP_LDST(evldw, 0x01, 3),
11087 GEN_SPEOP_LDST(evldh, 0x02, 3),
11088 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11089 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11090 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11091 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11092 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11093 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11094 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11095 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11096
11097 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11098 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11099 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11100 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11101 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11102 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11103 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11104 };
11105
11106 #include "helper_regs.h"
11107 #include "translate_init.c"
11108
11109 /*****************************************************************************/
11110 /* Misc PowerPC helpers */
11111 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11112 int flags)
11113 {
11114 #define RGPL 4
11115 #define RFPL 4
11116
11117 PowerPCCPU *cpu = POWERPC_CPU(cs);
11118 CPUPPCState *env = &cpu->env;
11119 int i;
11120
11121 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11122 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11123 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11124 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11125 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11126 env->hflags, env->mmu_idx);
11127 #if !defined(NO_TIMER_DUMP)
11128 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11129 #if !defined(CONFIG_USER_ONLY)
11130 " DECR %08" PRIu32
11131 #endif
11132 "\n",
11133 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11134 #if !defined(CONFIG_USER_ONLY)
11135 , cpu_ppc_load_decr(env)
11136 #endif
11137 );
11138 #endif
11139 for (i = 0; i < 32; i++) {
11140 if ((i & (RGPL - 1)) == 0)
11141 cpu_fprintf(f, "GPR%02d", i);
11142 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11143 if ((i & (RGPL - 1)) == (RGPL - 1))
11144 cpu_fprintf(f, "\n");
11145 }
11146 cpu_fprintf(f, "CR ");
11147 for (i = 0; i < 8; i++)
11148 cpu_fprintf(f, "%01x", env->crf[i]);
11149 cpu_fprintf(f, " [");
11150 for (i = 0; i < 8; i++) {
11151 char a = '-';
11152 if (env->crf[i] & 0x08)
11153 a = 'L';
11154 else if (env->crf[i] & 0x04)
11155 a = 'G';
11156 else if (env->crf[i] & 0x02)
11157 a = 'E';
11158 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11159 }
11160 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11161 env->reserve_addr);
11162 for (i = 0; i < 32; i++) {
11163 if ((i & (RFPL - 1)) == 0)
11164 cpu_fprintf(f, "FPR%02d", i);
11165 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11166 if ((i & (RFPL - 1)) == (RFPL - 1))
11167 cpu_fprintf(f, "\n");
11168 }
11169 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11170 #if !defined(CONFIG_USER_ONLY)
11171 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11172 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11173 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11174 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11175
11176 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11177 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11178 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11179 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11180
11181 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11182 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11183 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11184 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11185
11186 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11187 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11188 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11189 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11190 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11191
11192 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11193 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11194 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11195 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11196
11197 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11198 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11199 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11200 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11201
11202 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11203 " EPR " TARGET_FMT_lx "\n",
11204 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11205 env->spr[SPR_BOOKE_EPR]);
11206
11207 /* FSL-specific */
11208 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11209 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11210 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11211 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11212
11213 /*
11214 * IVORs are left out as they are large and do not change often --
11215 * they can be read with "p $ivor0", "p $ivor1", etc.
11216 */
11217 }
11218
11219 #if defined(TARGET_PPC64)
11220 if (env->flags & POWERPC_FLAG_CFAR) {
11221 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11222 }
11223 #endif
11224
11225 switch (env->mmu_model) {
11226 case POWERPC_MMU_32B:
11227 case POWERPC_MMU_601:
11228 case POWERPC_MMU_SOFT_6xx:
11229 case POWERPC_MMU_SOFT_74xx:
11230 #if defined(TARGET_PPC64)
11231 case POWERPC_MMU_64B:
11232 case POWERPC_MMU_2_06:
11233 case POWERPC_MMU_2_06a:
11234 case POWERPC_MMU_2_06d:
11235 #endif
11236 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11237 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11238 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11239 break;
11240 case POWERPC_MMU_BOOKE206:
11241 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11242 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11243 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11244 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11245
11246 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11247 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11248 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11249 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11250
11251 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11252 " TLB1CFG " TARGET_FMT_lx "\n",
11253 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11254 env->spr[SPR_BOOKE_TLB1CFG]);
11255 break;
11256 default:
11257 break;
11258 }
11259 #endif
11260
11261 #undef RGPL
11262 #undef RFPL
11263 }
11264
11265 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11266 fprintf_function cpu_fprintf, int flags)
11267 {
11268 #if defined(DO_PPC_STATISTICS)
11269 PowerPCCPU *cpu = POWERPC_CPU(cs);
11270 opc_handler_t **t1, **t2, **t3, *handler;
11271 int op1, op2, op3;
11272
11273 t1 = cpu->env.opcodes;
11274 for (op1 = 0; op1 < 64; op1++) {
11275 handler = t1[op1];
11276 if (is_indirect_opcode(handler)) {
11277 t2 = ind_table(handler);
11278 for (op2 = 0; op2 < 32; op2++) {
11279 handler = t2[op2];
11280 if (is_indirect_opcode(handler)) {
11281 t3 = ind_table(handler);
11282 for (op3 = 0; op3 < 32; op3++) {
11283 handler = t3[op3];
11284 if (handler->count == 0)
11285 continue;
11286 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11287 "%016" PRIx64 " %" PRId64 "\n",
11288 op1, op2, op3, op1, (op3 << 5) | op2,
11289 handler->oname,
11290 handler->count, handler->count);
11291 }
11292 } else {
11293 if (handler->count == 0)
11294 continue;
11295 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11296 "%016" PRIx64 " %" PRId64 "\n",
11297 op1, op2, op1, op2, handler->oname,
11298 handler->count, handler->count);
11299 }
11300 }
11301 } else {
11302 if (handler->count == 0)
11303 continue;
11304 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11305 " %" PRId64 "\n",
11306 op1, op1, handler->oname,
11307 handler->count, handler->count);
11308 }
11309 }
11310 #endif
11311 }
11312
11313 /*****************************************************************************/
11314 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11315 TranslationBlock *tb,
11316 bool search_pc)
11317 {
11318 CPUState *cs = CPU(cpu);
11319 CPUPPCState *env = &cpu->env;
11320 DisasContext ctx, *ctxp = &ctx;
11321 opc_handler_t **table, *handler;
11322 target_ulong pc_start;
11323 uint16_t *gen_opc_end;
11324 CPUBreakpoint *bp;
11325 int j, lj = -1;
11326 int num_insns;
11327 int max_insns;
11328
11329 pc_start = tb->pc;
11330 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11331 ctx.nip = pc_start;
11332 ctx.tb = tb;
11333 ctx.exception = POWERPC_EXCP_NONE;
11334 ctx.spr_cb = env->spr_cb;
11335 ctx.mem_idx = env->mmu_idx;
11336 ctx.insns_flags = env->insns_flags;
11337 ctx.insns_flags2 = env->insns_flags2;
11338 ctx.access_type = -1;
11339 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11340 #if defined(TARGET_PPC64)
11341 ctx.sf_mode = msr_is_64bit(env, env->msr);
11342 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11343 #endif
11344 ctx.fpu_enabled = msr_fp;
11345 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11346 ctx.spe_enabled = msr_spe;
11347 else
11348 ctx.spe_enabled = 0;
11349 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11350 ctx.altivec_enabled = msr_vr;
11351 else
11352 ctx.altivec_enabled = 0;
11353 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11354 ctx.vsx_enabled = msr_vsx;
11355 } else {
11356 ctx.vsx_enabled = 0;
11357 }
11358 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11359 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11360 else
11361 ctx.singlestep_enabled = 0;
11362 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11363 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11364 if (unlikely(cs->singlestep_enabled)) {
11365 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11366 }
11367 #if defined (DO_SINGLE_STEP) && 0
11368 /* Single step trace mode */
11369 msr_se = 1;
11370 #endif
11371 num_insns = 0;
11372 max_insns = tb->cflags & CF_COUNT_MASK;
11373 if (max_insns == 0)
11374 max_insns = CF_COUNT_MASK;
11375
11376 gen_tb_start();
11377 /* Set env in case of segfault during code fetch */
11378 while (ctx.exception == POWERPC_EXCP_NONE
11379 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11380 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11381 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11382 if (bp->pc == ctx.nip) {
11383 gen_debug_exception(ctxp);
11384 break;
11385 }
11386 }
11387 }
11388 if (unlikely(search_pc)) {
11389 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11390 if (lj < j) {
11391 lj++;
11392 while (lj < j)
11393 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11394 }
11395 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11396 tcg_ctx.gen_opc_instr_start[lj] = 1;
11397 tcg_ctx.gen_opc_icount[lj] = num_insns;
11398 }
11399 LOG_DISAS("----------------\n");
11400 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11401 ctx.nip, ctx.mem_idx, (int)msr_ir);
11402 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11403 gen_io_start();
11404 if (unlikely(ctx.le_mode)) {
11405 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11406 } else {
11407 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11408 }
11409 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11410 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11411 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11412 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11413 tcg_gen_debug_insn_start(ctx.nip);
11414 }
11415 ctx.nip += 4;
11416 table = env->opcodes;
11417 num_insns++;
11418 handler = table[opc1(ctx.opcode)];
11419 if (is_indirect_opcode(handler)) {
11420 table = ind_table(handler);
11421 handler = table[opc2(ctx.opcode)];
11422 if (is_indirect_opcode(handler)) {
11423 table = ind_table(handler);
11424 handler = table[opc3(ctx.opcode)];
11425 }
11426 }
11427 /* Is opcode *REALLY* valid ? */
11428 if (unlikely(handler->handler == &gen_invalid)) {
11429 if (qemu_log_enabled()) {
11430 qemu_log("invalid/unsupported opcode: "
11431 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11432 opc1(ctx.opcode), opc2(ctx.opcode),
11433 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11434 }
11435 } else {
11436 uint32_t inval;
11437
11438 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11439 inval = handler->inval2;
11440 } else {
11441 inval = handler->inval1;
11442 }
11443
11444 if (unlikely((ctx.opcode & inval) != 0)) {
11445 if (qemu_log_enabled()) {
11446 qemu_log("invalid bits: %08x for opcode: "
11447 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11448 ctx.opcode & inval, opc1(ctx.opcode),
11449 opc2(ctx.opcode), opc3(ctx.opcode),
11450 ctx.opcode, ctx.nip - 4);
11451 }
11452 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11453 break;
11454 }
11455 }
11456 (*(handler->handler))(&ctx);
11457 #if defined(DO_PPC_STATISTICS)
11458 handler->count++;
11459 #endif
11460 /* Check trace mode exceptions */
11461 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11462 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11463 ctx.exception != POWERPC_SYSCALL &&
11464 ctx.exception != POWERPC_EXCP_TRAP &&
11465 ctx.exception != POWERPC_EXCP_BRANCH)) {
11466 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11467 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11468 (cs->singlestep_enabled) ||
11469 singlestep ||
11470 num_insns >= max_insns)) {
11471 /* if we reach a page boundary or are single stepping, stop
11472 * generation
11473 */
11474 break;
11475 }
11476 }
11477 if (tb->cflags & CF_LAST_IO)
11478 gen_io_end();
11479 if (ctx.exception == POWERPC_EXCP_NONE) {
11480 gen_goto_tb(&ctx, 0, ctx.nip);
11481 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11482 if (unlikely(cs->singlestep_enabled)) {
11483 gen_debug_exception(ctxp);
11484 }
11485 /* Generate the return instruction */
11486 tcg_gen_exit_tb(0);
11487 }
11488 gen_tb_end(tb, num_insns);
11489 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11490 if (unlikely(search_pc)) {
11491 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11492 lj++;
11493 while (lj <= j)
11494 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11495 } else {
11496 tb->size = ctx.nip - pc_start;
11497 tb->icount = num_insns;
11498 }
11499 #if defined(DEBUG_DISAS)
11500 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11501 int flags;
11502 flags = env->bfd_mach;
11503 flags |= ctx.le_mode << 16;
11504 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11505 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11506 qemu_log("\n");
11507 }
11508 #endif
11509 }
11510
11511 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11512 {
11513 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11514 }
11515
11516 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11517 {
11518 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11519 }
11520
11521 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11522 {
11523 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11524 }
AR7 emulation for QEMU