hw/arm/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "hw/sysbus.h"
  25 #include "hw/arm/arm.h"
  26 #include "hw/arm/primecell.h"
  27 #include "hw/devices.h"
  28 #include "net/net.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/boards.h"
  31 #include "exec/address-spaces.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/block/flash.h"
  34 #include "sysemu/device_tree.h"
  35 #include "qemu/error-report.h"
  36 #include <libfdt.h>
  37
  38 #define VEXPRESS_BOARD_ID 0x8e0
  39 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
  40 #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
  41
  42 /* Number of virtio transports to create (0..8; limited by
  43  * number of available IRQ lines).
  44  */
  45 #define NUM_VIRTIO_TRANSPORTS 4
  46
  47 /* Address maps for peripherals:
  48  * the Versatile Express motherboard has two possible maps,
  49  * the "legacy" one (used for A9) and the "Cortex-A Series"
  50  * map (used for newer cores).
  51  * Individual daughterboards can also have different maps for
  52  * their peripherals.
  53  */
  54
  55 enum {
  56     VE_SYSREGS,
  57     VE_SP810,
  58     VE_SERIALPCI,
  59     VE_PL041,
  60     VE_MMCI,
  61     VE_KMI0,
  62     VE_KMI1,
  63     VE_UART0,
  64     VE_UART1,
  65     VE_UART2,
  66     VE_UART3,
  67     VE_WDT,
  68     VE_TIMER01,
  69     VE_TIMER23,
  70     VE_SERIALDVI,
  71     VE_RTC,
  72     VE_COMPACTFLASH,
  73     VE_CLCD,
  74     VE_NORFLASH0,
  75     VE_NORFLASH1,
  76     VE_NORFLASHALIAS,
  77     VE_SRAM,
  78     VE_VIDEORAM,
  79     VE_ETHERNET,
  80     VE_USB,
  81     VE_DAPROM,
  82     VE_VIRTIO,
  83 };
  84
  85 static hwaddr motherboard_legacy_map[] = {
  86     /* CS7: 0x10000000 .. 0x10020000 */
  87     [VE_SYSREGS] = 0x10000000,
  88     [VE_SP810] = 0x10001000,
  89     [VE_SERIALPCI] = 0x10002000,
  90     [VE_PL041] = 0x10004000,
  91     [VE_MMCI] = 0x10005000,
  92     [VE_KMI0] = 0x10006000,
  93     [VE_KMI1] = 0x10007000,
  94     [VE_UART0] = 0x10009000,
  95     [VE_UART1] = 0x1000a000,
  96     [VE_UART2] = 0x1000b000,
  97     [VE_UART3] = 0x1000c000,
  98     [VE_WDT] = 0x1000f000,
  99     [VE_TIMER01] = 0x10011000,
 100     [VE_TIMER23] = 0x10012000,
 101     [VE_VIRTIO] = 0x10013000,
 102     [VE_SERIALDVI] = 0x10016000,
 103     [VE_RTC] = 0x10017000,
 104     [VE_COMPACTFLASH] = 0x1001a000,
 105     [VE_CLCD] = 0x1001f000,
 106     /* CS0: 0x40000000 .. 0x44000000 */
 107     [VE_NORFLASH0] = 0x40000000,
 108     /* CS1: 0x44000000 .. 0x48000000 */
 109     [VE_NORFLASH1] = 0x44000000,
 110     /* CS2: 0x48000000 .. 0x4a000000 */
 111     [VE_SRAM] = 0x48000000,
 112     /* CS3: 0x4c000000 .. 0x50000000 */
 113     [VE_VIDEORAM] = 0x4c000000,
 114     [VE_ETHERNET] = 0x4e000000,
 115     [VE_USB] = 0x4f000000,
 116     [VE_NORFLASHALIAS] = -1, /* not present */
 117 };
 118
 119 static hwaddr motherboard_aseries_map[] = {
 120     [VE_NORFLASHALIAS] = 0,
 121     /* CS0: 0x08000000 .. 0x0c000000 */
 122     [VE_NORFLASH0] = 0x08000000,
 123     /* CS4: 0x0c000000 .. 0x10000000 */
 124     [VE_NORFLASH1] = 0x0c000000,
 125     /* CS5: 0x10000000 .. 0x14000000 */
 126     /* CS1: 0x14000000 .. 0x18000000 */
 127     [VE_SRAM] = 0x14000000,
 128     /* CS2: 0x18000000 .. 0x1c000000 */
 129     [VE_VIDEORAM] = 0x18000000,
 130     [VE_ETHERNET] = 0x1a000000,
 131     [VE_USB] = 0x1b000000,
 132     /* CS3: 0x1c000000 .. 0x20000000 */
 133     [VE_DAPROM] = 0x1c000000,
 134     [VE_SYSREGS] = 0x1c010000,
 135     [VE_SP810] = 0x1c020000,
 136     [VE_SERIALPCI] = 0x1c030000,
 137     [VE_PL041] = 0x1c040000,
 138     [VE_MMCI] = 0x1c050000,
 139     [VE_KMI0] = 0x1c060000,
 140     [VE_KMI1] = 0x1c070000,
 141     [VE_UART0] = 0x1c090000,
 142     [VE_UART1] = 0x1c0a0000,
 143     [VE_UART2] = 0x1c0b0000,
 144     [VE_UART3] = 0x1c0c0000,
 145     [VE_WDT] = 0x1c0f0000,
 146     [VE_TIMER01] = 0x1c110000,
 147     [VE_TIMER23] = 0x1c120000,
 148     [VE_VIRTIO] = 0x1c130000,
 149     [VE_SERIALDVI] = 0x1c160000,
 150     [VE_RTC] = 0x1c170000,
 151     [VE_COMPACTFLASH] = 0x1c1a0000,
 152     [VE_CLCD] = 0x1c1f0000,
 153 };
 154
 155 /* Structure defining the peculiarities of a specific daughterboard */
 156
 157 typedef struct VEDBoardInfo VEDBoardInfo;
 158
 159 typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
 160                           ram_addr_t ram_size,
 161                           const char *cpu_model,
 162                           qemu_irq *pic);
 163
 164 struct VEDBoardInfo {
 165     struct arm_boot_info bootinfo;
 166     const hwaddr *motherboard_map;
 167     hwaddr loader_start;
 168     const hwaddr gic_cpu_if_addr;
 169     uint32_t proc_id;
 170     uint32_t num_voltage_sensors;
 171     const uint32_t *voltages;
 172     uint32_t num_clocks;
 173     const uint32_t *clocks;
 174     DBoardInitFn *init;
 175 };
 176
 177 static void init_cpus(const char *cpu_model, const char *privdev,
 178                       hwaddr periphbase, qemu_irq *pic)
 179 {
 180     ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 181     DeviceState *dev;
 182     SysBusDevice *busdev;
 183     int n;
 184
 185     if (!cpu_oc) {
 186         fprintf(stderr, "Unable to find CPU definition\n");
 187         exit(1);
 188     }
 189
 190     /* Create the actual CPUs */
 191     for (n = 0; n < smp_cpus; n++) {
 192         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
 193         Error *err = NULL;
 194
 195         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 196             object_property_set_int(cpuobj, periphbase,
 197                                     "reset-cbar", &error_abort);
 198         }
 199         object_property_set_bool(cpuobj, true, "realized", &err);
 200         if (err) {
 201             error_report("%s", error_get_pretty(err));
 202             exit(1);
 203         }
 204     }
 205
 206     /* Create the private peripheral devices (including the GIC);
 207      * this must happen after the CPUs are created because a15mpcore_priv
 208      * wires itself up to the CPU's generic_timer gpio out lines.
 209      */
 210     dev = qdev_create(NULL, privdev);
 211     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 212     qdev_init_nofail(dev);
 213     busdev = SYS_BUS_DEVICE(dev);
 214     sysbus_mmio_map(busdev, 0, periphbase);
 215
 216     /* Interrupts [42:0] are from the motherboard;
 217      * [47:43] are reserved; [63:48] are daughterboard
 218      * peripherals. Note that some documentation numbers
 219      * external interrupts starting from 32 (because there
 220      * are internal interrupts 0..31).
 221      */
 222     for (n = 0; n < 64; n++) {
 223         pic[n] = qdev_get_gpio_in(dev, n);
 224     }
 225
 226     /* Connect the CPUs to the GIC */
 227     for (n = 0; n < smp_cpus; n++) {
 228         DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
 229
 230         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 231     }
 232 }
 233
 234 static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
 235                                   ram_addr_t ram_size,
 236                                   const char *cpu_model,
 237                                   qemu_irq *pic)
 238 {
 239     MemoryRegion *sysmem = get_system_memory();
 240     MemoryRegion *ram = g_new(MemoryRegion, 1);
 241     MemoryRegion *lowram = g_new(MemoryRegion, 1);
 242     ram_addr_t low_ram_size;
 243
 244     if (!cpu_model) {
 245         cpu_model = "cortex-a9";
 246     }
 247
 248     if (ram_size > 0x40000000) {
 249         /* 1GB is the maximum the address space permits */
 250         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
 251         exit(1);
 252     }
 253
 254     memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
 255     vmstate_register_ram_global(ram);
 256     low_ram_size = ram_size;
 257     if (low_ram_size > 0x4000000) {
 258         low_ram_size = 0x4000000;
 259     }
 260     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
 261      * address space should in theory be remappable to various
 262      * things including ROM or RAM; we always map the RAM there.
 263      */
 264     memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
 265     memory_region_add_subregion(sysmem, 0x0, lowram);
 266     memory_region_add_subregion(sysmem, 0x60000000, ram);
 267
 268     /* 0x1e000000 A9MPCore (SCU) private memory region */
 269     init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic);
 270
 271     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 272
 273     /* 0x10020000 PL111 CLCD (daughterboard) */
 274     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 275
 276     /* 0x10060000 AXI RAM */
 277     /* 0x100e0000 PL341 Dynamic Memory Controller */
 278     /* 0x100e1000 PL354 Static Memory Controller */
 279     /* 0x100e2000 System Configuration Controller */
 280
 281     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 282     /* 0x100e5000 SP805 Watchdog module */
 283     /* 0x100e6000 BP147 TrustZone Protection Controller */
 284     /* 0x100e9000 PL301 'Fast' AXI matrix */
 285     /* 0x100ea000 PL301 'Slow' AXI matrix */
 286     /* 0x100ec000 TrustZone Address Space Controller */
 287     /* 0x10200000 CoreSight debug APB */
 288     /* 0x1e00a000 PL310 L2 Cache Controller */
 289     sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
 290 }
 291
 292 /* Voltage values for SYS_CFG_VOLT daughterboard registers;
 293  * values are in microvolts.
 294  */
 295 static const uint32_t a9_voltages[] = {
 296     1000000, /* VD10 : 1.0V : SoC internal logic voltage */
 297     1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
 298     1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
 299     1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
 300     900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
 301     3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
 302 };
 303
 304 /* Reset values for daughterboard oscillators (in Hz) */
 305 static const uint32_t a9_clocks[] = {
 306     45000000, /* AMBA AXI ACLK: 45MHz */
 307     23750000, /* daughterboard CLCD clock: 23.75MHz */
 308     66670000, /* Test chip reference clock: 66.67MHz */
 309 };
 310
 311 static VEDBoardInfo a9_daughterboard = {
 312     .motherboard_map = motherboard_legacy_map,
 313     .loader_start = 0x60000000,
 314     .gic_cpu_if_addr = 0x1e000100,
 315     .proc_id = 0x0c000191,
 316     .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
 317     .voltages = a9_voltages,
 318     .num_clocks = ARRAY_SIZE(a9_clocks),
 319     .clocks = a9_clocks,
 320     .init = a9_daughterboard_init,
 321 };
 322
 323 static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
 324                                    ram_addr_t ram_size,
 325                                    const char *cpu_model,
 326                                    qemu_irq *pic)
 327 {
 328     MemoryRegion *sysmem = get_system_memory();
 329     MemoryRegion *ram = g_new(MemoryRegion, 1);
 330     MemoryRegion *sram = g_new(MemoryRegion, 1);
 331
 332     if (!cpu_model) {
 333         cpu_model = "cortex-a15";
 334     }
 335
 336     {
 337         /* We have to use a separate 64 bit variable here to avoid the gcc
 338          * "comparison is always false due to limited range of data type"
 339          * warning if we are on a host where ram_addr_t is 32 bits.
 340          */
 341         uint64_t rsz = ram_size;
 342         if (rsz > (30ULL * 1024 * 1024 * 1024)) {
 343             fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
 344             exit(1);
 345         }
 346     }
 347
 348     memory_region_init_ram(ram, NULL, "vexpress.highmem", ram_size);
 349     vmstate_register_ram_global(ram);
 350     /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
 351     memory_region_add_subregion(sysmem, 0x80000000, ram);
 352
 353     /* 0x2c000000 A15MPCore private memory region (GIC) */
 354     init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic);
 355
 356     /* A15 daughterboard peripherals: */
 357
 358     /* 0x20000000: CoreSight interfaces: not modelled */
 359     /* 0x2a000000: PL301 AXI interconnect: not modelled */
 360     /* 0x2a420000: SCC: not modelled */
 361     /* 0x2a430000: system counter: not modelled */
 362     /* 0x2b000000: HDLCD controller: not modelled */
 363     /* 0x2b060000: SP805 watchdog: not modelled */
 364     /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
 365     /* 0x2e000000: system SRAM */
 366     memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000);
 367     vmstate_register_ram_global(sram);
 368     memory_region_add_subregion(sysmem, 0x2e000000, sram);
 369
 370     /* 0x7ffb0000: DMA330 DMA controller: not modelled */
 371     /* 0x7ffd0000: PL354 static memory controller: not modelled */
 372 }
 373
 374 static const uint32_t a15_voltages[] = {
 375     900000, /* Vcore: 0.9V : CPU core voltage */
 376 };
 377
 378 static const uint32_t a15_clocks[] = {
 379     60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
 380     0, /* OSCCLK1: reserved */
 381     0, /* OSCCLK2: reserved */
 382     0, /* OSCCLK3: reserved */
 383     40000000, /* OSCCLK4: 40MHz : external AXI master clock */
 384     23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
 385     50000000, /* OSCCLK6: 50MHz : static memory controller clock */
 386     60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
 387     40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
 388 };
 389
 390 static VEDBoardInfo a15_daughterboard = {
 391     .motherboard_map = motherboard_aseries_map,
 392     .loader_start = 0x80000000,
 393     .gic_cpu_if_addr = 0x2c002000,
 394     .proc_id = 0x14000237,
 395     .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
 396     .voltages = a15_voltages,
 397     .num_clocks = ARRAY_SIZE(a15_clocks),
 398     .clocks = a15_clocks,
 399     .init = a15_daughterboard_init,
 400 };
 401
 402 static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
 403                                 hwaddr addr, hwaddr size, uint32_t intc,
 404                                 int irq)
 405 {
 406     /* Add a virtio_mmio node to the device tree blob:
 407      *   virtio_mmio@ADDRESS {
 408      *       compatible = "virtio,mmio";
 409      *       reg = <ADDRESS, SIZE>;
 410      *       interrupt-parent = <&intc>;
 411      *       interrupts = <0, irq, 1>;
 412      *   }
 413      * (Note that the format of the interrupts property is dependent on the
 414      * interrupt controller that interrupt-parent points to; these are for
 415      * the ARM GIC and indicate an SPI interrupt, rising-edge-triggered.)
 416      */
 417     int rc;
 418     char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
 419
 420     rc = qemu_fdt_add_subnode(fdt, nodename);
 421     rc |= qemu_fdt_setprop_string(fdt, nodename,
 422                                   "compatible", "virtio,mmio");
 423     rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
 424                                        acells, addr, scells, size);
 425     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
 426     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
 427     g_free(nodename);
 428     if (rc) {
 429         return -1;
 430     }
 431     return 0;
 432 }
 433
 434 static uint32_t find_int_controller(void *fdt)
 435 {
 436     /* Find the FDT node corresponding to the interrupt controller
 437      * for virtio-mmio devices. We do this by scanning the fdt for
 438      * a node with the right compatibility, since we know there is
 439      * only one GIC on a vexpress board.
 440      * We return the phandle of the node, or 0 if none was found.
 441      */
 442     const char *compat = "arm,cortex-a9-gic";
 443     int offset;
 444
 445     offset = fdt_node_offset_by_compatible(fdt, -1, compat);
 446     if (offset >= 0) {
 447         return fdt_get_phandle(fdt, offset);
 448     }
 449     return 0;
 450 }
 451
 452 static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
 453 {
 454     uint32_t acells, scells, intc;
 455     const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
 456
 457     acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells");
 458     scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells");
 459     intc = find_int_controller(fdt);
 460     if (!intc) {
 461         /* Not fatal, we just won't provide virtio. This will
 462          * happen with older device tree blobs.
 463          */
 464         fprintf(stderr, "QEMU: warning: couldn't find interrupt controller in "
 465                 "dtb; will not include virtio-mmio devices in the dtb.\n");
 466     } else {
 467         int i;
 468         const hwaddr *map = daughterboard->motherboard_map;
 469
 470         /* We iterate backwards here because adding nodes
 471          * to the dtb puts them in last-first.
 472          */
 473         for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 474             add_virtio_mmio_node(fdt, acells, scells,
 475                                  map[VE_VIRTIO] + 0x200 * i,
 476                                  0x200, intc, 40 + i);
 477         }
 478     }
 479 }
 480
 481
 482 /* Open code a private version of pflash registration since we
 483  * need to set non-default device width for VExpress platform.
 484  */
 485 static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
 486                                           DriveInfo *di)
 487 {
 488     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 489
 490     if (di && qdev_prop_set_drive(dev, "drive", di->bdrv)) {
 491         abort();
 492     }
 493
 494     qdev_prop_set_uint32(dev, "num-blocks",
 495                          VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
 496     qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
 497     qdev_prop_set_uint8(dev, "width", 4);
 498     qdev_prop_set_uint8(dev, "device-width", 2);
 499     qdev_prop_set_uint8(dev, "big-endian", 0);
 500     qdev_prop_set_uint16(dev, "id0", 0x89);
 501     qdev_prop_set_uint16(dev, "id1", 0x18);
 502     qdev_prop_set_uint16(dev, "id2", 0x00);
 503     qdev_prop_set_uint16(dev, "id3", 0x00);
 504     qdev_prop_set_string(dev, "name", name);
 505     qdev_init_nofail(dev);
 506
 507     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 508     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 509 }
 510
 511 static void vexpress_common_init(VEDBoardInfo *daughterboard,
 512                                  QEMUMachineInitArgs *args)
 513 {
 514     DeviceState *dev, *sysctl, *pl041;
 515     qemu_irq pic[64];
 516     uint32_t sys_id;
 517     DriveInfo *dinfo;
 518     pflash_t *pflash0;
 519     ram_addr_t vram_size, sram_size;
 520     MemoryRegion *sysmem = get_system_memory();
 521     MemoryRegion *vram = g_new(MemoryRegion, 1);
 522     MemoryRegion *sram = g_new(MemoryRegion, 1);
 523     MemoryRegion *flashalias = g_new(MemoryRegion, 1);
 524     MemoryRegion *flash0mem;
 525     const hwaddr *map = daughterboard->motherboard_map;
 526     int i;
 527
 528     daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
 529
 530     /* Motherboard peripherals: the wiring is the same but the
 531      * addresses vary between the legacy and A-Series memory maps.
 532      */
 533
 534     sys_id = 0x1190f500;
 535
 536     sysctl = qdev_create(NULL, "realview_sysctl");
 537     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 538     qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
 539     qdev_prop_set_uint32(sysctl, "len-db-voltage",
 540                          daughterboard->num_voltage_sensors);
 541     for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
 542         char *propname = g_strdup_printf("db-voltage[%d]", i);
 543         qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
 544         g_free(propname);
 545     }
 546     qdev_prop_set_uint32(sysctl, "len-db-clock",
 547                          daughterboard->num_clocks);
 548     for (i = 0; i < daughterboard->num_clocks; i++) {
 549         char *propname = g_strdup_printf("db-clock[%d]", i);
 550         qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
 551         g_free(propname);
 552     }
 553     qdev_init_nofail(sysctl);
 554     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
 555
 556     /* VE_SP810: not modelled */
 557     /* VE_SERIALPCI: not modelled */
 558
 559     pl041 = qdev_create(NULL, "pl041");
 560     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 561     qdev_init_nofail(pl041);
 562     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
 563     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
 564
 565     dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
 566     /* Wire up MMC card detect and read-only signals */
 567     qdev_connect_gpio_out(dev, 0,
 568                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 569     qdev_connect_gpio_out(dev, 1,
 570                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 571
 572     sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
 573     sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
 574
 575     sysbus_create_simple("pl011", map[VE_UART0], pic[5]);
 576     sysbus_create_simple("pl011", map[VE_UART1], pic[6]);
 577     sysbus_create_simple("pl011", map[VE_UART2], pic[7]);
 578     sysbus_create_simple("pl011", map[VE_UART3], pic[8]);
 579
 580     sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
 581     sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
 582
 583     /* VE_SERIALDVI: not modelled */
 584
 585     sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */
 586
 587     /* VE_COMPACTFLASH: not modelled */
 588
 589     sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
 590
 591     dinfo = drive_get_next(IF_PFLASH);
 592     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
 593                                        dinfo);
 594     if (!pflash0) {
 595         fprintf(stderr, "vexpress: error registering flash 0.\n");
 596         exit(1);
 597     }
 598
 599     if (map[VE_NORFLASHALIAS] != -1) {
 600         /* Map flash 0 as an alias into low memory */
 601         flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
 602         memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
 603                                  flash0mem, 0, VEXPRESS_FLASH_SIZE);
 604         memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
 605     }
 606
 607     dinfo = drive_get_next(IF_PFLASH);
 608     if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
 609                                   dinfo)) {
 610         fprintf(stderr, "vexpress: error registering flash 1.\n");
 611         exit(1);
 612     }
 613
 614     sram_size = 0x2000000;
 615     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size);
 616     vmstate_register_ram_global(sram);
 617     memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
 618
 619     vram_size = 0x800000;
 620     memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size);
 621     vmstate_register_ram_global(vram);
 622     memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
 623
 624     /* 0x4e000000 LAN9118 Ethernet */
 625     if (nd_table[0].used) {
 626         lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
 627     }
 628
 629     /* VE_USB: not modelled */
 630
 631     /* VE_DAPROM: not modelled */
 632
 633     /* Create mmio transports, so the user can create virtio backends
 634      * (which will be automatically plugged in to the transports). If
 635      * no backend is created the transport will just sit harmlessly idle.
 636      */
 637     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 638         sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
 639                              pic[40 + i]);
 640     }
 641
 642     daughterboard->bootinfo.ram_size = args->ram_size;
 643     daughterboard->bootinfo.kernel_filename = args->kernel_filename;
 644     daughterboard->bootinfo.kernel_cmdline = args->kernel_cmdline;
 645     daughterboard->bootinfo.initrd_filename = args->initrd_filename;
 646     daughterboard->bootinfo.nb_cpus = smp_cpus;
 647     daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
 648     daughterboard->bootinfo.loader_start = daughterboard->loader_start;
 649     daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
 650     daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
 651     daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
 652     daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
 653     arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
 654 }
 655
 656 static void vexpress_a9_init(QEMUMachineInitArgs *args)
 657 {
 658     vexpress_common_init(&a9_daughterboard, args);
 659 }
 660
 661 static void vexpress_a15_init(QEMUMachineInitArgs *args)
 662 {
 663     vexpress_common_init(&a15_daughterboard, args);
 664 }
 665
 666 static QEMUMachine vexpress_a9_machine = {
 667     .name = "vexpress-a9",
 668     .desc = "ARM Versatile Express for Cortex-A9",
 669     .init = vexpress_a9_init,
 670     .block_default_type = IF_SCSI,
 671     .max_cpus = 4,
 672 };
 673
 674 static QEMUMachine vexpress_a15_machine = {
 675     .name = "vexpress-a15",
 676     .desc = "ARM Versatile Express for Cortex-A15",
 677     .init = vexpress_a15_init,
 678     .block_default_type = IF_SCSI,
 679     .max_cpus = 4,
 680 };
 681
 682 static void vexpress_machine_init(void)
 683 {
 684     qemu_register_machine(&vexpress_a9_machine);
 685     qemu_register_machine(&vexpress_a15_machine);
 686 }
 687
 688 machine_init(vexpress_machine_init);