4 #include "qemu-common.h"
10 /* PCI includes legacy ISA access. */
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
26 /* QEMU-specific Vendor and Device ID definitions */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
65 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
66 #define PCI_DEVICE_ID_INTEL_82557 0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU 0x1100
74 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
78 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
80 #define FMT_PCIBUS PRIx64
82 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
83 uint32_t address
, uint32_t data
, int len
);
84 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
85 uint32_t address
, int len
);
86 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
87 pcibus_t addr
, pcibus_t size
, int type
);
88 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
90 typedef struct PCIIORegion
{
91 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
96 MemoryRegion
*address_space
;
99 #define PCI_ROM_SLOT 6
100 #define PCI_NUM_REGIONS 7
102 #include "pci_regs.h"
104 /* PCI HEADER_TYPE */
105 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
107 /* Size of the standard PCI config header */
108 #define PCI_CONFIG_HEADER_SIZE 0x40
109 /* Size of the standard PCI config space */
110 #define PCI_CONFIG_SPACE_SIZE 0x100
111 /* Size of the standart PCIe config space: 4KB */
112 #define PCIE_CONFIG_SPACE_SIZE 0x1000
114 #define PCI_NUM_PINS 4 /* A-D */
116 /* Bits in cap_present field. */
118 QEMU_PCI_CAP_MSI
= 0x1,
119 QEMU_PCI_CAP_MSIX
= 0x2,
120 QEMU_PCI_CAP_EXPRESS
= 0x4,
122 /* multifunction capable device */
123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
124 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
126 /* command register SERR bit enabled */
127 #define QEMU_PCI_CAP_SERR_BITNR 4
128 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
129 /* Standard hot plug controller. */
130 #define QEMU_PCI_SHPC_BITNR 5
131 QEMU_PCI_CAP_SHPC
= (1 << QEMU_PCI_SHPC_BITNR
),
132 #define QEMU_PCI_SLOTID_BITNR 6
133 QEMU_PCI_CAP_SLOTID
= (1 << QEMU_PCI_SLOTID_BITNR
),
136 #define TYPE_PCI_DEVICE "pci-device"
137 #define PCI_DEVICE(obj) \
138 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
139 #define PCI_DEVICE_CLASS(klass) \
140 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
141 #define PCI_DEVICE_GET_CLASS(obj) \
142 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
144 typedef struct PCIDeviceClass
{
145 DeviceClass parent_class
;
147 int (*init
)(PCIDevice
*dev
);
148 PCIUnregisterFunc
*exit
;
149 PCIConfigReadFunc
*config_read
;
150 PCIConfigWriteFunc
*config_write
;
156 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
157 uint16_t subsystem_id
; /* only for header type = 0 */
160 * pci-to-pci bridge or normal device.
161 * This doesn't mean pci host switch.
162 * When card bus bridge is supported, this would be enhanced.
167 int is_express
; /* is this device pci express? */
169 /* device isn't hot-pluggable */
176 typedef int (*MSIVectorUseNotifier
)(PCIDevice
*dev
, unsigned int vector
,
178 typedef void (*MSIVectorReleaseNotifier
)(PCIDevice
*dev
, unsigned int vector
);
182 /* PCI config space */
185 /* Used to enable config checks on load. Note that writable bits are
186 * never checked even if set in cmask. */
189 /* Used to implement R/W bytes */
192 /* Used to implement RW1C(Write 1 to Clear) bytes */
195 /* Used to allocate config space for capabilities. */
198 /* the following fields are read only */
202 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
204 /* do not access the following fields */
205 PCIConfigReadFunc
*config_read
;
206 PCIConfigWriteFunc
*config_write
;
208 /* IRQ objects for the INTA-INTD pins. */
211 /* Current IRQ levels. Used internally by the generic PCI code. */
214 /* Capability bits */
215 uint32_t cap_present
;
217 /* Offset of MSI-X capability in config space */
223 /* Space to store MSIX table & pending bit array */
226 /* MemoryRegion container for msix exclusive BAR setup */
227 MemoryRegion msix_exclusive_bar
;
228 /* Memory Regions for MSIX table and pending bit entries. */
229 MemoryRegion msix_table_mmio
;
230 MemoryRegion msix_pba_mmio
;
231 /* Reference-count for entries actually in use by driver. */
232 unsigned *msix_entry_used
;
233 /* MSIX function mask set or MSIX disabled */
234 bool msix_function_masked
;
235 /* Version id needed for VMState */
238 /* Offset of MSI capability in config space */
242 PCIExpressDevice exp
;
247 /* Location of option rom */
253 /* MSI-X notifiers */
254 MSIVectorUseNotifier msix_vector_use_notifier
;
255 MSIVectorReleaseNotifier msix_vector_release_notifier
;
258 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
259 uint8_t attr
, MemoryRegion
*memory
);
260 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
262 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
263 uint8_t offset
, uint8_t size
);
265 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
267 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
270 uint32_t pci_default_read_config(PCIDevice
*d
,
271 uint32_t address
, int len
);
272 void pci_default_write_config(PCIDevice
*d
,
273 uint32_t address
, uint32_t val
, int len
);
274 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
275 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
276 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
277 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
);
279 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
280 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
283 PCI_HOTPLUG_DISABLED
,
285 PCI_COLDPLUG_ENABLED
,
288 typedef int (*pci_hotplug_fn
)(DeviceState
*qdev
, PCIDevice
*pci_dev
,
289 PCIHotplugState state
);
290 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
292 MemoryRegion
*address_space_mem
,
293 MemoryRegion
*address_space_io
,
295 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
296 MemoryRegion
*address_space_mem
,
297 MemoryRegion
*address_space_io
,
299 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
300 void *irq_opaque
, int nirq
);
301 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
302 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*dev
);
303 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
304 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
306 MemoryRegion
*address_space_mem
,
307 MemoryRegion
*address_space_io
,
308 uint8_t devfn_min
, int nirq
);
309 void pci_device_reset(PCIDevice
*dev
);
310 void pci_bus_reset(PCIBus
*bus
);
312 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
313 const char *default_devaddr
);
314 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
315 const char *default_devaddr
);
316 int pci_bus_num(PCIBus
*s
);
317 void pci_for_each_device(PCIBus
*bus
, int bus_num
, void (*fn
)(PCIBus
*bus
, PCIDevice
*d
));
318 PCIBus
*pci_find_root_bus(int domain
);
319 int pci_find_domain(const PCIBus
*bus
);
320 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
321 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
322 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
);
324 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
327 void pci_device_deassert_intx(PCIDevice
*dev
);
330 pci_set_byte(uint8_t *config
, uint8_t val
)
335 static inline uint8_t
336 pci_get_byte(const uint8_t *config
)
342 pci_set_word(uint8_t *config
, uint16_t val
)
344 cpu_to_le16wu((uint16_t *)config
, val
);
347 static inline uint16_t
348 pci_get_word(const uint8_t *config
)
350 return le16_to_cpupu((const uint16_t *)config
);
354 pci_set_long(uint8_t *config
, uint32_t val
)
356 cpu_to_le32wu((uint32_t *)config
, val
);
359 static inline uint32_t
360 pci_get_long(const uint8_t *config
)
362 return le32_to_cpupu((const uint32_t *)config
);
366 pci_set_quad(uint8_t *config
, uint64_t val
)
368 cpu_to_le64w((uint64_t *)config
, val
);
371 static inline uint64_t
372 pci_get_quad(const uint8_t *config
)
374 return le64_to_cpup((const uint64_t *)config
);
378 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
380 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
384 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
386 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
390 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
392 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
396 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
398 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
402 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
404 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
408 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
410 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
414 * helper functions to do bit mask operation on configuration space.
415 * Just to set bit, use test-and-set and discard returned value.
416 * Just to clear bit, use test-and-clear and discard returned value.
417 * NOTE: They aren't atomic.
419 static inline uint8_t
420 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
422 uint8_t val
= pci_get_byte(config
);
423 pci_set_byte(config
, val
& ~mask
);
427 static inline uint8_t
428 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
430 uint8_t val
= pci_get_byte(config
);
431 pci_set_byte(config
, val
| mask
);
435 static inline uint16_t
436 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
438 uint16_t val
= pci_get_word(config
);
439 pci_set_word(config
, val
& ~mask
);
443 static inline uint16_t
444 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
446 uint16_t val
= pci_get_word(config
);
447 pci_set_word(config
, val
| mask
);
451 static inline uint32_t
452 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
454 uint32_t val
= pci_get_long(config
);
455 pci_set_long(config
, val
& ~mask
);
459 static inline uint32_t
460 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
462 uint32_t val
= pci_get_long(config
);
463 pci_set_long(config
, val
| mask
);
467 static inline uint64_t
468 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
470 uint64_t val
= pci_get_quad(config
);
471 pci_set_quad(config
, val
& ~mask
);
475 static inline uint64_t
476 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
478 uint64_t val
= pci_get_quad(config
);
479 pci_set_quad(config
, val
| mask
);
483 /* Access a register specified by a mask */
485 pci_set_byte_by_mask(uint8_t *config
, uint8_t mask
, uint8_t reg
)
487 uint8_t val
= pci_get_byte(config
);
488 uint8_t rval
= reg
<< (ffs(mask
) - 1);
489 pci_set_byte(config
, (~mask
& val
) | (mask
& rval
));
492 static inline uint8_t
493 pci_get_byte_by_mask(uint8_t *config
, uint8_t mask
)
495 uint8_t val
= pci_get_byte(config
);
496 return (val
& mask
) >> (ffs(mask
) - 1);
500 pci_set_word_by_mask(uint8_t *config
, uint16_t mask
, uint16_t reg
)
502 uint16_t val
= pci_get_word(config
);
503 uint16_t rval
= reg
<< (ffs(mask
) - 1);
504 pci_set_word(config
, (~mask
& val
) | (mask
& rval
));
507 static inline uint16_t
508 pci_get_word_by_mask(uint8_t *config
, uint16_t mask
)
510 uint16_t val
= pci_get_word(config
);
511 return (val
& mask
) >> (ffs(mask
) - 1);
515 pci_set_long_by_mask(uint8_t *config
, uint32_t mask
, uint32_t reg
)
517 uint32_t val
= pci_get_long(config
);
518 uint32_t rval
= reg
<< (ffs(mask
) - 1);
519 pci_set_long(config
, (~mask
& val
) | (mask
& rval
));
522 static inline uint32_t
523 pci_get_long_by_mask(uint8_t *config
, uint32_t mask
)
525 uint32_t val
= pci_get_long(config
);
526 return (val
& mask
) >> (ffs(mask
) - 1);
530 pci_set_quad_by_mask(uint8_t *config
, uint64_t mask
, uint64_t reg
)
532 uint64_t val
= pci_get_quad(config
);
533 uint64_t rval
= reg
<< (ffs(mask
) - 1);
534 pci_set_quad(config
, (~mask
& val
) | (mask
& rval
));
537 static inline uint64_t
538 pci_get_quad_by_mask(uint8_t *config
, uint64_t mask
)
540 uint64_t val
= pci_get_quad(config
);
541 return (val
& mask
) >> (ffs(mask
) - 1);
544 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
546 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
549 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
550 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
552 static inline int pci_is_express(const PCIDevice
*d
)
554 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
557 static inline uint32_t pci_config_size(const PCIDevice
*d
)
559 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
562 /* DMA access functions */
563 static inline int pci_dma_rw(PCIDevice
*dev
, dma_addr_t addr
,
564 void *buf
, dma_addr_t len
, DMADirection dir
)
566 cpu_physical_memory_rw(addr
, buf
, len
, dir
== DMA_DIRECTION_FROM_DEVICE
);
570 static inline int pci_dma_read(PCIDevice
*dev
, dma_addr_t addr
,
571 void *buf
, dma_addr_t len
)
573 return pci_dma_rw(dev
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
576 static inline int pci_dma_write(PCIDevice
*dev
, dma_addr_t addr
,
577 const void *buf
, dma_addr_t len
)
579 return pci_dma_rw(dev
, addr
, (void *) buf
, len
, DMA_DIRECTION_FROM_DEVICE
);
582 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
583 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
586 return ld##_l##_phys(addr); \
588 static inline void st##_s##_pci_dma(PCIDevice *dev, \
589 dma_addr_t addr, uint##_bits##_t val) \
591 st##_s##_phys(addr, val); \
594 PCI_DMA_DEFINE_LDST(ub
, b
, 8);
595 PCI_DMA_DEFINE_LDST(uw_le
, w_le
, 16)
596 PCI_DMA_DEFINE_LDST(l_le
, l_le
, 32);
597 PCI_DMA_DEFINE_LDST(q_le
, q_le
, 64);
598 PCI_DMA_DEFINE_LDST(uw_be
, w_be
, 16)
599 PCI_DMA_DEFINE_LDST(l_be
, l_be
, 32);
600 PCI_DMA_DEFINE_LDST(q_be
, q_be
, 64);
602 #undef PCI_DMA_DEFINE_LDST
604 static inline void *pci_dma_map(PCIDevice
*dev
, dma_addr_t addr
,
605 dma_addr_t
*plen
, DMADirection dir
)
607 target_phys_addr_t len
= *plen
;
610 buf
= cpu_physical_memory_map(addr
, &len
, dir
== DMA_DIRECTION_FROM_DEVICE
);
615 static inline void pci_dma_unmap(PCIDevice
*dev
, void *buffer
, dma_addr_t len
,
616 DMADirection dir
, dma_addr_t access_len
)
618 cpu_physical_memory_unmap(buffer
, len
, dir
== DMA_DIRECTION_FROM_DEVICE
,
622 static inline void pci_dma_sglist_init(QEMUSGList
*qsg
, PCIDevice
*dev
,
625 qemu_sglist_init(qsg
, alloc_hint
);
628 extern const VMStateDescription vmstate_pci_device
;
630 #define VMSTATE_PCI_DEVICE(_field, _state) { \
631 .name = (stringify(_field)), \
632 .size = sizeof(PCIDevice), \
633 .vmsd = &vmstate_pci_device, \
634 .flags = VMS_STRUCT, \
635 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
638 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
639 .name = (stringify(_field)), \
640 .size = sizeof(PCIDevice), \
641 .vmsd = &vmstate_pci_device, \
642 .flags = VMS_STRUCT|VMS_POINTER, \
643 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \