?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
move QEMUSGList typedef
[qemu/ar7.git] / hw / pxa2xx.c
blobcf9311014d81fb9294ad51ada53cdc1054df678b
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
92 {
93 PXA2xxState *s = (PXA2xxState *) opaque;
94
95 switch (addr) {
96 case PMCR ... PCMD31:
97 if (addr & 3)
98 goto fail;
99
100 return s->pm_regs[addr >> 2];
101 default:
102 fail:
103 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
104 break;
105 }
106 return 0;
107 }
108
109 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
110 uint32_t value)
111 {
112 PXA2xxState *s = (PXA2xxState *) opaque;
113
114 switch (addr) {
115 case PMCR:
116 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
117 s->pm_regs[addr >> 2] |= value & 0x15;
118 break;
119
120 case PSSR: /* Read-clean registers */
121 case RCSR:
122 case PKSR:
123 s->pm_regs[addr >> 2] &= ~value;
124 break;
125
126 default: /* Read-write registers */
127 if (!(addr & 3)) {
128 s->pm_regs[addr >> 2] = value;
129 break;
130 }
131
132 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
133 break;
134 }
135 }
136
137 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
138 pxa2xx_pm_read,
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 };
142
143 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
144 pxa2xx_pm_write,
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 };
148
149 static const VMStateDescription vmstate_pxa2xx_pm = {
150 .name = "pxa2xx_pm",
151 .version_id = 0,
152 .minimum_version_id = 0,
153 .minimum_version_id_old = 0,
154 .fields = (VMStateField[]) {
155 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
156 VMSTATE_END_OF_LIST()
157 }
158 };
159
160 #define CCCR 0x00 /* Core Clock Configuration register */
161 #define CKEN 0x04 /* Clock Enable register */
162 #define OSCC 0x08 /* Oscillator Configuration register */
163 #define CCSR 0x0c /* Core Clock Status register */
164
165 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
166 {
167 PXA2xxState *s = (PXA2xxState *) opaque;
168
169 switch (addr) {
170 case CCCR:
171 case CKEN:
172 case OSCC:
173 return s->cm_regs[addr >> 2];
174
175 case CCSR:
176 return s->cm_regs[CCCR >> 2] | (3 << 28);
177
178 default:
179 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
180 break;
181 }
182 return 0;
183 }
184
185 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
186 uint32_t value)
187 {
188 PXA2xxState *s = (PXA2xxState *) opaque;
189
190 switch (addr) {
191 case CCCR:
192 case CKEN:
193 s->cm_regs[addr >> 2] = value;
194 break;
195
196 case OSCC:
197 s->cm_regs[addr >> 2] &= ~0x6c;
198 s->cm_regs[addr >> 2] |= value & 0x6e;
199 if ((value >> 1) & 1) /* OON */
200 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
201 break;
202
203 default:
204 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
205 break;
206 }
207 }
208
209 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
210 pxa2xx_cm_read,
211 pxa2xx_cm_read,
212 pxa2xx_cm_read,
213 };
214
215 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
216 pxa2xx_cm_write,
217 pxa2xx_cm_write,
218 pxa2xx_cm_write,
219 };
220
221 static const VMStateDescription vmstate_pxa2xx_cm = {
222 .name = "pxa2xx_cm",
223 .version_id = 0,
224 .minimum_version_id = 0,
225 .minimum_version_id_old = 0,
226 .fields = (VMStateField[]) {
227 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
228 VMSTATE_UINT32(clkcfg, PXA2xxState),
229 VMSTATE_UINT32(pmnc, PXA2xxState),
230 VMSTATE_END_OF_LIST()
231 }
232 };
233
234 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
235 {
236 PXA2xxState *s = (PXA2xxState *) opaque;
237
238 switch (reg) {
239 case 6: /* Clock Configuration register */
240 return s->clkcfg;
241
242 case 7: /* Power Mode register */
243 return 0;
244
245 default:
246 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
247 break;
248 }
249 return 0;
250 }
251
252 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
253 uint32_t value)
254 {
255 PXA2xxState *s = (PXA2xxState *) opaque;
256 static const char *pwrmode[8] = {
257 "Normal", "Idle", "Deep-idle", "Standby",
258 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
259 };
260
261 switch (reg) {
262 case 6: /* Clock Configuration register */
263 s->clkcfg = value & 0xf;
264 if (value & 2)
265 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
266 break;
267
268 case 7: /* Power Mode register */
269 if (value & 8)
270 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
271 switch (value & 7) {
272 case 0:
273 /* Do nothing */
274 break;
275
276 case 1:
277 /* Idle */
278 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
279 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
280 break;
281 }
282 /* Fall through. */
283
284 case 2:
285 /* Deep-Idle */
286 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
287 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
288 goto message;
289
290 case 3:
291 s->env->uncached_cpsr =
292 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
293 s->env->cp15.c1_sys = 0;
294 s->env->cp15.c1_coproc = 0;
295 s->env->cp15.c2_base0 = 0;
296 s->env->cp15.c3 = 0;
297 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
298 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
299
300 /*
301 * The scratch-pad register is almost universally used
302 * for storing the return address on suspend. For the
303 * lack of a resuming bootloader, perform a jump
304 * directly to that address.
305 */
306 memset(s->env->regs, 0, 4 * 15);
307 s->env->regs[15] = s->pm_regs[PSPR >> 2];
308
309 #if 0
310 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
311 cpu_physical_memory_write(0, &buffer, 4);
312 buffer = s->pm_regs[PSPR >> 2];
313 cpu_physical_memory_write(8, &buffer, 4);
314 #endif
315
316 /* Suspend */
317 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
318
319 goto message;
320
321 default:
322 message:
323 printf("%s: machine entered %s mode\n", __FUNCTION__,
324 pwrmode[value & 7]);
325 }
326 break;
327
328 default:
329 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
330 break;
331 }
332 }
333
334 /* Performace Monitoring Registers */
335 #define CPPMNC 0 /* Performance Monitor Control register */
336 #define CPCCNT 1 /* Clock Counter register */
337 #define CPINTEN 4 /* Interrupt Enable register */
338 #define CPFLAG 5 /* Overflow Flag register */
339 #define CPEVTSEL 8 /* Event Selection register */
340
341 #define CPPMN0 0 /* Performance Count register 0 */
342 #define CPPMN1 1 /* Performance Count register 1 */
343 #define CPPMN2 2 /* Performance Count register 2 */
344 #define CPPMN3 3 /* Performance Count register 3 */
345
346 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
347 {
348 PXA2xxState *s = (PXA2xxState *) opaque;
349
350 switch (reg) {
351 case CPPMNC:
352 return s->pmnc;
353 case CPCCNT:
354 if (s->pmnc & 1)
355 return qemu_get_clock_ns(vm_clock);
356 else
357 return 0;
358 case CPINTEN:
359 case CPFLAG:
360 case CPEVTSEL:
361 return 0;
362
363 default:
364 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
365 break;
366 }
367 return 0;
368 }
369
370 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
371 uint32_t value)
372 {
373 PXA2xxState *s = (PXA2xxState *) opaque;
374
375 switch (reg) {
376 case CPPMNC:
377 s->pmnc = value;
378 break;
379
380 case CPCCNT:
381 case CPINTEN:
382 case CPFLAG:
383 case CPEVTSEL:
384 break;
385
386 default:
387 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
388 break;
389 }
390 }
391
392 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
393 {
394 switch (crm) {
395 case 0:
396 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
397 case 1:
398 return pxa2xx_perf_read(opaque, op2, reg, crm);
399 case 2:
400 switch (reg) {
401 case CPPMN0:
402 case CPPMN1:
403 case CPPMN2:
404 case CPPMN3:
405 return 0;
406 }
407 /* Fall through */
408 default:
409 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
410 break;
411 }
412 return 0;
413 }
414
415 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
416 uint32_t value)
417 {
418 switch (crm) {
419 case 0:
420 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
421 break;
422 case 1:
423 pxa2xx_perf_write(opaque, op2, reg, crm, value);
424 break;
425 case 2:
426 switch (reg) {
427 case CPPMN0:
428 case CPPMN1:
429 case CPPMN2:
430 case CPPMN3:
431 return;
432 }
433 /* Fall through */
434 default:
435 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
436 break;
437 }
438 }
439
440 #define MDCNFG 0x00 /* SDRAM Configuration register */
441 #define MDREFR 0x04 /* SDRAM Refresh Control register */
442 #define MSC0 0x08 /* Static Memory Control register 0 */
443 #define MSC1 0x0c /* Static Memory Control register 1 */
444 #define MSC2 0x10 /* Static Memory Control register 2 */
445 #define MECR 0x14 /* Expansion Memory Bus Config register */
446 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
447 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
448 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
449 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
450 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
451 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
452 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
453 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
454 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
455 #define ARB_CNTL 0x48 /* Arbiter Control register */
456 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
457 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
458 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
459 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
460 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
461 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
462 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
463
464 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
465 {
466 PXA2xxState *s = (PXA2xxState *) opaque;
467
468 switch (addr) {
469 case MDCNFG ... SA1110:
470 if ((addr & 3) == 0)
471 return s->mm_regs[addr >> 2];
472
473 default:
474 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
475 break;
476 }
477 return 0;
478 }
479
480 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
481 uint32_t value)
482 {
483 PXA2xxState *s = (PXA2xxState *) opaque;
484
485 switch (addr) {
486 case MDCNFG ... SA1110:
487 if ((addr & 3) == 0) {
488 s->mm_regs[addr >> 2] = value;
489 break;
490 }
491
492 default:
493 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
494 break;
495 }
496 }
497
498 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
499 pxa2xx_mm_read,
500 pxa2xx_mm_read,
501 pxa2xx_mm_read,
502 };
503
504 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
505 pxa2xx_mm_write,
506 pxa2xx_mm_write,
507 pxa2xx_mm_write,
508 };
509
510 static const VMStateDescription vmstate_pxa2xx_mm = {
511 .name = "pxa2xx_mm",
512 .version_id = 0,
513 .minimum_version_id = 0,
514 .minimum_version_id_old = 0,
515 .fields = (VMStateField[]) {
516 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
517 VMSTATE_END_OF_LIST()
518 }
519 };
520
521 /* Synchronous Serial Ports */
522 typedef struct {
523 SysBusDevice busdev;
524 qemu_irq irq;
525 int enable;
526 SSIBus *bus;
527
528 uint32_t sscr[2];
529 uint32_t sspsp;
530 uint32_t ssto;
531 uint32_t ssitr;
532 uint32_t sssr;
533 uint8_t sstsa;
534 uint8_t ssrsa;
535 uint8_t ssacd;
536
537 uint32_t rx_fifo[16];
538 int rx_level;
539 int rx_start;
540 } PXA2xxSSPState;
541
542 #define SSCR0 0x00 /* SSP Control register 0 */
543 #define SSCR1 0x04 /* SSP Control register 1 */
544 #define SSSR 0x08 /* SSP Status register */
545 #define SSITR 0x0c /* SSP Interrupt Test register */
546 #define SSDR 0x10 /* SSP Data register */
547 #define SSTO 0x28 /* SSP Time-Out register */
548 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
549 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
550 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
551 #define SSTSS 0x38 /* SSP Time Slot Status register */
552 #define SSACD 0x3c /* SSP Audio Clock Divider register */
553
554 /* Bitfields for above registers */
555 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
556 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
557 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
558 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
559 #define SSCR0_SSE (1 << 7)
560 #define SSCR0_RIM (1 << 22)
561 #define SSCR0_TIM (1 << 23)
562 #define SSCR0_MOD (1 << 31)
563 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
564 #define SSCR1_RIE (1 << 0)
565 #define SSCR1_TIE (1 << 1)
566 #define SSCR1_LBM (1 << 2)
567 #define SSCR1_MWDS (1 << 5)
568 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
569 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
570 #define SSCR1_EFWR (1 << 14)
571 #define SSCR1_PINTE (1 << 18)
572 #define SSCR1_TINTE (1 << 19)
573 #define SSCR1_RSRE (1 << 20)
574 #define SSCR1_TSRE (1 << 21)
575 #define SSCR1_EBCEI (1 << 29)
576 #define SSITR_INT (7 << 5)
577 #define SSSR_TNF (1 << 2)
578 #define SSSR_RNE (1 << 3)
579 #define SSSR_TFS (1 << 5)
580 #define SSSR_RFS (1 << 6)
581 #define SSSR_ROR (1 << 7)
582 #define SSSR_PINT (1 << 18)
583 #define SSSR_TINT (1 << 19)
584 #define SSSR_EOC (1 << 20)
585 #define SSSR_TUR (1 << 21)
586 #define SSSR_BCE (1 << 23)
587 #define SSSR_RW 0x00bc0080
588
589 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
590 {
591 int level = 0;
592
593 level |= s->ssitr & SSITR_INT;
594 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
595 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
596 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
597 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
598 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
599 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
600 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
601 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
602 qemu_set_irq(s->irq, !!level);
603 }
604
605 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
606 {
607 s->sssr &= ~(0xf << 12); /* Clear RFL */
608 s->sssr &= ~(0xf << 8); /* Clear TFL */
609 s->sssr &= ~SSSR_TFS;
610 s->sssr &= ~SSSR_TNF;
611 if (s->enable) {
612 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
613 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
614 s->sssr |= SSSR_RFS;
615 else
616 s->sssr &= ~SSSR_RFS;
617 if (s->rx_level)
618 s->sssr |= SSSR_RNE;
619 else
620 s->sssr &= ~SSSR_RNE;
621 /* TX FIFO is never filled, so it is always in underrun
622 condition if SSP is enabled */
623 s->sssr |= SSSR_TFS;
624 s->sssr |= SSSR_TNF;
625 }
626
627 pxa2xx_ssp_int_update(s);
628 }
629
630 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
631 {
632 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
633 uint32_t retval;
634
635 switch (addr) {
636 case SSCR0:
637 return s->sscr[0];
638 case SSCR1:
639 return s->sscr[1];
640 case SSPSP:
641 return s->sspsp;
642 case SSTO:
643 return s->ssto;
644 case SSITR:
645 return s->ssitr;
646 case SSSR:
647 return s->sssr | s->ssitr;
648 case SSDR:
649 if (!s->enable)
650 return 0xffffffff;
651 if (s->rx_level < 1) {
652 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
653 return 0xffffffff;
654 }
655 s->rx_level --;
656 retval = s->rx_fifo[s->rx_start ++];
657 s->rx_start &= 0xf;
658 pxa2xx_ssp_fifo_update(s);
659 return retval;
660 case SSTSA:
661 return s->sstsa;
662 case SSRSA:
663 return s->ssrsa;
664 case SSTSS:
665 return 0;
666 case SSACD:
667 return s->ssacd;
668 default:
669 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
670 break;
671 }
672 return 0;
673 }
674
675 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
676 uint32_t value)
677 {
678 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
679
680 switch (addr) {
681 case SSCR0:
682 s->sscr[0] = value & 0xc7ffffff;
683 s->enable = value & SSCR0_SSE;
684 if (value & SSCR0_MOD)
685 printf("%s: Attempt to use network mode\n", __FUNCTION__);
686 if (s->enable && SSCR0_DSS(value) < 4)
687 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
688 SSCR0_DSS(value));
689 if (!(value & SSCR0_SSE)) {
690 s->sssr = 0;
691 s->ssitr = 0;
692 s->rx_level = 0;
693 }
694 pxa2xx_ssp_fifo_update(s);
695 break;
696
697 case SSCR1:
698 s->sscr[1] = value;
699 if (value & (SSCR1_LBM | SSCR1_EFWR))
700 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
701 pxa2xx_ssp_fifo_update(s);
702 break;
703
704 case SSPSP:
705 s->sspsp = value;
706 break;
707
708 case SSTO:
709 s->ssto = value;
710 break;
711
712 case SSITR:
713 s->ssitr = value & SSITR_INT;
714 pxa2xx_ssp_int_update(s);
715 break;
716
717 case SSSR:
718 s->sssr &= ~(value & SSSR_RW);
719 pxa2xx_ssp_int_update(s);
720 break;
721
722 case SSDR:
723 if (SSCR0_UWIRE(s->sscr[0])) {
724 if (s->sscr[1] & SSCR1_MWDS)
725 value &= 0xffff;
726 else
727 value &= 0xff;
728 } else
729 /* Note how 32bits overflow does no harm here */
730 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
731
732 /* Data goes from here to the Tx FIFO and is shifted out from
733 * there directly to the slave, no need to buffer it.
734 */
735 if (s->enable) {
736 uint32_t readval;
737 readval = ssi_transfer(s->bus, value);
738 if (s->rx_level < 0x10) {
739 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
740 } else {
741 s->sssr |= SSSR_ROR;
742 }
743 }
744 pxa2xx_ssp_fifo_update(s);
745 break;
746
747 case SSTSA:
748 s->sstsa = value;
749 break;
750
751 case SSRSA:
752 s->ssrsa = value;
753 break;
754
755 case SSACD:
756 s->ssacd = value;
757 break;
758
759 default:
760 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
761 break;
762 }
763 }
764
765 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
766 pxa2xx_ssp_read,
767 pxa2xx_ssp_read,
768 pxa2xx_ssp_read,
769 };
770
771 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
772 pxa2xx_ssp_write,
773 pxa2xx_ssp_write,
774 pxa2xx_ssp_write,
775 };
776
777 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
778 {
779 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
780 int i;
781
782 qemu_put_be32(f, s->enable);
783
784 qemu_put_be32s(f, &s->sscr[0]);
785 qemu_put_be32s(f, &s->sscr[1]);
786 qemu_put_be32s(f, &s->sspsp);
787 qemu_put_be32s(f, &s->ssto);
788 qemu_put_be32s(f, &s->ssitr);
789 qemu_put_be32s(f, &s->sssr);
790 qemu_put_8s(f, &s->sstsa);
791 qemu_put_8s(f, &s->ssrsa);
792 qemu_put_8s(f, &s->ssacd);
793
794 qemu_put_byte(f, s->rx_level);
795 for (i = 0; i < s->rx_level; i ++)
796 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
797 }
798
799 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
800 {
801 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
802 int i;
803
804 s->enable = qemu_get_be32(f);
805
806 qemu_get_be32s(f, &s->sscr[0]);
807 qemu_get_be32s(f, &s->sscr[1]);
808 qemu_get_be32s(f, &s->sspsp);
809 qemu_get_be32s(f, &s->ssto);
810 qemu_get_be32s(f, &s->ssitr);
811 qemu_get_be32s(f, &s->sssr);
812 qemu_get_8s(f, &s->sstsa);
813 qemu_get_8s(f, &s->ssrsa);
814 qemu_get_8s(f, &s->ssacd);
815
816 s->rx_level = qemu_get_byte(f);
817 s->rx_start = 0;
818 for (i = 0; i < s->rx_level; i ++)
819 s->rx_fifo[i] = qemu_get_byte(f);
820
821 return 0;
822 }
823
824 static int pxa2xx_ssp_init(SysBusDevice *dev)
825 {
826 int iomemtype;
827 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
828
829 sysbus_init_irq(dev, &s->irq);
830
831 iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
832 pxa2xx_ssp_writefn, s,
833 DEVICE_NATIVE_ENDIAN);
834 sysbus_init_mmio(dev, 0x1000, iomemtype);
835 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
836 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
837
838 s->bus = ssi_create_bus(&dev->qdev, "ssi");
839 return 0;
840 }
841
842 /* Real-Time Clock */
843 #define RCNR 0x00 /* RTC Counter register */
844 #define RTAR 0x04 /* RTC Alarm register */
845 #define RTSR 0x08 /* RTC Status register */
846 #define RTTR 0x0c /* RTC Timer Trim register */
847 #define RDCR 0x10 /* RTC Day Counter register */
848 #define RYCR 0x14 /* RTC Year Counter register */
849 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
850 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
851 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
852 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
853 #define SWCR 0x28 /* RTC Stopwatch Counter register */
854 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
855 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
856 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
857 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
858
859 typedef struct {
860 SysBusDevice busdev;
861 uint32_t rttr;
862 uint32_t rtsr;
863 uint32_t rtar;
864 uint32_t rdar1;
865 uint32_t rdar2;
866 uint32_t ryar1;
867 uint32_t ryar2;
868 uint32_t swar1;
869 uint32_t swar2;
870 uint32_t piar;
871 uint32_t last_rcnr;
872 uint32_t last_rdcr;
873 uint32_t last_rycr;
874 uint32_t last_swcr;
875 uint32_t last_rtcpicr;
876 int64_t last_hz;
877 int64_t last_sw;
878 int64_t last_pi;
879 QEMUTimer *rtc_hz;
880 QEMUTimer *rtc_rdal1;
881 QEMUTimer *rtc_rdal2;
882 QEMUTimer *rtc_swal1;
883 QEMUTimer *rtc_swal2;
884 QEMUTimer *rtc_pi;
885 qemu_irq rtc_irq;
886 } PXA2xxRTCState;
887
888 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
889 {
890 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
891 }
892
893 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
894 {
895 int64_t rt = qemu_get_clock_ms(rt_clock);
896 s->last_rcnr += ((rt - s->last_hz) << 15) /
897 (1000 * ((s->rttr & 0xffff) + 1));
898 s->last_rdcr += ((rt - s->last_hz) << 15) /
899 (1000 * ((s->rttr & 0xffff) + 1));
900 s->last_hz = rt;
901 }
902
903 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
904 {
905 int64_t rt = qemu_get_clock_ms(rt_clock);
906 if (s->rtsr & (1 << 12))
907 s->last_swcr += (rt - s->last_sw) / 10;
908 s->last_sw = rt;
909 }
910
911 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
912 {
913 int64_t rt = qemu_get_clock_ms(rt_clock);
914 if (s->rtsr & (1 << 15))
915 s->last_swcr += rt - s->last_pi;
916 s->last_pi = rt;
917 }
918
919 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
920 uint32_t rtsr)
921 {
922 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
923 qemu_mod_timer(s->rtc_hz, s->last_hz +
924 (((s->rtar - s->last_rcnr) * 1000 *
925 ((s->rttr & 0xffff) + 1)) >> 15));
926 else
927 qemu_del_timer(s->rtc_hz);
928
929 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
930 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
931 (((s->rdar1 - s->last_rdcr) * 1000 *
932 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
933 else
934 qemu_del_timer(s->rtc_rdal1);
935
936 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
937 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
938 (((s->rdar2 - s->last_rdcr) * 1000 *
939 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
940 else
941 qemu_del_timer(s->rtc_rdal2);
942
943 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
944 qemu_mod_timer(s->rtc_swal1, s->last_sw +
945 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
946 else
947 qemu_del_timer(s->rtc_swal1);
948
949 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
950 qemu_mod_timer(s->rtc_swal2, s->last_sw +
951 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
952 else
953 qemu_del_timer(s->rtc_swal2);
954
955 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
956 qemu_mod_timer(s->rtc_pi, s->last_pi +
957 (s->piar & 0xffff) - s->last_rtcpicr);
958 else
959 qemu_del_timer(s->rtc_pi);
960 }
961
962 static inline void pxa2xx_rtc_hz_tick(void *opaque)
963 {
964 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
965 s->rtsr |= (1 << 0);
966 pxa2xx_rtc_alarm_update(s, s->rtsr);
967 pxa2xx_rtc_int_update(s);
968 }
969
970 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
971 {
972 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
973 s->rtsr |= (1 << 4);
974 pxa2xx_rtc_alarm_update(s, s->rtsr);
975 pxa2xx_rtc_int_update(s);
976 }
977
978 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
979 {
980 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
981 s->rtsr |= (1 << 6);
982 pxa2xx_rtc_alarm_update(s, s->rtsr);
983 pxa2xx_rtc_int_update(s);
984 }
985
986 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
987 {
988 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
989 s->rtsr |= (1 << 8);
990 pxa2xx_rtc_alarm_update(s, s->rtsr);
991 pxa2xx_rtc_int_update(s);
992 }
993
994 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
995 {
996 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
997 s->rtsr |= (1 << 10);
998 pxa2xx_rtc_alarm_update(s, s->rtsr);
999 pxa2xx_rtc_int_update(s);
1000 }
1001
1002 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1003 {
1004 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1005 s->rtsr |= (1 << 13);
1006 pxa2xx_rtc_piupdate(s);
1007 s->last_rtcpicr = 0;
1008 pxa2xx_rtc_alarm_update(s, s->rtsr);
1009 pxa2xx_rtc_int_update(s);
1010 }
1011
1012 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1013 {
1014 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1015
1016 switch (addr) {
1017 case RTTR:
1018 return s->rttr;
1019 case RTSR:
1020 return s->rtsr;
1021 case RTAR:
1022 return s->rtar;
1023 case RDAR1:
1024 return s->rdar1;
1025 case RDAR2:
1026 return s->rdar2;
1027 case RYAR1:
1028 return s->ryar1;
1029 case RYAR2:
1030 return s->ryar2;
1031 case SWAR1:
1032 return s->swar1;
1033 case SWAR2:
1034 return s->swar2;
1035 case PIAR:
1036 return s->piar;
1037 case RCNR:
1038 return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1039 (1000 * ((s->rttr & 0xffff) + 1));
1040 case RDCR:
1041 return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1042 (1000 * ((s->rttr & 0xffff) + 1));
1043 case RYCR:
1044 return s->last_rycr;
1045 case SWCR:
1046 if (s->rtsr & (1 << 12))
1047 return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
1048 else
1049 return s->last_swcr;
1050 default:
1051 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1052 break;
1053 }
1054 return 0;
1055 }
1056
1057 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1058 uint32_t value)
1059 {
1060 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1061
1062 switch (addr) {
1063 case RTTR:
1064 if (!(s->rttr & (1 << 31))) {
1065 pxa2xx_rtc_hzupdate(s);
1066 s->rttr = value;
1067 pxa2xx_rtc_alarm_update(s, s->rtsr);
1068 }
1069 break;
1070
1071 case RTSR:
1072 if ((s->rtsr ^ value) & (1 << 15))
1073 pxa2xx_rtc_piupdate(s);
1074
1075 if ((s->rtsr ^ value) & (1 << 12))
1076 pxa2xx_rtc_swupdate(s);
1077
1078 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1079 pxa2xx_rtc_alarm_update(s, value);
1080
1081 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1082 pxa2xx_rtc_int_update(s);
1083 break;
1084
1085 case RTAR:
1086 s->rtar = value;
1087 pxa2xx_rtc_alarm_update(s, s->rtsr);
1088 break;
1089
1090 case RDAR1:
1091 s->rdar1 = value;
1092 pxa2xx_rtc_alarm_update(s, s->rtsr);
1093 break;
1094
1095 case RDAR2:
1096 s->rdar2 = value;
1097 pxa2xx_rtc_alarm_update(s, s->rtsr);
1098 break;
1099
1100 case RYAR1:
1101 s->ryar1 = value;
1102 pxa2xx_rtc_alarm_update(s, s->rtsr);
1103 break;
1104
1105 case RYAR2:
1106 s->ryar2 = value;
1107 pxa2xx_rtc_alarm_update(s, s->rtsr);
1108 break;
1109
1110 case SWAR1:
1111 pxa2xx_rtc_swupdate(s);
1112 s->swar1 = value;
1113 s->last_swcr = 0;
1114 pxa2xx_rtc_alarm_update(s, s->rtsr);
1115 break;
1116
1117 case SWAR2:
1118 s->swar2 = value;
1119 pxa2xx_rtc_alarm_update(s, s->rtsr);
1120 break;
1121
1122 case PIAR:
1123 s->piar = value;
1124 pxa2xx_rtc_alarm_update(s, s->rtsr);
1125 break;
1126
1127 case RCNR:
1128 pxa2xx_rtc_hzupdate(s);
1129 s->last_rcnr = value;
1130 pxa2xx_rtc_alarm_update(s, s->rtsr);
1131 break;
1132
1133 case RDCR:
1134 pxa2xx_rtc_hzupdate(s);
1135 s->last_rdcr = value;
1136 pxa2xx_rtc_alarm_update(s, s->rtsr);
1137 break;
1138
1139 case RYCR:
1140 s->last_rycr = value;
1141 break;
1142
1143 case SWCR:
1144 pxa2xx_rtc_swupdate(s);
1145 s->last_swcr = value;
1146 pxa2xx_rtc_alarm_update(s, s->rtsr);
1147 break;
1148
1149 case RTCPICR:
1150 pxa2xx_rtc_piupdate(s);
1151 s->last_rtcpicr = value & 0xffff;
1152 pxa2xx_rtc_alarm_update(s, s->rtsr);
1153 break;
1154
1155 default:
1156 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1157 }
1158 }
1159
1160 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1161 pxa2xx_rtc_read,
1162 pxa2xx_rtc_read,
1163 pxa2xx_rtc_read,
1164 };
1165
1166 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1167 pxa2xx_rtc_write,
1168 pxa2xx_rtc_write,
1169 pxa2xx_rtc_write,
1170 };
1171
1172 static int pxa2xx_rtc_init(SysBusDevice *dev)
1173 {
1174 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1175 struct tm tm;
1176 int wom;
1177 int iomemtype;
1178
1179 s->rttr = 0x7fff;
1180 s->rtsr = 0;
1181
1182 qemu_get_timedate(&tm, 0);
1183 wom = ((tm.tm_mday - 1) / 7) + 1;
1184
1185 s->last_rcnr = (uint32_t) mktimegm(&tm);
1186 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1187 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1188 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1189 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1190 s->last_swcr = (tm.tm_hour << 19) |
1191 (tm.tm_min << 13) | (tm.tm_sec << 7);
1192 s->last_rtcpicr = 0;
1193 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
1194
1195 s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
1196 s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1197 s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1198 s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
1199 s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
1200 s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
1201
1202 sysbus_init_irq(dev, &s->rtc_irq);
1203
1204 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
1205 pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
1206 sysbus_init_mmio(dev, 0x10000, iomemtype);
1207
1208 return 0;
1209 }
1210
1211 static void pxa2xx_rtc_pre_save(void *opaque)
1212 {
1213 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1214
1215 pxa2xx_rtc_hzupdate(s);
1216 pxa2xx_rtc_piupdate(s);
1217 pxa2xx_rtc_swupdate(s);
1218 }
1219
1220 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1221 {
1222 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1223
1224 pxa2xx_rtc_alarm_update(s, s->rtsr);
1225
1226 return 0;
1227 }
1228
1229 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1230 .name = "pxa2xx_rtc",
1231 .version_id = 0,
1232 .minimum_version_id = 0,
1233 .minimum_version_id_old = 0,
1234 .pre_save = pxa2xx_rtc_pre_save,
1235 .post_load = pxa2xx_rtc_post_load,
1236 .fields = (VMStateField[]) {
1237 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1238 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1239 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1240 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1241 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1242 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1243 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1244 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1245 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1246 VMSTATE_UINT32(piar, PXA2xxRTCState),
1247 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1248 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1249 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1250 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1251 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1252 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1253 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1254 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1255 VMSTATE_END_OF_LIST(),
1256 },
1257 };
1258
1259 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info = {
1260 .init = pxa2xx_rtc_init,
1261 .qdev.name = "pxa2xx_rtc",
1262 .qdev.desc = "PXA2xx RTC Controller",
1263 .qdev.size = sizeof(PXA2xxRTCState),
1264 .qdev.vmsd = &vmstate_pxa2xx_rtc_regs,
1265 };
1266
1267 /* I2C Interface */
1268 typedef struct {
1269 i2c_slave i2c;
1270 PXA2xxI2CState *host;
1271 } PXA2xxI2CSlaveState;
1272
1273 struct PXA2xxI2CState {
1274 SysBusDevice busdev;
1275 PXA2xxI2CSlaveState *slave;
1276 i2c_bus *bus;
1277 qemu_irq irq;
1278 uint32_t offset;
1279 uint32_t region_size;
1280
1281 uint16_t control;
1282 uint16_t status;
1283 uint8_t ibmr;
1284 uint8_t data;
1285 };
1286
1287 #define IBMR 0x80 /* I2C Bus Monitor register */
1288 #define IDBR 0x88 /* I2C Data Buffer register */
1289 #define ICR 0x90 /* I2C Control register */
1290 #define ISR 0x98 /* I2C Status register */
1291 #define ISAR 0xa0 /* I2C Slave Address register */
1292
1293 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1294 {
1295 uint16_t level = 0;
1296 level |= s->status & s->control & (1 << 10); /* BED */
1297 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1298 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1299 level |= s->status & (1 << 9); /* SAD */
1300 qemu_set_irq(s->irq, !!level);
1301 }
1302
1303 /* These are only stubs now. */
1304 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1305 {
1306 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1307 PXA2xxI2CState *s = slave->host;
1308
1309 switch (event) {
1310 case I2C_START_SEND:
1311 s->status |= (1 << 9); /* set SAD */
1312 s->status &= ~(1 << 0); /* clear RWM */
1313 break;
1314 case I2C_START_RECV:
1315 s->status |= (1 << 9); /* set SAD */
1316 s->status |= 1 << 0; /* set RWM */
1317 break;
1318 case I2C_FINISH:
1319 s->status |= (1 << 4); /* set SSD */
1320 break;
1321 case I2C_NACK:
1322 s->status |= 1 << 1; /* set ACKNAK */
1323 break;
1324 }
1325 pxa2xx_i2c_update(s);
1326 }
1327
1328 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1329 {
1330 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1331 PXA2xxI2CState *s = slave->host;
1332 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1333 return 0;
1334
1335 if (s->status & (1 << 0)) { /* RWM */
1336 s->status |= 1 << 6; /* set ITE */
1337 }
1338 pxa2xx_i2c_update(s);
1339
1340 return s->data;
1341 }
1342
1343 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1344 {
1345 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1346 PXA2xxI2CState *s = slave->host;
1347 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1348 return 1;
1349
1350 if (!(s->status & (1 << 0))) { /* RWM */
1351 s->status |= 1 << 7; /* set IRF */
1352 s->data = data;
1353 }
1354 pxa2xx_i2c_update(s);
1355
1356 return 1;
1357 }
1358
1359 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1360 {
1361 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1362
1363 addr -= s->offset;
1364 switch (addr) {
1365 case ICR:
1366 return s->control;
1367 case ISR:
1368 return s->status | (i2c_bus_busy(s->bus) << 2);
1369 case ISAR:
1370 return s->slave->i2c.address;
1371 case IDBR:
1372 return s->data;
1373 case IBMR:
1374 if (s->status & (1 << 2))
1375 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1376 else
1377 s->ibmr = 0;
1378 return s->ibmr;
1379 default:
1380 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1381 break;
1382 }
1383 return 0;
1384 }
1385
1386 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1387 uint32_t value)
1388 {
1389 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1390 int ack;
1391
1392 addr -= s->offset;
1393 switch (addr) {
1394 case ICR:
1395 s->control = value & 0xfff7;
1396 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1397 /* TODO: slave mode */
1398 if (value & (1 << 0)) { /* START condition */
1399 if (s->data & 1)
1400 s->status |= 1 << 0; /* set RWM */
1401 else
1402 s->status &= ~(1 << 0); /* clear RWM */
1403 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1404 } else {
1405 if (s->status & (1 << 0)) { /* RWM */
1406 s->data = i2c_recv(s->bus);
1407 if (value & (1 << 2)) /* ACKNAK */
1408 i2c_nack(s->bus);
1409 ack = 1;
1410 } else
1411 ack = !i2c_send(s->bus, s->data);
1412 }
1413
1414 if (value & (1 << 1)) /* STOP condition */
1415 i2c_end_transfer(s->bus);
1416
1417 if (ack) {
1418 if (value & (1 << 0)) /* START condition */
1419 s->status |= 1 << 6; /* set ITE */
1420 else
1421 if (s->status & (1 << 0)) /* RWM */
1422 s->status |= 1 << 7; /* set IRF */
1423 else
1424 s->status |= 1 << 6; /* set ITE */
1425 s->status &= ~(1 << 1); /* clear ACKNAK */
1426 } else {
1427 s->status |= 1 << 6; /* set ITE */
1428 s->status |= 1 << 10; /* set BED */
1429 s->status |= 1 << 1; /* set ACKNAK */
1430 }
1431 }
1432 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1433 if (value & (1 << 4)) /* MA */
1434 i2c_end_transfer(s->bus);
1435 pxa2xx_i2c_update(s);
1436 break;
1437
1438 case ISR:
1439 s->status &= ~(value & 0x07f0);
1440 pxa2xx_i2c_update(s);
1441 break;
1442
1443 case ISAR:
1444 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1445 break;
1446
1447 case IDBR:
1448 s->data = value & 0xff;
1449 break;
1450
1451 default:
1452 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1453 }
1454 }
1455
1456 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1457 pxa2xx_i2c_read,
1458 pxa2xx_i2c_read,
1459 pxa2xx_i2c_read,
1460 };
1461
1462 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1463 pxa2xx_i2c_write,
1464 pxa2xx_i2c_write,
1465 pxa2xx_i2c_write,
1466 };
1467
1468 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1469 .name = "pxa2xx_i2c_slave",
1470 .version_id = 1,
1471 .minimum_version_id = 1,
1472 .minimum_version_id_old = 1,
1473 .fields = (VMStateField []) {
1474 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1475 VMSTATE_END_OF_LIST()
1476 }
1477 };
1478
1479 static const VMStateDescription vmstate_pxa2xx_i2c = {
1480 .name = "pxa2xx_i2c",
1481 .version_id = 1,
1482 .minimum_version_id = 1,
1483 .minimum_version_id_old = 1,
1484 .fields = (VMStateField []) {
1485 VMSTATE_UINT16(control, PXA2xxI2CState),
1486 VMSTATE_UINT16(status, PXA2xxI2CState),
1487 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1488 VMSTATE_UINT8(data, PXA2xxI2CState),
1489 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1490 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1491 VMSTATE_END_OF_LIST()
1492 }
1493 };
1494
1495 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1496 {
1497 /* Nothing to do. */
1498 return 0;
1499 }
1500
1501 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1502 .qdev.name = "pxa2xx-i2c-slave",
1503 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1504 .init = pxa2xx_i2c_slave_init,
1505 .event = pxa2xx_i2c_event,
1506 .recv = pxa2xx_i2c_rx,
1507 .send = pxa2xx_i2c_tx
1508 };
1509
1510 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1511 qemu_irq irq, uint32_t region_size)
1512 {
1513 DeviceState *dev;
1514 SysBusDevice *i2c_dev;
1515 PXA2xxI2CState *s;
1516
1517 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1518 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1519 qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
1520 base - (base & (~region_size) & TARGET_PAGE_MASK));
1521
1522 qdev_init_nofail(&i2c_dev->qdev);
1523
1524 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1525 sysbus_connect_irq(i2c_dev, 0, irq);
1526
1527 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1528 /* FIXME: Should the slave device really be on a separate bus? */
1529 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1530 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1531 s->slave->host = s;
1532
1533 return s;
1534 }
1535
1536 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1537 {
1538 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1539 int iomemtype;
1540
1541 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1542
1543 iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1544 pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
1545 sysbus_init_mmio(dev, s->region_size, iomemtype);
1546 sysbus_init_irq(dev, &s->irq);
1547
1548 return 0;
1549 }
1550
1551 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1552 {
1553 return s->bus;
1554 }
1555
1556 static SysBusDeviceInfo pxa2xx_i2c_info = {
1557 .init = pxa2xx_i2c_initfn,
1558 .qdev.name = "pxa2xx_i2c",
1559 .qdev.desc = "PXA2xx I2C Bus Controller",
1560 .qdev.size = sizeof(PXA2xxI2CState),
1561 .qdev.vmsd = &vmstate_pxa2xx_i2c,
1562 .qdev.props = (Property[]) {
1563 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1564 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1565 DEFINE_PROP_END_OF_LIST(),
1566 },
1567 };
1568
1569 /* PXA Inter-IC Sound Controller */
1570 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1571 {
1572 i2s->rx_len = 0;
1573 i2s->tx_len = 0;
1574 i2s->fifo_len = 0;
1575 i2s->clk = 0x1a;
1576 i2s->control[0] = 0x00;
1577 i2s->control[1] = 0x00;
1578 i2s->status = 0x00;
1579 i2s->mask = 0x00;
1580 }
1581
1582 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1583 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1584 #define SACR_DREC(val) (val & (1 << 3))
1585 #define SACR_DPRL(val) (val & (1 << 4))
1586
1587 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1588 {
1589 int rfs, tfs;
1590 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1591 !SACR_DREC(i2s->control[1]);
1592 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1593 i2s->enable && !SACR_DPRL(i2s->control[1]);
1594
1595 qemu_set_irq(i2s->rx_dma, rfs);
1596 qemu_set_irq(i2s->tx_dma, tfs);
1597
1598 i2s->status &= 0xe0;
1599 if (i2s->fifo_len < 16 || !i2s->enable)
1600 i2s->status |= 1 << 0; /* TNF */
1601 if (i2s->rx_len)
1602 i2s->status |= 1 << 1; /* RNE */
1603 if (i2s->enable)
1604 i2s->status |= 1 << 2; /* BSY */
1605 if (tfs)
1606 i2s->status |= 1 << 3; /* TFS */
1607 if (rfs)
1608 i2s->status |= 1 << 4; /* RFS */
1609 if (!(i2s->tx_len && i2s->enable))
1610 i2s->status |= i2s->fifo_len << 8; /* TFL */
1611 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1612
1613 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1614 }
1615
1616 #define SACR0 0x00 /* Serial Audio Global Control register */
1617 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1618 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1619 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1620 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1621 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1622 #define SADR 0x80 /* Serial Audio Data register */
1623
1624 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1625 {
1626 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1627
1628 switch (addr) {
1629 case SACR0:
1630 return s->control[0];
1631 case SACR1:
1632 return s->control[1];
1633 case SASR0:
1634 return s->status;
1635 case SAIMR:
1636 return s->mask;
1637 case SAICR:
1638 return 0;
1639 case SADIV:
1640 return s->clk;
1641 case SADR:
1642 if (s->rx_len > 0) {
1643 s->rx_len --;
1644 pxa2xx_i2s_update(s);
1645 return s->codec_in(s->opaque);
1646 }
1647 return 0;
1648 default:
1649 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1650 break;
1651 }
1652 return 0;
1653 }
1654
1655 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1656 uint32_t value)
1657 {
1658 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1659 uint32_t *sample;
1660
1661 switch (addr) {
1662 case SACR0:
1663 if (value & (1 << 3)) /* RST */
1664 pxa2xx_i2s_reset(s);
1665 s->control[0] = value & 0xff3d;
1666 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1667 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1668 s->codec_out(s->opaque, *sample);
1669 s->status &= ~(1 << 7); /* I2SOFF */
1670 }
1671 if (value & (1 << 4)) /* EFWR */
1672 printf("%s: Attempt to use special function\n", __FUNCTION__);
1673 s->enable = (value & 9) == 1; /* ENB && !RST*/
1674 pxa2xx_i2s_update(s);
1675 break;
1676 case SACR1:
1677 s->control[1] = value & 0x0039;
1678 if (value & (1 << 5)) /* ENLBF */
1679 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1680 if (value & (1 << 4)) /* DPRL */
1681 s->fifo_len = 0;
1682 pxa2xx_i2s_update(s);
1683 break;
1684 case SAIMR:
1685 s->mask = value & 0x0078;
1686 pxa2xx_i2s_update(s);
1687 break;
1688 case SAICR:
1689 s->status &= ~(value & (3 << 5));
1690 pxa2xx_i2s_update(s);
1691 break;
1692 case SADIV:
1693 s->clk = value & 0x007f;
1694 break;
1695 case SADR:
1696 if (s->tx_len && s->enable) {
1697 s->tx_len --;
1698 pxa2xx_i2s_update(s);
1699 s->codec_out(s->opaque, value);
1700 } else if (s->fifo_len < 16) {
1701 s->fifo[s->fifo_len ++] = value;
1702 pxa2xx_i2s_update(s);
1703 }
1704 break;
1705 default:
1706 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1707 }
1708 }
1709
1710 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1711 pxa2xx_i2s_read,
1712 pxa2xx_i2s_read,
1713 pxa2xx_i2s_read,
1714 };
1715
1716 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1717 pxa2xx_i2s_write,
1718 pxa2xx_i2s_write,
1719 pxa2xx_i2s_write,
1720 };
1721
1722 static const VMStateDescription vmstate_pxa2xx_i2s = {
1723 .name = "pxa2xx_i2s",
1724 .version_id = 0,
1725 .minimum_version_id = 0,
1726 .minimum_version_id_old = 0,
1727 .fields = (VMStateField[]) {
1728 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1729 VMSTATE_UINT32(status, PXA2xxI2SState),
1730 VMSTATE_UINT32(mask, PXA2xxI2SState),
1731 VMSTATE_UINT32(clk, PXA2xxI2SState),
1732 VMSTATE_INT32(enable, PXA2xxI2SState),
1733 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1734 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1735 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1736 VMSTATE_END_OF_LIST()
1737 }
1738 };
1739
1740 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1741 {
1742 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1743 uint32_t *sample;
1744
1745 /* Signal FIFO errors */
1746 if (s->enable && s->tx_len)
1747 s->status |= 1 << 5; /* TUR */
1748 if (s->enable && s->rx_len)
1749 s->status |= 1 << 6; /* ROR */
1750
1751 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1752 * handle the cases where it makes a difference. */
1753 s->tx_len = tx - s->fifo_len;
1754 s->rx_len = rx;
1755 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1756 if (s->enable)
1757 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1758 s->codec_out(s->opaque, *sample);
1759 pxa2xx_i2s_update(s);
1760 }
1761
1762 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1763 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1764 {
1765 int iomemtype;
1766 PXA2xxI2SState *s = (PXA2xxI2SState *)
1767 qemu_mallocz(sizeof(PXA2xxI2SState));
1768
1769 s->irq = irq;
1770 s->rx_dma = rx_dma;
1771 s->tx_dma = tx_dma;
1772 s->data_req = pxa2xx_i2s_data_req;
1773
1774 pxa2xx_i2s_reset(s);
1775
1776 iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1777 pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
1778 cpu_register_physical_memory(base, 0x100000, iomemtype);
1779
1780 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1781
1782 return s;
1783 }
1784
1785 /* PXA Fast Infra-red Communications Port */
1786 struct PXA2xxFIrState {
1787 qemu_irq irq;
1788 qemu_irq rx_dma;
1789 qemu_irq tx_dma;
1790 int enable;
1791 CharDriverState *chr;
1792
1793 uint8_t control[3];
1794 uint8_t status[2];
1795
1796 int rx_len;
1797 int rx_start;
1798 uint8_t rx_fifo[64];
1799 };
1800
1801 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1802 {
1803 s->control[0] = 0x00;
1804 s->control[1] = 0x00;
1805 s->control[2] = 0x00;
1806 s->status[0] = 0x00;
1807 s->status[1] = 0x00;
1808 s->enable = 0;
1809 }
1810
1811 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1812 {
1813 static const int tresh[4] = { 8, 16, 32, 0 };
1814 int intr = 0;
1815 if ((s->control[0] & (1 << 4)) && /* RXE */
1816 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1817 s->status[0] |= 1 << 4; /* RFS */
1818 else
1819 s->status[0] &= ~(1 << 4); /* RFS */
1820 if (s->control[0] & (1 << 3)) /* TXE */
1821 s->status[0] |= 1 << 3; /* TFS */
1822 else
1823 s->status[0] &= ~(1 << 3); /* TFS */
1824 if (s->rx_len)
1825 s->status[1] |= 1 << 2; /* RNE */
1826 else
1827 s->status[1] &= ~(1 << 2); /* RNE */
1828 if (s->control[0] & (1 << 4)) /* RXE */
1829 s->status[1] |= 1 << 0; /* RSY */
1830 else
1831 s->status[1] &= ~(1 << 0); /* RSY */
1832
1833 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1834 (s->status[0] & (1 << 4)); /* RFS */
1835 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1836 (s->status[0] & (1 << 3)); /* TFS */
1837 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1838 (s->status[0] & (1 << 6)); /* EOC */
1839 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1840 (s->status[0] & (1 << 1)); /* TUR */
1841 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1842
1843 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1844 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1845
1846 qemu_set_irq(s->irq, intr && s->enable);
1847 }
1848
1849 #define ICCR0 0x00 /* FICP Control register 0 */
1850 #define ICCR1 0x04 /* FICP Control register 1 */
1851 #define ICCR2 0x08 /* FICP Control register 2 */
1852 #define ICDR 0x0c /* FICP Data register */
1853 #define ICSR0 0x14 /* FICP Status register 0 */
1854 #define ICSR1 0x18 /* FICP Status register 1 */
1855 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1856
1857 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1858 {
1859 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1860 uint8_t ret;
1861
1862 switch (addr) {
1863 case ICCR0:
1864 return s->control[0];
1865 case ICCR1:
1866 return s->control[1];
1867 case ICCR2:
1868 return s->control[2];
1869 case ICDR:
1870 s->status[0] &= ~0x01;
1871 s->status[1] &= ~0x72;
1872 if (s->rx_len) {
1873 s->rx_len --;
1874 ret = s->rx_fifo[s->rx_start ++];
1875 s->rx_start &= 63;
1876 pxa2xx_fir_update(s);
1877 return ret;
1878 }
1879 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1880 break;
1881 case ICSR0:
1882 return s->status[0];
1883 case ICSR1:
1884 return s->status[1] | (1 << 3); /* TNF */
1885 case ICFOR:
1886 return s->rx_len;
1887 default:
1888 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1889 break;
1890 }
1891 return 0;
1892 }
1893
1894 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1895 uint32_t value)
1896 {
1897 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1898 uint8_t ch;
1899
1900 switch (addr) {
1901 case ICCR0:
1902 s->control[0] = value;
1903 if (!(value & (1 << 4))) /* RXE */
1904 s->rx_len = s->rx_start = 0;
1905 if (!(value & (1 << 3))) { /* TXE */
1906 /* Nop */
1907 }
1908 s->enable = value & 1; /* ITR */
1909 if (!s->enable)
1910 s->status[0] = 0;
1911 pxa2xx_fir_update(s);
1912 break;
1913 case ICCR1:
1914 s->control[1] = value;
1915 break;
1916 case ICCR2:
1917 s->control[2] = value & 0x3f;
1918 pxa2xx_fir_update(s);
1919 break;
1920 case ICDR:
1921 if (s->control[2] & (1 << 2)) /* TXP */
1922 ch = value;
1923 else
1924 ch = ~value;
1925 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1926 qemu_chr_write(s->chr, &ch, 1);
1927 break;
1928 case ICSR0:
1929 s->status[0] &= ~(value & 0x66);
1930 pxa2xx_fir_update(s);
1931 break;
1932 case ICFOR:
1933 break;
1934 default:
1935 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1936 }
1937 }
1938
1939 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1940 pxa2xx_fir_read,
1941 pxa2xx_fir_read,
1942 pxa2xx_fir_read,
1943 };
1944
1945 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1946 pxa2xx_fir_write,
1947 pxa2xx_fir_write,
1948 pxa2xx_fir_write,
1949 };
1950
1951 static int pxa2xx_fir_is_empty(void *opaque)
1952 {
1953 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1954 return (s->rx_len < 64);
1955 }
1956
1957 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1958 {
1959 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1960 if (!(s->control[0] & (1 << 4))) /* RXE */
1961 return;
1962
1963 while (size --) {
1964 s->status[1] |= 1 << 4; /* EOF */
1965 if (s->rx_len >= 64) {
1966 s->status[1] |= 1 << 6; /* ROR */
1967 break;
1968 }
1969
1970 if (s->control[2] & (1 << 3)) /* RXP */
1971 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1972 else
1973 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1974 }
1975
1976 pxa2xx_fir_update(s);
1977 }
1978
1979 static void pxa2xx_fir_event(void *opaque, int event)
1980 {
1981 }
1982
1983 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1984 {
1985 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1986 int i;
1987
1988 qemu_put_be32(f, s->enable);
1989
1990 qemu_put_8s(f, &s->control[0]);
1991 qemu_put_8s(f, &s->control[1]);
1992 qemu_put_8s(f, &s->control[2]);
1993 qemu_put_8s(f, &s->status[0]);
1994 qemu_put_8s(f, &s->status[1]);
1995
1996 qemu_put_byte(f, s->rx_len);
1997 for (i = 0; i < s->rx_len; i ++)
1998 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1999 }
2000
2001 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
2002 {
2003 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
2004 int i;
2005
2006 s->enable = qemu_get_be32(f);
2007
2008 qemu_get_8s(f, &s->control[0]);
2009 qemu_get_8s(f, &s->control[1]);
2010 qemu_get_8s(f, &s->control[2]);
2011 qemu_get_8s(f, &s->status[0]);
2012 qemu_get_8s(f, &s->status[1]);
2013
2014 s->rx_len = qemu_get_byte(f);
2015 s->rx_start = 0;
2016 for (i = 0; i < s->rx_len; i ++)
2017 s->rx_fifo[i] = qemu_get_byte(f);
2018
2019 return 0;
2020 }
2021
2022 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
2023 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
2024 CharDriverState *chr)
2025 {
2026 int iomemtype;
2027 PXA2xxFIrState *s = (PXA2xxFIrState *)
2028 qemu_mallocz(sizeof(PXA2xxFIrState));
2029
2030 s->irq = irq;
2031 s->rx_dma = rx_dma;
2032 s->tx_dma = tx_dma;
2033 s->chr = chr;
2034
2035 pxa2xx_fir_reset(s);
2036
2037 iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2038 pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
2039 cpu_register_physical_memory(base, 0x1000, iomemtype);
2040
2041 if (chr)
2042 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2043 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2044
2045 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2046 pxa2xx_fir_load, s);
2047
2048 return s;
2049 }
2050
2051 static void pxa2xx_reset(void *opaque, int line, int level)
2052 {
2053 PXA2xxState *s = (PXA2xxState *) opaque;
2054
2055 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2056 cpu_reset(s->env);
2057 /* TODO: reset peripherals */
2058 }
2059 }
2060
2061 /* Initialise a PXA270 integrated chip (ARM based core). */
2062 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2063 {
2064 PXA2xxState *s;
2065 int iomemtype, i;
2066 DriveInfo *dinfo;
2067 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2068
2069 if (revision && strncmp(revision, "pxa27", 5)) {
2070 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2071 exit(1);
2072 }
2073 if (!revision)
2074 revision = "pxa270";
2075
2076 s->env = cpu_init(revision);
2077 if (!s->env) {
2078 fprintf(stderr, "Unable to find CPU definition\n");
2079 exit(1);
2080 }
2081 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2082
2083 /* SDRAM & Internal Memory Storage */
2084 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2085 sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
2086 sdram_size) | IO_MEM_RAM);
2087 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2088 0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
2089 0x40000) | IO_MEM_RAM);
2090
2091 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2092
2093 s->dma = pxa27x_dma_init(0x40000000,
2094 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2095
2096 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2097 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2098 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2099 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2100 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2101 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2102 NULL);
2103
2104 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2105
2106 dinfo = drive_get(IF_SD, 0, 0);
2107 if (!dinfo) {
2108 fprintf(stderr, "qemu: missing SecureDigital device\n");
2109 exit(1);
2110 }
2111 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2112 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2113 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2114 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2115
2116 for (i = 0; pxa270_serial[i].io_base; i ++)
2117 if (serial_hds[i])
2118 #ifdef TARGET_WORDS_BIGENDIAN
2119 serial_mm_init(pxa270_serial[i].io_base, 2,
2120 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2121 14857000 / 16, serial_hds[i], 1, 1);
2122 #else
2123 serial_mm_init(pxa270_serial[i].io_base, 2,
2124 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2125 14857000 / 16, serial_hds[i], 1, 0);
2126 #endif
2127 else
2128 break;
2129 if (serial_hds[i])
2130 s->fir = pxa2xx_fir_init(0x40800000,
2131 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2132 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2133 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2134 serial_hds[i]);
2135
2136 s->lcd = pxa2xx_lcdc_init(0x44000000,
2137 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2138
2139 s->cm_base = 0x41300000;
2140 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2141 s->clkcfg = 0x00000009; /* Turbo mode active */
2142 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2143 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2144 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2145 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2146
2147 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2148
2149 s->mm_base = 0x48000000;
2150 s->mm_regs[MDMRS >> 2] = 0x00020002;
2151 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2152 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2153 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2154 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2155 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2156 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2157
2158 s->pm_base = 0x40f00000;
2159 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2160 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2161 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2162 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2163
2164 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2165 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2166 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2167 DeviceState *dev;
2168 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2169 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2170 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2171 }
2172
2173 if (usb_enabled) {
2174 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2175 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2176 }
2177
2178 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2179 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2180
2181 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2182 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2183
2184 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2185 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2186 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2187 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2188
2189 s->i2s = pxa2xx_i2s_init(0x40400000,
2190 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2191 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2192 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2193
2194 s->kp = pxa27x_keypad_init(0x41500000,
2195 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2196
2197 /* GPIO1 resets the processor */
2198 /* The handler can be overridden by board-specific code */
2199 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2200 return s;
2201 }
2202
2203 /* Initialise a PXA255 integrated chip (ARM based core). */
2204 PXA2xxState *pxa255_init(unsigned int sdram_size)
2205 {
2206 PXA2xxState *s;
2207 int iomemtype, i;
2208 DriveInfo *dinfo;
2209
2210 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2211
2212 s->env = cpu_init("pxa255");
2213 if (!s->env) {
2214 fprintf(stderr, "Unable to find CPU definition\n");
2215 exit(1);
2216 }
2217 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2218
2219 /* SDRAM & Internal Memory Storage */
2220 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2221 qemu_ram_alloc(NULL, "pxa255.sdram",
2222 sdram_size) | IO_MEM_RAM);
2223 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2224 qemu_ram_alloc(NULL, "pxa255.internal",
2225 PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2226
2227 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2228
2229 s->dma = pxa255_dma_init(0x40000000,
2230 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2231
2232 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2233 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2234 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2235 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2236 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2237 NULL);
2238
2239 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2240
2241 dinfo = drive_get(IF_SD, 0, 0);
2242 if (!dinfo) {
2243 fprintf(stderr, "qemu: missing SecureDigital device\n");
2244 exit(1);
2245 }
2246 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2247 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2248 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2249 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2250
2251 for (i = 0; pxa255_serial[i].io_base; i ++)
2252 if (serial_hds[i]) {
2253 #ifdef TARGET_WORDS_BIGENDIAN
2254 serial_mm_init(pxa255_serial[i].io_base, 2,
2255 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2256 14745600 / 16, serial_hds[i], 1, 1);
2257 #else
2258 serial_mm_init(pxa255_serial[i].io_base, 2,
2259 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2260 14745600 / 16, serial_hds[i], 1, 0);
2261 #endif
2262 } else {
2263 break;
2264 }
2265 if (serial_hds[i])
2266 s->fir = pxa2xx_fir_init(0x40800000,
2267 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2268 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2269 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2270 serial_hds[i]);
2271
2272 s->lcd = pxa2xx_lcdc_init(0x44000000,
2273 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2274
2275 s->cm_base = 0x41300000;
2276 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2277 s->clkcfg = 0x00000009; /* Turbo mode active */
2278 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2279 pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
2280 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2281 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2282
2283 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2284
2285 s->mm_base = 0x48000000;
2286 s->mm_regs[MDMRS >> 2] = 0x00020002;
2287 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2288 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2289 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2290 pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
2291 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2292 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2293
2294 s->pm_base = 0x40f00000;
2295 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2296 pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
2297 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2298 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2299
2300 for (i = 0; pxa255_ssp[i].io_base; i ++);
2301 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2302 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2303 DeviceState *dev;
2304 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2305 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2306 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2307 }
2308
2309 if (usb_enabled) {
2310 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2311 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2312 }
2313
2314 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2315 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2316
2317 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2318 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2319
2320 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2321 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2322 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2323 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2324
2325 s->i2s = pxa2xx_i2s_init(0x40400000,
2326 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2327 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2328 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2329
2330 /* GPIO1 resets the processor */
2331 /* The handler can be overridden by board-specific code */
2332 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2333 return s;
2334 }
2335
2336 static void pxa2xx_register_devices(void)
2337 {
2338 i2c_register_slave(&pxa2xx_i2c_slave_info);
2339 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2340 sysbus_register_withprop(&pxa2xx_i2c_info);
2341 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info);
2342 }
2343
2344 device_init(pxa2xx_register_devices)
AR7 emulation for QEMU