target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #include "config.h"
  23
  24 #include "kvm-consts.h"
  25
  26 #if defined(TARGET_AARCH64)
  27   /* AArch64 definitions */
  28 #  define TARGET_LONG_BITS 64
  29 #  define ELF_MACHINE EM_AARCH64
  30 #else
  31 #  define TARGET_LONG_BITS 32
  32 #  define ELF_MACHINE EM_ARM
  33 #endif
  34
  35 #define CPUArchState struct CPUARMState
  36
  37 #include "qemu-common.h"
  38 #include "exec/cpu-defs.h"
  39
  40 #include "fpu/softfloat.h"
  41
  42 #define TARGET_HAS_ICE 1
  43
  44 #define EXCP_UDEF            1   /* undefined instruction */
  45 #define EXCP_SWI             2   /* software interrupt */
  46 #define EXCP_PREFETCH_ABORT  3
  47 #define EXCP_DATA_ABORT      4
  48 #define EXCP_IRQ             5
  49 #define EXCP_FIQ             6
  50 #define EXCP_BKPT            7
  51 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  52 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  53 #define EXCP_STREX          10
  54
  55 #define ARMV7M_EXCP_RESET   1
  56 #define ARMV7M_EXCP_NMI     2
  57 #define ARMV7M_EXCP_HARD    3
  58 #define ARMV7M_EXCP_MEM     4
  59 #define ARMV7M_EXCP_BUS     5
  60 #define ARMV7M_EXCP_USAGE   6
  61 #define ARMV7M_EXCP_SVC     11
  62 #define ARMV7M_EXCP_DEBUG   12
  63 #define ARMV7M_EXCP_PENDSV  14
  64 #define ARMV7M_EXCP_SYSTICK 15
  65
  66 /* ARM-specific interrupt pending bits.  */
  67 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  68
  69 /* Meanings of the ARMCPU object's two inbound GPIO lines */
  70 #define ARM_CPU_IRQ 0
  71 #define ARM_CPU_FIQ 1
  72
  73 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  74                             int srcreg, int operand, uint32_t value);
  75 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  76                                int dstreg, int operand);
  77
  78 struct arm_boot_info;
  79
  80 #define NB_MMU_MODES 2
  81
  82 /* We currently assume float and double are IEEE single and double
  83    precision respectively.
  84    Doing runtime conversions is tricky because VFP registers may contain
  85    integer values (eg. as the result of a FTOSI instruction).
  86    s<2n> maps to the least significant half of d<n>
  87    s<2n+1> maps to the most significant half of d<n>
  88  */
  89
  90 /* CPU state for each instance of a generic timer (in cp15 c14) */
  91 typedef struct ARMGenericTimer {
  92     uint64_t cval; /* Timer CompareValue register */
  93     uint32_t ctl; /* Timer Control register */
  94 } ARMGenericTimer;
  95
  96 #define GTIMER_PHYS 0
  97 #define GTIMER_VIRT 1
  98 #define NUM_GTIMERS 2
  99
 100 /* Scale factor for generic timers, ie number of ns per tick.
 101  * This gives a 62.5MHz timer.
 102  */
 103 #define GTIMER_SCALE 16
 104
 105 typedef struct CPUARMState {
 106     /* Regs for current mode.  */
 107     uint32_t regs[16];
 108
 109     /* 32/64 switch only happens when taking and returning from
 110      * exceptions so the overlap semantics are taken care of then
 111      * instead of having a complicated union.
 112      */
 113     /* Regs for A64 mode.  */
 114     uint64_t xregs[32];
 115     uint64_t pc;
 116     /* PSTATE isn't an architectural register for ARMv8. However, it is
 117      * convenient for us to assemble the underlying state into a 32 bit format
 118      * identical to the architectural format used for the SPSR. (This is also
 119      * what the Linux kernel's 'pstate' field in signal handlers and KVM's
 120      * 'pstate' register are.) Of the PSTATE bits:
 121      *  NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
 122      *    semantics as for AArch32, as described in the comments on each field)
 123      *  nRW (also known as M[4]) is kept, inverted, in env->aarch64
 124      *  all other bits are stored in their correct places in env->pstate
 125      */
 126     uint32_t pstate;
 127     uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
 128
 129     /* Frequently accessed CPSR bits are stored separately for efficiency.
 130        This contains all the other bits.  Use cpsr_{read,write} to access
 131        the whole CPSR.  */
 132     uint32_t uncached_cpsr;
 133     uint32_t spsr;
 134
 135     /* Banked registers.  */
 136     uint32_t banked_spsr[6];
 137     uint32_t banked_r13[6];
 138     uint32_t banked_r14[6];
 139
 140     /* These hold r8-r12.  */
 141     uint32_t usr_regs[5];
 142     uint32_t fiq_regs[5];
 143
 144     /* cpsr flag cache for faster execution */
 145     uint32_t CF; /* 0 or 1 */
 146     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 147     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 148     uint32_t ZF; /* Z set if zero.  */
 149     uint32_t QF; /* 0 or 1 */
 150     uint32_t GE; /* cpsr[19:16] */
 151     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 152     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 153
 154     /* System control coprocessor (cp15) */
 155     struct {
 156         uint32_t c0_cpuid;
 157         uint32_t c0_cssel; /* Cache size selection.  */
 158         uint32_t c1_sys; /* System control register.  */
 159         uint32_t c1_coproc; /* Coprocessor access register.  */
 160         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 161         uint32_t c1_scr; /* secure config register.  */
 162         uint32_t c2_base0; /* MMU translation table base 0.  */
 163         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 164         uint32_t c2_base1; /* MMU translation table base 0.  */
 165         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 166         uint32_t c2_control; /* MMU translation table base control.  */
 167         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 168         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 169         uint32_t c2_data; /* MPU data cachable bits.  */
 170         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 171         uint32_t c3; /* MMU domain access control register
 172                         MPU write buffer control.  */
 173         uint32_t c5_insn; /* Fault status registers.  */
 174         uint32_t c5_data;
 175         uint32_t c6_region[8]; /* MPU base/size registers.  */
 176         uint32_t c6_insn; /* Fault address registers.  */
 177         uint32_t c6_data;
 178         uint32_t c7_par;  /* Translation result. */
 179         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 180         uint32_t c9_insn; /* Cache lockdown registers.  */
 181         uint32_t c9_data;
 182         uint32_t c9_pmcr; /* performance monitor control register */
 183         uint32_t c9_pmcnten; /* perf monitor counter enables */
 184         uint32_t c9_pmovsr; /* perf monitor overflow status */
 185         uint32_t c9_pmxevtyper; /* perf monitor event type */
 186         uint32_t c9_pmuserenr; /* perf monitor user enable */
 187         uint32_t c9_pminten; /* perf monitor interrupt enables */
 188         uint32_t c12_vbar; /* vector base address register */
 189         uint32_t c13_fcse; /* FCSE PID.  */
 190         uint32_t c13_context; /* Context ID.  */
 191         uint32_t c13_tls1; /* User RW Thread register.  */
 192         uint32_t c13_tls2; /* User RO Thread register.  */
 193         uint32_t c13_tls3; /* Privileged Thread register.  */
 194         uint32_t c14_cntfrq; /* Counter Frequency register */
 195         uint32_t c14_cntkctl; /* Timer Control register */
 196         ARMGenericTimer c14_timer[NUM_GTIMERS];
 197         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 198         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 199         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 200         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 201         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 202         uint32_t c15_config_base_address; /* SCU base address.  */
 203         uint32_t c15_diagnostic; /* diagnostic register */
 204         uint32_t c15_power_diagnostic;
 205         uint32_t c15_power_control; /* power control */
 206     } cp15;
 207
 208     /* System registers (AArch64) */
 209     struct {
 210         uint64_t tpidr_el0;
 211     } sr;
 212
 213     struct {
 214         uint32_t other_sp;
 215         uint32_t vecbase;
 216         uint32_t basepri;
 217         uint32_t control;
 218         int current_sp;
 219         int exception;
 220         int pending_exception;
 221     } v7m;
 222
 223     /* Thumb-2 EE state.  */
 224     uint32_t teecr;
 225     uint32_t teehbr;
 226
 227     /* VFP coprocessor state.  */
 228     struct {
 229         /* VFP/Neon register state. Note that the mapping between S, D and Q
 230          * views of the register bank differs between AArch64 and AArch32:
 231          * In AArch32:
 232          *  Qn = regs[2n+1]:regs[2n]
 233          *  Dn = regs[n]
 234          *  Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
 235          * (and regs[32] to regs[63] are inaccessible)
 236          * In AArch64:
 237          *  Qn = regs[2n+1]:regs[2n]
 238          *  Dn = regs[2n]
 239          *  Sn = regs[2n] bits 31..0
 240          * This corresponds to the architecturally defined mapping between
 241          * the two execution states, and means we do not need to explicitly
 242          * map these registers when changing states.
 243          */
 244         float64 regs[64];
 245
 246         uint32_t xregs[16];
 247         /* We store these fpcsr fields separately for convenience.  */
 248         int vec_len;
 249         int vec_stride;
 250
 251         /* scratch space when Tn are not sufficient.  */
 252         uint32_t scratch[8];
 253
 254         /* fp_status is the "normal" fp status. standard_fp_status retains
 255          * values corresponding to the ARM "Standard FPSCR Value", ie
 256          * default-NaN, flush-to-zero, round-to-nearest and is used by
 257          * any operations (generally Neon) which the architecture defines
 258          * as controlled by the standard FPSCR value rather than the FPSCR.
 259          *
 260          * To avoid having to transfer exception bits around, we simply
 261          * say that the FPSCR cumulative exception flags are the logical
 262          * OR of the flags in the two fp statuses. This relies on the
 263          * only thing which needs to read the exception flags being
 264          * an explicit FPSCR read.
 265          */
 266         float_status fp_status;
 267         float_status standard_fp_status;
 268     } vfp;
 269     uint32_t exclusive_addr;
 270     uint32_t exclusive_val;
 271     uint32_t exclusive_high;
 272 #if defined(CONFIG_USER_ONLY)
 273     uint32_t exclusive_test;
 274     uint32_t exclusive_info;
 275 #endif
 276
 277     /* iwMMXt coprocessor state.  */
 278     struct {
 279         uint64_t regs[16];
 280         uint64_t val;
 281
 282         uint32_t cregs[16];
 283     } iwmmxt;
 284
 285     /* For mixed endian mode.  */
 286     bool bswap_code;
 287
 288 #if defined(CONFIG_USER_ONLY)
 289     /* For usermode syscall translation.  */
 290     int eabi;
 291 #endif
 292
 293     CPU_COMMON
 294
 295     /* These fields after the common ones so they are preserved on reset.  */
 296
 297     /* Internal CPU feature flags.  */
 298     uint64_t features;
 299
 300     void *nvic;
 301     const struct arm_boot_info *boot_info;
 302 } CPUARMState;
 303
 304 #include "cpu-qom.h"
 305
 306 ARMCPU *cpu_arm_init(const char *cpu_model);
 307 void arm_translate_init(void);
 308 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 309 int cpu_arm_exec(CPUARMState *s);
 310 int bank_number(int mode);
 311 void switch_mode(CPUARMState *, int);
 312 uint32_t do_arm_semihosting(CPUARMState *env);
 313
 314 static inline bool is_a64(CPUARMState *env)
 315 {
 316     return env->aarch64;
 317 }
 318
 319 /* you can call this signal handler from your SIGBUS and SIGSEGV
 320    signal handlers to inform the virtual CPU of exceptions. non zero
 321    is returned if the signal was handled by the virtual CPU.  */
 322 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 323                            void *puc);
 324 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 325                               int mmu_idx);
 326 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 327
 328 #define CPSR_M (0x1fU)
 329 #define CPSR_T (1U << 5)
 330 #define CPSR_F (1U << 6)
 331 #define CPSR_I (1U << 7)
 332 #define CPSR_A (1U << 8)
 333 #define CPSR_E (1U << 9)
 334 #define CPSR_IT_2_7 (0xfc00U)
 335 #define CPSR_GE (0xfU << 16)
 336 #define CPSR_RESERVED (0xfU << 20)
 337 #define CPSR_J (1U << 24)
 338 #define CPSR_IT_0_1 (3U << 25)
 339 #define CPSR_Q (1U << 27)
 340 #define CPSR_V (1U << 28)
 341 #define CPSR_C (1U << 29)
 342 #define CPSR_Z (1U << 30)
 343 #define CPSR_N (1U << 31)
 344 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 345
 346 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 347 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 348 /* Bits writable in user mode.  */
 349 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 350 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 351 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 352
 353 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
 354  * Only these are valid when in AArch64 mode; in
 355  * AArch32 mode SPSRs are basically CPSR-format.
 356  */
 357 #define PSTATE_M (0xFU)
 358 #define PSTATE_nRW (1U << 4)
 359 #define PSTATE_F (1U << 6)
 360 #define PSTATE_I (1U << 7)
 361 #define PSTATE_A (1U << 8)
 362 #define PSTATE_D (1U << 9)
 363 #define PSTATE_IL (1U << 20)
 364 #define PSTATE_SS (1U << 21)
 365 #define PSTATE_V (1U << 28)
 366 #define PSTATE_C (1U << 29)
 367 #define PSTATE_Z (1U << 30)
 368 #define PSTATE_N (1U << 31)
 369 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
 370 #define CACHED_PSTATE_BITS (PSTATE_NZCV)
 371 /* Mode values for AArch64 */
 372 #define PSTATE_MODE_EL3h 13
 373 #define PSTATE_MODE_EL3t 12
 374 #define PSTATE_MODE_EL2h 9
 375 #define PSTATE_MODE_EL2t 8
 376 #define PSTATE_MODE_EL1h 5
 377 #define PSTATE_MODE_EL1t 4
 378 #define PSTATE_MODE_EL0t 0
 379
 380 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
 381  * interprocessing, so we don't attempt to sync with the cpsr state used by
 382  * the 32 bit decoder.
 383  */
 384 static inline uint32_t pstate_read(CPUARMState *env)
 385 {
 386     int ZF;
 387
 388     ZF = (env->ZF == 0);
 389     return (env->NF & 0x80000000) | (ZF << 30)
 390         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
 391         | env->pstate;
 392 }
 393
 394 static inline void pstate_write(CPUARMState *env, uint32_t val)
 395 {
 396     env->ZF = (~val) & PSTATE_Z;
 397     env->NF = val;
 398     env->CF = (val >> 29) & 1;
 399     env->VF = (val << 3) & 0x80000000;
 400     env->pstate = val & ~CACHED_PSTATE_BITS;
 401 }
 402
 403 /* Return the current CPSR value.  */
 404 uint32_t cpsr_read(CPUARMState *env);
 405 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 406 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 407
 408 /* Return the current xPSR value.  */
 409 static inline uint32_t xpsr_read(CPUARMState *env)
 410 {
 411     int ZF;
 412     ZF = (env->ZF == 0);
 413     return (env->NF & 0x80000000) | (ZF << 30)
 414         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 415         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 416         | ((env->condexec_bits & 0xfc) << 8)
 417         | env->v7m.exception;
 418 }
 419
 420 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 421 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 422 {
 423     if (mask & CPSR_NZCV) {
 424         env->ZF = (~val) & CPSR_Z;
 425         env->NF = val;
 426         env->CF = (val >> 29) & 1;
 427         env->VF = (val << 3) & 0x80000000;
 428     }
 429     if (mask & CPSR_Q)
 430         env->QF = ((val & CPSR_Q) != 0);
 431     if (mask & (1 << 24))
 432         env->thumb = ((val & (1 << 24)) != 0);
 433     if (mask & CPSR_IT_0_1) {
 434         env->condexec_bits &= ~3;
 435         env->condexec_bits |= (val >> 25) & 3;
 436     }
 437     if (mask & CPSR_IT_2_7) {
 438         env->condexec_bits &= 3;
 439         env->condexec_bits |= (val >> 8) & 0xfc;
 440     }
 441     if (mask & 0x1ff) {
 442         env->v7m.exception = val & 0x1ff;
 443     }
 444 }
 445
 446 /* Return the current FPSCR value.  */
 447 uint32_t vfp_get_fpscr(CPUARMState *env);
 448 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 449
 450 enum arm_cpu_mode {
 451   ARM_CPU_MODE_USR = 0x10,
 452   ARM_CPU_MODE_FIQ = 0x11,
 453   ARM_CPU_MODE_IRQ = 0x12,
 454   ARM_CPU_MODE_SVC = 0x13,
 455   ARM_CPU_MODE_ABT = 0x17,
 456   ARM_CPU_MODE_UND = 0x1b,
 457   ARM_CPU_MODE_SYS = 0x1f
 458 };
 459
 460 /* VFP system registers.  */
 461 #define ARM_VFP_FPSID   0
 462 #define ARM_VFP_FPSCR   1
 463 #define ARM_VFP_MVFR1   6
 464 #define ARM_VFP_MVFR0   7
 465 #define ARM_VFP_FPEXC   8
 466 #define ARM_VFP_FPINST  9
 467 #define ARM_VFP_FPINST2 10
 468
 469 /* iwMMXt coprocessor control registers.  */
 470 #define ARM_IWMMXT_wCID         0
 471 #define ARM_IWMMXT_wCon         1
 472 #define ARM_IWMMXT_wCSSF        2
 473 #define ARM_IWMMXT_wCASF        3
 474 #define ARM_IWMMXT_wCGR0        8
 475 #define ARM_IWMMXT_wCGR1        9
 476 #define ARM_IWMMXT_wCGR2        10
 477 #define ARM_IWMMXT_wCGR3        11
 478
 479 /* If adding a feature bit which corresponds to a Linux ELF
 480  * HWCAP bit, remember to update the feature-bit-to-hwcap
 481  * mapping in linux-user/elfload.c:get_elf_hwcap().
 482  */
 483 enum arm_features {
 484     ARM_FEATURE_VFP,
 485     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 486     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 487     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 488     ARM_FEATURE_V6,
 489     ARM_FEATURE_V6K,
 490     ARM_FEATURE_V7,
 491     ARM_FEATURE_THUMB2,
 492     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 493     ARM_FEATURE_VFP3,
 494     ARM_FEATURE_VFP_FP16,
 495     ARM_FEATURE_NEON,
 496     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 497     ARM_FEATURE_M, /* Microcontroller profile.  */
 498     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 499     ARM_FEATURE_THUMB2EE,
 500     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 501     ARM_FEATURE_V4T,
 502     ARM_FEATURE_V5,
 503     ARM_FEATURE_STRONGARM,
 504     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 505     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 506     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 507     ARM_FEATURE_GENERIC_TIMER,
 508     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 509     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 510     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 511     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 512     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 513     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 514     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 515     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 516     ARM_FEATURE_V8,
 517     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
 518     ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
 519     ARM_FEATURE_CBAR, /* has cp15 CBAR */
 520 };
 521
 522 static inline int arm_feature(CPUARMState *env, int feature)
 523 {
 524     return (env->features & (1ULL << feature)) != 0;
 525 }
 526
 527 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 528
 529 /* Interface between CPU and Interrupt controller.  */
 530 void armv7m_nvic_set_pending(void *opaque, int irq);
 531 int armv7m_nvic_acknowledge_irq(void *opaque);
 532 void armv7m_nvic_complete_irq(void *opaque, int irq);
 533
 534 /* Interface for defining coprocessor registers.
 535  * Registers are defined in tables of arm_cp_reginfo structs
 536  * which are passed to define_arm_cp_regs().
 537  */
 538
 539 /* When looking up a coprocessor register we look for it
 540  * via an integer which encodes all of:
 541  *  coprocessor number
 542  *  Crn, Crm, opc1, opc2 fields
 543  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 544  *    or via MRRC/MCRR?)
 545  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 546  * (In this case crn and opc2 should be zero.)
 547  */
 548 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 549     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 550      ((crm) << 7) | ((opc1) << 3) | (opc2))
 551
 552 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 553  * version used as a key for the coprocessor register hashtable
 554  */
 555 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 556 {
 557     uint32_t cpregid = kvmid;
 558     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 559         cpregid |= (1 << 15);
 560     }
 561     return cpregid;
 562 }
 563
 564 /* Convert a truncated 32 bit hashtable key into the full
 565  * 64 bit KVM register ID.
 566  */
 567 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 568 {
 569     uint64_t kvmid = cpregid & ~(1 << 15);
 570     if (cpregid & (1 << 15)) {
 571         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 572     } else {
 573         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 574     }
 575     return kvmid;
 576 }
 577
 578 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 579  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 580  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 581  * TCG can assume the value to be constant (ie load at translate time)
 582  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 583  * indicates that the TB should not be ended after a write to this register
 584  * (the default is that the TB ends after cp writes). OVERRIDE permits
 585  * a register definition to override a previous definition for the
 586  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 587  * old must have the OVERRIDE bit set.
 588  * NO_MIGRATE indicates that this register should be ignored for migration;
 589  * (eg because any state is accessed via some other coprocessor register).
 590  * IO indicates that this register does I/O and therefore its accesses
 591  * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
 592  * registers which implement clocks or timers require this.
 593  */
 594 #define ARM_CP_SPECIAL 1
 595 #define ARM_CP_CONST 2
 596 #define ARM_CP_64BIT 4
 597 #define ARM_CP_SUPPRESS_TB_END 8
 598 #define ARM_CP_OVERRIDE 16
 599 #define ARM_CP_NO_MIGRATE 32
 600 #define ARM_CP_IO 64
 601 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 602 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 603 #define ARM_LAST_SPECIAL ARM_CP_WFI
 604 /* Used only as a terminator for ARMCPRegInfo lists */
 605 #define ARM_CP_SENTINEL 0xffff
 606 /* Mask of only the flag bits in a type field */
 607 #define ARM_CP_FLAG_MASK 0x7f
 608
 609 /* Return true if cptype is a valid type field. This is used to try to
 610  * catch errors where the sentinel has been accidentally left off the end
 611  * of a list of registers.
 612  */
 613 static inline bool cptype_valid(int cptype)
 614 {
 615     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 616         || ((cptype & ARM_CP_SPECIAL) &&
 617             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 618 }
 619
 620 /* Access rights:
 621  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 622  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 623  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 624  * (ie any of the privileged modes in Secure state, or Monitor mode).
 625  * If a register is accessible in one privilege level it's always accessible
 626  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 627  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 628  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 629  * terminology a little and call this PL3.
 630  *
 631  * If access permissions for a register are more complex than can be
 632  * described with these bits, then use a laxer set of restrictions, and
 633  * do the more restrictive/complex check inside a helper function.
 634  */
 635 #define PL3_R 0x80
 636 #define PL3_W 0x40
 637 #define PL2_R (0x20 | PL3_R)
 638 #define PL2_W (0x10 | PL3_W)
 639 #define PL1_R (0x08 | PL2_R)
 640 #define PL1_W (0x04 | PL2_W)
 641 #define PL0_R (0x02 | PL1_R)
 642 #define PL0_W (0x01 | PL1_W)
 643
 644 #define PL3_RW (PL3_R | PL3_W)
 645 #define PL2_RW (PL2_R | PL2_W)
 646 #define PL1_RW (PL1_R | PL1_W)
 647 #define PL0_RW (PL0_R | PL0_W)
 648
 649 static inline int arm_current_pl(CPUARMState *env)
 650 {
 651     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 652         return 0;
 653     }
 654     /* We don't currently implement the Virtualization or TrustZone
 655      * extensions, so PL2 and PL3 don't exist for us.
 656      */
 657     return 1;
 658 }
 659
 660 typedef struct ARMCPRegInfo ARMCPRegInfo;
 661
 662 /* Access functions for coprocessor registers. These should return
 663  * 0 on success, or one of the EXCP_* constants if access should cause
 664  * an exception (in which case *value is not written).
 665  */
 666 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 667                      uint64_t *value);
 668 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 669                       uint64_t value);
 670 /* Hook function for register reset */
 671 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 672
 673 #define CP_ANY 0xff
 674
 675 /* Definition of an ARM coprocessor register */
 676 struct ARMCPRegInfo {
 677     /* Name of register (useful mainly for debugging, need not be unique) */
 678     const char *name;
 679     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 680      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 681      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 682      * will be decoded to this register. The register read and write
 683      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 684      * used by the program, so it is possible to register a wildcard and
 685      * then behave differently on read/write if necessary.
 686      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 687      * must both be zero.
 688      */
 689     uint8_t cp;
 690     uint8_t crn;
 691     uint8_t crm;
 692     uint8_t opc1;
 693     uint8_t opc2;
 694     /* Register type: ARM_CP_* bits/values */
 695     int type;
 696     /* Access rights: PL*_[RW] */
 697     int access;
 698     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 699      * this register was defined: can be used to hand data through to the
 700      * register read/write functions, since they are passed the ARMCPRegInfo*.
 701      */
 702     void *opaque;
 703     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 704      * fieldoffset is non-zero, the reset value of the register.
 705      */
 706     uint64_t resetvalue;
 707     /* Offset of the field in CPUARMState for this register. This is not
 708      * needed if either:
 709      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 710      *  2. both readfn and writefn are specified
 711      */
 712     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 713     /* Function for handling reads of this register. If NULL, then reads
 714      * will be done by loading from the offset into CPUARMState specified
 715      * by fieldoffset.
 716      */
 717     CPReadFn *readfn;
 718     /* Function for handling writes of this register. If NULL, then writes
 719      * will be done by writing to the offset into CPUARMState specified
 720      * by fieldoffset.
 721      */
 722     CPWriteFn *writefn;
 723     /* Function for doing a "raw" read; used when we need to copy
 724      * coprocessor state to the kernel for KVM or out for
 725      * migration. This only needs to be provided if there is also a
 726      * readfn and it makes an access permission check.
 727      */
 728     CPReadFn *raw_readfn;
 729     /* Function for doing a "raw" write; used when we need to copy KVM
 730      * kernel coprocessor state into userspace, or for inbound
 731      * migration. This only needs to be provided if there is also a
 732      * writefn and it makes an access permission check or masks out
 733      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 734      */
 735     CPWriteFn *raw_writefn;
 736     /* Function for resetting the register. If NULL, then reset will be done
 737      * by writing resetvalue to the field specified in fieldoffset. If
 738      * fieldoffset is 0 then no reset will be done.
 739      */
 740     CPResetFn *resetfn;
 741 };
 742
 743 /* Macros which are lvalues for the field in CPUARMState for the
 744  * ARMCPRegInfo *ri.
 745  */
 746 #define CPREG_FIELD32(env, ri) \
 747     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 748 #define CPREG_FIELD64(env, ri) \
 749     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 750
 751 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 752
 753 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 754                                     const ARMCPRegInfo *regs, void *opaque);
 755 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 756                                        const ARMCPRegInfo *regs, void *opaque);
 757 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 758 {
 759     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 760 }
 761 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 762 {
 763     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 764 }
 765 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 766
 767 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 768 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 769                         uint64_t value);
 770 /* CPReadFn that can be used for read-as-zero behaviour */
 771 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 772
 773 static inline bool cp_access_ok(CPUARMState *env,
 774                                 const ARMCPRegInfo *ri, int isread)
 775 {
 776     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 777 }
 778
 779 /**
 780  * write_list_to_cpustate
 781  * @cpu: ARMCPU
 782  *
 783  * For each register listed in the ARMCPU cpreg_indexes list, write
 784  * its value from the cpreg_values list into the ARMCPUState structure.
 785  * This updates TCG's working data structures from KVM data or
 786  * from incoming migration state.
 787  *
 788  * Returns: true if all register values were updated correctly,
 789  * false if some register was unknown or could not be written.
 790  * Note that we do not stop early on failure -- we will attempt
 791  * writing all registers in the list.
 792  */
 793 bool write_list_to_cpustate(ARMCPU *cpu);
 794
 795 /**
 796  * write_cpustate_to_list:
 797  * @cpu: ARMCPU
 798  *
 799  * For each register listed in the ARMCPU cpreg_indexes list, write
 800  * its value from the ARMCPUState structure into the cpreg_values list.
 801  * This is used to copy info from TCG's working data structures into
 802  * KVM or for outbound migration.
 803  *
 804  * Returns: true if all register values were read correctly,
 805  * false if some register was unknown or could not be read.
 806  * Note that we do not stop early on failure -- we will attempt
 807  * reading all registers in the list.
 808  */
 809 bool write_cpustate_to_list(ARMCPU *cpu);
 810
 811 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 812    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 813    conventional cores (ie. Application or Realtime profile).  */
 814
 815 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 816
 817 #define ARM_CPUID_TI915T      0x54029152
 818 #define ARM_CPUID_TI925T      0x54029252
 819
 820 #if defined(CONFIG_USER_ONLY)
 821 #define TARGET_PAGE_BITS 12
 822 #else
 823 /* The ARM MMU allows 1k pages.  */
 824 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 825    architecture revisions.  Maybe a configure option to disable them.  */
 826 #define TARGET_PAGE_BITS 10
 827 #endif
 828
 829 #if defined(TARGET_AARCH64)
 830 #  define TARGET_PHYS_ADDR_SPACE_BITS 48
 831 #  define TARGET_VIRT_ADDR_SPACE_BITS 64
 832 #else
 833 #  define TARGET_PHYS_ADDR_SPACE_BITS 40
 834 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 835 #endif
 836
 837 static inline CPUARMState *cpu_init(const char *cpu_model)
 838 {
 839     ARMCPU *cpu = cpu_arm_init(cpu_model);
 840     if (cpu) {
 841         return &cpu->env;
 842     }
 843     return NULL;
 844 }
 845
 846 #define cpu_exec cpu_arm_exec
 847 #define cpu_gen_code cpu_arm_gen_code
 848 #define cpu_signal_handler cpu_arm_signal_handler
 849 #define cpu_list arm_cpu_list
 850
 851 /* MMU modes definitions */
 852 #define MMU_MODE0_SUFFIX _kernel
 853 #define MMU_MODE1_SUFFIX _user
 854 #define MMU_USER_IDX 1
 855 static inline int cpu_mmu_index (CPUARMState *env)
 856 {
 857     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 858 }
 859
 860 #include "exec/cpu-all.h"
 861
 862 /* Bit usage in the TB flags field: bit 31 indicates whether we are
 863  * in 32 or 64 bit mode. The meaning of the other bits depends on that.
 864  */
 865 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
 866 #define ARM_TBFLAG_AARCH64_STATE_MASK  (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
 867
 868 /* Bit usage when in AArch32 state: */
 869 #define ARM_TBFLAG_THUMB_SHIFT      0
 870 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 871 #define ARM_TBFLAG_VECLEN_SHIFT     1
 872 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 873 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 874 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 875 #define ARM_TBFLAG_PRIV_SHIFT       6
 876 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 877 #define ARM_TBFLAG_VFPEN_SHIFT      7
 878 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 879 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 880 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 881 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 882 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 883
 884 /* Bit usage when in AArch64 state: currently no bits defined */
 885
 886 /* some convenience accessor macros */
 887 #define ARM_TBFLAG_AARCH64_STATE(F) \
 888     (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
 889 #define ARM_TBFLAG_THUMB(F) \
 890     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 891 #define ARM_TBFLAG_VECLEN(F) \
 892     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 893 #define ARM_TBFLAG_VECSTRIDE(F) \
 894     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 895 #define ARM_TBFLAG_PRIV(F) \
 896     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 897 #define ARM_TBFLAG_VFPEN(F) \
 898     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 899 #define ARM_TBFLAG_CONDEXEC(F) \
 900     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 901 #define ARM_TBFLAG_BSWAP_CODE(F) \
 902     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 903
 904 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 905                                         target_ulong *cs_base, int *flags)
 906 {
 907     if (is_a64(env)) {
 908         *pc = env->pc;
 909         *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
 910     } else {
 911         int privmode;
 912         *pc = env->regs[15];
 913         *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 914             | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 915             | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 916             | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 917             | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 918         if (arm_feature(env, ARM_FEATURE_M)) {
 919             privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 920         } else {
 921             privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 922         }
 923         if (privmode) {
 924             *flags |= ARM_TBFLAG_PRIV_MASK;
 925         }
 926         if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 927             *flags |= ARM_TBFLAG_VFPEN_MASK;
 928         }
 929     }
 930
 931     *cs_base = 0;
 932 }
 933
 934 static inline bool cpu_has_work(CPUState *cpu)
 935 {
 936     return cpu->interrupt_request &
 937         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 938 }
 939
 940 #include "exec/exec-all.h"
 941
 942 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
 943 {
 944     if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
 945         env->pc = tb->pc;
 946     } else {
 947         env->regs[15] = tb->pc;
 948     }
 949 }
 950
 951 /* Load an instruction and return it in the standard little-endian order */
 952 static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 953                                     bool do_swap)
 954 {
 955     uint32_t insn = cpu_ldl_code(env, addr);
 956     if (do_swap) {
 957         return bswap32(insn);
 958     }
 959     return insn;
 960 }
 961
 962 /* Ditto, for a halfword (Thumb) instruction */
 963 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
 964                                      bool do_swap)
 965 {
 966     uint16_t insn = cpu_lduw_code(env, addr);
 967     if (do_swap) {
 968         return bswap16(insn);
 969     }
 970     return insn;
 971 }
 972
 973 #endif