target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #include "qapi/qmp/qerror.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31
  32 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     ARMCPU *cpu = ARM_CPU(cs);
  35
  36     cpu->env.regs[15] = value;
  37 }
  38
  39 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  40 {
  41     /* Reset a single ARMCPRegInfo register */
  42     ARMCPRegInfo *ri = value;
  43     ARMCPU *cpu = opaque;
  44
  45     if (ri->type & ARM_CP_SPECIAL) {
  46         return;
  47     }
  48
  49     if (ri->resetfn) {
  50         ri->resetfn(&cpu->env, ri);
  51         return;
  52     }
  53
  54     /* A zero offset is never possible as it would be regs[0]
  55      * so we use it to indicate that reset is being handled elsewhere.
  56      * This is basically only used for fields in non-core coprocessors
  57      * (like the pxa2xx ones).
  58      */
  59     if (!ri->fieldoffset) {
  60         return;
  61     }
  62
  63     if (ri->type & ARM_CP_64BIT) {
  64         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  65     } else {
  66         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  67     }
  68 }
  69
  70 /* CPUClass::reset() */
  71 static void arm_cpu_reset(CPUState *s)
  72 {
  73     ARMCPU *cpu = ARM_CPU(s);
  74     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  75     CPUARMState *env = &cpu->env;
  76
  77     acc->parent_reset(s);
  78
  79     memset(env, 0, offsetof(CPUARMState, breakpoints));
  80     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  81     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  82     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  83     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  84
  85     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  86         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  87     }
  88
  89     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  90         /* 64 bit CPUs always start in 64 bit mode */
  91         env->aarch64 = 1;
  92 #if defined(CONFIG_USER_ONLY)
  93         env->pstate = PSTATE_MODE_EL0t;
  94 #else
  95         env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F
  96             | PSTATE_MODE_EL1h;
  97 #endif
  98     }
  99
 100 #if defined(CONFIG_USER_ONLY)
 101     env->uncached_cpsr = ARM_CPU_MODE_USR;
 102     /* For user mode we must enable access to coprocessors */
 103     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 104     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 105         env->cp15.c15_cpar = 3;
 106     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 107         env->cp15.c15_cpar = 1;
 108     }
 109 #else
 110     /* SVC mode with interrupts disabled.  */
 111     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 112     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 113        clear at reset.  Initial SP and PC are loaded from ROM.  */
 114     if (IS_M(env)) {
 115         uint32_t pc;
 116         uint8_t *rom;
 117         env->uncached_cpsr &= ~CPSR_I;
 118         rom = rom_ptr(0);
 119         if (rom) {
 120             /* We should really use ldl_phys here, in case the guest
 121                modified flash and reset itself.  However images
 122                loaded via -kernel have not been copied yet, so load the
 123                values directly from there.  */
 124             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 125             pc = ldl_p(rom + 4);
 126             env->thumb = pc & 1;
 127             env->regs[15] = pc & ~1;
 128         }
 129     }
 130
 131     if (env->cp15.c1_sys & (1 << 13)) {
 132             env->regs[15] = 0xFFFF0000;
 133     }
 134
 135     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 136 #endif
 137     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 138     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 139     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 140     set_float_detect_tininess(float_tininess_before_rounding,
 141                               &env->vfp.fp_status);
 142     set_float_detect_tininess(float_tininess_before_rounding,
 143                               &env->vfp.standard_fp_status);
 144     tlb_flush(env, 1);
 145     /* Reset is a state change for some CPUARMState fields which we
 146      * bake assumptions about into translated code, so we need to
 147      * tb_flush().
 148      */
 149     tb_flush(env);
 150 }
 151
 152 #ifndef CONFIG_USER_ONLY
 153 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 154 {
 155     ARMCPU *cpu = opaque;
 156     CPUState *cs = CPU(cpu);
 157
 158     switch (irq) {
 159     case ARM_CPU_IRQ:
 160         if (level) {
 161             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 162         } else {
 163             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 164         }
 165         break;
 166     case ARM_CPU_FIQ:
 167         if (level) {
 168             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 169         } else {
 170             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 171         }
 172         break;
 173     default:
 174         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 175     }
 176 }
 177
 178 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 179 {
 180 #ifdef CONFIG_KVM
 181     ARMCPU *cpu = opaque;
 182     CPUState *cs = CPU(cpu);
 183     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 184
 185     switch (irq) {
 186     case ARM_CPU_IRQ:
 187         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 188         break;
 189     case ARM_CPU_FIQ:
 190         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 191         break;
 192     default:
 193         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 194     }
 195     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 196     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 197 #endif
 198 }
 199 #endif
 200
 201 static inline void set_feature(CPUARMState *env, int feature)
 202 {
 203     env->features |= 1ULL << feature;
 204 }
 205
 206 static void arm_cpu_initfn(Object *obj)
 207 {
 208     CPUState *cs = CPU(obj);
 209     ARMCPU *cpu = ARM_CPU(obj);
 210     static bool inited;
 211
 212     cs->env_ptr = &cpu->env;
 213     cpu_exec_init(&cpu->env);
 214     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 215                                          g_free, g_free);
 216
 217 #ifndef CONFIG_USER_ONLY
 218     /* Our inbound IRQ and FIQ lines */
 219     if (kvm_enabled()) {
 220         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 221     } else {
 222         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 223     }
 224
 225     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 226                                                 arm_gt_ptimer_cb, cpu);
 227     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 228                                                 arm_gt_vtimer_cb, cpu);
 229     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 230                        ARRAY_SIZE(cpu->gt_timer_outputs));
 231 #endif
 232
 233     /* DTB consumers generally don't in fact care what the 'compatible'
 234      * string is, so always provide some string and trust that a hypothetical
 235      * picky DTB consumer will also provide a helpful error message.
 236      */
 237     cpu->dtb_compatible = "qemu,unknown";
 238     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 239
 240     if (tcg_enabled() && !inited) {
 241         inited = true;
 242         arm_translate_init();
 243     }
 244 }
 245
 246 static Property arm_cpu_reset_cbar_property =
 247             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 248
 249 static Property arm_cpu_reset_hivecs_property =
 250             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 251
 252 static void arm_cpu_post_init(Object *obj)
 253 {
 254     ARMCPU *cpu = ARM_CPU(obj);
 255     Error *err = NULL;
 256
 257     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
 258         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 259                                  &err);
 260         assert_no_error(err);
 261     }
 262
 263     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 264         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 265                                  &err);
 266         assert_no_error(err);
 267     }
 268 }
 269
 270 static void arm_cpu_finalizefn(Object *obj)
 271 {
 272     ARMCPU *cpu = ARM_CPU(obj);
 273     g_hash_table_destroy(cpu->cp_regs);
 274 }
 275
 276 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 277 {
 278     CPUState *cs = CPU(dev);
 279     ARMCPU *cpu = ARM_CPU(dev);
 280     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 281     CPUARMState *env = &cpu->env;
 282
 283     /* Some features automatically imply others: */
 284     if (arm_feature(env, ARM_FEATURE_V8)) {
 285         set_feature(env, ARM_FEATURE_V7);
 286         set_feature(env, ARM_FEATURE_ARM_DIV);
 287         set_feature(env, ARM_FEATURE_LPAE);
 288         set_feature(env, ARM_FEATURE_V8_AES);
 289     }
 290     if (arm_feature(env, ARM_FEATURE_V7)) {
 291         set_feature(env, ARM_FEATURE_VAPA);
 292         set_feature(env, ARM_FEATURE_THUMB2);
 293         set_feature(env, ARM_FEATURE_MPIDR);
 294         if (!arm_feature(env, ARM_FEATURE_M)) {
 295             set_feature(env, ARM_FEATURE_V6K);
 296         } else {
 297             set_feature(env, ARM_FEATURE_V6);
 298         }
 299     }
 300     if (arm_feature(env, ARM_FEATURE_V6K)) {
 301         set_feature(env, ARM_FEATURE_V6);
 302         set_feature(env, ARM_FEATURE_MVFR);
 303     }
 304     if (arm_feature(env, ARM_FEATURE_V6)) {
 305         set_feature(env, ARM_FEATURE_V5);
 306         if (!arm_feature(env, ARM_FEATURE_M)) {
 307             set_feature(env, ARM_FEATURE_AUXCR);
 308         }
 309     }
 310     if (arm_feature(env, ARM_FEATURE_V5)) {
 311         set_feature(env, ARM_FEATURE_V4T);
 312     }
 313     if (arm_feature(env, ARM_FEATURE_M)) {
 314         set_feature(env, ARM_FEATURE_THUMB_DIV);
 315     }
 316     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 317         set_feature(env, ARM_FEATURE_THUMB_DIV);
 318     }
 319     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 320         set_feature(env, ARM_FEATURE_VFP3);
 321     }
 322     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 323         set_feature(env, ARM_FEATURE_VFP);
 324     }
 325     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 326         set_feature(env, ARM_FEATURE_V7MP);
 327         set_feature(env, ARM_FEATURE_PXN);
 328     }
 329
 330     if (cpu->reset_hivecs) {
 331             cpu->reset_sctlr |= (1 << 13);
 332     }
 333
 334     register_cp_regs_for_features(cpu);
 335     arm_cpu_register_gdb_regs_for_features(cpu);
 336
 337     init_cpreg_list(cpu);
 338
 339     cpu_reset(cs);
 340     qemu_init_vcpu(cs);
 341
 342     acc->parent_realize(dev, errp);
 343 }
 344
 345 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 346 {
 347     ObjectClass *oc;
 348     char *typename;
 349
 350     if (!cpu_model) {
 351         return NULL;
 352     }
 353
 354     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 355     oc = object_class_by_name(typename);
 356     g_free(typename);
 357     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 358         object_class_is_abstract(oc)) {
 359         return NULL;
 360     }
 361     return oc;
 362 }
 363
 364 /* CPU models. These are not needed for the AArch64 linux-user build. */
 365 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 366
 367 static void arm926_initfn(Object *obj)
 368 {
 369     ARMCPU *cpu = ARM_CPU(obj);
 370
 371     cpu->dtb_compatible = "arm,arm926";
 372     set_feature(&cpu->env, ARM_FEATURE_V5);
 373     set_feature(&cpu->env, ARM_FEATURE_VFP);
 374     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 375     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 376     cpu->midr = 0x41069265;
 377     cpu->reset_fpsid = 0x41011090;
 378     cpu->ctr = 0x1dd20d2;
 379     cpu->reset_sctlr = 0x00090078;
 380 }
 381
 382 static void arm946_initfn(Object *obj)
 383 {
 384     ARMCPU *cpu = ARM_CPU(obj);
 385
 386     cpu->dtb_compatible = "arm,arm946";
 387     set_feature(&cpu->env, ARM_FEATURE_V5);
 388     set_feature(&cpu->env, ARM_FEATURE_MPU);
 389     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 390     cpu->midr = 0x41059461;
 391     cpu->ctr = 0x0f004006;
 392     cpu->reset_sctlr = 0x00000078;
 393 }
 394
 395 static void arm1026_initfn(Object *obj)
 396 {
 397     ARMCPU *cpu = ARM_CPU(obj);
 398
 399     cpu->dtb_compatible = "arm,arm1026";
 400     set_feature(&cpu->env, ARM_FEATURE_V5);
 401     set_feature(&cpu->env, ARM_FEATURE_VFP);
 402     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 403     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 404     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 405     cpu->midr = 0x4106a262;
 406     cpu->reset_fpsid = 0x410110a0;
 407     cpu->ctr = 0x1dd20d2;
 408     cpu->reset_sctlr = 0x00090078;
 409     cpu->reset_auxcr = 1;
 410     {
 411         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 412         ARMCPRegInfo ifar = {
 413             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 414             .access = PL1_RW,
 415             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 416             .resetvalue = 0
 417         };
 418         define_one_arm_cp_reg(cpu, &ifar);
 419     }
 420 }
 421
 422 static void arm1136_r2_initfn(Object *obj)
 423 {
 424     ARMCPU *cpu = ARM_CPU(obj);
 425     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 426      * older core than plain "arm1136". In particular this does not
 427      * have the v6K features.
 428      * These ID register values are correct for 1136 but may be wrong
 429      * for 1136_r2 (in particular r0p2 does not actually implement most
 430      * of the ID registers).
 431      */
 432
 433     cpu->dtb_compatible = "arm,arm1136";
 434     set_feature(&cpu->env, ARM_FEATURE_V6);
 435     set_feature(&cpu->env, ARM_FEATURE_VFP);
 436     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 437     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 438     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 439     cpu->midr = 0x4107b362;
 440     cpu->reset_fpsid = 0x410120b4;
 441     cpu->mvfr0 = 0x11111111;
 442     cpu->mvfr1 = 0x00000000;
 443     cpu->ctr = 0x1dd20d2;
 444     cpu->reset_sctlr = 0x00050078;
 445     cpu->id_pfr0 = 0x111;
 446     cpu->id_pfr1 = 0x1;
 447     cpu->id_dfr0 = 0x2;
 448     cpu->id_afr0 = 0x3;
 449     cpu->id_mmfr0 = 0x01130003;
 450     cpu->id_mmfr1 = 0x10030302;
 451     cpu->id_mmfr2 = 0x01222110;
 452     cpu->id_isar0 = 0x00140011;
 453     cpu->id_isar1 = 0x12002111;
 454     cpu->id_isar2 = 0x11231111;
 455     cpu->id_isar3 = 0x01102131;
 456     cpu->id_isar4 = 0x141;
 457     cpu->reset_auxcr = 7;
 458 }
 459
 460 static void arm1136_initfn(Object *obj)
 461 {
 462     ARMCPU *cpu = ARM_CPU(obj);
 463
 464     cpu->dtb_compatible = "arm,arm1136";
 465     set_feature(&cpu->env, ARM_FEATURE_V6K);
 466     set_feature(&cpu->env, ARM_FEATURE_V6);
 467     set_feature(&cpu->env, ARM_FEATURE_VFP);
 468     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 469     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 470     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 471     cpu->midr = 0x4117b363;
 472     cpu->reset_fpsid = 0x410120b4;
 473     cpu->mvfr0 = 0x11111111;
 474     cpu->mvfr1 = 0x00000000;
 475     cpu->ctr = 0x1dd20d2;
 476     cpu->reset_sctlr = 0x00050078;
 477     cpu->id_pfr0 = 0x111;
 478     cpu->id_pfr1 = 0x1;
 479     cpu->id_dfr0 = 0x2;
 480     cpu->id_afr0 = 0x3;
 481     cpu->id_mmfr0 = 0x01130003;
 482     cpu->id_mmfr1 = 0x10030302;
 483     cpu->id_mmfr2 = 0x01222110;
 484     cpu->id_isar0 = 0x00140011;
 485     cpu->id_isar1 = 0x12002111;
 486     cpu->id_isar2 = 0x11231111;
 487     cpu->id_isar3 = 0x01102131;
 488     cpu->id_isar4 = 0x141;
 489     cpu->reset_auxcr = 7;
 490 }
 491
 492 static void arm1176_initfn(Object *obj)
 493 {
 494     ARMCPU *cpu = ARM_CPU(obj);
 495
 496     cpu->dtb_compatible = "arm,arm1176";
 497     set_feature(&cpu->env, ARM_FEATURE_V6K);
 498     set_feature(&cpu->env, ARM_FEATURE_VFP);
 499     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 500     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 501     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 502     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 503     cpu->midr = 0x410fb767;
 504     cpu->reset_fpsid = 0x410120b5;
 505     cpu->mvfr0 = 0x11111111;
 506     cpu->mvfr1 = 0x00000000;
 507     cpu->ctr = 0x1dd20d2;
 508     cpu->reset_sctlr = 0x00050078;
 509     cpu->id_pfr0 = 0x111;
 510     cpu->id_pfr1 = 0x11;
 511     cpu->id_dfr0 = 0x33;
 512     cpu->id_afr0 = 0;
 513     cpu->id_mmfr0 = 0x01130003;
 514     cpu->id_mmfr1 = 0x10030302;
 515     cpu->id_mmfr2 = 0x01222100;
 516     cpu->id_isar0 = 0x0140011;
 517     cpu->id_isar1 = 0x12002111;
 518     cpu->id_isar2 = 0x11231121;
 519     cpu->id_isar3 = 0x01102131;
 520     cpu->id_isar4 = 0x01141;
 521     cpu->reset_auxcr = 7;
 522 }
 523
 524 static void arm11mpcore_initfn(Object *obj)
 525 {
 526     ARMCPU *cpu = ARM_CPU(obj);
 527
 528     cpu->dtb_compatible = "arm,arm11mpcore";
 529     set_feature(&cpu->env, ARM_FEATURE_V6K);
 530     set_feature(&cpu->env, ARM_FEATURE_VFP);
 531     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 532     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 533     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 534     cpu->midr = 0x410fb022;
 535     cpu->reset_fpsid = 0x410120b4;
 536     cpu->mvfr0 = 0x11111111;
 537     cpu->mvfr1 = 0x00000000;
 538     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 539     cpu->id_pfr0 = 0x111;
 540     cpu->id_pfr1 = 0x1;
 541     cpu->id_dfr0 = 0;
 542     cpu->id_afr0 = 0x2;
 543     cpu->id_mmfr0 = 0x01100103;
 544     cpu->id_mmfr1 = 0x10020302;
 545     cpu->id_mmfr2 = 0x01222000;
 546     cpu->id_isar0 = 0x00100011;
 547     cpu->id_isar1 = 0x12002111;
 548     cpu->id_isar2 = 0x11221011;
 549     cpu->id_isar3 = 0x01102131;
 550     cpu->id_isar4 = 0x141;
 551     cpu->reset_auxcr = 1;
 552 }
 553
 554 static void cortex_m3_initfn(Object *obj)
 555 {
 556     ARMCPU *cpu = ARM_CPU(obj);
 557     set_feature(&cpu->env, ARM_FEATURE_V7);
 558     set_feature(&cpu->env, ARM_FEATURE_M);
 559     cpu->midr = 0x410fc231;
 560 }
 561
 562 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 563 {
 564 #ifndef CONFIG_USER_ONLY
 565     CPUClass *cc = CPU_CLASS(oc);
 566
 567     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 568 #endif
 569 }
 570
 571 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 572     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 573       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 574     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 575       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 576     REGINFO_SENTINEL
 577 };
 578
 579 static void cortex_a8_initfn(Object *obj)
 580 {
 581     ARMCPU *cpu = ARM_CPU(obj);
 582
 583     cpu->dtb_compatible = "arm,cortex-a8";
 584     set_feature(&cpu->env, ARM_FEATURE_V7);
 585     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 586     set_feature(&cpu->env, ARM_FEATURE_NEON);
 587     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 588     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 589     cpu->midr = 0x410fc080;
 590     cpu->reset_fpsid = 0x410330c0;
 591     cpu->mvfr0 = 0x11110222;
 592     cpu->mvfr1 = 0x00011100;
 593     cpu->ctr = 0x82048004;
 594     cpu->reset_sctlr = 0x00c50078;
 595     cpu->id_pfr0 = 0x1031;
 596     cpu->id_pfr1 = 0x11;
 597     cpu->id_dfr0 = 0x400;
 598     cpu->id_afr0 = 0;
 599     cpu->id_mmfr0 = 0x31100003;
 600     cpu->id_mmfr1 = 0x20000000;
 601     cpu->id_mmfr2 = 0x01202000;
 602     cpu->id_mmfr3 = 0x11;
 603     cpu->id_isar0 = 0x00101111;
 604     cpu->id_isar1 = 0x12112111;
 605     cpu->id_isar2 = 0x21232031;
 606     cpu->id_isar3 = 0x11112131;
 607     cpu->id_isar4 = 0x00111142;
 608     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 609     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 610     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 611     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 612     cpu->reset_auxcr = 2;
 613     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 614 }
 615
 616 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 617     /* power_control should be set to maximum latency. Again,
 618      * default to 0 and set by private hook
 619      */
 620     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 621       .access = PL1_RW, .resetvalue = 0,
 622       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 623     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 624       .access = PL1_RW, .resetvalue = 0,
 625       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 626     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 627       .access = PL1_RW, .resetvalue = 0,
 628       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 629     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 630       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 631     /* TLB lockdown control */
 632     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 633       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 634     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 635       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 636     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 637       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 638     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 639       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 640     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 641       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 642     REGINFO_SENTINEL
 643 };
 644
 645 static void cortex_a9_initfn(Object *obj)
 646 {
 647     ARMCPU *cpu = ARM_CPU(obj);
 648
 649     cpu->dtb_compatible = "arm,cortex-a9";
 650     set_feature(&cpu->env, ARM_FEATURE_V7);
 651     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 652     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 653     set_feature(&cpu->env, ARM_FEATURE_NEON);
 654     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 655     /* Note that A9 supports the MP extensions even for
 656      * A9UP and single-core A9MP (which are both different
 657      * and valid configurations; we don't model A9UP).
 658      */
 659     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 660     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 661     cpu->midr = 0x410fc090;
 662     cpu->reset_fpsid = 0x41033090;
 663     cpu->mvfr0 = 0x11110222;
 664     cpu->mvfr1 = 0x01111111;
 665     cpu->ctr = 0x80038003;
 666     cpu->reset_sctlr = 0x00c50078;
 667     cpu->id_pfr0 = 0x1031;
 668     cpu->id_pfr1 = 0x11;
 669     cpu->id_dfr0 = 0x000;
 670     cpu->id_afr0 = 0;
 671     cpu->id_mmfr0 = 0x00100103;
 672     cpu->id_mmfr1 = 0x20000000;
 673     cpu->id_mmfr2 = 0x01230000;
 674     cpu->id_mmfr3 = 0x00002111;
 675     cpu->id_isar0 = 0x00101111;
 676     cpu->id_isar1 = 0x13112111;
 677     cpu->id_isar2 = 0x21232041;
 678     cpu->id_isar3 = 0x11112131;
 679     cpu->id_isar4 = 0x00111142;
 680     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 681     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 682     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 683     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 684 }
 685
 686 #ifndef CONFIG_USER_ONLY
 687 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 688                            uint64_t *value)
 689 {
 690     /* Linux wants the number of processors from here.
 691      * Might as well set the interrupt-controller bit too.
 692      */
 693     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 694     return 0;
 695 }
 696 #endif
 697
 698 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 699 #ifndef CONFIG_USER_ONLY
 700     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 701       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 702       .writefn = arm_cp_write_ignore, },
 703 #endif
 704     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 705       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 706     REGINFO_SENTINEL
 707 };
 708
 709 static void cortex_a15_initfn(Object *obj)
 710 {
 711     ARMCPU *cpu = ARM_CPU(obj);
 712
 713     cpu->dtb_compatible = "arm,cortex-a15";
 714     set_feature(&cpu->env, ARM_FEATURE_V7);
 715     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 716     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 717     set_feature(&cpu->env, ARM_FEATURE_NEON);
 718     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 719     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 720     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 721     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 722     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 723     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 724     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 725     cpu->midr = 0x412fc0f1;
 726     cpu->reset_fpsid = 0x410430f0;
 727     cpu->mvfr0 = 0x10110222;
 728     cpu->mvfr1 = 0x11111111;
 729     cpu->ctr = 0x8444c004;
 730     cpu->reset_sctlr = 0x00c50078;
 731     cpu->id_pfr0 = 0x00001131;
 732     cpu->id_pfr1 = 0x00011011;
 733     cpu->id_dfr0 = 0x02010555;
 734     cpu->id_afr0 = 0x00000000;
 735     cpu->id_mmfr0 = 0x10201105;
 736     cpu->id_mmfr1 = 0x20000000;
 737     cpu->id_mmfr2 = 0x01240000;
 738     cpu->id_mmfr3 = 0x02102211;
 739     cpu->id_isar0 = 0x02101110;
 740     cpu->id_isar1 = 0x13112111;
 741     cpu->id_isar2 = 0x21232041;
 742     cpu->id_isar3 = 0x11112131;
 743     cpu->id_isar4 = 0x10011142;
 744     cpu->clidr = 0x0a200023;
 745     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 746     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 747     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 748     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 749 }
 750
 751 static void ti925t_initfn(Object *obj)
 752 {
 753     ARMCPU *cpu = ARM_CPU(obj);
 754     set_feature(&cpu->env, ARM_FEATURE_V4T);
 755     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 756     cpu->midr = ARM_CPUID_TI925T;
 757     cpu->ctr = 0x5109149;
 758     cpu->reset_sctlr = 0x00000070;
 759 }
 760
 761 static void sa1100_initfn(Object *obj)
 762 {
 763     ARMCPU *cpu = ARM_CPU(obj);
 764
 765     cpu->dtb_compatible = "intel,sa1100";
 766     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 767     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 768     cpu->midr = 0x4401A11B;
 769     cpu->reset_sctlr = 0x00000070;
 770 }
 771
 772 static void sa1110_initfn(Object *obj)
 773 {
 774     ARMCPU *cpu = ARM_CPU(obj);
 775     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 776     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 777     cpu->midr = 0x6901B119;
 778     cpu->reset_sctlr = 0x00000070;
 779 }
 780
 781 static void pxa250_initfn(Object *obj)
 782 {
 783     ARMCPU *cpu = ARM_CPU(obj);
 784
 785     cpu->dtb_compatible = "marvell,xscale";
 786     set_feature(&cpu->env, ARM_FEATURE_V5);
 787     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 788     cpu->midr = 0x69052100;
 789     cpu->ctr = 0xd172172;
 790     cpu->reset_sctlr = 0x00000078;
 791 }
 792
 793 static void pxa255_initfn(Object *obj)
 794 {
 795     ARMCPU *cpu = ARM_CPU(obj);
 796
 797     cpu->dtb_compatible = "marvell,xscale";
 798     set_feature(&cpu->env, ARM_FEATURE_V5);
 799     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 800     cpu->midr = 0x69052d00;
 801     cpu->ctr = 0xd172172;
 802     cpu->reset_sctlr = 0x00000078;
 803 }
 804
 805 static void pxa260_initfn(Object *obj)
 806 {
 807     ARMCPU *cpu = ARM_CPU(obj);
 808
 809     cpu->dtb_compatible = "marvell,xscale";
 810     set_feature(&cpu->env, ARM_FEATURE_V5);
 811     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 812     cpu->midr = 0x69052903;
 813     cpu->ctr = 0xd172172;
 814     cpu->reset_sctlr = 0x00000078;
 815 }
 816
 817 static void pxa261_initfn(Object *obj)
 818 {
 819     ARMCPU *cpu = ARM_CPU(obj);
 820
 821     cpu->dtb_compatible = "marvell,xscale";
 822     set_feature(&cpu->env, ARM_FEATURE_V5);
 823     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 824     cpu->midr = 0x69052d05;
 825     cpu->ctr = 0xd172172;
 826     cpu->reset_sctlr = 0x00000078;
 827 }
 828
 829 static void pxa262_initfn(Object *obj)
 830 {
 831     ARMCPU *cpu = ARM_CPU(obj);
 832
 833     cpu->dtb_compatible = "marvell,xscale";
 834     set_feature(&cpu->env, ARM_FEATURE_V5);
 835     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 836     cpu->midr = 0x69052d06;
 837     cpu->ctr = 0xd172172;
 838     cpu->reset_sctlr = 0x00000078;
 839 }
 840
 841 static void pxa270a0_initfn(Object *obj)
 842 {
 843     ARMCPU *cpu = ARM_CPU(obj);
 844
 845     cpu->dtb_compatible = "marvell,xscale";
 846     set_feature(&cpu->env, ARM_FEATURE_V5);
 847     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 848     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 849     cpu->midr = 0x69054110;
 850     cpu->ctr = 0xd172172;
 851     cpu->reset_sctlr = 0x00000078;
 852 }
 853
 854 static void pxa270a1_initfn(Object *obj)
 855 {
 856     ARMCPU *cpu = ARM_CPU(obj);
 857
 858     cpu->dtb_compatible = "marvell,xscale";
 859     set_feature(&cpu->env, ARM_FEATURE_V5);
 860     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 861     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 862     cpu->midr = 0x69054111;
 863     cpu->ctr = 0xd172172;
 864     cpu->reset_sctlr = 0x00000078;
 865 }
 866
 867 static void pxa270b0_initfn(Object *obj)
 868 {
 869     ARMCPU *cpu = ARM_CPU(obj);
 870
 871     cpu->dtb_compatible = "marvell,xscale";
 872     set_feature(&cpu->env, ARM_FEATURE_V5);
 873     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 874     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 875     cpu->midr = 0x69054112;
 876     cpu->ctr = 0xd172172;
 877     cpu->reset_sctlr = 0x00000078;
 878 }
 879
 880 static void pxa270b1_initfn(Object *obj)
 881 {
 882     ARMCPU *cpu = ARM_CPU(obj);
 883
 884     cpu->dtb_compatible = "marvell,xscale";
 885     set_feature(&cpu->env, ARM_FEATURE_V5);
 886     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 887     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 888     cpu->midr = 0x69054113;
 889     cpu->ctr = 0xd172172;
 890     cpu->reset_sctlr = 0x00000078;
 891 }
 892
 893 static void pxa270c0_initfn(Object *obj)
 894 {
 895     ARMCPU *cpu = ARM_CPU(obj);
 896
 897     cpu->dtb_compatible = "marvell,xscale";
 898     set_feature(&cpu->env, ARM_FEATURE_V5);
 899     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 900     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 901     cpu->midr = 0x69054114;
 902     cpu->ctr = 0xd172172;
 903     cpu->reset_sctlr = 0x00000078;
 904 }
 905
 906 static void pxa270c5_initfn(Object *obj)
 907 {
 908     ARMCPU *cpu = ARM_CPU(obj);
 909
 910     cpu->dtb_compatible = "marvell,xscale";
 911     set_feature(&cpu->env, ARM_FEATURE_V5);
 912     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 913     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 914     cpu->midr = 0x69054117;
 915     cpu->ctr = 0xd172172;
 916     cpu->reset_sctlr = 0x00000078;
 917 }
 918
 919 #ifdef CONFIG_USER_ONLY
 920 static void arm_any_initfn(Object *obj)
 921 {
 922     ARMCPU *cpu = ARM_CPU(obj);
 923     set_feature(&cpu->env, ARM_FEATURE_V8);
 924     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 925     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 926     set_feature(&cpu->env, ARM_FEATURE_NEON);
 927     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 928     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 929     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 930 #ifdef TARGET_AARCH64
 931     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 932 #endif
 933     cpu->midr = 0xffffffff;
 934 }
 935 #endif
 936
 937 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 938
 939 typedef struct ARMCPUInfo {
 940     const char *name;
 941     void (*initfn)(Object *obj);
 942     void (*class_init)(ObjectClass *oc, void *data);
 943 } ARMCPUInfo;
 944
 945 static const ARMCPUInfo arm_cpus[] = {
 946 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 947     { .name = "arm926",      .initfn = arm926_initfn },
 948     { .name = "arm946",      .initfn = arm946_initfn },
 949     { .name = "arm1026",     .initfn = arm1026_initfn },
 950     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 951      * older core than plain "arm1136". In particular this does not
 952      * have the v6K features.
 953      */
 954     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 955     { .name = "arm1136",     .initfn = arm1136_initfn },
 956     { .name = "arm1176",     .initfn = arm1176_initfn },
 957     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 958     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 959                              .class_init = arm_v7m_class_init },
 960     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 961     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 962     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 963     { .name = "ti925t",      .initfn = ti925t_initfn },
 964     { .name = "sa1100",      .initfn = sa1100_initfn },
 965     { .name = "sa1110",      .initfn = sa1110_initfn },
 966     { .name = "pxa250",      .initfn = pxa250_initfn },
 967     { .name = "pxa255",      .initfn = pxa255_initfn },
 968     { .name = "pxa260",      .initfn = pxa260_initfn },
 969     { .name = "pxa261",      .initfn = pxa261_initfn },
 970     { .name = "pxa262",      .initfn = pxa262_initfn },
 971     /* "pxa270" is an alias for "pxa270-a0" */
 972     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 973     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 974     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 975     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 976     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 977     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 978     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 979 #ifdef CONFIG_USER_ONLY
 980     { .name = "any",         .initfn = arm_any_initfn },
 981 #endif
 982 #endif
 983 };
 984
 985 static Property arm_cpu_properties[] = {
 986     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 987     DEFINE_PROP_END_OF_LIST()
 988 };
 989
 990 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 991 {
 992     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 993     CPUClass *cc = CPU_CLASS(acc);
 994     DeviceClass *dc = DEVICE_CLASS(oc);
 995
 996     acc->parent_realize = dc->realize;
 997     dc->realize = arm_cpu_realizefn;
 998     dc->props = arm_cpu_properties;
 999
1000     acc->parent_reset = cc->reset;
1001     cc->reset = arm_cpu_reset;
1002
1003     cc->class_by_name = arm_cpu_class_by_name;
1004     cc->do_interrupt = arm_cpu_do_interrupt;
1005     cc->dump_state = arm_cpu_dump_state;
1006     cc->set_pc = arm_cpu_set_pc;
1007     cc->gdb_read_register = arm_cpu_gdb_read_register;
1008     cc->gdb_write_register = arm_cpu_gdb_write_register;
1009 #ifndef CONFIG_USER_ONLY
1010     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1011     cc->vmsd = &vmstate_arm_cpu;
1012 #endif
1013     cc->gdb_num_core_regs = 26;
1014     cc->gdb_core_xml_file = "arm-core.xml";
1015 }
1016
1017 static void cpu_register(const ARMCPUInfo *info)
1018 {
1019     TypeInfo type_info = {
1020         .parent = TYPE_ARM_CPU,
1021         .instance_size = sizeof(ARMCPU),
1022         .instance_init = info->initfn,
1023         .class_size = sizeof(ARMCPUClass),
1024         .class_init = info->class_init,
1025     };
1026
1027     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1028     type_register(&type_info);
1029     g_free((void *)type_info.name);
1030 }
1031
1032 static const TypeInfo arm_cpu_type_info = {
1033     .name = TYPE_ARM_CPU,
1034     .parent = TYPE_CPU,
1035     .instance_size = sizeof(ARMCPU),
1036     .instance_init = arm_cpu_initfn,
1037     .instance_post_init = arm_cpu_post_init,
1038     .instance_finalize = arm_cpu_finalizefn,
1039     .abstract = true,
1040     .class_size = sizeof(ARMCPUClass),
1041     .class_init = arm_cpu_class_init,
1042 };
1043
1044 static void arm_cpu_register_types(void)
1045 {
1046     int i;
1047
1048     type_register_static(&arm_cpu_type_info);
1049     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
1050         cpu_register(&arm_cpus[i]);
1051     }
1052 }
1053
1054 type_init(arm_cpu_register_types)