2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24 #include "sysemu/kvm.h"
26 /*****************************************************************************/
27 /* Exceptions processing helpers */
30 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
33 do_raise_exception_err(env
, exception
, error_code
, 0);
37 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
39 do_raise_exception(env
, exception
, GETPC());
42 QEMU_NORETURN
void helper_raise_exception_debug(CPUMIPSState
*env
)
44 do_raise_exception(env
, EXCP_DEBUG
, 0);
48 void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
50 do_raise_exception(env
, exception
, 0);
53 #if defined(CONFIG_USER_ONLY)
54 #define HELPER_LD(name, insn, type) \
55 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
56 int mem_idx, uintptr_t retaddr) \
58 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61 #define HELPER_LD(name, insn, type) \
62 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
63 int mem_idx, uintptr_t retaddr) \
67 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
68 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
70 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
74 HELPER_LD(lw
, ldl
, int32_t)
75 #if defined(TARGET_MIPS64)
76 HELPER_LD(ld
, ldq
, int64_t)
80 #if defined(CONFIG_USER_ONLY)
81 #define HELPER_ST(name, insn, type) \
82 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
83 type val, int mem_idx, uintptr_t retaddr) \
85 cpu_##insn##_data_ra(env, addr, val, retaddr); \
88 #define HELPER_ST(name, insn, type) \
89 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
90 type val, int mem_idx, uintptr_t retaddr) \
94 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
95 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
97 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
101 HELPER_ST(sb
, stb
, uint8_t)
102 HELPER_ST(sw
, stl
, uint32_t)
103 #if defined(TARGET_MIPS64)
104 HELPER_ST(sd
, stq
, uint64_t)
108 target_ulong
helper_clo (target_ulong arg1
)
113 target_ulong
helper_clz (target_ulong arg1
)
118 #if defined(TARGET_MIPS64)
119 target_ulong
helper_dclo (target_ulong arg1
)
124 target_ulong
helper_dclz (target_ulong arg1
)
128 #endif /* TARGET_MIPS64 */
130 /* 64 bits arithmetic for 32 bits hosts */
131 static inline uint64_t get_HILO(CPUMIPSState
*env
)
133 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
136 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
139 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
140 tmp
= env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
144 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
146 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
147 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
151 /* Multiplication variants of the vr54xx. */
152 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
155 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
156 (int64_t)(int32_t)arg2
));
159 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
162 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
163 (uint64_t)(uint32_t)arg2
);
166 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
169 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
170 (int64_t)(int32_t)arg2
);
173 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
176 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
177 (int64_t)(int32_t)arg2
);
180 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
183 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
184 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
187 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
190 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
191 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
194 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
197 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
198 (int64_t)(int32_t)arg2
);
201 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
204 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
205 (int64_t)(int32_t)arg2
);
208 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
211 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
212 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
215 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
218 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
219 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
222 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
225 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
228 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
231 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
232 (uint64_t)(uint32_t)arg2
);
235 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
238 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
239 (int64_t)(int32_t)arg2
);
242 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
245 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
246 (uint64_t)(uint32_t)arg2
);
249 static inline target_ulong
bitswap(target_ulong v
)
251 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
252 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
253 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
254 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
255 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
256 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
261 target_ulong
helper_dbitswap(target_ulong rt
)
267 target_ulong
helper_bitswap(target_ulong rt
)
269 return (int32_t)bitswap(rt
);
272 #ifndef CONFIG_USER_ONLY
274 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
275 target_ulong address
,
276 int rw
, uintptr_t retaddr
)
279 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
281 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
283 if (lladdr
== -1LL) {
284 cpu_loop_exit_restore(cs
, retaddr
);
290 #define HELPER_LD_ATOMIC(name, insn, almask) \
291 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
293 if (arg & almask) { \
294 env->CP0_BadVAddr = arg; \
295 do_raise_exception(env, EXCP_AdEL, GETPC()); \
297 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
298 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
301 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
303 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
305 #undef HELPER_LD_ATOMIC
307 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
308 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
309 target_ulong arg2, int mem_idx) \
313 if (arg2 & almask) { \
314 env->CP0_BadVAddr = arg2; \
315 do_raise_exception(env, EXCP_AdES, GETPC()); \
317 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
318 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
319 if (tmp == env->llval) { \
320 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
326 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
328 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
330 #undef HELPER_ST_ATOMIC
333 #ifdef TARGET_WORDS_BIGENDIAN
334 #define GET_LMASK(v) ((v) & 3)
335 #define GET_OFFSET(addr, offset) (addr + (offset))
337 #define GET_LMASK(v) (((v) & 3) ^ 3)
338 #define GET_OFFSET(addr, offset) (addr - (offset))
341 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
344 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
346 if (GET_LMASK(arg2
) <= 2) {
347 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
351 if (GET_LMASK(arg2
) <= 1) {
352 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
356 if (GET_LMASK(arg2
) == 0) {
357 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
362 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
365 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
367 if (GET_LMASK(arg2
) >= 1) {
368 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
372 if (GET_LMASK(arg2
) >= 2) {
373 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
377 if (GET_LMASK(arg2
) == 3) {
378 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
383 #if defined(TARGET_MIPS64)
384 /* "half" load and stores. We must do the memory access inline,
385 or fault handling won't work. */
387 #ifdef TARGET_WORDS_BIGENDIAN
388 #define GET_LMASK64(v) ((v) & 7)
390 #define GET_LMASK64(v) (((v) & 7) ^ 7)
393 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
396 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
398 if (GET_LMASK64(arg2
) <= 6) {
399 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
403 if (GET_LMASK64(arg2
) <= 5) {
404 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
408 if (GET_LMASK64(arg2
) <= 4) {
409 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
413 if (GET_LMASK64(arg2
) <= 3) {
414 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
418 if (GET_LMASK64(arg2
) <= 2) {
419 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
423 if (GET_LMASK64(arg2
) <= 1) {
424 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
428 if (GET_LMASK64(arg2
) <= 0) {
429 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
434 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
437 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
439 if (GET_LMASK64(arg2
) >= 1) {
440 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
444 if (GET_LMASK64(arg2
) >= 2) {
445 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
449 if (GET_LMASK64(arg2
) >= 3) {
450 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
454 if (GET_LMASK64(arg2
) >= 4) {
455 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
459 if (GET_LMASK64(arg2
) >= 5) {
460 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
464 if (GET_LMASK64(arg2
) >= 6) {
465 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
469 if (GET_LMASK64(arg2
) == 7) {
470 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
474 #endif /* TARGET_MIPS64 */
476 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
478 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
481 target_ulong base_reglist
= reglist
& 0xf;
482 target_ulong do_r31
= reglist
& 0x10;
484 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
487 for (i
= 0; i
< base_reglist
; i
++) {
488 env
->active_tc
.gpr
[multiple_regs
[i
]] =
489 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
495 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
500 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
503 target_ulong base_reglist
= reglist
& 0xf;
504 target_ulong do_r31
= reglist
& 0x10;
506 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
509 for (i
= 0; i
< base_reglist
; i
++) {
510 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
517 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
521 #if defined(TARGET_MIPS64)
522 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
525 target_ulong base_reglist
= reglist
& 0xf;
526 target_ulong do_r31
= reglist
& 0x10;
528 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
531 for (i
= 0; i
< base_reglist
; i
++) {
532 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
539 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
543 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
546 target_ulong base_reglist
= reglist
& 0xf;
547 target_ulong do_r31
= reglist
& 0x10;
549 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
552 for (i
= 0; i
< base_reglist
; i
++) {
553 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
560 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
565 #ifndef CONFIG_USER_ONLY
567 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
569 CPUState
*cpu
= CPU(c
);
570 CPUMIPSState
*env
= &c
->env
;
572 /* If the VPE is halted but otherwise active, it means it's waiting for
574 return cpu
->halted
&& mips_vpe_active(env
);
577 static bool mips_vp_is_wfi(MIPSCPU
*c
)
579 CPUState
*cpu
= CPU(c
);
580 CPUMIPSState
*env
= &c
->env
;
582 return cpu
->halted
&& mips_vp_active(env
);
585 static inline void mips_vpe_wake(MIPSCPU
*c
)
587 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
588 because there might be other conditions that state that c should
590 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
593 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
595 CPUState
*cs
= CPU(cpu
);
597 /* The VPE was shut off, really go to bed.
598 Reset any old _WAKE requests. */
600 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
603 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
605 CPUMIPSState
*c
= &cpu
->env
;
607 /* FIXME: TC reschedule. */
608 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
613 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
615 CPUMIPSState
*c
= &cpu
->env
;
617 /* FIXME: TC reschedule. */
618 if (!mips_vpe_active(c
)) {
625 * @env: CPU from which mapping is performed.
626 * @tc: Should point to an int with the value of the global TC index.
628 * This function will transform @tc into a local index within the
629 * returned #CPUMIPSState.
631 /* FIXME: This code assumes that all VPEs have the same number of TCs,
632 which depends on runtime setup. Can probably be fixed by
633 walking the list of CPUMIPSStates. */
634 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
642 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
643 /* Not allowed to address other CPUs. */
644 *tc
= env
->current_tc
;
648 cs
= CPU(mips_env_get_cpu(env
));
649 vpe_idx
= tc_idx
/ cs
->nr_threads
;
650 *tc
= tc_idx
% cs
->nr_threads
;
651 other_cs
= qemu_get_cpu(vpe_idx
);
652 if (other_cs
== NULL
) {
655 cpu
= MIPS_CPU(other_cs
);
659 /* The per VPE CP0_Status register shares some fields with the per TC
660 CP0_TCStatus registers. These fields are wired to the same registers,
661 so changes to either of them should be reflected on both registers.
663 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
665 These helper call synchronizes the regs for a given cpu. */
667 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
668 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
671 /* Called for updates to CP0_TCStatus. */
672 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
676 uint32_t tcu
, tmx
, tasid
, tksu
;
677 uint32_t mask
= ((1U << CP0St_CU3
)
684 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
685 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
687 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
689 status
= tcu
<< CP0St_CU0
;
690 status
|= tmx
<< CP0St_MX
;
691 status
|= tksu
<< CP0St_KSU
;
693 cpu
->CP0_Status
&= ~mask
;
694 cpu
->CP0_Status
|= status
;
696 /* Sync the TASID with EntryHi. */
697 cpu
->CP0_EntryHi
&= ~0xff;
698 cpu
->CP0_EntryHi
|= tasid
;
703 /* Called for updates to CP0_EntryHi. */
704 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
707 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
711 if (tc
== cpu
->current_tc
) {
712 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
714 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
722 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
724 return env
->mvp
->CP0_MVPControl
;
727 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
729 return env
->mvp
->CP0_MVPConf0
;
732 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
734 return env
->mvp
->CP0_MVPConf1
;
737 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
739 return (int32_t)cpu_mips_get_random(env
);
742 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
744 return env
->active_tc
.CP0_TCStatus
;
747 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
749 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
750 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
752 if (other_tc
== other
->current_tc
)
753 return other
->active_tc
.CP0_TCStatus
;
755 return other
->tcs
[other_tc
].CP0_TCStatus
;
758 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
760 return env
->active_tc
.CP0_TCBind
;
763 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
765 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
766 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
768 if (other_tc
== other
->current_tc
)
769 return other
->active_tc
.CP0_TCBind
;
771 return other
->tcs
[other_tc
].CP0_TCBind
;
774 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
776 return env
->active_tc
.PC
;
779 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
781 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
782 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
784 if (other_tc
== other
->current_tc
)
785 return other
->active_tc
.PC
;
787 return other
->tcs
[other_tc
].PC
;
790 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
792 return env
->active_tc
.CP0_TCHalt
;
795 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
797 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
798 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
800 if (other_tc
== other
->current_tc
)
801 return other
->active_tc
.CP0_TCHalt
;
803 return other
->tcs
[other_tc
].CP0_TCHalt
;
806 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
808 return env
->active_tc
.CP0_TCContext
;
811 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
813 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
814 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
816 if (other_tc
== other
->current_tc
)
817 return other
->active_tc
.CP0_TCContext
;
819 return other
->tcs
[other_tc
].CP0_TCContext
;
822 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
824 return env
->active_tc
.CP0_TCSchedule
;
827 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
829 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
830 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
832 if (other_tc
== other
->current_tc
)
833 return other
->active_tc
.CP0_TCSchedule
;
835 return other
->tcs
[other_tc
].CP0_TCSchedule
;
838 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
840 return env
->active_tc
.CP0_TCScheFBack
;
843 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
845 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
846 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
848 if (other_tc
== other
->current_tc
)
849 return other
->active_tc
.CP0_TCScheFBack
;
851 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
854 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
856 return (int32_t)cpu_mips_get_count(env
);
859 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
861 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
862 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
864 return other
->CP0_EntryHi
;
867 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
869 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
871 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
873 if (other_tc
== other
->current_tc
) {
874 tccause
= other
->CP0_Cause
;
876 tccause
= other
->CP0_Cause
;
882 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
884 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
885 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
887 return other
->CP0_Status
;
890 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
892 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
895 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
897 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
900 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
902 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
905 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
907 return (int32_t)env
->CP0_WatchLo
[sel
];
910 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
912 return env
->CP0_WatchHi
[sel
];
915 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
917 target_ulong t0
= env
->CP0_Debug
;
918 if (env
->hflags
& MIPS_HFLAG_DM
)
924 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
926 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
928 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
930 if (other_tc
== other
->current_tc
)
931 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
933 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
935 /* XXX: Might be wrong, check with EJTAG spec. */
936 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
937 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
940 #if defined(TARGET_MIPS64)
941 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
943 return env
->active_tc
.PC
;
946 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
948 return env
->active_tc
.CP0_TCHalt
;
951 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
953 return env
->active_tc
.CP0_TCContext
;
956 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
958 return env
->active_tc
.CP0_TCSchedule
;
961 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
963 return env
->active_tc
.CP0_TCScheFBack
;
966 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
968 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
971 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
973 return env
->CP0_MAAR
[env
->CP0_MAARI
];
976 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
978 return env
->CP0_WatchLo
[sel
];
980 #endif /* TARGET_MIPS64 */
982 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
984 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
985 uint32_t tlb_index
= arg1
& 0x7fffffff;
986 if (tlb_index
< env
->tlb
->nb_tlb
) {
987 if (env
->insn_flags
& ISA_MIPS32R6
) {
988 index_p
|= arg1
& 0x80000000;
990 env
->CP0_Index
= index_p
| tlb_index
;
994 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
999 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
1000 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
1001 (1 << CP0MVPCo_EVP
);
1002 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1003 mask
|= (1 << CP0MVPCo_STLB
);
1004 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
1006 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1008 env
->mvp
->CP0_MVPControl
= newval
;
1011 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1016 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1017 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1018 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1020 /* Yield scheduler intercept not implemented. */
1021 /* Gating storage scheduler intercept not implemented. */
1023 // TODO: Enable/disable TCs.
1025 env
->CP0_VPEControl
= newval
;
1028 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1030 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1031 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1035 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1036 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1037 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1039 /* TODO: Enable/disable TCs. */
1041 other
->CP0_VPEControl
= newval
;
1044 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1046 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1047 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1048 /* FIXME: Mask away return zero on read bits. */
1049 return other
->CP0_VPEControl
;
1052 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1054 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1055 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1057 return other
->CP0_VPEConf0
;
1060 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1065 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1066 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1067 mask
|= (0xff << CP0VPEC0_XTC
);
1068 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1070 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1072 // TODO: TC exclusive handling due to ERL/EXL.
1074 env
->CP0_VPEConf0
= newval
;
1077 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1079 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1080 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1084 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1085 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1087 /* TODO: TC exclusive handling due to ERL/EXL. */
1088 other
->CP0_VPEConf0
= newval
;
1091 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1096 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1097 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1098 (0xff << CP0VPEC1_NCP1
);
1099 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1101 /* UDI not implemented. */
1102 /* CP2 not implemented. */
1104 // TODO: Handle FPU (CP1) binding.
1106 env
->CP0_VPEConf1
= newval
;
1109 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1111 /* Yield qualifier inputs not implemented. */
1112 env
->CP0_YQMask
= 0x00000000;
1115 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1117 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1120 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1122 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1124 /* 1k pages not implemented */
1125 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1126 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1127 | (rxi
<< (CP0EnLo_XI
- 30));
1130 #if defined(TARGET_MIPS64)
1131 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1133 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1135 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1136 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1140 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1142 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1145 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1147 env
->active_tc
.CP0_TCStatus
= newval
;
1148 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1151 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1153 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1154 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1156 if (other_tc
== other
->current_tc
)
1157 other
->active_tc
.CP0_TCStatus
= arg1
;
1159 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1160 sync_c0_tcstatus(other
, other_tc
, arg1
);
1163 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1165 uint32_t mask
= (1 << CP0TCBd_TBE
);
1168 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1169 mask
|= (1 << CP0TCBd_CurVPE
);
1170 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1171 env
->active_tc
.CP0_TCBind
= newval
;
1174 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1176 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1177 uint32_t mask
= (1 << CP0TCBd_TBE
);
1179 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1181 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1182 mask
|= (1 << CP0TCBd_CurVPE
);
1183 if (other_tc
== other
->current_tc
) {
1184 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1185 other
->active_tc
.CP0_TCBind
= newval
;
1187 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1188 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1192 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1194 env
->active_tc
.PC
= arg1
;
1195 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1197 /* MIPS16 not implemented. */
1200 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1202 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1203 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1205 if (other_tc
== other
->current_tc
) {
1206 other
->active_tc
.PC
= arg1
;
1207 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1208 other
->lladdr
= 0ULL;
1209 /* MIPS16 not implemented. */
1211 other
->tcs
[other_tc
].PC
= arg1
;
1212 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1213 other
->lladdr
= 0ULL;
1214 /* MIPS16 not implemented. */
1218 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1220 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1222 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1224 // TODO: Halt TC / Restart (if allocated+active) TC.
1225 if (env
->active_tc
.CP0_TCHalt
& 1) {
1226 mips_tc_sleep(cpu
, env
->current_tc
);
1228 mips_tc_wake(cpu
, env
->current_tc
);
1232 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1234 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1235 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1236 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1238 // TODO: Halt TC / Restart (if allocated+active) TC.
1240 if (other_tc
== other
->current_tc
)
1241 other
->active_tc
.CP0_TCHalt
= arg1
;
1243 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1246 mips_tc_sleep(other_cpu
, other_tc
);
1248 mips_tc_wake(other_cpu
, other_tc
);
1252 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1254 env
->active_tc
.CP0_TCContext
= arg1
;
1257 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1259 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1260 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1262 if (other_tc
== other
->current_tc
)
1263 other
->active_tc
.CP0_TCContext
= arg1
;
1265 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1268 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1270 env
->active_tc
.CP0_TCSchedule
= arg1
;
1273 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1275 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1276 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1278 if (other_tc
== other
->current_tc
)
1279 other
->active_tc
.CP0_TCSchedule
= arg1
;
1281 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1284 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1286 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1289 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1291 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1292 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1294 if (other_tc
== other
->current_tc
)
1295 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1297 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1300 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1302 /* 1k pages not implemented */
1303 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1304 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1305 | (rxi
<< (CP0EnLo_XI
- 30));
1308 #if defined(TARGET_MIPS64)
1309 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1311 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1312 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1316 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1318 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1321 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1323 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1324 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1325 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1326 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1327 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1328 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1332 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1334 /* SmartMIPS not implemented */
1335 /* 1k pages not implemented */
1336 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1337 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1338 compute_hflags(env
);
1339 restore_pamask(env
);
1342 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1344 if (env
->insn_flags
& ISA_MIPS32R6
) {
1345 if (arg1
< env
->tlb
->nb_tlb
) {
1346 env
->CP0_Wired
= arg1
;
1349 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1353 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1355 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1358 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1360 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1363 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1365 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1368 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1370 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1373 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1375 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1378 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1380 uint32_t mask
= 0x0000000F;
1382 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1383 (env
->insn_flags
& ISA_MIPS32R6
)) {
1386 if (env
->insn_flags
& ISA_MIPS32R6
) {
1389 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1392 if (arg1
& (1 << 29)) {
1393 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1395 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1399 env
->CP0_HWREna
= arg1
& mask
;
1402 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1404 cpu_mips_store_count(env
, arg1
);
1407 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1409 target_ulong old
, val
, mask
;
1410 mask
= (TARGET_PAGE_MASK
<< 1) | 0xFF;
1411 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1412 mask
|= 1 << CP0EnHi_EHINV
;
1415 /* 1k pages not implemented */
1416 #if defined(TARGET_MIPS64)
1417 if (env
->insn_flags
& ISA_MIPS32R6
) {
1418 int entryhi_r
= extract64(arg1
, 62, 2);
1419 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1420 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1421 if ((entryhi_r
== 2) ||
1422 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1423 /* skip EntryHi.R field if new value is reserved */
1424 mask
&= ~(0x3ull
<< 62);
1427 mask
&= env
->SEGMask
;
1429 old
= env
->CP0_EntryHi
;
1430 val
= (arg1
& mask
) | (old
& ~mask
);
1431 env
->CP0_EntryHi
= val
;
1432 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1433 sync_c0_entryhi(env
, env
->current_tc
);
1435 /* If the ASID changes, flush qemu's TLB. */
1436 if ((old
& 0xFF) != (val
& 0xFF))
1437 cpu_mips_tlb_flush(env
, 1);
1440 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1442 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1443 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1445 other
->CP0_EntryHi
= arg1
;
1446 sync_c0_entryhi(other
, other_tc
);
1449 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1451 cpu_mips_store_compare(env
, arg1
);
1454 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1456 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1459 old
= env
->CP0_Status
;
1460 cpu_mips_store_status(env
, arg1
);
1461 val
= env
->CP0_Status
;
1463 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1464 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1465 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1466 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1468 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1469 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1470 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1471 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1473 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1479 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1481 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1482 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1483 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1485 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1486 sync_c0_status(env
, other
, other_tc
);
1489 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1491 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1494 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1496 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1497 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1500 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1502 cpu_mips_store_cause(env
, arg1
);
1505 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1507 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1508 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1510 cpu_mips_store_cause(other
, arg1
);
1513 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1515 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1516 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1518 return other
->CP0_EPC
;
1521 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1523 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1524 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1526 return other
->CP0_EBase
;
1529 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1531 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1534 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1536 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1537 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1538 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1541 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1543 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1544 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1547 case 0: return other
->CP0_Config0
;
1548 case 1: return other
->CP0_Config1
;
1549 case 2: return other
->CP0_Config2
;
1550 case 3: return other
->CP0_Config3
;
1551 /* 4 and 5 are reserved. */
1552 case 6: return other
->CP0_Config6
;
1553 case 7: return other
->CP0_Config7
;
1560 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1562 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1565 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1567 /* tertiary/secondary caches not implemented */
1568 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1571 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1573 if (env
->insn_flags
& ASE_MICROMIPS
) {
1574 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1575 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1579 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1581 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1582 (arg1
& env
->CP0_Config4_rw_bitmask
);
1585 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1587 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1588 (arg1
& env
->CP0_Config5_rw_bitmask
);
1589 compute_hflags(env
);
1592 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1594 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1595 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1596 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1599 #define MTC0_MAAR_MASK(env) \
1600 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1602 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1604 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1607 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1609 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1610 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1611 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1614 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1616 int index
= arg1
& 0x3f;
1617 if (index
== 0x3f) {
1618 /* Software may write all ones to INDEX to determine the
1619 maximum value supported. */
1620 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1621 } else if (index
< MIPS_MAAR_MAX
) {
1622 env
->CP0_MAARI
= index
;
1624 /* Other than the all ones, if the
1625 value written is not supported, then INDEX is unchanged
1626 from its previous value. */
1629 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1631 /* Watch exceptions for instructions, data loads, data stores
1633 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1636 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1638 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1639 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1642 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1644 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1645 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1648 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1650 env
->CP0_Framemask
= arg1
; /* XXX */
1653 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1655 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1656 if (arg1
& (1 << CP0DB_DM
))
1657 env
->hflags
|= MIPS_HFLAG_DM
;
1659 env
->hflags
&= ~MIPS_HFLAG_DM
;
1662 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1664 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1665 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1666 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1668 /* XXX: Might be wrong, check with EJTAG spec. */
1669 if (other_tc
== other
->current_tc
)
1670 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1672 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1673 other
->CP0_Debug
= (other
->CP0_Debug
&
1674 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1675 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1678 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1680 env
->CP0_Performance0
= arg1
& 0x000007ff;
1683 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1685 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1686 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1687 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1689 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1691 if (itc
&& !wst
&& !spr
) {
1692 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1694 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1698 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1700 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1701 /* If CACHE instruction is configured for ITC tags then make all
1702 CP0.TagLo bits writable. The actual write to ITC Configuration
1703 Tag will take care of the read-only bits. */
1704 env
->CP0_TagLo
= arg1
;
1706 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1710 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1712 env
->CP0_DataLo
= arg1
; /* XXX */
1715 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1717 env
->CP0_TagHi
= arg1
; /* XXX */
1720 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1722 env
->CP0_DataHi
= arg1
; /* XXX */
1725 /* MIPS MT functions */
1726 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1728 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1729 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1731 if (other_tc
== other
->current_tc
)
1732 return other
->active_tc
.gpr
[sel
];
1734 return other
->tcs
[other_tc
].gpr
[sel
];
1737 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1739 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1740 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1742 if (other_tc
== other
->current_tc
)
1743 return other
->active_tc
.LO
[sel
];
1745 return other
->tcs
[other_tc
].LO
[sel
];
1748 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1750 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1751 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1753 if (other_tc
== other
->current_tc
)
1754 return other
->active_tc
.HI
[sel
];
1756 return other
->tcs
[other_tc
].HI
[sel
];
1759 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1761 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1762 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1764 if (other_tc
== other
->current_tc
)
1765 return other
->active_tc
.ACX
[sel
];
1767 return other
->tcs
[other_tc
].ACX
[sel
];
1770 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1772 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1773 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1775 if (other_tc
== other
->current_tc
)
1776 return other
->active_tc
.DSPControl
;
1778 return other
->tcs
[other_tc
].DSPControl
;
1781 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1783 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1784 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1786 if (other_tc
== other
->current_tc
)
1787 other
->active_tc
.gpr
[sel
] = arg1
;
1789 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1792 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1794 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1795 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1797 if (other_tc
== other
->current_tc
)
1798 other
->active_tc
.LO
[sel
] = arg1
;
1800 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1803 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1805 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1806 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1808 if (other_tc
== other
->current_tc
)
1809 other
->active_tc
.HI
[sel
] = arg1
;
1811 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1814 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1816 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1817 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1819 if (other_tc
== other
->current_tc
)
1820 other
->active_tc
.ACX
[sel
] = arg1
;
1822 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1825 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1827 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1828 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1830 if (other_tc
== other
->current_tc
)
1831 other
->active_tc
.DSPControl
= arg1
;
1833 other
->tcs
[other_tc
].DSPControl
= arg1
;
1836 /* MIPS MT functions */
1837 target_ulong
helper_dmt(void)
1843 target_ulong
helper_emt(void)
1849 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1851 CPUState
*other_cs
= first_cpu
;
1852 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1854 CPU_FOREACH(other_cs
) {
1855 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1856 /* Turn off all VPEs except the one executing the dvpe. */
1857 if (&other_cpu
->env
!= env
) {
1858 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1859 mips_vpe_sleep(other_cpu
);
1865 target_ulong
helper_evpe(CPUMIPSState
*env
)
1867 CPUState
*other_cs
= first_cpu
;
1868 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1870 CPU_FOREACH(other_cs
) {
1871 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1873 if (&other_cpu
->env
!= env
1874 /* If the VPE is WFI, don't disturb its sleep. */
1875 && !mips_vpe_is_wfi(other_cpu
)) {
1876 /* Enable the VPE. */
1877 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1878 mips_vpe_wake(other_cpu
); /* And wake it up. */
1883 #endif /* !CONFIG_USER_ONLY */
1885 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1887 fprintf(stderr
, "%s:%u - %s\n", __FILE__
, __LINE__
, __func__
);
1888 // arg1 = rt, arg2 = rs
1889 // TODO: store to TC register, assert to detect test cases.
1890 g_assert_not_reached();
1893 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1895 target_long arg1
= arg
;
1898 /* No scheduling policy implemented. */
1900 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1901 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1902 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1903 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1904 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1907 } else if (arg1
== 0) {
1908 if (0 /* TODO: TC underflow */) {
1909 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1910 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1912 // TODO: Deallocate TC
1914 } else if (arg1
> 0) {
1915 /* Yield qualifier inputs not implemented. */
1916 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1917 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1918 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1920 return env
->CP0_YQMask
;
1923 /* R6 Multi-threading */
1924 #ifndef CONFIG_USER_ONLY
1925 target_ulong
helper_dvp(CPUMIPSState
*env
)
1927 CPUState
*other_cs
= first_cpu
;
1928 target_ulong prev
= env
->CP0_VPControl
;
1930 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
1931 CPU_FOREACH(other_cs
) {
1932 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1933 /* Turn off all VPs except the one executing the dvp. */
1934 if (&other_cpu
->env
!= env
) {
1935 mips_vpe_sleep(other_cpu
);
1938 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
1943 target_ulong
helper_evp(CPUMIPSState
*env
)
1945 CPUState
*other_cs
= first_cpu
;
1946 target_ulong prev
= env
->CP0_VPControl
;
1948 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
1949 CPU_FOREACH(other_cs
) {
1950 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1951 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
1952 /* If the VP is WFI, don't disturb its sleep.
1953 * Otherwise, wake it up. */
1954 mips_vpe_wake(other_cpu
);
1957 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
1961 #endif /* !CONFIG_USER_ONLY */
1963 #ifndef CONFIG_USER_ONLY
1964 /* TLB management */
1965 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1967 /* Discard entries from env->tlb[first] onwards. */
1968 while (env
->tlb
->tlb_in_use
> first
) {
1969 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1973 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
1975 #if defined(TARGET_MIPS64)
1976 return extract64(entrylo
, 6, 54);
1978 return extract64(entrylo
, 6, 24) | /* PFN */
1979 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
1983 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
1987 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1988 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1989 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
1994 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1995 #if defined(TARGET_MIPS64)
1996 tlb
->VPN
&= env
->SEGMask
;
1998 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1999 tlb
->PageMask
= env
->CP0_PageMask
;
2000 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2001 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
2002 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
2003 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
2004 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
2005 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
2006 tlb
->PFN
[0] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) << 12;
2007 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
2008 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
2009 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
2010 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
2011 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
2012 tlb
->PFN
[1] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) << 12;
2015 void r4k_helper_tlbinv(CPUMIPSState
*env
)
2019 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
2021 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2022 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2023 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
2027 cpu_mips_tlb_flush(env
, 1);
2030 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
2034 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
2035 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
2037 cpu_mips_tlb_flush(env
, 1);
2040 void r4k_helper_tlbwi(CPUMIPSState
*env
)
2046 bool G
, V0
, D0
, V1
, D1
;
2048 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2049 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2050 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
2051 #if defined(TARGET_MIPS64)
2052 VPN
&= env
->SEGMask
;
2054 ASID
= env
->CP0_EntryHi
& 0xff;
2055 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
2056 V0
= (env
->CP0_EntryLo0
& 2) != 0;
2057 D0
= (env
->CP0_EntryLo0
& 4) != 0;
2058 V1
= (env
->CP0_EntryLo1
& 2) != 0;
2059 D1
= (env
->CP0_EntryLo1
& 4) != 0;
2061 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2062 permissions on the current entry. */
2063 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
2064 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
2065 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
)) {
2066 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2069 r4k_invalidate_tlb(env
, idx
, 0);
2070 r4k_fill_tlb(env
, idx
);
2073 void r4k_helper_tlbwr(CPUMIPSState
*env
)
2075 int r
= cpu_mips_get_random(env
);
2077 r4k_invalidate_tlb(env
, r
, 1);
2078 r4k_fill_tlb(env
, r
);
2081 void r4k_helper_tlbp(CPUMIPSState
*env
)
2090 ASID
= env
->CP0_EntryHi
& 0xFF;
2091 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
2092 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2093 /* 1k pages are not supported. */
2094 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2095 tag
= env
->CP0_EntryHi
& ~mask
;
2096 VPN
= tlb
->VPN
& ~mask
;
2097 #if defined(TARGET_MIPS64)
2098 tag
&= env
->SEGMask
;
2100 /* Check ASID, virtual page number & size */
2101 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2107 if (i
== env
->tlb
->nb_tlb
) {
2108 /* No match. Discard any shadow entries, if any of them match. */
2109 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2110 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2111 /* 1k pages are not supported. */
2112 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2113 tag
= env
->CP0_EntryHi
& ~mask
;
2114 VPN
= tlb
->VPN
& ~mask
;
2115 #if defined(TARGET_MIPS64)
2116 tag
&= env
->SEGMask
;
2118 /* Check ASID, virtual page number & size */
2119 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2120 r4k_mips_tlb_flush_extra (env
, i
);
2125 env
->CP0_Index
|= 0x80000000;
2129 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2131 #if defined(TARGET_MIPS64)
2132 return tlb_pfn
<< 6;
2134 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2135 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2139 void r4k_helper_tlbr(CPUMIPSState
*env
)
2145 ASID
= env
->CP0_EntryHi
& 0xFF;
2146 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2147 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2149 /* If this will change the current ASID, flush qemu's TLB. */
2150 if (ASID
!= tlb
->ASID
)
2151 cpu_mips_tlb_flush (env
, 1);
2153 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2156 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2157 env
->CP0_PageMask
= 0;
2158 env
->CP0_EntryLo0
= 0;
2159 env
->CP0_EntryLo1
= 0;
2161 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2162 env
->CP0_PageMask
= tlb
->PageMask
;
2163 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2164 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2165 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2166 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2167 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2168 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2169 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2170 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2174 void helper_tlbwi(CPUMIPSState
*env
)
2176 env
->tlb
->helper_tlbwi(env
);
2179 void helper_tlbwr(CPUMIPSState
*env
)
2181 env
->tlb
->helper_tlbwr(env
);
2184 void helper_tlbp(CPUMIPSState
*env
)
2186 env
->tlb
->helper_tlbp(env
);
2189 void helper_tlbr(CPUMIPSState
*env
)
2191 env
->tlb
->helper_tlbr(env
);
2194 void helper_tlbinv(CPUMIPSState
*env
)
2196 env
->tlb
->helper_tlbinv(env
);
2199 void helper_tlbinvf(CPUMIPSState
*env
)
2201 env
->tlb
->helper_tlbinvf(env
);
2205 target_ulong
helper_di(CPUMIPSState
*env
)
2207 target_ulong t0
= env
->CP0_Status
;
2209 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2213 target_ulong
helper_ei(CPUMIPSState
*env
)
2215 target_ulong t0
= env
->CP0_Status
;
2217 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2221 static void debug_pre_eret(CPUMIPSState
*env
)
2223 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2224 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2225 env
->active_tc
.PC
, env
->CP0_EPC
);
2226 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2227 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2228 if (env
->hflags
& MIPS_HFLAG_DM
)
2229 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2234 static void debug_post_eret(CPUMIPSState
*env
)
2236 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2238 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2239 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2240 env
->active_tc
.PC
, env
->CP0_EPC
);
2241 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2242 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2243 if (env
->hflags
& MIPS_HFLAG_DM
)
2244 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2245 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
2246 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2247 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2248 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2250 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2256 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2258 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2260 env
->hflags
|= MIPS_HFLAG_M16
;
2262 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2266 static inline void exception_return(CPUMIPSState
*env
)
2268 debug_pre_eret(env
);
2269 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2270 set_pc(env
, env
->CP0_ErrorEPC
);
2271 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2273 set_pc(env
, env
->CP0_EPC
);
2274 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2276 compute_hflags(env
);
2277 debug_post_eret(env
);
2280 void helper_eret(CPUMIPSState
*env
)
2282 exception_return(env
);
2286 void helper_eretnc(CPUMIPSState
*env
)
2288 exception_return(env
);
2291 void helper_deret(CPUMIPSState
*env
)
2293 debug_pre_eret(env
);
2294 set_pc(env
, env
->CP0_DEPC
);
2296 env
->hflags
&= ~MIPS_HFLAG_DM
;
2297 compute_hflags(env
);
2298 debug_post_eret(env
);
2300 #endif /* !CONFIG_USER_ONLY */
2302 static inline void check_hwrena(CPUMIPSState
*env
, int reg
, uintptr_t pc
)
2304 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2307 do_raise_exception(env
, EXCP_RI
, pc
);
2310 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2312 check_hwrena(env
, 0, GETPC());
2313 return env
->CP0_EBase
& 0x3ff;
2316 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2318 check_hwrena(env
, 1, GETPC());
2319 return env
->SYNCI_Step
;
2322 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2324 check_hwrena(env
, 2, GETPC());
2325 #ifdef CONFIG_USER_ONLY
2326 return env
->CP0_Count
;
2328 return (int32_t)cpu_mips_get_count(env
);
2332 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2334 check_hwrena(env
, 3, GETPC());
2338 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2340 check_hwrena(env
, 4, GETPC());
2341 return env
->CP0_Performance0
;
2344 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2346 check_hwrena(env
, 5, GETPC());
2347 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2350 void helper_pmon(CPUMIPSState
*env
, int function
)
2354 case 2: /* TODO: char inbyte(int waitflag); */
2355 if (env
->active_tc
.gpr
[4] == 0)
2356 env
->active_tc
.gpr
[2] = -1;
2358 case 11: /* TODO: char inbyte (void); */
2359 env
->active_tc
.gpr
[2] = -1;
2363 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2367 #ifndef CONFIG_USER_ONLY
2370 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2378 void QEMU_NORETURN
helper_wait(CPUMIPSState
*env
)
2380 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2383 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2384 /* Last instruction in the block, PC was updated before
2385 - no need to recover PC and icount */
2386 raise_exception(env
, EXCP_HLT
);
2389 #if !defined(CONFIG_USER_ONLY)
2391 void QEMU_NORETURN
mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2392 int access_type
, int is_user
,
2395 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2396 CPUMIPSState
*env
= &cpu
->env
;
2400 env
->CP0_BadVAddr
= addr
;
2402 if (access_type
== MMU_DATA_STORE
) {
2406 if (access_type
== MMU_INST_FETCH
) {
2407 error_code
|= EXCP_INST_NOTAVAIL
;
2411 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2414 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
2419 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
2421 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2422 CPUMIPSState
*env
= &cpu
->env
;
2424 do_raise_exception_err(env
, cs
->exception_index
,
2425 env
->error_code
, retaddr
);
2429 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2430 bool is_write
, bool is_exec
, int unused
,
2433 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2434 CPUMIPSState
*env
= &cpu
->env
;
2437 * Raising an exception with KVM enabled will crash because it won't be from
2438 * the main execution loop so the longjmp won't have a matching setjmp.
2439 * Until we can trigger a bus error exception through KVM lets just ignore
2442 if (kvm_enabled()) {
2443 /* TODO: here a return was replaced by an assertion. */
2444 g_assert_not_reached();
2448 raise_exception(env
, EXCP_IBE
);
2450 raise_exception(env
, EXCP_DBE
);
2453 #endif /* !CONFIG_USER_ONLY */
2455 /* Complex FPU operations which may need stack space. */
2457 #define FLOAT_TWO32 make_float32(1 << 30)
2458 #define FLOAT_TWO64 make_float64(1ULL << 62)
2459 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2460 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2462 /* convert MIPS rounding mode in FCR31 to IEEE library */
2463 unsigned int ieee_rm
[] = {
2464 float_round_nearest_even
,
2465 float_round_to_zero
,
2470 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2472 target_ulong arg1
= 0;
2476 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2479 /* UFR Support - Read Status FR */
2480 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2481 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2483 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2485 do_raise_exception(env
, EXCP_RI
, GETPC());
2490 /* FRE Support - read Config5.FRE bit */
2491 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2492 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2493 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2495 helper_raise_exception(env
, EXCP_RI
);
2500 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2503 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2506 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2509 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2516 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2520 /* UFR Alias - Reset Status FR */
2521 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2524 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2525 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2526 compute_hflags(env
);
2528 do_raise_exception(env
, EXCP_RI
, GETPC());
2532 /* UNFR Alias - Set Status FR */
2533 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2536 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2537 env
->CP0_Status
|= (1 << CP0St_FR
);
2538 compute_hflags(env
);
2540 do_raise_exception(env
, EXCP_RI
, GETPC());
2544 /* FRE Support - clear Config5.FRE bit */
2545 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2548 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2549 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2550 compute_hflags(env
);
2552 helper_raise_exception(env
, EXCP_RI
);
2556 /* FRE Support - set Config5.FRE bit */
2557 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2560 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2561 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2562 compute_hflags(env
);
2564 helper_raise_exception(env
, EXCP_RI
);
2568 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2571 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2572 ((arg1
& 0x1) << 23);
2575 if (arg1
& 0x007c0000)
2577 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2580 if (arg1
& 0x007c0000)
2582 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2583 ((arg1
& 0x4) << 22);
2586 if (env
->insn_flags
& ISA_MIPS32R6
) {
2587 uint32_t mask
= 0xfefc0000;
2588 env
->active_fpu
.fcr31
= (arg1
& ~mask
) |
2589 (env
->active_fpu
.fcr31
& mask
);
2590 } else if (!(arg1
& 0x007c0000)) {
2591 env
->active_fpu
.fcr31
= arg1
;
2597 /* set rounding mode */
2598 restore_rounding_mode(env
);
2599 /* set flush-to-zero mode */
2600 restore_flush_mode(env
);
2601 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2602 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
)) {
2603 do_raise_exception(env
, EXCP_FPE
, GETPC());
2607 int ieee_ex_to_mips(int xcpt
)
2611 if (xcpt
& float_flag_invalid
) {
2614 if (xcpt
& float_flag_overflow
) {
2617 if (xcpt
& float_flag_underflow
) {
2618 ret
|= FP_UNDERFLOW
;
2620 if (xcpt
& float_flag_divbyzero
) {
2623 if (xcpt
& float_flag_inexact
) {
2630 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2632 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2634 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2637 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2639 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2640 do_raise_exception(env
, EXCP_FPE
, pc
);
2642 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2648 Single precition routines have a "s" suffix, double precision a
2649 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2650 paired single lower "pl", paired single upper "pu". */
2652 /* unary operations, modifying fp status */
2653 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2655 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2656 update_fcr31(env
, GETPC());
2660 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2662 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2663 update_fcr31(env
, GETPC());
2667 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2671 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2672 fdt2
= float64_maybe_silence_nan(fdt2
);
2673 update_fcr31(env
, GETPC());
2677 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2681 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2682 update_fcr31(env
, GETPC());
2686 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2690 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2691 update_fcr31(env
, GETPC());
2695 uint64_t helper_float_cvtl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2699 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2700 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2701 & (float_flag_invalid
| float_flag_overflow
)) {
2702 dt2
= FP_TO_INT64_OVERFLOW
;
2704 update_fcr31(env
, GETPC());
2708 uint64_t helper_float_cvtl_s(CPUMIPSState
*env
, uint32_t fst0
)
2712 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2713 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2714 & (float_flag_invalid
| float_flag_overflow
)) {
2715 dt2
= FP_TO_INT64_OVERFLOW
;
2717 update_fcr31(env
, GETPC());
2721 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2726 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2727 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2728 update_fcr31(env
, GETPC());
2729 return ((uint64_t)fsth2
<< 32) | fst2
;
2732 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2738 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2739 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2740 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2741 wt2
= FP_TO_INT32_OVERFLOW
;
2744 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2745 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2746 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2747 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2748 wth2
= FP_TO_INT32_OVERFLOW
;
2751 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2752 update_fcr31(env
, GETPC());
2754 return ((uint64_t)wth2
<< 32) | wt2
;
2757 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2761 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2762 fst2
= float32_maybe_silence_nan(fst2
);
2763 update_fcr31(env
, GETPC());
2767 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2771 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2772 update_fcr31(env
, GETPC());
2776 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2780 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2781 update_fcr31(env
, GETPC());
2785 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2790 update_fcr31(env
, GETPC());
2794 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2799 update_fcr31(env
, GETPC());
2803 uint32_t helper_float_cvtw_s(CPUMIPSState
*env
, uint32_t fst0
)
2807 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2808 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2809 & (float_flag_invalid
| float_flag_overflow
)) {
2810 wt2
= FP_TO_INT32_OVERFLOW
;
2812 update_fcr31(env
, GETPC());
2816 uint32_t helper_float_cvtw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2820 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2821 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2822 & (float_flag_invalid
| float_flag_overflow
)) {
2823 wt2
= FP_TO_INT32_OVERFLOW
;
2825 update_fcr31(env
, GETPC());
2829 uint64_t helper_float_roundl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2833 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2834 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2835 restore_rounding_mode(env
);
2836 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2837 & (float_flag_invalid
| float_flag_overflow
)) {
2838 dt2
= FP_TO_INT64_OVERFLOW
;
2840 update_fcr31(env
, GETPC());
2844 uint64_t helper_float_roundl_s(CPUMIPSState
*env
, uint32_t fst0
)
2848 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2849 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2850 restore_rounding_mode(env
);
2851 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2852 & (float_flag_invalid
| float_flag_overflow
)) {
2853 dt2
= FP_TO_INT64_OVERFLOW
;
2855 update_fcr31(env
, GETPC());
2859 uint32_t helper_float_roundw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2863 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2864 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2865 restore_rounding_mode(env
);
2866 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2867 & (float_flag_invalid
| float_flag_overflow
)) {
2868 wt2
= FP_TO_INT32_OVERFLOW
;
2870 update_fcr31(env
, GETPC());
2874 uint32_t helper_float_roundw_s(CPUMIPSState
*env
, uint32_t fst0
)
2878 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2879 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2880 restore_rounding_mode(env
);
2881 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2882 & (float_flag_invalid
| float_flag_overflow
)) {
2883 wt2
= FP_TO_INT32_OVERFLOW
;
2885 update_fcr31(env
, GETPC());
2889 uint64_t helper_float_truncl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2893 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2894 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2895 & (float_flag_invalid
| float_flag_overflow
)) {
2896 dt2
= FP_TO_INT64_OVERFLOW
;
2898 update_fcr31(env
, GETPC());
2902 uint64_t helper_float_truncl_s(CPUMIPSState
*env
, uint32_t fst0
)
2906 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2907 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2908 & (float_flag_invalid
| float_flag_overflow
)) {
2909 dt2
= FP_TO_INT64_OVERFLOW
;
2911 update_fcr31(env
, GETPC());
2915 uint32_t helper_float_truncw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2919 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2920 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2921 & (float_flag_invalid
| float_flag_overflow
)) {
2922 wt2
= FP_TO_INT32_OVERFLOW
;
2924 update_fcr31(env
, GETPC());
2928 uint32_t helper_float_truncw_s(CPUMIPSState
*env
, uint32_t fst0
)
2932 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2933 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2934 & (float_flag_invalid
| float_flag_overflow
)) {
2935 wt2
= FP_TO_INT32_OVERFLOW
;
2937 update_fcr31(env
, GETPC());
2941 uint64_t helper_float_ceill_d(CPUMIPSState
*env
, uint64_t fdt0
)
2945 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2946 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2947 restore_rounding_mode(env
);
2948 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2949 & (float_flag_invalid
| float_flag_overflow
)) {
2950 dt2
= FP_TO_INT64_OVERFLOW
;
2952 update_fcr31(env
, GETPC());
2956 uint64_t helper_float_ceill_s(CPUMIPSState
*env
, uint32_t fst0
)
2960 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2961 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2962 restore_rounding_mode(env
);
2963 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2964 & (float_flag_invalid
| float_flag_overflow
)) {
2965 dt2
= FP_TO_INT64_OVERFLOW
;
2967 update_fcr31(env
, GETPC());
2971 uint32_t helper_float_ceilw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2975 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2976 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2977 restore_rounding_mode(env
);
2978 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2979 & (float_flag_invalid
| float_flag_overflow
)) {
2980 wt2
= FP_TO_INT32_OVERFLOW
;
2982 update_fcr31(env
, GETPC());
2986 uint32_t helper_float_ceilw_s(CPUMIPSState
*env
, uint32_t fst0
)
2990 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2991 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2992 restore_rounding_mode(env
);
2993 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2994 & (float_flag_invalid
| float_flag_overflow
)) {
2995 wt2
= FP_TO_INT32_OVERFLOW
;
2997 update_fcr31(env
, GETPC());
3001 uint64_t helper_float_floorl_d(CPUMIPSState
*env
, uint64_t fdt0
)
3005 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3006 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
3007 restore_rounding_mode(env
);
3008 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3009 & (float_flag_invalid
| float_flag_overflow
)) {
3010 dt2
= FP_TO_INT64_OVERFLOW
;
3012 update_fcr31(env
, GETPC());
3016 uint64_t helper_float_floorl_s(CPUMIPSState
*env
, uint32_t fst0
)
3020 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3021 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
3022 restore_rounding_mode(env
);
3023 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3024 & (float_flag_invalid
| float_flag_overflow
)) {
3025 dt2
= FP_TO_INT64_OVERFLOW
;
3027 update_fcr31(env
, GETPC());
3031 uint32_t helper_float_floorw_d(CPUMIPSState
*env
, uint64_t fdt0
)
3035 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3036 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
3037 restore_rounding_mode(env
);
3038 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3039 & (float_flag_invalid
| float_flag_overflow
)) {
3040 wt2
= FP_TO_INT32_OVERFLOW
;
3042 update_fcr31(env
, GETPC());
3046 uint32_t helper_float_floorw_s(CPUMIPSState
*env
, uint32_t fst0
)
3050 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
3051 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
3052 restore_rounding_mode(env
);
3053 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
3054 & (float_flag_invalid
| float_flag_overflow
)) {
3055 wt2
= FP_TO_INT32_OVERFLOW
;
3057 update_fcr31(env
, GETPC());
3061 /* unary operations, not modifying fp status */
3062 #define FLOAT_UNOP(name) \
3063 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3065 return float64_ ## name(fdt0); \
3067 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3069 return float32_ ## name(fst0); \
3071 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3076 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3077 wth0 = float32_ ## name(fdt0 >> 32); \
3078 return ((uint64_t)wth0 << 32) | wt0; \
3084 /* MIPS specific unary operations */
3085 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
3089 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3090 update_fcr31(env
, GETPC());
3094 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
3098 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3099 update_fcr31(env
, GETPC());
3103 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
3107 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3108 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3109 update_fcr31(env
, GETPC());
3113 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3117 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3118 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3119 update_fcr31(env
, GETPC());
3123 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3127 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3128 update_fcr31(env
, GETPC());
3132 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3136 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3137 update_fcr31(env
, GETPC());
3141 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3146 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3147 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3148 update_fcr31(env
, GETPC());
3149 return ((uint64_t)fsth2
<< 32) | fst2
;
3152 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3156 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3157 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3158 update_fcr31(env
, GETPC());
3162 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3166 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3167 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3168 update_fcr31(env
, GETPC());
3172 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3177 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3178 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3179 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3180 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3181 update_fcr31(env
, GETPC());
3182 return ((uint64_t)fsth2
<< 32) | fst2
;
3185 #define FLOAT_RINT(name, bits) \
3186 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3187 uint ## bits ## _t fs) \
3189 uint ## bits ## _t fdret; \
3191 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3192 update_fcr31(env, GETPC()); \
3196 FLOAT_RINT(rint_s
, 32)
3197 FLOAT_RINT(rint_d
, 64)
3200 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3201 #define FLOAT_CLASS_QUIET_NAN 0x002
3202 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3203 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3204 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3205 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3206 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3207 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3208 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3209 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3211 #define FLOAT_CLASS(name, bits) \
3212 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3214 if (float ## bits ## _is_signaling_nan(arg)) { \
3215 return FLOAT_CLASS_SIGNALING_NAN; \
3216 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3217 return FLOAT_CLASS_QUIET_NAN; \
3218 } else if (float ## bits ## _is_neg(arg)) { \
3219 if (float ## bits ## _is_infinity(arg)) { \
3220 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3221 } else if (float ## bits ## _is_zero(arg)) { \
3222 return FLOAT_CLASS_NEGATIVE_ZERO; \
3223 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3224 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3226 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3229 if (float ## bits ## _is_infinity(arg)) { \
3230 return FLOAT_CLASS_POSITIVE_INFINITY; \
3231 } else if (float ## bits ## _is_zero(arg)) { \
3232 return FLOAT_CLASS_POSITIVE_ZERO; \
3233 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3234 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3236 return FLOAT_CLASS_POSITIVE_NORMAL; \
3241 FLOAT_CLASS(class_s
, 32)
3242 FLOAT_CLASS(class_d
, 64)
3245 /* binary operations */
3246 #define FLOAT_BINOP(name) \
3247 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3248 uint64_t fdt0, uint64_t fdt1) \
3252 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3253 update_fcr31(env, GETPC()); \
3257 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3258 uint32_t fst0, uint32_t fst1) \
3262 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3263 update_fcr31(env, GETPC()); \
3267 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3271 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3272 uint32_t fsth0 = fdt0 >> 32; \
3273 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3274 uint32_t fsth1 = fdt1 >> 32; \
3278 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3279 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3280 update_fcr31(env, GETPC()); \
3281 return ((uint64_t)wth2 << 32) | wt2; \
3290 /* MIPS specific binary operations */
3291 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3293 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3294 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3295 update_fcr31(env
, GETPC());
3299 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3301 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3302 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3303 update_fcr31(env
, GETPC());
3307 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3309 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3310 uint32_t fsth0
= fdt0
>> 32;
3311 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3312 uint32_t fsth2
= fdt2
>> 32;
3314 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3315 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3316 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3317 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3318 update_fcr31(env
, GETPC());
3319 return ((uint64_t)fsth2
<< 32) | fst2
;
3322 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3324 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3325 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3326 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3327 update_fcr31(env
, GETPC());
3331 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3333 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3334 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3335 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3336 update_fcr31(env
, GETPC());
3340 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3342 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3343 uint32_t fsth0
= fdt0
>> 32;
3344 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3345 uint32_t fsth2
= fdt2
>> 32;
3347 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3348 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3349 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3350 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3351 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3352 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3353 update_fcr31(env
, GETPC());
3354 return ((uint64_t)fsth2
<< 32) | fst2
;
3357 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3359 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3360 uint32_t fsth0
= fdt0
>> 32;
3361 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3362 uint32_t fsth1
= fdt1
>> 32;
3366 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3367 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3368 update_fcr31(env
, GETPC());
3369 return ((uint64_t)fsth2
<< 32) | fst2
;
3372 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3374 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3375 uint32_t fsth0
= fdt0
>> 32;
3376 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3377 uint32_t fsth1
= fdt1
>> 32;
3381 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3382 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3383 update_fcr31(env
, GETPC());
3384 return ((uint64_t)fsth2
<< 32) | fst2
;
3387 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3388 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3389 uint ## bits ## _t fs, \
3390 uint ## bits ## _t ft) \
3392 uint ## bits ## _t fdret; \
3394 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3395 &env->active_fpu.fp_status); \
3396 update_fcr31(env, GETPC()); \
3400 FLOAT_MINMAX(max_s
, 32, maxnum
)
3401 FLOAT_MINMAX(max_d
, 64, maxnum
)
3402 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3403 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3405 FLOAT_MINMAX(min_s
, 32, minnum
)
3406 FLOAT_MINMAX(min_d
, 64, minnum
)
3407 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3408 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3411 /* ternary operations */
3412 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3414 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3415 if ((flags) & float_muladd_negate_c) { \
3416 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3418 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3420 if ((flags) & float_muladd_negate_result) { \
3421 a = prefix##_chs(a); \
3425 /* FMA based operations */
3426 #define FLOAT_FMA(name, type) \
3427 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3428 uint64_t fdt0, uint64_t fdt1, \
3431 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3432 update_fcr31(env, GETPC()); \
3436 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3437 uint32_t fst0, uint32_t fst1, \
3440 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3441 update_fcr31(env, GETPC()); \
3445 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3446 uint64_t fdt0, uint64_t fdt1, \
3449 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3450 uint32_t fsth0 = fdt0 >> 32; \
3451 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3452 uint32_t fsth1 = fdt1 >> 32; \
3453 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3454 uint32_t fsth2 = fdt2 >> 32; \
3456 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3457 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3458 update_fcr31(env, GETPC()); \
3459 return ((uint64_t)fsth0 << 32) | fst0; \
3462 FLOAT_FMA(msub
, float_muladd_negate_c
)
3463 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
3464 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
3467 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3468 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3469 uint ## bits ## _t fs, \
3470 uint ## bits ## _t ft, \
3471 uint ## bits ## _t fd) \
3473 uint ## bits ## _t fdret; \
3475 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3476 &env->active_fpu.fp_status); \
3477 update_fcr31(env, GETPC()); \
3481 FLOAT_FMADDSUB(maddf_s
, 32, 0)
3482 FLOAT_FMADDSUB(maddf_d
, 64, 0)
3483 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
3484 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
3485 #undef FLOAT_FMADDSUB
3487 /* compare operations */
3488 #define FOP_COND_D(op, cond) \
3489 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3490 uint64_t fdt1, int cc) \
3494 update_fcr31(env, GETPC()); \
3496 SET_FP_COND(cc, env->active_fpu); \
3498 CLEAR_FP_COND(cc, env->active_fpu); \
3500 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3501 uint64_t fdt1, int cc) \
3504 fdt0 = float64_abs(fdt0); \
3505 fdt1 = float64_abs(fdt1); \
3507 update_fcr31(env, GETPC()); \
3509 SET_FP_COND(cc, env->active_fpu); \
3511 CLEAR_FP_COND(cc, env->active_fpu); \
3514 /* NOTE: the comma operator will make "cond" to eval to false,
3515 * but float64_unordered_quiet() is still called. */
3516 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3517 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3518 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3519 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3520 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3521 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3522 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3523 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3524 /* NOTE: the comma operator will make "cond" to eval to false,
3525 * but float64_unordered() is still called. */
3526 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3527 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3528 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3529 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3530 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3531 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3532 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3533 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3535 #define FOP_COND_S(op, cond) \
3536 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3537 uint32_t fst1, int cc) \
3541 update_fcr31(env, GETPC()); \
3543 SET_FP_COND(cc, env->active_fpu); \
3545 CLEAR_FP_COND(cc, env->active_fpu); \
3547 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3548 uint32_t fst1, int cc) \
3551 fst0 = float32_abs(fst0); \
3552 fst1 = float32_abs(fst1); \
3554 update_fcr31(env, GETPC()); \
3556 SET_FP_COND(cc, env->active_fpu); \
3558 CLEAR_FP_COND(cc, env->active_fpu); \
3561 /* NOTE: the comma operator will make "cond" to eval to false,
3562 * but float32_unordered_quiet() is still called. */
3563 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3564 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3565 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3566 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3567 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3568 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3569 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3570 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3571 /* NOTE: the comma operator will make "cond" to eval to false,
3572 * but float32_unordered() is still called. */
3573 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3574 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3575 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3576 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3577 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3578 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3579 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3580 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3582 #define FOP_COND_PS(op, condl, condh) \
3583 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3584 uint64_t fdt1, int cc) \
3586 uint32_t fst0, fsth0, fst1, fsth1; \
3588 fst0 = fdt0 & 0XFFFFFFFF; \
3589 fsth0 = fdt0 >> 32; \
3590 fst1 = fdt1 & 0XFFFFFFFF; \
3591 fsth1 = fdt1 >> 32; \
3594 update_fcr31(env, GETPC()); \
3596 SET_FP_COND(cc, env->active_fpu); \
3598 CLEAR_FP_COND(cc, env->active_fpu); \
3600 SET_FP_COND(cc + 1, env->active_fpu); \
3602 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3604 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3605 uint64_t fdt1, int cc) \
3607 uint32_t fst0, fsth0, fst1, fsth1; \
3609 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3610 fsth0 = float32_abs(fdt0 >> 32); \
3611 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3612 fsth1 = float32_abs(fdt1 >> 32); \
3615 update_fcr31(env, GETPC()); \
3617 SET_FP_COND(cc, env->active_fpu); \
3619 CLEAR_FP_COND(cc, env->active_fpu); \
3621 SET_FP_COND(cc + 1, env->active_fpu); \
3623 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3626 /* NOTE: the comma operator will make "cond" to eval to false,
3627 * but float32_unordered_quiet() is still called. */
3628 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3629 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3630 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3631 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3632 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3633 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3634 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3635 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3636 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3637 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3638 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3639 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3640 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3641 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3642 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3643 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3644 /* NOTE: the comma operator will make "cond" to eval to false,
3645 * but float32_unordered() is still called. */
3646 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3647 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3648 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3649 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3650 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3651 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3652 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3653 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3654 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3655 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3656 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3657 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3658 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3659 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3660 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3661 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3663 /* R6 compare operations */
3664 #define FOP_CONDN_D(op, cond) \
3665 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3670 update_fcr31(env, GETPC()); \
3678 /* NOTE: the comma operator will make "cond" to eval to false,
3679 * but float64_unordered_quiet() is still called. */
3680 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3681 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
3682 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3683 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3684 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3685 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3686 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3687 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3688 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3689 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3690 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3691 /* NOTE: the comma operator will make "cond" to eval to false,
3692 * but float64_unordered() is still called. */
3693 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3694 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
3695 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3696 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3697 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3698 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3699 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3700 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3701 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3702 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3703 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3704 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3705 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3706 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3707 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3708 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3709 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3710 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3711 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3712 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3713 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3714 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3715 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3716 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3717 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3719 #define FOP_CONDN_S(op, cond) \
3720 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
3725 update_fcr31(env, GETPC()); \
3733 /* NOTE: the comma operator will make "cond" to eval to false,
3734 * but float32_unordered_quiet() is still called. */
3735 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3736 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
3737 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3738 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3739 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3740 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3741 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3742 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3743 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3744 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3745 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3746 /* NOTE: the comma operator will make "cond" to eval to false,
3747 * but float32_unordered() is still called. */
3748 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3749 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
3750 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3751 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3752 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3753 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3754 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3755 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3756 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3757 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3758 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3759 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3760 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3761 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3762 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3763 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3764 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3765 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3766 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3767 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3768 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3769 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3770 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3771 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3772 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3775 /* Data format min and max values */
3776 #define DF_BITS(df) (1 << ((df) + 3))
3778 /* Element-by-element access macros */
3779 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3781 #if !defined(CONFIG_USER_ONLY)
3782 #define MEMOP_IDX(DF) \
3783 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
3784 cpu_mmu_index(env, false));
3786 #define MEMOP_IDX(DF)
3789 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
3790 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3791 target_ulong addr) \
3793 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3797 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3798 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
3800 memcpy(pwd, &wx, sizeof(wr_t)); \
3803 #if !defined(CONFIG_USER_ONLY)
3804 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETRA())
3805 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETRA())
3806 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETRA())
3807 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETRA())
3809 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
3810 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
3811 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
3812 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
3815 #define MSA_PAGESPAN(x) \
3816 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3818 static inline void ensure_writable_pages(CPUMIPSState
*env
,
3823 #if !defined(CONFIG_USER_ONLY)
3824 target_ulong page_addr
;
3825 if (unlikely(MSA_PAGESPAN(addr
))) {
3827 probe_write(env
, addr
, mmu_idx
, retaddr
);
3829 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3830 probe_write(env
, page_addr
, mmu_idx
, retaddr
);
3835 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
3836 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3837 target_ulong addr) \
3839 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3840 int mmu_idx = cpu_mmu_index(env, false); \
3843 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
3844 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3845 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
3849 #if !defined(CONFIG_USER_ONLY)
3850 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETRA())
3851 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETRA())
3852 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETRA())
3853 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETRA())
3855 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
3856 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
3857 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
3858 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)
3861 void helper_cache(CPUMIPSState
*env
, target_ulong addr
, uint32_t op
)
3863 #ifndef CONFIG_USER_ONLY
3864 target_ulong index
= addr
& 0x1fffffff;
3866 /* Index Store Tag */
3867 memory_region_dispatch_write(env
->itc_tag
, index
, env
->CP0_TagLo
,
3868 8, MEMTXATTRS_UNSPECIFIED
);
3869 } else if (op
== 5) {
3870 /* Index Load Tag */
3871 memory_region_dispatch_read(env
->itc_tag
, index
, &env
->CP0_TagLo
,
3872 8, MEMTXATTRS_UNSPECIFIED
);