target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri,
 348                                         bool isread)
 349 {
 350     bool secure = arm_is_secure_below_el3(env);
 351
 352     assert(!arm_el_is_aa64(env, 3));
 353     if (secure) {
 354         return CP_ACCESS_TRAP_UNCATEGORIZED;
 355     }
 356     return CP_ACCESS_OK;
 357 }
 358
 359 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 360                                                 const ARMCPRegInfo *ri,
 361                                                 bool isread)
 362 {
 363     if (!arm_el_is_aa64(env, 3)) {
 364         return access_el3_aa32ns(env, ri, isread);
 365     }
 366     return CP_ACCESS_OK;
 367 }
 368
 369 /* Some secure-only AArch32 registers trap to EL3 if used from
 370  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
 371  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
 372  * We assume that the .access field is set to PL1_RW.
 373  */
 374 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
 375                                             const ARMCPRegInfo *ri,
 376                                             bool isread)
 377 {
 378     if (arm_current_el(env) == 3) {
 379         return CP_ACCESS_OK;
 380     }
 381     if (arm_is_secure_below_el3(env)) {
 382         return CP_ACCESS_TRAP_EL3;
 383     }
 384     /* This will be EL1 NS and EL2 NS, which just UNDEF */
 385     return CP_ACCESS_TRAP_UNCATEGORIZED;
 386 }
 387
 388 /* Check for traps to "powerdown debug" registers, which are controlled
 389  * by MDCR.TDOSA
 390  */
 391 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
 392                                    bool isread)
 393 {
 394     int el = arm_current_el(env);
 395
 396     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
 397         && !arm_is_secure_below_el3(env)) {
 398         return CP_ACCESS_TRAP_EL2;
 399     }
 400     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
 401         return CP_ACCESS_TRAP_EL3;
 402     }
 403     return CP_ACCESS_OK;
 404 }
 405
 406 /* Check for traps to "debug ROM" registers, which are controlled
 407  * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
 408  */
 409 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
 410                                   bool isread)
 411 {
 412     int el = arm_current_el(env);
 413
 414     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
 415         && !arm_is_secure_below_el3(env)) {
 416         return CP_ACCESS_TRAP_EL2;
 417     }
 418     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 419         return CP_ACCESS_TRAP_EL3;
 420     }
 421     return CP_ACCESS_OK;
 422 }
 423
 424 /* Check for traps to general debug registers, which are controlled
 425  * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
 426  */
 427 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
 428                                   bool isread)
 429 {
 430     int el = arm_current_el(env);
 431
 432     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
 433         && !arm_is_secure_below_el3(env)) {
 434         return CP_ACCESS_TRAP_EL2;
 435     }
 436     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 437         return CP_ACCESS_TRAP_EL3;
 438     }
 439     return CP_ACCESS_OK;
 440 }
 441
 442 /* Check for traps to performance monitor registers, which are controlled
 443  * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
 444  */
 445 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 446                                  bool isread)
 447 {
 448     int el = arm_current_el(env);
 449
 450     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 451         && !arm_is_secure_below_el3(env)) {
 452         return CP_ACCESS_TRAP_EL2;
 453     }
 454     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 455         return CP_ACCESS_TRAP_EL3;
 456     }
 457     return CP_ACCESS_OK;
 458 }
 459
 460 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 461 {
 462     ARMCPU *cpu = arm_env_get_cpu(env);
 463
 464     raw_write(env, ri, value);
 465     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 466 }
 467
 468 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 469 {
 470     ARMCPU *cpu = arm_env_get_cpu(env);
 471
 472     if (raw_read(env, ri) != value) {
 473         /* Unlike real hardware the qemu TLB uses virtual addresses,
 474          * not modified virtual addresses, so this causes a TLB flush.
 475          */
 476         tlb_flush(CPU(cpu), 1);
 477         raw_write(env, ri, value);
 478     }
 479 }
 480
 481 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 482                              uint64_t value)
 483 {
 484     ARMCPU *cpu = arm_env_get_cpu(env);
 485
 486     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 487         && !extended_addresses_enabled(env)) {
 488         /* For VMSA (when not using the LPAE long descriptor page table
 489          * format) this register includes the ASID, so do a TLB flush.
 490          * For PMSA it is purely a process ID and no action is needed.
 491          */
 492         tlb_flush(CPU(cpu), 1);
 493     }
 494     raw_write(env, ri, value);
 495 }
 496
 497 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 498                           uint64_t value)
 499 {
 500     /* Invalidate all (TLBIALL) */
 501     ARMCPU *cpu = arm_env_get_cpu(env);
 502
 503     tlb_flush(CPU(cpu), 1);
 504 }
 505
 506 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 507                           uint64_t value)
 508 {
 509     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 510     ARMCPU *cpu = arm_env_get_cpu(env);
 511
 512     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 513 }
 514
 515 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 516                            uint64_t value)
 517 {
 518     /* Invalidate by ASID (TLBIASID) */
 519     ARMCPU *cpu = arm_env_get_cpu(env);
 520
 521     tlb_flush(CPU(cpu), value == 0);
 522 }
 523
 524 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 525                            uint64_t value)
 526 {
 527     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 528     ARMCPU *cpu = arm_env_get_cpu(env);
 529
 530     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 531 }
 532
 533 /* IS variants of TLB operations must affect all cores */
 534 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 535                              uint64_t value)
 536 {
 537     CPUState *other_cs;
 538
 539     CPU_FOREACH(other_cs) {
 540         tlb_flush(other_cs, 1);
 541     }
 542 }
 543
 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 545                              uint64_t value)
 546 {
 547     CPUState *other_cs;
 548
 549     CPU_FOREACH(other_cs) {
 550         tlb_flush(other_cs, value == 0);
 551     }
 552 }
 553
 554 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 555                              uint64_t value)
 556 {
 557     CPUState *other_cs;
 558
 559     CPU_FOREACH(other_cs) {
 560         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 561     }
 562 }
 563
 564 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 565                              uint64_t value)
 566 {
 567     CPUState *other_cs;
 568
 569     CPU_FOREACH(other_cs) {
 570         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 571     }
 572 }
 573
 574 static const ARMCPRegInfo cp_reginfo[] = {
 575     /* Define the secure and non-secure FCSE identifier CP registers
 576      * separately because there is no secure bank in V8 (no _EL3).  This allows
 577      * the secure register to be properly reset and migrated. There is also no
 578      * v8 EL1 version of the register so the non-secure instance stands alone.
 579      */
 580     { .name = "FCSEIDR(NS)",
 581       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 582       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 583       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 584       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 585     { .name = "FCSEIDR(S)",
 586       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 587       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 588       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 589       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 590     /* Define the secure and non-secure context identifier CP registers
 591      * separately because there is no secure bank in V8 (no _EL3).  This allows
 592      * the secure register to be properly reset and migrated.  In the
 593      * non-secure case, the 32-bit register will have reset and migration
 594      * disabled during registration as it is handled by the 64-bit instance.
 595      */
 596     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 597       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 598       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 599       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 600       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 601     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 602       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 603       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 604       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 605       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 606     REGINFO_SENTINEL
 607 };
 608
 609 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 610     /* NB: Some of these registers exist in v8 but with more precise
 611      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 612      */
 613     /* MMU Domain access control / MPU write buffer control */
 614     { .name = "DACR",
 615       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 616       .access = PL1_RW, .resetvalue = 0,
 617       .writefn = dacr_write, .raw_writefn = raw_write,
 618       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 619                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 620     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 621      * For v6 and v5, these mappings are overly broad.
 622      */
 623     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 624       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 625     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 626       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 627     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 628       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 629     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 630       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 631     /* Cache maintenance ops; some of this space may be overridden later. */
 632     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 633       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 634       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 635     REGINFO_SENTINEL
 636 };
 637
 638 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 639     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 640      * over-broad.
 641      */
 642     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 643       .access = PL1_W, .type = ARM_CP_WFI },
 644     REGINFO_SENTINEL
 645 };
 646
 647 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 648     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 649      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 650      */
 651     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 652       .access = PL1_W, .type = ARM_CP_WFI },
 653     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 654      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 655      * OMAPCP will override this space.
 656      */
 657     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 658       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 659       .resetvalue = 0 },
 660     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 661       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 662       .resetvalue = 0 },
 663     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 664     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 665       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 666       .resetvalue = 0 },
 667     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 668      * implementing it as RAZ means the "debug architecture version" bits
 669      * will read as a reserved value, which should cause Linux to not try
 670      * to use the debug hardware.
 671      */
 672     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 673       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 674     /* MMU TLB control. Note that the wildcarding means we cover not just
 675      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 676      */
 677     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 678       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 679       .type = ARM_CP_NO_RAW },
 680     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 681       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 682       .type = ARM_CP_NO_RAW },
 683     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 684       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 685       .type = ARM_CP_NO_RAW },
 686     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 687       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 688       .type = ARM_CP_NO_RAW },
 689     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 690       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 691     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 692       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 697                         uint64_t value)
 698 {
 699     uint32_t mask = 0;
 700
 701     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 702     if (!arm_feature(env, ARM_FEATURE_V8)) {
 703         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 704          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 705          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 706          */
 707         if (arm_feature(env, ARM_FEATURE_VFP)) {
 708             /* VFP coprocessor: cp10 & cp11 [23:20] */
 709             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 710
 711             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 712                 /* ASEDIS [31] bit is RAO/WI */
 713                 value |= (1 << 31);
 714             }
 715
 716             /* VFPv3 and upwards with NEON implement 32 double precision
 717              * registers (D0-D31).
 718              */
 719             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 720                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 721                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 722                 value |= (1 << 30);
 723             }
 724         }
 725         value &= mask;
 726     }
 727     env->cp15.cpacr_el1 = value;
 728 }
 729
 730 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 731                                    bool isread)
 732 {
 733     if (arm_feature(env, ARM_FEATURE_V8)) {
 734         /* Check if CPACR accesses are to be trapped to EL2 */
 735         if (arm_current_el(env) == 1 &&
 736             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 737             return CP_ACCESS_TRAP_EL2;
 738         /* Check if CPACR accesses are to be trapped to EL3 */
 739         } else if (arm_current_el(env) < 3 &&
 740                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 741             return CP_ACCESS_TRAP_EL3;
 742         }
 743     }
 744
 745     return CP_ACCESS_OK;
 746 }
 747
 748 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 749                                   bool isread)
 750 {
 751     /* Check if CPTR accesses are set to trap to EL3 */
 752     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 753         return CP_ACCESS_TRAP_EL3;
 754     }
 755
 756     return CP_ACCESS_OK;
 757 }
 758
 759 static const ARMCPRegInfo v6_cp_reginfo[] = {
 760     /* prefetch by MVA in v6, NOP in v7 */
 761     { .name = "MVA_prefetch",
 762       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 763       .access = PL1_W, .type = ARM_CP_NOP },
 764     /* We need to break the TB after ISB to execute self-modifying code
 765      * correctly and also to take any pending interrupts immediately.
 766      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 767      */
 768     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 769       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 770     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 771       .access = PL0_W, .type = ARM_CP_NOP },
 772     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 773       .access = PL0_W, .type = ARM_CP_NOP },
 774     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 775       .access = PL1_RW,
 776       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 777                              offsetof(CPUARMState, cp15.ifar_ns) },
 778       .resetvalue = 0, },
 779     /* Watchpoint Fault Address Register : should actually only be present
 780      * for 1136, 1176, 11MPCore.
 781      */
 782     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 783       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 784     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 785       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 786       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 787       .resetvalue = 0, .writefn = cpacr_write },
 788     REGINFO_SENTINEL
 789 };
 790
 791 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
 792                                    bool isread)
 793 {
 794     /* Performance monitor registers user accessibility is controlled
 795      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
 796      * trapping to EL2 or EL3 for other accesses.
 797      */
 798     int el = arm_current_el(env);
 799
 800     if (el == 0 && !env->cp15.c9_pmuserenr) {
 801         return CP_ACCESS_TRAP;
 802     }
 803     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 804         && !arm_is_secure_below_el3(env)) {
 805         return CP_ACCESS_TRAP_EL2;
 806     }
 807     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 808         return CP_ACCESS_TRAP_EL3;
 809     }
 810
 811     return CP_ACCESS_OK;
 812 }
 813
 814 #ifndef CONFIG_USER_ONLY
 815
 816 static inline bool arm_ccnt_enabled(CPUARMState *env)
 817 {
 818     /* This does not support checking PMCCFILTR_EL0 register */
 819
 820     if (!(env->cp15.c9_pmcr & PMCRE)) {
 821         return false;
 822     }
 823
 824     return true;
 825 }
 826
 827 void pmccntr_sync(CPUARMState *env)
 828 {
 829     uint64_t temp_ticks;
 830
 831     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 832                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 833
 834     if (env->cp15.c9_pmcr & PMCRD) {
 835         /* Increment once every 64 processor clock cycles */
 836         temp_ticks /= 64;
 837     }
 838
 839     if (arm_ccnt_enabled(env)) {
 840         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 841     }
 842 }
 843
 844 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 845                        uint64_t value)
 846 {
 847     pmccntr_sync(env);
 848
 849     if (value & PMCRC) {
 850         /* The counter has been reset */
 851         env->cp15.c15_ccnt = 0;
 852     }
 853
 854     /* only the DP, X, D and E bits are writable */
 855     env->cp15.c9_pmcr &= ~0x39;
 856     env->cp15.c9_pmcr |= (value & 0x39);
 857
 858     pmccntr_sync(env);
 859 }
 860
 861 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 862 {
 863     uint64_t total_ticks;
 864
 865     if (!arm_ccnt_enabled(env)) {
 866         /* Counter is disabled, do not change value */
 867         return env->cp15.c15_ccnt;
 868     }
 869
 870     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 871                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 872
 873     if (env->cp15.c9_pmcr & PMCRD) {
 874         /* Increment once every 64 processor clock cycles */
 875         total_ticks /= 64;
 876     }
 877     return total_ticks - env->cp15.c15_ccnt;
 878 }
 879
 880 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 881                         uint64_t value)
 882 {
 883     uint64_t total_ticks;
 884
 885     if (!arm_ccnt_enabled(env)) {
 886         /* Counter is disabled, set the absolute value */
 887         env->cp15.c15_ccnt = value;
 888         return;
 889     }
 890
 891     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 892                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 893
 894     if (env->cp15.c9_pmcr & PMCRD) {
 895         /* Increment once every 64 processor clock cycles */
 896         total_ticks /= 64;
 897     }
 898     env->cp15.c15_ccnt = total_ticks - value;
 899 }
 900
 901 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 902                             uint64_t value)
 903 {
 904     uint64_t cur_val = pmccntr_read(env, NULL);
 905
 906     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 907 }
 908
 909 #else /* CONFIG_USER_ONLY */
 910
 911 void pmccntr_sync(CPUARMState *env)
 912 {
 913 }
 914
 915 #endif
 916
 917 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 918                             uint64_t value)
 919 {
 920     pmccntr_sync(env);
 921     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 922     pmccntr_sync(env);
 923 }
 924
 925 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 926                             uint64_t value)
 927 {
 928     value &= (1 << 31);
 929     env->cp15.c9_pmcnten |= value;
 930 }
 931
 932 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 933                              uint64_t value)
 934 {
 935     value &= (1 << 31);
 936     env->cp15.c9_pmcnten &= ~value;
 937 }
 938
 939 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 940                          uint64_t value)
 941 {
 942     env->cp15.c9_pmovsr &= ~value;
 943 }
 944
 945 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 946                              uint64_t value)
 947 {
 948     env->cp15.c9_pmxevtyper = value & 0xff;
 949 }
 950
 951 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 952                             uint64_t value)
 953 {
 954     env->cp15.c9_pmuserenr = value & 1;
 955 }
 956
 957 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 958                              uint64_t value)
 959 {
 960     /* We have no event counters so only the C bit can be changed */
 961     value &= (1 << 31);
 962     env->cp15.c9_pminten |= value;
 963 }
 964
 965 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 966                              uint64_t value)
 967 {
 968     value &= (1 << 31);
 969     env->cp15.c9_pminten &= ~value;
 970 }
 971
 972 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 973                        uint64_t value)
 974 {
 975     /* Note that even though the AArch64 view of this register has bits
 976      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 977      * architectural requirements for bits which are RES0 only in some
 978      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 979      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 980      */
 981     raw_write(env, ri, value & ~0x1FULL);
 982 }
 983
 984 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 985 {
 986     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 987      * For bits that vary between AArch32/64, code needs to check the
 988      * current execution mode before directly using the feature bit.
 989      */
 990     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 991
 992     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 993         valid_mask &= ~SCR_HCE;
 994
 995         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 996          * supported if EL2 exists. The bit is UNK/SBZP when
 997          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 998          * when EL2 is unavailable.
 999          * On ARMv8, this bit is always available.
1000          */
1001         if (arm_feature(env, ARM_FEATURE_V7) &&
1002             !arm_feature(env, ARM_FEATURE_V8)) {
1003             valid_mask &= ~SCR_SMD;
1004         }
1005     }
1006
1007     /* Clear all-context RES0 bits.  */
1008     value &= valid_mask;
1009     raw_write(env, ri, value);
1010 }
1011
1012 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1013 {
1014     ARMCPU *cpu = arm_env_get_cpu(env);
1015
1016     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1017      * bank
1018      */
1019     uint32_t index = A32_BANKED_REG_GET(env, csselr,
1020                                         ri->secure & ARM_CP_SECSTATE_S);
1021
1022     return cpu->ccsidr[index];
1023 }
1024
1025 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1026                          uint64_t value)
1027 {
1028     raw_write(env, ri, value & 0xf);
1029 }
1030
1031 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1032 {
1033     CPUState *cs = ENV_GET_CPU(env);
1034     uint64_t ret = 0;
1035
1036     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1037         ret |= CPSR_I;
1038     }
1039     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1040         ret |= CPSR_F;
1041     }
1042     /* External aborts are not possible in QEMU so A bit is always clear */
1043     return ret;
1044 }
1045
1046 static const ARMCPRegInfo v7_cp_reginfo[] = {
1047     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1048     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1049       .access = PL1_W, .type = ARM_CP_NOP },
1050     /* Performance monitors are implementation defined in v7,
1051      * but with an ARM recommended set of registers, which we
1052      * follow (although we don't actually implement any counters)
1053      *
1054      * Performance registers fall into three categories:
1055      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1056      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1057      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1058      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1059      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1060      */
1061     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1062       .access = PL0_RW, .type = ARM_CP_ALIAS,
1063       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1064       .writefn = pmcntenset_write,
1065       .accessfn = pmreg_access,
1066       .raw_writefn = raw_write },
1067     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1068       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1069       .access = PL0_RW, .accessfn = pmreg_access,
1070       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1071       .writefn = pmcntenset_write, .raw_writefn = raw_write },
1072     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1073       .access = PL0_RW,
1074       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1075       .accessfn = pmreg_access,
1076       .writefn = pmcntenclr_write,
1077       .type = ARM_CP_ALIAS },
1078     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1079       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1080       .access = PL0_RW, .accessfn = pmreg_access,
1081       .type = ARM_CP_ALIAS,
1082       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1083       .writefn = pmcntenclr_write },
1084     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1085       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1086       .accessfn = pmreg_access,
1087       .writefn = pmovsr_write,
1088       .raw_writefn = raw_write },
1089     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1090       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1091       .access = PL0_RW, .accessfn = pmreg_access,
1092       .type = ARM_CP_ALIAS,
1093       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1094       .writefn = pmovsr_write,
1095       .raw_writefn = raw_write },
1096     /* Unimplemented so WI. */
1097     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1098       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
1099     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
1100      * We choose to RAZ/WI.
1101      */
1102     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1103       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1104       .accessfn = pmreg_access },
1105 #ifndef CONFIG_USER_ONLY
1106     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1107       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1108       .readfn = pmccntr_read, .writefn = pmccntr_write32,
1109       .accessfn = pmreg_access },
1110     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1111       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1112       .access = PL0_RW, .accessfn = pmreg_access,
1113       .type = ARM_CP_IO,
1114       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1115 #endif
1116     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1117       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1118       .writefn = pmccfiltr_write,
1119       .access = PL0_RW, .accessfn = pmreg_access,
1120       .type = ARM_CP_IO,
1121       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1122       .resetvalue = 0, },
1123     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1124       .access = PL0_RW,
1125       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1126       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1127       .raw_writefn = raw_write },
1128     /* Unimplemented, RAZ/WI. */
1129     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1130       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1131       .accessfn = pmreg_access },
1132     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1133       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1134       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1135       .resetvalue = 0,
1136       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1137     { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1138       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1139       .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1140       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1141       .resetvalue = 0,
1142       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1143     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1144       .access = PL1_RW, .accessfn = access_tpm,
1145       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1146       .resetvalue = 0,
1147       .writefn = pmintenset_write, .raw_writefn = raw_write },
1148     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1149       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1150       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1151       .writefn = pmintenclr_write, },
1152     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1153       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1154       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1155       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1156       .writefn = pmintenclr_write },
1157     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1158       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1159       .access = PL1_RW, .writefn = vbar_write,
1160       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1161                              offsetof(CPUARMState, cp15.vbar_ns) },
1162       .resetvalue = 0 },
1163     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1164       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1165       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1166     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1167       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1168       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1169       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1170                              offsetof(CPUARMState, cp15.csselr_ns) } },
1171     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1172      * just RAZ for all cores:
1173      */
1174     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1175       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1176       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1177     /* Auxiliary fault status registers: these also are IMPDEF, and we
1178      * choose to RAZ/WI for all cores.
1179      */
1180     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1181       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1182       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1183     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1184       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1185       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1186     /* MAIR can just read-as-written because we don't implement caches
1187      * and so don't need to care about memory attributes.
1188      */
1189     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1190       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1191       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1192       .resetvalue = 0 },
1193     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1194       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1195       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1196       .resetvalue = 0 },
1197     /* For non-long-descriptor page tables these are PRRR and NMRR;
1198      * regardless they still act as reads-as-written for QEMU.
1199      */
1200      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1201       * allows them to assign the correct fieldoffset based on the endianness
1202       * handled in the field definitions.
1203       */
1204     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1205       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1206       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1207                              offsetof(CPUARMState, cp15.mair0_ns) },
1208       .resetfn = arm_cp_reset_ignore },
1209     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1210       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1211       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1212                              offsetof(CPUARMState, cp15.mair1_ns) },
1213       .resetfn = arm_cp_reset_ignore },
1214     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1215       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1216       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1217     /* 32 bit ITLB invalidates */
1218     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1219       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1220     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1221       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1222     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1223       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1224     /* 32 bit DTLB invalidates */
1225     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1226       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1227     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1228       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1229     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1230       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1231     /* 32 bit TLB invalidates */
1232     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1233       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1234     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1235       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1236     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1237       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1238     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1239       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1240     REGINFO_SENTINEL
1241 };
1242
1243 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1244     /* 32 bit TLB invalidates, Inner Shareable */
1245     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1246       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1247     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1248       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1249     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1250       .type = ARM_CP_NO_RAW, .access = PL1_W,
1251       .writefn = tlbiasid_is_write },
1252     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1253       .type = ARM_CP_NO_RAW, .access = PL1_W,
1254       .writefn = tlbimvaa_is_write },
1255     REGINFO_SENTINEL
1256 };
1257
1258 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1259                         uint64_t value)
1260 {
1261     value &= 1;
1262     env->teecr = value;
1263 }
1264
1265 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1266                                     bool isread)
1267 {
1268     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1269         return CP_ACCESS_TRAP;
1270     }
1271     return CP_ACCESS_OK;
1272 }
1273
1274 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1275     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1276       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1277       .resetvalue = 0,
1278       .writefn = teecr_write },
1279     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1280       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1281       .accessfn = teehbr_access, .resetvalue = 0 },
1282     REGINFO_SENTINEL
1283 };
1284
1285 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1286     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1287       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1288       .access = PL0_RW,
1289       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1290     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1291       .access = PL0_RW,
1292       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1293                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1294       .resetfn = arm_cp_reset_ignore },
1295     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1296       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1297       .access = PL0_R|PL1_W,
1298       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1299       .resetvalue = 0},
1300     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1301       .access = PL0_R|PL1_W,
1302       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1303                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1304       .resetfn = arm_cp_reset_ignore },
1305     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1306       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1307       .access = PL1_RW,
1308       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1309     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1310       .access = PL1_RW,
1311       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1312                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1313       .resetvalue = 0 },
1314     REGINFO_SENTINEL
1315 };
1316
1317 #ifndef CONFIG_USER_ONLY
1318
1319 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1320                                        bool isread)
1321 {
1322     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1323      * Writable only at the highest implemented exception level.
1324      */
1325     int el = arm_current_el(env);
1326
1327     switch (el) {
1328     case 0:
1329         if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1330             return CP_ACCESS_TRAP;
1331         }
1332         break;
1333     case 1:
1334         if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1335             arm_is_secure_below_el3(env)) {
1336             /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1337             return CP_ACCESS_TRAP_UNCATEGORIZED;
1338         }
1339         break;
1340     case 2:
1341     case 3:
1342         break;
1343     }
1344
1345     if (!isread && el < arm_highest_el(env)) {
1346         return CP_ACCESS_TRAP_UNCATEGORIZED;
1347     }
1348
1349     return CP_ACCESS_OK;
1350 }
1351
1352 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1353                                         bool isread)
1354 {
1355     unsigned int cur_el = arm_current_el(env);
1356     bool secure = arm_is_secure(env);
1357
1358     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1359     if (cur_el == 0 &&
1360         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1361         return CP_ACCESS_TRAP;
1362     }
1363
1364     if (arm_feature(env, ARM_FEATURE_EL2) &&
1365         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1366         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1367         return CP_ACCESS_TRAP_EL2;
1368     }
1369     return CP_ACCESS_OK;
1370 }
1371
1372 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1373                                       bool isread)
1374 {
1375     unsigned int cur_el = arm_current_el(env);
1376     bool secure = arm_is_secure(env);
1377
1378     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1379      * EL0[PV]TEN is zero.
1380      */
1381     if (cur_el == 0 &&
1382         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1383         return CP_ACCESS_TRAP;
1384     }
1385
1386     if (arm_feature(env, ARM_FEATURE_EL2) &&
1387         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1388         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1389         return CP_ACCESS_TRAP_EL2;
1390     }
1391     return CP_ACCESS_OK;
1392 }
1393
1394 static CPAccessResult gt_pct_access(CPUARMState *env,
1395                                     const ARMCPRegInfo *ri,
1396                                     bool isread)
1397 {
1398     return gt_counter_access(env, GTIMER_PHYS, isread);
1399 }
1400
1401 static CPAccessResult gt_vct_access(CPUARMState *env,
1402                                     const ARMCPRegInfo *ri,
1403                                     bool isread)
1404 {
1405     return gt_counter_access(env, GTIMER_VIRT, isread);
1406 }
1407
1408 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1409                                        bool isread)
1410 {
1411     return gt_timer_access(env, GTIMER_PHYS, isread);
1412 }
1413
1414 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1415                                        bool isread)
1416 {
1417     return gt_timer_access(env, GTIMER_VIRT, isread);
1418 }
1419
1420 static CPAccessResult gt_stimer_access(CPUARMState *env,
1421                                        const ARMCPRegInfo *ri,
1422                                        bool isread)
1423 {
1424     /* The AArch64 register view of the secure physical timer is
1425      * always accessible from EL3, and configurably accessible from
1426      * Secure EL1.
1427      */
1428     switch (arm_current_el(env)) {
1429     case 1:
1430         if (!arm_is_secure(env)) {
1431             return CP_ACCESS_TRAP;
1432         }
1433         if (!(env->cp15.scr_el3 & SCR_ST)) {
1434             return CP_ACCESS_TRAP_EL3;
1435         }
1436         return CP_ACCESS_OK;
1437     case 0:
1438     case 2:
1439         return CP_ACCESS_TRAP;
1440     case 3:
1441         return CP_ACCESS_OK;
1442     default:
1443         g_assert_not_reached();
1444     }
1445 }
1446
1447 static uint64_t gt_get_countervalue(CPUARMState *env)
1448 {
1449     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1450 }
1451
1452 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1453 {
1454     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1455
1456     if (gt->ctl & 1) {
1457         /* Timer enabled: calculate and set current ISTATUS, irq, and
1458          * reset timer to when ISTATUS next has to change
1459          */
1460         uint64_t offset = timeridx == GTIMER_VIRT ?
1461                                       cpu->env.cp15.cntvoff_el2 : 0;
1462         uint64_t count = gt_get_countervalue(&cpu->env);
1463         /* Note that this must be unsigned 64 bit arithmetic: */
1464         int istatus = count - offset >= gt->cval;
1465         uint64_t nexttick;
1466
1467         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1468         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1469                      (istatus && !(gt->ctl & 2)));
1470         if (istatus) {
1471             /* Next transition is when count rolls back over to zero */
1472             nexttick = UINT64_MAX;
1473         } else {
1474             /* Next transition is when we hit cval */
1475             nexttick = gt->cval + offset;
1476         }
1477         /* Note that the desired next expiry time might be beyond the
1478          * signed-64-bit range of a QEMUTimer -- in this case we just
1479          * set the timer for as far in the future as possible. When the
1480          * timer expires we will reset the timer for any remaining period.
1481          */
1482         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1483             nexttick = INT64_MAX / GTIMER_SCALE;
1484         }
1485         timer_mod(cpu->gt_timer[timeridx], nexttick);
1486     } else {
1487         /* Timer disabled: ISTATUS and timer output always clear */
1488         gt->ctl &= ~4;
1489         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1490         timer_del(cpu->gt_timer[timeridx]);
1491     }
1492 }
1493
1494 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1495                            int timeridx)
1496 {
1497     ARMCPU *cpu = arm_env_get_cpu(env);
1498
1499     timer_del(cpu->gt_timer[timeridx]);
1500 }
1501
1502 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1503 {
1504     return gt_get_countervalue(env);
1505 }
1506
1507 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1508 {
1509     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1510 }
1511
1512 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1513                           int timeridx,
1514                           uint64_t value)
1515 {
1516     env->cp15.c14_timer[timeridx].cval = value;
1517     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1518 }
1519
1520 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1521                              int timeridx)
1522 {
1523     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1524
1525     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1526                       (gt_get_countervalue(env) - offset));
1527 }
1528
1529 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1530                           int timeridx,
1531                           uint64_t value)
1532 {
1533     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1534
1535     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1536                                          sextract64(value, 0, 32);
1537     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1538 }
1539
1540 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1541                          int timeridx,
1542                          uint64_t value)
1543 {
1544     ARMCPU *cpu = arm_env_get_cpu(env);
1545     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1546
1547     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1548     if ((oldval ^ value) & 1) {
1549         /* Enable toggled */
1550         gt_recalc_timer(cpu, timeridx);
1551     } else if ((oldval ^ value) & 2) {
1552         /* IMASK toggled: don't need to recalculate,
1553          * just set the interrupt line based on ISTATUS
1554          */
1555         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1556                      (oldval & 4) && !(value & 2));
1557     }
1558 }
1559
1560 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1561 {
1562     gt_timer_reset(env, ri, GTIMER_PHYS);
1563 }
1564
1565 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1566                                uint64_t value)
1567 {
1568     gt_cval_write(env, ri, GTIMER_PHYS, value);
1569 }
1570
1571 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1572 {
1573     return gt_tval_read(env, ri, GTIMER_PHYS);
1574 }
1575
1576 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1577                                uint64_t value)
1578 {
1579     gt_tval_write(env, ri, GTIMER_PHYS, value);
1580 }
1581
1582 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1583                               uint64_t value)
1584 {
1585     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1586 }
1587
1588 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1589 {
1590     gt_timer_reset(env, ri, GTIMER_VIRT);
1591 }
1592
1593 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1594                                uint64_t value)
1595 {
1596     gt_cval_write(env, ri, GTIMER_VIRT, value);
1597 }
1598
1599 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1600 {
1601     return gt_tval_read(env, ri, GTIMER_VIRT);
1602 }
1603
1604 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1605                                uint64_t value)
1606 {
1607     gt_tval_write(env, ri, GTIMER_VIRT, value);
1608 }
1609
1610 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1611                               uint64_t value)
1612 {
1613     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1614 }
1615
1616 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1617                               uint64_t value)
1618 {
1619     ARMCPU *cpu = arm_env_get_cpu(env);
1620
1621     raw_write(env, ri, value);
1622     gt_recalc_timer(cpu, GTIMER_VIRT);
1623 }
1624
1625 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1626 {
1627     gt_timer_reset(env, ri, GTIMER_HYP);
1628 }
1629
1630 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1631                               uint64_t value)
1632 {
1633     gt_cval_write(env, ri, GTIMER_HYP, value);
1634 }
1635
1636 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1637 {
1638     return gt_tval_read(env, ri, GTIMER_HYP);
1639 }
1640
1641 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1642                               uint64_t value)
1643 {
1644     gt_tval_write(env, ri, GTIMER_HYP, value);
1645 }
1646
1647 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1648                               uint64_t value)
1649 {
1650     gt_ctl_write(env, ri, GTIMER_HYP, value);
1651 }
1652
1653 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1654 {
1655     gt_timer_reset(env, ri, GTIMER_SEC);
1656 }
1657
1658 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1659                               uint64_t value)
1660 {
1661     gt_cval_write(env, ri, GTIMER_SEC, value);
1662 }
1663
1664 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1665 {
1666     return gt_tval_read(env, ri, GTIMER_SEC);
1667 }
1668
1669 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1670                               uint64_t value)
1671 {
1672     gt_tval_write(env, ri, GTIMER_SEC, value);
1673 }
1674
1675 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1676                               uint64_t value)
1677 {
1678     gt_ctl_write(env, ri, GTIMER_SEC, value);
1679 }
1680
1681 void arm_gt_ptimer_cb(void *opaque)
1682 {
1683     ARMCPU *cpu = opaque;
1684
1685     gt_recalc_timer(cpu, GTIMER_PHYS);
1686 }
1687
1688 void arm_gt_vtimer_cb(void *opaque)
1689 {
1690     ARMCPU *cpu = opaque;
1691
1692     gt_recalc_timer(cpu, GTIMER_VIRT);
1693 }
1694
1695 void arm_gt_htimer_cb(void *opaque)
1696 {
1697     ARMCPU *cpu = opaque;
1698
1699     gt_recalc_timer(cpu, GTIMER_HYP);
1700 }
1701
1702 void arm_gt_stimer_cb(void *opaque)
1703 {
1704     ARMCPU *cpu = opaque;
1705
1706     gt_recalc_timer(cpu, GTIMER_SEC);
1707 }
1708
1709 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1710     /* Note that CNTFRQ is purely reads-as-written for the benefit
1711      * of software; writing it doesn't actually change the timer frequency.
1712      * Our reset value matches the fixed frequency we implement the timer at.
1713      */
1714     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1715       .type = ARM_CP_ALIAS,
1716       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1717       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1718     },
1719     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1720       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1721       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1722       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1723       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1724     },
1725     /* overall control: mostly access permissions */
1726     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1727       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1728       .access = PL1_RW,
1729       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1730       .resetvalue = 0,
1731     },
1732     /* per-timer control */
1733     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1734       .secure = ARM_CP_SECSTATE_NS,
1735       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1736       .accessfn = gt_ptimer_access,
1737       .fieldoffset = offsetoflow32(CPUARMState,
1738                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1739       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1740     },
1741     { .name = "CNTP_CTL(S)",
1742       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1743       .secure = ARM_CP_SECSTATE_S,
1744       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1745       .accessfn = gt_ptimer_access,
1746       .fieldoffset = offsetoflow32(CPUARMState,
1747                                    cp15.c14_timer[GTIMER_SEC].ctl),
1748       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1749     },
1750     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1751       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1752       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1753       .accessfn = gt_ptimer_access,
1754       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1755       .resetvalue = 0,
1756       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1757     },
1758     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1759       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1760       .accessfn = gt_vtimer_access,
1761       .fieldoffset = offsetoflow32(CPUARMState,
1762                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1763       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1764     },
1765     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1766       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1767       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1768       .accessfn = gt_vtimer_access,
1769       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1770       .resetvalue = 0,
1771       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1772     },
1773     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1774     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1775       .secure = ARM_CP_SECSTATE_NS,
1776       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1777       .accessfn = gt_ptimer_access,
1778       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1779     },
1780     { .name = "CNTP_TVAL(S)",
1781       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1782       .secure = ARM_CP_SECSTATE_S,
1783       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1784       .accessfn = gt_ptimer_access,
1785       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1786     },
1787     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1788       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1789       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1790       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1791       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1792     },
1793     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1794       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1795       .accessfn = gt_vtimer_access,
1796       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1797     },
1798     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1799       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1800       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1801       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1802       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1803     },
1804     /* The counter itself */
1805     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1806       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1807       .accessfn = gt_pct_access,
1808       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1809     },
1810     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1811       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1812       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1813       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1814     },
1815     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1816       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1817       .accessfn = gt_vct_access,
1818       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1819     },
1820     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1821       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1822       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1823       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1824     },
1825     /* Comparison value, indicating when the timer goes off */
1826     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1827       .secure = ARM_CP_SECSTATE_NS,
1828       .access = PL1_RW | PL0_R,
1829       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1830       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1831       .accessfn = gt_ptimer_access,
1832       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1833     },
1834     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1835       .secure = ARM_CP_SECSTATE_S,
1836       .access = PL1_RW | PL0_R,
1837       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1838       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1839       .accessfn = gt_ptimer_access,
1840       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1841     },
1842     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1843       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1844       .access = PL1_RW | PL0_R,
1845       .type = ARM_CP_IO,
1846       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1847       .resetvalue = 0, .accessfn = gt_ptimer_access,
1848       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1849     },
1850     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1851       .access = PL1_RW | PL0_R,
1852       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1853       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1854       .accessfn = gt_vtimer_access,
1855       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1856     },
1857     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1858       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1859       .access = PL1_RW | PL0_R,
1860       .type = ARM_CP_IO,
1861       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1862       .resetvalue = 0, .accessfn = gt_vtimer_access,
1863       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1864     },
1865     /* Secure timer -- this is actually restricted to only EL3
1866      * and configurably Secure-EL1 via the accessfn.
1867      */
1868     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1869       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1870       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1871       .accessfn = gt_stimer_access,
1872       .readfn = gt_sec_tval_read,
1873       .writefn = gt_sec_tval_write,
1874       .resetfn = gt_sec_timer_reset,
1875     },
1876     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1877       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1878       .type = ARM_CP_IO, .access = PL1_RW,
1879       .accessfn = gt_stimer_access,
1880       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1881       .resetvalue = 0,
1882       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1883     },
1884     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1885       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1886       .type = ARM_CP_IO, .access = PL1_RW,
1887       .accessfn = gt_stimer_access,
1888       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1889       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1890     },
1891     REGINFO_SENTINEL
1892 };
1893
1894 #else
1895 /* In user-mode none of the generic timer registers are accessible,
1896  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1897  * so instead just don't register any of them.
1898  */
1899 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1900     REGINFO_SENTINEL
1901 };
1902
1903 #endif
1904
1905 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1906 {
1907     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1908         raw_write(env, ri, value);
1909     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1910         raw_write(env, ri, value & 0xfffff6ff);
1911     } else {
1912         raw_write(env, ri, value & 0xfffff1ff);
1913     }
1914 }
1915
1916 #ifndef CONFIG_USER_ONLY
1917 /* get_phys_addr() isn't present for user-mode-only targets */
1918
1919 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
1920                                  bool isread)
1921 {
1922     if (ri->opc2 & 4) {
1923         /* The ATS12NSO* operations must trap to EL3 if executed in
1924          * Secure EL1 (which can only happen if EL3 is AArch64).
1925          * They are simply UNDEF if executed from NS EL1.
1926          * They function normally from EL2 or EL3.
1927          */
1928         if (arm_current_el(env) == 1) {
1929             if (arm_is_secure_below_el3(env)) {
1930                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1931             }
1932             return CP_ACCESS_TRAP_UNCATEGORIZED;
1933         }
1934     }
1935     return CP_ACCESS_OK;
1936 }
1937
1938 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1939                              int access_type, ARMMMUIdx mmu_idx)
1940 {
1941     hwaddr phys_addr;
1942     target_ulong page_size;
1943     int prot;
1944     uint32_t fsr;
1945     bool ret;
1946     uint64_t par64;
1947     MemTxAttrs attrs = {};
1948     ARMMMUFaultInfo fi = {};
1949
1950     ret = get_phys_addr(env, value, access_type, mmu_idx,
1951                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1952     if (extended_addresses_enabled(env)) {
1953         /* fsr is a DFSR/IFSR value for the long descriptor
1954          * translation table format, but with WnR always clear.
1955          * Convert it to a 64-bit PAR.
1956          */
1957         par64 = (1 << 11); /* LPAE bit always set */
1958         if (!ret) {
1959             par64 |= phys_addr & ~0xfffULL;
1960             if (!attrs.secure) {
1961                 par64 |= (1 << 9); /* NS */
1962             }
1963             /* We don't set the ATTR or SH fields in the PAR. */
1964         } else {
1965             par64 |= 1; /* F */
1966             par64 |= (fsr & 0x3f) << 1; /* FS */
1967             /* Note that S2WLK and FSTAGE are always zero, because we don't
1968              * implement virtualization and therefore there can't be a stage 2
1969              * fault.
1970              */
1971         }
1972     } else {
1973         /* fsr is a DFSR/IFSR value for the short descriptor
1974          * translation table format (with WnR always clear).
1975          * Convert it to a 32-bit PAR.
1976          */
1977         if (!ret) {
1978             /* We do not set any attribute bits in the PAR */
1979             if (page_size == (1 << 24)
1980                 && arm_feature(env, ARM_FEATURE_V7)) {
1981                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1982             } else {
1983                 par64 = phys_addr & 0xfffff000;
1984             }
1985             if (!attrs.secure) {
1986                 par64 |= (1 << 9); /* NS */
1987             }
1988         } else {
1989             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1990                     ((fsr & 0xf) << 1) | 1;
1991         }
1992     }
1993     return par64;
1994 }
1995
1996 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1997 {
1998     int access_type = ri->opc2 & 1;
1999     uint64_t par64;
2000     ARMMMUIdx mmu_idx;
2001     int el = arm_current_el(env);
2002     bool secure = arm_is_secure_below_el3(env);
2003
2004     switch (ri->opc2 & 6) {
2005     case 0:
2006         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2007         switch (el) {
2008         case 3:
2009             mmu_idx = ARMMMUIdx_S1E3;
2010             break;
2011         case 2:
2012             mmu_idx = ARMMMUIdx_S1NSE1;
2013             break;
2014         case 1:
2015             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2016             break;
2017         default:
2018             g_assert_not_reached();
2019         }
2020         break;
2021     case 2:
2022         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2023         switch (el) {
2024         case 3:
2025             mmu_idx = ARMMMUIdx_S1SE0;
2026             break;
2027         case 2:
2028             mmu_idx = ARMMMUIdx_S1NSE0;
2029             break;
2030         case 1:
2031             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2032             break;
2033         default:
2034             g_assert_not_reached();
2035         }
2036         break;
2037     case 4:
2038         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2039         mmu_idx = ARMMMUIdx_S12NSE1;
2040         break;
2041     case 6:
2042         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2043         mmu_idx = ARMMMUIdx_S12NSE0;
2044         break;
2045     default:
2046         g_assert_not_reached();
2047     }
2048
2049     par64 = do_ats_write(env, value, access_type, mmu_idx);
2050
2051     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2052 }
2053
2054 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2055                         uint64_t value)
2056 {
2057     int access_type = ri->opc2 & 1;
2058     uint64_t par64;
2059
2060     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2061
2062     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2063 }
2064
2065 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2066                                      bool isread)
2067 {
2068     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2069         return CP_ACCESS_TRAP;
2070     }
2071     return CP_ACCESS_OK;
2072 }
2073
2074 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2075                         uint64_t value)
2076 {
2077     int access_type = ri->opc2 & 1;
2078     ARMMMUIdx mmu_idx;
2079     int secure = arm_is_secure_below_el3(env);
2080
2081     switch (ri->opc2 & 6) {
2082     case 0:
2083         switch (ri->opc1) {
2084         case 0: /* AT S1E1R, AT S1E1W */
2085             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2086             break;
2087         case 4: /* AT S1E2R, AT S1E2W */
2088             mmu_idx = ARMMMUIdx_S1E2;
2089             break;
2090         case 6: /* AT S1E3R, AT S1E3W */
2091             mmu_idx = ARMMMUIdx_S1E3;
2092             break;
2093         default:
2094             g_assert_not_reached();
2095         }
2096         break;
2097     case 2: /* AT S1E0R, AT S1E0W */
2098         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2099         break;
2100     case 4: /* AT S12E1R, AT S12E1W */
2101         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2102         break;
2103     case 6: /* AT S12E0R, AT S12E0W */
2104         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2105         break;
2106     default:
2107         g_assert_not_reached();
2108     }
2109
2110     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2111 }
2112 #endif
2113
2114 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2115     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2116       .access = PL1_RW, .resetvalue = 0,
2117       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2118                              offsetoflow32(CPUARMState, cp15.par_ns) },
2119       .writefn = par_write },
2120 #ifndef CONFIG_USER_ONLY
2121     /* This underdecoding is safe because the reginfo is NO_RAW. */
2122     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2123       .access = PL1_W, .accessfn = ats_access,
2124       .writefn = ats_write, .type = ARM_CP_NO_RAW },
2125 #endif
2126     REGINFO_SENTINEL
2127 };
2128
2129 /* Return basic MPU access permission bits.  */
2130 static uint32_t simple_mpu_ap_bits(uint32_t val)
2131 {
2132     uint32_t ret;
2133     uint32_t mask;
2134     int i;
2135     ret = 0;
2136     mask = 3;
2137     for (i = 0; i < 16; i += 2) {
2138         ret |= (val >> i) & mask;
2139         mask <<= 2;
2140     }
2141     return ret;
2142 }
2143
2144 /* Pad basic MPU access permission bits to extended format.  */
2145 static uint32_t extended_mpu_ap_bits(uint32_t val)
2146 {
2147     uint32_t ret;
2148     uint32_t mask;
2149     int i;
2150     ret = 0;
2151     mask = 3;
2152     for (i = 0; i < 16; i += 2) {
2153         ret |= (val & mask) << i;
2154         mask <<= 2;
2155     }
2156     return ret;
2157 }
2158
2159 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2160                                  uint64_t value)
2161 {
2162     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2163 }
2164
2165 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2166 {
2167     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2168 }
2169
2170 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2171                                  uint64_t value)
2172 {
2173     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2174 }
2175
2176 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2177 {
2178     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2179 }
2180
2181 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2182 {
2183     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2184
2185     if (!u32p) {
2186         return 0;
2187     }
2188
2189     u32p += env->cp15.c6_rgnr;
2190     return *u32p;
2191 }
2192
2193 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2194                          uint64_t value)
2195 {
2196     ARMCPU *cpu = arm_env_get_cpu(env);
2197     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2198
2199     if (!u32p) {
2200         return;
2201     }
2202
2203     u32p += env->cp15.c6_rgnr;
2204     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2205     *u32p = value;
2206 }
2207
2208 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2209 {
2210     ARMCPU *cpu = arm_env_get_cpu(env);
2211     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2212
2213     if (!u32p) {
2214         return;
2215     }
2216
2217     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2218 }
2219
2220 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2221                               uint64_t value)
2222 {
2223     ARMCPU *cpu = arm_env_get_cpu(env);
2224     uint32_t nrgs = cpu->pmsav7_dregion;
2225
2226     if (value >= nrgs) {
2227         qemu_log_mask(LOG_GUEST_ERROR,
2228                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2229                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2230         return;
2231     }
2232
2233     raw_write(env, ri, value);
2234 }
2235
2236 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2237     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2238       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2239       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2240       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2241     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2242       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2243       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2244       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2245     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2246       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2247       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2248       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2249     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2250       .access = PL1_RW,
2251       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2252       .writefn = pmsav7_rgnr_write },
2253     REGINFO_SENTINEL
2254 };
2255
2256 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2257     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2258       .access = PL1_RW, .type = ARM_CP_ALIAS,
2259       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2260       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2261     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2262       .access = PL1_RW, .type = ARM_CP_ALIAS,
2263       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2264       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2265     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2266       .access = PL1_RW,
2267       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2268       .resetvalue = 0, },
2269     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2270       .access = PL1_RW,
2271       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2272       .resetvalue = 0, },
2273     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2274       .access = PL1_RW,
2275       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2276     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2277       .access = PL1_RW,
2278       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2279     /* Protection region base and size registers */
2280     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2281       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2282       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2283     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2284       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2285       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2286     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2287       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2288       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2289     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2290       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2291       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2292     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2293       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2294       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2295     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2296       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2297       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2298     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2299       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2300       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2301     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2302       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2303       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2304     REGINFO_SENTINEL
2305 };
2306
2307 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2308                                  uint64_t value)
2309 {
2310     TCR *tcr = raw_ptr(env, ri);
2311     int maskshift = extract32(value, 0, 3);
2312
2313     if (!arm_feature(env, ARM_FEATURE_V8)) {
2314         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2315             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2316              * using Long-desciptor translation table format */
2317             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2318         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2319             /* In an implementation that includes the Security Extensions
2320              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2321              * Short-descriptor translation table format.
2322              */
2323             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2324         } else {
2325             value &= TTBCR_N;
2326         }
2327     }
2328
2329     /* Update the masks corresponding to the TCR bank being written
2330      * Note that we always calculate mask and base_mask, but
2331      * they are only used for short-descriptor tables (ie if EAE is 0);
2332      * for long-descriptor tables the TCR fields are used differently
2333      * and the mask and base_mask values are meaningless.
2334      */
2335     tcr->raw_tcr = value;
2336     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2337     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2338 }
2339
2340 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2341                              uint64_t value)
2342 {
2343     ARMCPU *cpu = arm_env_get_cpu(env);
2344
2345     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2346         /* With LPAE the TTBCR could result in a change of ASID
2347          * via the TTBCR.A1 bit, so do a TLB flush.
2348          */
2349         tlb_flush(CPU(cpu), 1);
2350     }
2351     vmsa_ttbcr_raw_write(env, ri, value);
2352 }
2353
2354 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2355 {
2356     TCR *tcr = raw_ptr(env, ri);
2357
2358     /* Reset both the TCR as well as the masks corresponding to the bank of
2359      * the TCR being reset.
2360      */
2361     tcr->raw_tcr = 0;
2362     tcr->mask = 0;
2363     tcr->base_mask = 0xffffc000u;
2364 }
2365
2366 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2367                                uint64_t value)
2368 {
2369     ARMCPU *cpu = arm_env_get_cpu(env);
2370     TCR *tcr = raw_ptr(env, ri);
2371
2372     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2373     tlb_flush(CPU(cpu), 1);
2374     tcr->raw_tcr = value;
2375 }
2376
2377 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2378                             uint64_t value)
2379 {
2380     /* 64 bit accesses to the TTBRs can change the ASID and so we
2381      * must flush the TLB.
2382      */
2383     if (cpreg_field_is_64bit(ri)) {
2384         ARMCPU *cpu = arm_env_get_cpu(env);
2385
2386         tlb_flush(CPU(cpu), 1);
2387     }
2388     raw_write(env, ri, value);
2389 }
2390
2391 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2392                         uint64_t value)
2393 {
2394     ARMCPU *cpu = arm_env_get_cpu(env);
2395     CPUState *cs = CPU(cpu);
2396
2397     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2398     if (raw_read(env, ri) != value) {
2399         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2400                             ARMMMUIdx_S2NS, -1);
2401         raw_write(env, ri, value);
2402     }
2403 }
2404
2405 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2406     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2407       .access = PL1_RW, .type = ARM_CP_ALIAS,
2408       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2409                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2410     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2411       .access = PL1_RW, .resetvalue = 0,
2412       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2413                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2414     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2415       .access = PL1_RW, .resetvalue = 0,
2416       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2417                              offsetof(CPUARMState, cp15.dfar_ns) } },
2418     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2419       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2420       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2421       .resetvalue = 0, },
2422     REGINFO_SENTINEL
2423 };
2424
2425 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2426     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2427       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2428       .access = PL1_RW,
2429       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2430     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2431       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2432       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2433       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2434                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2435     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2436       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2437       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2438       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2439                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2440     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2441       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2442       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2443       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2444       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2445     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2446       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2447       .raw_writefn = vmsa_ttbcr_raw_write,
2448       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2449                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2450     REGINFO_SENTINEL
2451 };
2452
2453 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2454                                 uint64_t value)
2455 {
2456     env->cp15.c15_ticonfig = value & 0xe7;
2457     /* The OS_TYPE bit in this register changes the reported CPUID! */
2458     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2459         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2460 }
2461
2462 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2463                                 uint64_t value)
2464 {
2465     env->cp15.c15_threadid = value & 0xffff;
2466 }
2467
2468 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2469                            uint64_t value)
2470 {
2471     /* Wait-for-interrupt (deprecated) */
2472     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2473 }
2474
2475 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2476                                   uint64_t value)
2477 {
2478     /* On OMAP there are registers indicating the max/min index of dcache lines
2479      * containing a dirty line; cache flush operations have to reset these.
2480      */
2481     env->cp15.c15_i_max = 0x000;
2482     env->cp15.c15_i_min = 0xff0;
2483 }
2484
2485 static const ARMCPRegInfo omap_cp_reginfo[] = {
2486     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2487       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2488       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2489       .resetvalue = 0, },
2490     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2491       .access = PL1_RW, .type = ARM_CP_NOP },
2492     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2493       .access = PL1_RW,
2494       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2495       .writefn = omap_ticonfig_write },
2496     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2497       .access = PL1_RW,
2498       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2499     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2500       .access = PL1_RW, .resetvalue = 0xff0,
2501       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2502     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2503       .access = PL1_RW,
2504       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2505       .writefn = omap_threadid_write },
2506     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2507       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2508       .type = ARM_CP_NO_RAW,
2509       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2510     /* TODO: Peripheral port remap register:
2511      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2512      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2513      * when MMU is off.
2514      */
2515     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2516       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2517       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2518       .writefn = omap_cachemaint_write },
2519     { .name = "C9", .cp = 15, .crn = 9,
2520       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2521       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2522     REGINFO_SENTINEL
2523 };
2524
2525 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2526                               uint64_t value)
2527 {
2528     env->cp15.c15_cpar = value & 0x3fff;
2529 }
2530
2531 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2532     { .name = "XSCALE_CPAR",
2533       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2534       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2535       .writefn = xscale_cpar_write, },
2536     { .name = "XSCALE_AUXCR",
2537       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2538       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2539       .resetvalue = 0, },
2540     /* XScale specific cache-lockdown: since we have no cache we NOP these
2541      * and hope the guest does not really rely on cache behaviour.
2542      */
2543     { .name = "XSCALE_LOCK_ICACHE_LINE",
2544       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2545       .access = PL1_W, .type = ARM_CP_NOP },
2546     { .name = "XSCALE_UNLOCK_ICACHE",
2547       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2548       .access = PL1_W, .type = ARM_CP_NOP },
2549     { .name = "XSCALE_DCACHE_LOCK",
2550       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2551       .access = PL1_RW, .type = ARM_CP_NOP },
2552     { .name = "XSCALE_UNLOCK_DCACHE",
2553       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2554       .access = PL1_W, .type = ARM_CP_NOP },
2555     REGINFO_SENTINEL
2556 };
2557
2558 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2559     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2560      * implementation of this implementation-defined space.
2561      * Ideally this should eventually disappear in favour of actually
2562      * implementing the correct behaviour for all cores.
2563      */
2564     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2565       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2566       .access = PL1_RW,
2567       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2568       .resetvalue = 0 },
2569     REGINFO_SENTINEL
2570 };
2571
2572 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2573     /* Cache status: RAZ because we have no cache so it's always clean */
2574     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2575       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2576       .resetvalue = 0 },
2577     REGINFO_SENTINEL
2578 };
2579
2580 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2581     /* We never have a a block transfer operation in progress */
2582     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2583       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2584       .resetvalue = 0 },
2585     /* The cache ops themselves: these all NOP for QEMU */
2586     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2587       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2588     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2589       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2590     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2591       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2592     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2593       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2594     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2595       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2596     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2597       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2598     REGINFO_SENTINEL
2599 };
2600
2601 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2602     /* The cache test-and-clean instructions always return (1 << 30)
2603      * to indicate that there are no dirty cache lines.
2604      */
2605     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2606       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2607       .resetvalue = (1 << 30) },
2608     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2609       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2610       .resetvalue = (1 << 30) },
2611     REGINFO_SENTINEL
2612 };
2613
2614 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2615     /* Ignore ReadBuffer accesses */
2616     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2617       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2618       .access = PL1_RW, .resetvalue = 0,
2619       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2620     REGINFO_SENTINEL
2621 };
2622
2623 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2624 {
2625     ARMCPU *cpu = arm_env_get_cpu(env);
2626     unsigned int cur_el = arm_current_el(env);
2627     bool secure = arm_is_secure(env);
2628
2629     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2630         return env->cp15.vpidr_el2;
2631     }
2632     return raw_read(env, ri);
2633 }
2634
2635 static uint64_t mpidr_read_val(CPUARMState *env)
2636 {
2637     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2638     uint64_t mpidr = cpu->mp_affinity;
2639
2640     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2641         mpidr |= (1U << 31);
2642         /* Cores which are uniprocessor (non-coherent)
2643          * but still implement the MP extensions set
2644          * bit 30. (For instance, Cortex-R5).
2645          */
2646         if (cpu->mp_is_up) {
2647             mpidr |= (1u << 30);
2648         }
2649     }
2650     return mpidr;
2651 }
2652
2653 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2654 {
2655     unsigned int cur_el = arm_current_el(env);
2656     bool secure = arm_is_secure(env);
2657
2658     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2659         return env->cp15.vmpidr_el2;
2660     }
2661     return mpidr_read_val(env);
2662 }
2663
2664 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2665     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2666       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2667       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2668     REGINFO_SENTINEL
2669 };
2670
2671 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2672     /* NOP AMAIR0/1 */
2673     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2674       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2675       .access = PL1_RW, .type = ARM_CP_CONST,
2676       .resetvalue = 0 },
2677     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2678     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2679       .access = PL1_RW, .type = ARM_CP_CONST,
2680       .resetvalue = 0 },
2681     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2682       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2683       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2684                              offsetof(CPUARMState, cp15.par_ns)} },
2685     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2686       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2687       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2688                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2689       .writefn = vmsa_ttbr_write, },
2690     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2691       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2692       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2693                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2694       .writefn = vmsa_ttbr_write, },
2695     REGINFO_SENTINEL
2696 };
2697
2698 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2699 {
2700     return vfp_get_fpcr(env);
2701 }
2702
2703 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2704                             uint64_t value)
2705 {
2706     vfp_set_fpcr(env, value);
2707 }
2708
2709 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2710 {
2711     return vfp_get_fpsr(env);
2712 }
2713
2714 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2715                             uint64_t value)
2716 {
2717     vfp_set_fpsr(env, value);
2718 }
2719
2720 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2721                                        bool isread)
2722 {
2723     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2724         return CP_ACCESS_TRAP;
2725     }
2726     return CP_ACCESS_OK;
2727 }
2728
2729 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2730                             uint64_t value)
2731 {
2732     env->daif = value & PSTATE_DAIF;
2733 }
2734
2735 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2736                                           const ARMCPRegInfo *ri,
2737                                           bool isread)
2738 {
2739     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2740      * SCTLR_EL1.UCI is set.
2741      */
2742     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2743         return CP_ACCESS_TRAP;
2744     }
2745     return CP_ACCESS_OK;
2746 }
2747
2748 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2749  * Page D4-1736 (DDI0487A.b)
2750  */
2751
2752 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2753                                     uint64_t value)
2754 {
2755     ARMCPU *cpu = arm_env_get_cpu(env);
2756     CPUState *cs = CPU(cpu);
2757
2758     if (arm_is_secure_below_el3(env)) {
2759         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2760     } else {
2761         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2762     }
2763 }
2764
2765 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2766                                       uint64_t value)
2767 {
2768     bool sec = arm_is_secure_below_el3(env);
2769     CPUState *other_cs;
2770
2771     CPU_FOREACH(other_cs) {
2772         if (sec) {
2773             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2774         } else {
2775             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2776                                 ARMMMUIdx_S12NSE0, -1);
2777         }
2778     }
2779 }
2780
2781 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2782                                   uint64_t value)
2783 {
2784     /* Note that the 'ALL' scope must invalidate both stage 1 and
2785      * stage 2 translations, whereas most other scopes only invalidate
2786      * stage 1 translations.
2787      */
2788     ARMCPU *cpu = arm_env_get_cpu(env);
2789     CPUState *cs = CPU(cpu);
2790
2791     if (arm_is_secure_below_el3(env)) {
2792         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2793     } else {
2794         if (arm_feature(env, ARM_FEATURE_EL2)) {
2795             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2796                                 ARMMMUIdx_S2NS, -1);
2797         } else {
2798             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2799         }
2800     }
2801 }
2802
2803 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2804                                   uint64_t value)
2805 {
2806     ARMCPU *cpu = arm_env_get_cpu(env);
2807     CPUState *cs = CPU(cpu);
2808
2809     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2810 }
2811
2812 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2813                                   uint64_t value)
2814 {
2815     ARMCPU *cpu = arm_env_get_cpu(env);
2816     CPUState *cs = CPU(cpu);
2817
2818     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2819 }
2820
2821 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2822                                     uint64_t value)
2823 {
2824     /* Note that the 'ALL' scope must invalidate both stage 1 and
2825      * stage 2 translations, whereas most other scopes only invalidate
2826      * stage 1 translations.
2827      */
2828     bool sec = arm_is_secure_below_el3(env);
2829     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2830     CPUState *other_cs;
2831
2832     CPU_FOREACH(other_cs) {
2833         if (sec) {
2834             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2835         } else if (has_el2) {
2836             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2837                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2838         } else {
2839             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2840                                 ARMMMUIdx_S12NSE0, -1);
2841         }
2842     }
2843 }
2844
2845 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2846                                     uint64_t value)
2847 {
2848     CPUState *other_cs;
2849
2850     CPU_FOREACH(other_cs) {
2851         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2852     }
2853 }
2854
2855 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856                                     uint64_t value)
2857 {
2858     CPUState *other_cs;
2859
2860     CPU_FOREACH(other_cs) {
2861         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2862     }
2863 }
2864
2865 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2866                                  uint64_t value)
2867 {
2868     /* Invalidate by VA, EL1&0 (AArch64 version).
2869      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2870      * since we don't support flush-for-specific-ASID-only or
2871      * flush-last-level-only.
2872      */
2873     ARMCPU *cpu = arm_env_get_cpu(env);
2874     CPUState *cs = CPU(cpu);
2875     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2876
2877     if (arm_is_secure_below_el3(env)) {
2878         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2879                                  ARMMMUIdx_S1SE0, -1);
2880     } else {
2881         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2882                                  ARMMMUIdx_S12NSE0, -1);
2883     }
2884 }
2885
2886 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2887                                  uint64_t value)
2888 {
2889     /* Invalidate by VA, EL2
2890      * Currently handles both VAE2 and VALE2, since we don't support
2891      * flush-last-level-only.
2892      */
2893     ARMCPU *cpu = arm_env_get_cpu(env);
2894     CPUState *cs = CPU(cpu);
2895     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2896
2897     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2898 }
2899
2900 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2901                                  uint64_t value)
2902 {
2903     /* Invalidate by VA, EL3
2904      * Currently handles both VAE3 and VALE3, since we don't support
2905      * flush-last-level-only.
2906      */
2907     ARMCPU *cpu = arm_env_get_cpu(env);
2908     CPUState *cs = CPU(cpu);
2909     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2910
2911     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2912 }
2913
2914 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2915                                    uint64_t value)
2916 {
2917     bool sec = arm_is_secure_below_el3(env);
2918     CPUState *other_cs;
2919     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2920
2921     CPU_FOREACH(other_cs) {
2922         if (sec) {
2923             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2924                                      ARMMMUIdx_S1SE0, -1);
2925         } else {
2926             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2927                                      ARMMMUIdx_S12NSE0, -1);
2928         }
2929     }
2930 }
2931
2932 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2933                                    uint64_t value)
2934 {
2935     CPUState *other_cs;
2936     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2937
2938     CPU_FOREACH(other_cs) {
2939         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2940     }
2941 }
2942
2943 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2944                                    uint64_t value)
2945 {
2946     CPUState *other_cs;
2947     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2948
2949     CPU_FOREACH(other_cs) {
2950         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2951     }
2952 }
2953
2954 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2955                                     uint64_t value)
2956 {
2957     /* Invalidate by IPA. This has to invalidate any structures that
2958      * contain only stage 2 translation information, but does not need
2959      * to apply to structures that contain combined stage 1 and stage 2
2960      * translation information.
2961      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2962      */
2963     ARMCPU *cpu = arm_env_get_cpu(env);
2964     CPUState *cs = CPU(cpu);
2965     uint64_t pageaddr;
2966
2967     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2968         return;
2969     }
2970
2971     pageaddr = sextract64(value << 12, 0, 48);
2972
2973     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2974 }
2975
2976 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2977                                       uint64_t value)
2978 {
2979     CPUState *other_cs;
2980     uint64_t pageaddr;
2981
2982     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2983         return;
2984     }
2985
2986     pageaddr = sextract64(value << 12, 0, 48);
2987
2988     CPU_FOREACH(other_cs) {
2989         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2990     }
2991 }
2992
2993 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
2994                                       bool isread)
2995 {
2996     /* We don't implement EL2, so the only control on DC ZVA is the
2997      * bit in the SCTLR which can prohibit access for EL0.
2998      */
2999     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3000         return CP_ACCESS_TRAP;
3001     }
3002     return CP_ACCESS_OK;
3003 }
3004
3005 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3006 {
3007     ARMCPU *cpu = arm_env_get_cpu(env);
3008     int dzp_bit = 1 << 4;
3009
3010     /* DZP indicates whether DC ZVA access is allowed */
3011     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3012         dzp_bit = 0;
3013     }
3014     return cpu->dcz_blocksize | dzp_bit;
3015 }
3016
3017 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3018                                     bool isread)
3019 {
3020     if (!(env->pstate & PSTATE_SP)) {
3021         /* Access to SP_EL0 is undefined if it's being used as
3022          * the stack pointer.
3023          */
3024         return CP_ACCESS_TRAP_UNCATEGORIZED;
3025     }
3026     return CP_ACCESS_OK;
3027 }
3028
3029 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3030 {
3031     return env->pstate & PSTATE_SP;
3032 }
3033
3034 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3035 {
3036     update_spsel(env, val);
3037 }
3038
3039 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3040                         uint64_t value)
3041 {
3042     ARMCPU *cpu = arm_env_get_cpu(env);
3043
3044     if (raw_read(env, ri) == value) {
3045         /* Skip the TLB flush if nothing actually changed; Linux likes
3046          * to do a lot of pointless SCTLR writes.
3047          */
3048         return;
3049     }
3050
3051     raw_write(env, ri, value);
3052     /* ??? Lots of these bits are not implemented.  */
3053     /* This may enable/disable the MMU, so do a TLB flush.  */
3054     tlb_flush(CPU(cpu), 1);
3055 }
3056
3057 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3058                                      bool isread)
3059 {
3060     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3061         return CP_ACCESS_TRAP_FP_EL2;
3062     }
3063     if (env->cp15.cptr_el[3] & CPTR_TFP) {
3064         return CP_ACCESS_TRAP_FP_EL3;
3065     }
3066     return CP_ACCESS_OK;
3067 }
3068
3069 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3070                        uint64_t value)
3071 {
3072     env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3073 }
3074
3075 static const ARMCPRegInfo v8_cp_reginfo[] = {
3076     /* Minimal set of EL0-visible registers. This will need to be expanded
3077      * significantly for system emulation of AArch64 CPUs.
3078      */
3079     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3080       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3081       .access = PL0_RW, .type = ARM_CP_NZCV },
3082     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3083       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3084       .type = ARM_CP_NO_RAW,
3085       .access = PL0_RW, .accessfn = aa64_daif_access,
3086       .fieldoffset = offsetof(CPUARMState, daif),
3087       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3088     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3089       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3090       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3091     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3092       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3093       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3094     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3095       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3096       .access = PL0_R, .type = ARM_CP_NO_RAW,
3097       .readfn = aa64_dczid_read },
3098     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3099       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3100       .access = PL0_W, .type = ARM_CP_DC_ZVA,
3101 #ifndef CONFIG_USER_ONLY
3102       /* Avoid overhead of an access check that always passes in user-mode */
3103       .accessfn = aa64_zva_access,
3104 #endif
3105     },
3106     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3107       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3108       .access = PL1_R, .type = ARM_CP_CURRENTEL },
3109     /* Cache ops: all NOPs since we don't emulate caches */
3110     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3111       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3112       .access = PL1_W, .type = ARM_CP_NOP },
3113     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3114       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3115       .access = PL1_W, .type = ARM_CP_NOP },
3116     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3117       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3118       .access = PL0_W, .type = ARM_CP_NOP,
3119       .accessfn = aa64_cacheop_access },
3120     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3121       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3122       .access = PL1_W, .type = ARM_CP_NOP },
3123     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3124       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3125       .access = PL1_W, .type = ARM_CP_NOP },
3126     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3127       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3128       .access = PL0_W, .type = ARM_CP_NOP,
3129       .accessfn = aa64_cacheop_access },
3130     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3131       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3132       .access = PL1_W, .type = ARM_CP_NOP },
3133     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3134       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3135       .access = PL0_W, .type = ARM_CP_NOP,
3136       .accessfn = aa64_cacheop_access },
3137     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3138       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3139       .access = PL0_W, .type = ARM_CP_NOP,
3140       .accessfn = aa64_cacheop_access },
3141     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3142       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3143       .access = PL1_W, .type = ARM_CP_NOP },
3144     /* TLBI operations */
3145     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3146       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3147       .access = PL1_W, .type = ARM_CP_NO_RAW,
3148       .writefn = tlbi_aa64_vmalle1is_write },
3149     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3150       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3151       .access = PL1_W, .type = ARM_CP_NO_RAW,
3152       .writefn = tlbi_aa64_vae1is_write },
3153     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3154       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3155       .access = PL1_W, .type = ARM_CP_NO_RAW,
3156       .writefn = tlbi_aa64_vmalle1is_write },
3157     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3158       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3159       .access = PL1_W, .type = ARM_CP_NO_RAW,
3160       .writefn = tlbi_aa64_vae1is_write },
3161     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3162       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3163       .access = PL1_W, .type = ARM_CP_NO_RAW,
3164       .writefn = tlbi_aa64_vae1is_write },
3165     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3166       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3167       .access = PL1_W, .type = ARM_CP_NO_RAW,
3168       .writefn = tlbi_aa64_vae1is_write },
3169     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3170       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3171       .access = PL1_W, .type = ARM_CP_NO_RAW,
3172       .writefn = tlbi_aa64_vmalle1_write },
3173     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3174       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3175       .access = PL1_W, .type = ARM_CP_NO_RAW,
3176       .writefn = tlbi_aa64_vae1_write },
3177     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3178       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3179       .access = PL1_W, .type = ARM_CP_NO_RAW,
3180       .writefn = tlbi_aa64_vmalle1_write },
3181     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3182       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3183       .access = PL1_W, .type = ARM_CP_NO_RAW,
3184       .writefn = tlbi_aa64_vae1_write },
3185     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3186       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3187       .access = PL1_W, .type = ARM_CP_NO_RAW,
3188       .writefn = tlbi_aa64_vae1_write },
3189     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3190       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3191       .access = PL1_W, .type = ARM_CP_NO_RAW,
3192       .writefn = tlbi_aa64_vae1_write },
3193     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3194       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3195       .access = PL2_W, .type = ARM_CP_NO_RAW,
3196       .writefn = tlbi_aa64_ipas2e1is_write },
3197     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3198       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3199       .access = PL2_W, .type = ARM_CP_NO_RAW,
3200       .writefn = tlbi_aa64_ipas2e1is_write },
3201     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3202       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3203       .access = PL2_W, .type = ARM_CP_NO_RAW,
3204       .writefn = tlbi_aa64_alle1is_write },
3205     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3207       .access = PL2_W, .type = ARM_CP_NO_RAW,
3208       .writefn = tlbi_aa64_alle1is_write },
3209     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3210       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3211       .access = PL2_W, .type = ARM_CP_NO_RAW,
3212       .writefn = tlbi_aa64_ipas2e1_write },
3213     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3214       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3215       .access = PL2_W, .type = ARM_CP_NO_RAW,
3216       .writefn = tlbi_aa64_ipas2e1_write },
3217     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3218       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3219       .access = PL2_W, .type = ARM_CP_NO_RAW,
3220       .writefn = tlbi_aa64_alle1_write },
3221     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3222       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3223       .access = PL2_W, .type = ARM_CP_NO_RAW,
3224       .writefn = tlbi_aa64_alle1is_write },
3225 #ifndef CONFIG_USER_ONLY
3226     /* 64 bit address translation operations */
3227     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3228       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3229       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3230     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3231       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3232       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3233     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3234       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3235       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3236     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3237       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3238       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3239     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3240       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3241       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3242     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3243       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3244       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3245     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3246       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3247       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3248     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3249       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3250       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3251     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3252     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3253       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3254       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3255     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3256       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3257       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3258     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3259       .type = ARM_CP_ALIAS,
3260       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3261       .access = PL1_RW, .resetvalue = 0,
3262       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3263       .writefn = par_write },
3264 #endif
3265     /* TLB invalidate last level of translation table walk */
3266     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3267       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3268     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3269       .type = ARM_CP_NO_RAW, .access = PL1_W,
3270       .writefn = tlbimvaa_is_write },
3271     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3272       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3273     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3274       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3275     /* 32 bit cache operations */
3276     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3277       .type = ARM_CP_NOP, .access = PL1_W },
3278     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3279       .type = ARM_CP_NOP, .access = PL1_W },
3280     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3281       .type = ARM_CP_NOP, .access = PL1_W },
3282     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3283       .type = ARM_CP_NOP, .access = PL1_W },
3284     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3285       .type = ARM_CP_NOP, .access = PL1_W },
3286     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3287       .type = ARM_CP_NOP, .access = PL1_W },
3288     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3289       .type = ARM_CP_NOP, .access = PL1_W },
3290     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3291       .type = ARM_CP_NOP, .access = PL1_W },
3292     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3293       .type = ARM_CP_NOP, .access = PL1_W },
3294     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3295       .type = ARM_CP_NOP, .access = PL1_W },
3296     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3297       .type = ARM_CP_NOP, .access = PL1_W },
3298     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3299       .type = ARM_CP_NOP, .access = PL1_W },
3300     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3301       .type = ARM_CP_NOP, .access = PL1_W },
3302     /* MMU Domain access control / MPU write buffer control */
3303     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3304       .access = PL1_RW, .resetvalue = 0,
3305       .writefn = dacr_write, .raw_writefn = raw_write,
3306       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3307                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3308     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3309       .type = ARM_CP_ALIAS,
3310       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3311       .access = PL1_RW,
3312       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3313     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3314       .type = ARM_CP_ALIAS,
3315       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3316       .access = PL1_RW,
3317       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3318     /* We rely on the access checks not allowing the guest to write to the
3319      * state field when SPSel indicates that it's being used as the stack
3320      * pointer.
3321      */
3322     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3323       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3324       .access = PL1_RW, .accessfn = sp_el0_access,
3325       .type = ARM_CP_ALIAS,
3326       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3327     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3328       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3329       .access = PL2_RW, .type = ARM_CP_ALIAS,
3330       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3331     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3332       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3333       .type = ARM_CP_NO_RAW,
3334       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3335     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3336       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3337       .type = ARM_CP_ALIAS,
3338       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3339       .access = PL2_RW, .accessfn = fpexc32_access },
3340     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3341       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3342       .access = PL2_RW, .resetvalue = 0,
3343       .writefn = dacr_write, .raw_writefn = raw_write,
3344       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3345     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3346       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3347       .access = PL2_RW, .resetvalue = 0,
3348       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3349     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3350       .type = ARM_CP_ALIAS,
3351       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3352       .access = PL2_RW,
3353       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3354     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3355       .type = ARM_CP_ALIAS,
3356       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3357       .access = PL2_RW,
3358       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3359     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3360       .type = ARM_CP_ALIAS,
3361       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3362       .access = PL2_RW,
3363       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3364     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3365       .type = ARM_CP_ALIAS,
3366       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3367       .access = PL2_RW,
3368       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3369     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3370       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3371       .resetvalue = 0,
3372       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3373     { .name = "SDCR", .type = ARM_CP_ALIAS,
3374       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3375       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3376       .writefn = sdcr_write,
3377       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3378     REGINFO_SENTINEL
3379 };
3380
3381 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3382 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3383     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3384       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3385       .access = PL2_RW,
3386       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3387     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3388       .type = ARM_CP_NO_RAW,
3389       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3390       .access = PL2_RW,
3391       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3392     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3393       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3394       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3395     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3396       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3397       .access = PL2_RW, .type = ARM_CP_CONST,
3398       .resetvalue = 0 },
3399     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3400       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3401       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3402     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3403       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3404       .access = PL2_RW, .type = ARM_CP_CONST,
3405       .resetvalue = 0 },
3406     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3407       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3408       .access = PL2_RW, .type = ARM_CP_CONST,
3409       .resetvalue = 0 },
3410     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3411       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3412       .access = PL2_RW, .type = ARM_CP_CONST,
3413       .resetvalue = 0 },
3414     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3415       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3416       .access = PL2_RW, .type = ARM_CP_CONST,
3417       .resetvalue = 0 },
3418     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3419       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3420       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3421     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3422       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3423       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3424       .type = ARM_CP_CONST, .resetvalue = 0 },
3425     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3426       .cp = 15, .opc1 = 6, .crm = 2,
3427       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3428       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3429     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3430       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3431       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3432     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3433       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3434       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3435     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3436       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3437       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3438     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3439       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3440       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3441     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3442       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3443       .resetvalue = 0 },
3444     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3445       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3446       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3447     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3448       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3449       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3450     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3451       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3452       .resetvalue = 0 },
3453     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3454       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3455       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3456     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3457       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3458       .resetvalue = 0 },
3459     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3460       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3461       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3462     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3463       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3464       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3465     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3466       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3467       .access = PL2_RW, .accessfn = access_tda,
3468       .type = ARM_CP_CONST, .resetvalue = 0 },
3469     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3470       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3471       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3472       .type = ARM_CP_CONST, .resetvalue = 0 },
3473     REGINFO_SENTINEL
3474 };
3475
3476 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3477 {
3478     ARMCPU *cpu = arm_env_get_cpu(env);
3479     uint64_t valid_mask = HCR_MASK;
3480
3481     if (arm_feature(env, ARM_FEATURE_EL3)) {
3482         valid_mask &= ~HCR_HCD;
3483     } else {
3484         valid_mask &= ~HCR_TSC;
3485     }
3486
3487     /* Clear RES0 bits.  */
3488     value &= valid_mask;
3489
3490     /* These bits change the MMU setup:
3491      * HCR_VM enables stage 2 translation
3492      * HCR_PTW forbids certain page-table setups
3493      * HCR_DC Disables stage1 and enables stage2 translation
3494      */
3495     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3496         tlb_flush(CPU(cpu), 1);
3497     }
3498     raw_write(env, ri, value);
3499 }
3500
3501 static const ARMCPRegInfo el2_cp_reginfo[] = {
3502     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3503       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3504       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3505       .writefn = hcr_write },
3506     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3507       .type = ARM_CP_ALIAS,
3508       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3509       .access = PL2_RW,
3510       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3511     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3512       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3513       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3514     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3515       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3516       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3517     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3518       .type = ARM_CP_ALIAS,
3519       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3520       .access = PL2_RW,
3521       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3522     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3523       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3524       .access = PL2_RW, .writefn = vbar_write,
3525       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3526       .resetvalue = 0 },
3527     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3528       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3529       .access = PL3_RW, .type = ARM_CP_ALIAS,
3530       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3531     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3532       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3533       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3534       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3535     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3536       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3537       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3538       .resetvalue = 0 },
3539     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3540       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3541       .access = PL2_RW, .type = ARM_CP_ALIAS,
3542       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3543     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3544       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3545       .access = PL2_RW, .type = ARM_CP_CONST,
3546       .resetvalue = 0 },
3547     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3548     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3549       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3550       .access = PL2_RW, .type = ARM_CP_CONST,
3551       .resetvalue = 0 },
3552     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3553       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3554       .access = PL2_RW, .type = ARM_CP_CONST,
3555       .resetvalue = 0 },
3556     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3557       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3558       .access = PL2_RW, .type = ARM_CP_CONST,
3559       .resetvalue = 0 },
3560     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3561       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3562       .access = PL2_RW,
3563       /* no .writefn needed as this can't cause an ASID change;
3564        * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3565        */
3566       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3567     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3568       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3569       .type = ARM_CP_ALIAS,
3570       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3571       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3572     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3573       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3574       .access = PL2_RW,
3575       /* no .writefn needed as this can't cause an ASID change;
3576        * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3577        */
3578       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3579     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3580       .cp = 15, .opc1 = 6, .crm = 2,
3581       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3582       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3583       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3584       .writefn = vttbr_write },
3585     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3586       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3587       .access = PL2_RW, .writefn = vttbr_write,
3588       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3589     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3590       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3591       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3592       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3593     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3594       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3595       .access = PL2_RW, .resetvalue = 0,
3596       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3597     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3598       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3599       .access = PL2_RW, .resetvalue = 0,
3600       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3601     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3602       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3603       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3604     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3605       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3606       .type = ARM_CP_NO_RAW, .access = PL2_W,
3607       .writefn = tlbi_aa64_alle2_write },
3608     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3609       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3610       .type = ARM_CP_NO_RAW, .access = PL2_W,
3611       .writefn = tlbi_aa64_vae2_write },
3612     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3613       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3614       .access = PL2_W, .type = ARM_CP_NO_RAW,
3615       .writefn = tlbi_aa64_vae2_write },
3616     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3617       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3618       .access = PL2_W, .type = ARM_CP_NO_RAW,
3619       .writefn = tlbi_aa64_alle2is_write },
3620     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3621       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3622       .type = ARM_CP_NO_RAW, .access = PL2_W,
3623       .writefn = tlbi_aa64_vae2is_write },
3624     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3625       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3626       .access = PL2_W, .type = ARM_CP_NO_RAW,
3627       .writefn = tlbi_aa64_vae2is_write },
3628 #ifndef CONFIG_USER_ONLY
3629     /* Unlike the other EL2-related AT operations, these must
3630      * UNDEF from EL3 if EL2 is not implemented, which is why we
3631      * define them here rather than with the rest of the AT ops.
3632      */
3633     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3634       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3635       .access = PL2_W, .accessfn = at_s1e2_access,
3636       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3637     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3638       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3639       .access = PL2_W, .accessfn = at_s1e2_access,
3640       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3641     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3642      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3643      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3644      * to behave as if SCR.NS was 1.
3645      */
3646     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3647       .access = PL2_W,
3648       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3649     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3650       .access = PL2_W,
3651       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3652     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3653       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3654       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3655        * reset values as IMPDEF. We choose to reset to 3 to comply with
3656        * both ARMv7 and ARMv8.
3657        */
3658       .access = PL2_RW, .resetvalue = 3,
3659       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3660     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3661       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3662       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3663       .writefn = gt_cntvoff_write,
3664       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3665     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3666       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3667       .writefn = gt_cntvoff_write,
3668       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3669     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3670       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3671       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3672       .type = ARM_CP_IO, .access = PL2_RW,
3673       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3674     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3675       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3676       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3677       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3678     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3679       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3680       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
3681       .resetfn = gt_hyp_timer_reset,
3682       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3683     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3684       .type = ARM_CP_IO,
3685       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3686       .access = PL2_RW,
3687       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3688       .resetvalue = 0,
3689       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3690 #endif
3691     /* The only field of MDCR_EL2 that has a defined architectural reset value
3692      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3693      * don't impelment any PMU event counters, so using zero as a reset
3694      * value for MDCR_EL2 is okay
3695      */
3696     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3697       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3698       .access = PL2_RW, .resetvalue = 0,
3699       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3700     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3701       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3702       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3703       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3704     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3705       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3706       .access = PL2_RW,
3707       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3708     REGINFO_SENTINEL
3709 };
3710
3711 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3712                                    bool isread)
3713 {
3714     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3715      * At Secure EL1 it traps to EL3.
3716      */
3717     if (arm_current_el(env) == 3) {
3718         return CP_ACCESS_OK;
3719     }
3720     if (arm_is_secure_below_el3(env)) {
3721         return CP_ACCESS_TRAP_EL3;
3722     }
3723     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3724     if (isread) {
3725         return CP_ACCESS_OK;
3726     }
3727     return CP_ACCESS_TRAP_UNCATEGORIZED;
3728 }
3729
3730 static const ARMCPRegInfo el3_cp_reginfo[] = {
3731     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3732       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3733       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3734       .resetvalue = 0, .writefn = scr_write },
3735     { .name = "SCR",  .type = ARM_CP_ALIAS,
3736       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3737       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3738       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3739       .writefn = scr_write },
3740     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3741       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3742       .access = PL3_RW, .resetvalue = 0,
3743       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3744     { .name = "SDER",
3745       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3746       .access = PL3_RW, .resetvalue = 0,
3747       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3748     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3749       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3750       .writefn = vbar_write, .resetvalue = 0,
3751       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3752     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3753       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3754       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3755       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3756     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3757       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3758       .access = PL3_RW,
3759       /* no .writefn needed as this can't cause an ASID change;
3760        * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3761        */
3762       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3763     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3764       .type = ARM_CP_ALIAS,
3765       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3766       .access = PL3_RW,
3767       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3768     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3769       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3770       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3771     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3772       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3773       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3774     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3775       .type = ARM_CP_ALIAS,
3776       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3777       .access = PL3_RW,
3778       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3779     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3780       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3781       .access = PL3_RW, .writefn = vbar_write,
3782       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3783       .resetvalue = 0 },
3784     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3785       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3786       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3787       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3788     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3789       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3790       .access = PL3_RW, .resetvalue = 0,
3791       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3792     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3793       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3794       .access = PL3_RW, .type = ARM_CP_CONST,
3795       .resetvalue = 0 },
3796     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3797       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3798       .access = PL3_RW, .type = ARM_CP_CONST,
3799       .resetvalue = 0 },
3800     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3801       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3802       .access = PL3_RW, .type = ARM_CP_CONST,
3803       .resetvalue = 0 },
3804     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3805       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3806       .access = PL3_W, .type = ARM_CP_NO_RAW,
3807       .writefn = tlbi_aa64_alle3is_write },
3808     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3809       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3810       .access = PL3_W, .type = ARM_CP_NO_RAW,
3811       .writefn = tlbi_aa64_vae3is_write },
3812     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3813       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3814       .access = PL3_W, .type = ARM_CP_NO_RAW,
3815       .writefn = tlbi_aa64_vae3is_write },
3816     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3817       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3818       .access = PL3_W, .type = ARM_CP_NO_RAW,
3819       .writefn = tlbi_aa64_alle3_write },
3820     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3821       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3822       .access = PL3_W, .type = ARM_CP_NO_RAW,
3823       .writefn = tlbi_aa64_vae3_write },
3824     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3825       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3826       .access = PL3_W, .type = ARM_CP_NO_RAW,
3827       .writefn = tlbi_aa64_vae3_write },
3828     REGINFO_SENTINEL
3829 };
3830
3831 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3832                                      bool isread)
3833 {
3834     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3835      * but the AArch32 CTR has its own reginfo struct)
3836      */
3837     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3838         return CP_ACCESS_TRAP;
3839     }
3840     return CP_ACCESS_OK;
3841 }
3842
3843 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3844                         uint64_t value)
3845 {
3846     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3847      * read via a bit in OSLSR_EL1.
3848      */
3849     int oslock;
3850
3851     if (ri->state == ARM_CP_STATE_AA32) {
3852         oslock = (value == 0xC5ACCE55);
3853     } else {
3854         oslock = value & 1;
3855     }
3856
3857     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3858 }
3859
3860 static const ARMCPRegInfo debug_cp_reginfo[] = {
3861     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3862      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3863      * unlike DBGDRAR it is never accessible from EL0.
3864      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3865      * accessor.
3866      */
3867     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3868       .access = PL0_R, .accessfn = access_tdra,
3869       .type = ARM_CP_CONST, .resetvalue = 0 },
3870     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3871       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3872       .access = PL1_R, .accessfn = access_tdra,
3873       .type = ARM_CP_CONST, .resetvalue = 0 },
3874     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3875       .access = PL0_R, .accessfn = access_tdra,
3876       .type = ARM_CP_CONST, .resetvalue = 0 },
3877     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3878     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3879       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3880       .access = PL1_RW, .accessfn = access_tda,
3881       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3882       .resetvalue = 0 },
3883     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3884      * We don't implement the configurable EL0 access.
3885      */
3886     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3887       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3888       .type = ARM_CP_ALIAS,
3889       .access = PL1_R, .accessfn = access_tda,
3890       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3891     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3892       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3893       .access = PL1_W, .type = ARM_CP_NO_RAW,
3894       .accessfn = access_tdosa,
3895       .writefn = oslar_write },
3896     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3897       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3898       .access = PL1_R, .resetvalue = 10,
3899       .accessfn = access_tdosa,
3900       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3901     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3902     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3903       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3904       .access = PL1_RW, .accessfn = access_tdosa,
3905       .type = ARM_CP_NOP },
3906     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3907      * implement vector catch debug events yet.
3908      */
3909     { .name = "DBGVCR",
3910       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3911       .access = PL1_RW, .accessfn = access_tda,
3912       .type = ARM_CP_NOP },
3913     REGINFO_SENTINEL
3914 };
3915
3916 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3917     /* 64 bit access versions of the (dummy) debug registers */
3918     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3919       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3920     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3921       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3922     REGINFO_SENTINEL
3923 };
3924
3925 void hw_watchpoint_update(ARMCPU *cpu, int n)
3926 {
3927     CPUARMState *env = &cpu->env;
3928     vaddr len = 0;
3929     vaddr wvr = env->cp15.dbgwvr[n];
3930     uint64_t wcr = env->cp15.dbgwcr[n];
3931     int mask;
3932     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3933
3934     if (env->cpu_watchpoint[n]) {
3935         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3936         env->cpu_watchpoint[n] = NULL;
3937     }
3938
3939     if (!extract64(wcr, 0, 1)) {
3940         /* E bit clear : watchpoint disabled */
3941         return;
3942     }
3943
3944     switch (extract64(wcr, 3, 2)) {
3945     case 0:
3946         /* LSC 00 is reserved and must behave as if the wp is disabled */
3947         return;
3948     case 1:
3949         flags |= BP_MEM_READ;
3950         break;
3951     case 2:
3952         flags |= BP_MEM_WRITE;
3953         break;
3954     case 3:
3955         flags |= BP_MEM_ACCESS;
3956         break;
3957     }
3958
3959     /* Attempts to use both MASK and BAS fields simultaneously are
3960      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3961      * thus generating a watchpoint for every byte in the masked region.
3962      */
3963     mask = extract64(wcr, 24, 4);
3964     if (mask == 1 || mask == 2) {
3965         /* Reserved values of MASK; we must act as if the mask value was
3966          * some non-reserved value, or as if the watchpoint were disabled.
3967          * We choose the latter.
3968          */
3969         return;
3970     } else if (mask) {
3971         /* Watchpoint covers an aligned area up to 2GB in size */
3972         len = 1ULL << mask;
3973         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3974          * whether the watchpoint fires when the unmasked bits match; we opt
3975          * to generate the exceptions.
3976          */
3977         wvr &= ~(len - 1);
3978     } else {
3979         /* Watchpoint covers bytes defined by the byte address select bits */
3980         int bas = extract64(wcr, 5, 8);
3981         int basstart;
3982
3983         if (bas == 0) {
3984             /* This must act as if the watchpoint is disabled */
3985             return;
3986         }
3987
3988         if (extract64(wvr, 2, 1)) {
3989             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3990              * ignored, and BAS[3:0] define which bytes to watch.
3991              */
3992             bas &= 0xf;
3993         }
3994         /* The BAS bits are supposed to be programmed to indicate a contiguous
3995          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3996          * we fire for each byte in the word/doubleword addressed by the WVR.
3997          * We choose to ignore any non-zero bits after the first range of 1s.
3998          */
3999         basstart = ctz32(bas);
4000         len = cto32(bas >> basstart);
4001         wvr += basstart;
4002     }
4003
4004     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
4005                           &env->cpu_watchpoint[n]);
4006 }
4007
4008 void hw_watchpoint_update_all(ARMCPU *cpu)
4009 {
4010     int i;
4011     CPUARMState *env = &cpu->env;
4012
4013     /* Completely clear out existing QEMU watchpoints and our array, to
4014      * avoid possible stale entries following migration load.
4015      */
4016     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4017     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4018
4019     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4020         hw_watchpoint_update(cpu, i);
4021     }
4022 }
4023
4024 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4025                          uint64_t value)
4026 {
4027     ARMCPU *cpu = arm_env_get_cpu(env);
4028     int i = ri->crm;
4029
4030     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4031      * register reads and behaves as if values written are sign extended.
4032      * Bits [1:0] are RES0.
4033      */
4034     value = sextract64(value, 0, 49) & ~3ULL;
4035
4036     raw_write(env, ri, value);
4037     hw_watchpoint_update(cpu, i);
4038 }
4039
4040 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4041                          uint64_t value)
4042 {
4043     ARMCPU *cpu = arm_env_get_cpu(env);
4044     int i = ri->crm;
4045
4046     raw_write(env, ri, value);
4047     hw_watchpoint_update(cpu, i);
4048 }
4049
4050 void hw_breakpoint_update(ARMCPU *cpu, int n)
4051 {
4052     CPUARMState *env = &cpu->env;
4053     uint64_t bvr = env->cp15.dbgbvr[n];
4054     uint64_t bcr = env->cp15.dbgbcr[n];
4055     vaddr addr;
4056     int bt;
4057     int flags = BP_CPU;
4058
4059     if (env->cpu_breakpoint[n]) {
4060         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4061         env->cpu_breakpoint[n] = NULL;
4062     }
4063
4064     if (!extract64(bcr, 0, 1)) {
4065         /* E bit clear : watchpoint disabled */
4066         return;
4067     }
4068
4069     bt = extract64(bcr, 20, 4);
4070
4071     switch (bt) {
4072     case 4: /* unlinked address mismatch (reserved if AArch64) */
4073     case 5: /* linked address mismatch (reserved if AArch64) */
4074         qemu_log_mask(LOG_UNIMP,
4075                       "arm: address mismatch breakpoint types not implemented");
4076         return;
4077     case 0: /* unlinked address match */
4078     case 1: /* linked address match */
4079     {
4080         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4081          * we behave as if the register was sign extended. Bits [1:0] are
4082          * RES0. The BAS field is used to allow setting breakpoints on 16
4083          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4084          * a bp will fire if the addresses covered by the bp and the addresses
4085          * covered by the insn overlap but the insn doesn't start at the
4086          * start of the bp address range. We choose to require the insn and
4087          * the bp to have the same address. The constraints on writing to
4088          * BAS enforced in dbgbcr_write mean we have only four cases:
4089          *  0b0000  => no breakpoint
4090          *  0b0011  => breakpoint on addr
4091          *  0b1100  => breakpoint on addr + 2
4092          *  0b1111  => breakpoint on addr
4093          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4094          */
4095         int bas = extract64(bcr, 5, 4);
4096         addr = sextract64(bvr, 0, 49) & ~3ULL;
4097         if (bas == 0) {
4098             return;
4099         }
4100         if (bas == 0xc) {
4101             addr += 2;
4102         }
4103         break;
4104     }
4105     case 2: /* unlinked context ID match */
4106     case 8: /* unlinked VMID match (reserved if no EL2) */
4107     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4108         qemu_log_mask(LOG_UNIMP,
4109                       "arm: unlinked context breakpoint types not implemented");
4110         return;
4111     case 9: /* linked VMID match (reserved if no EL2) */
4112     case 11: /* linked context ID and VMID match (reserved if no EL2) */
4113     case 3: /* linked context ID match */
4114     default:
4115         /* We must generate no events for Linked context matches (unless
4116          * they are linked to by some other bp/wp, which is handled in
4117          * updates for the linking bp/wp). We choose to also generate no events
4118          * for reserved values.
4119          */
4120         return;
4121     }
4122
4123     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4124 }
4125
4126 void hw_breakpoint_update_all(ARMCPU *cpu)
4127 {
4128     int i;
4129     CPUARMState *env = &cpu->env;
4130
4131     /* Completely clear out existing QEMU breakpoints and our array, to
4132      * avoid possible stale entries following migration load.
4133      */
4134     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4135     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4136
4137     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4138         hw_breakpoint_update(cpu, i);
4139     }
4140 }
4141
4142 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4143                          uint64_t value)
4144 {
4145     ARMCPU *cpu = arm_env_get_cpu(env);
4146     int i = ri->crm;
4147
4148     raw_write(env, ri, value);
4149     hw_breakpoint_update(cpu, i);
4150 }
4151
4152 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4153                          uint64_t value)
4154 {
4155     ARMCPU *cpu = arm_env_get_cpu(env);
4156     int i = ri->crm;
4157
4158     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4159      * copy of BAS[0].
4160      */
4161     value = deposit64(value, 6, 1, extract64(value, 5, 1));
4162     value = deposit64(value, 8, 1, extract64(value, 7, 1));
4163
4164     raw_write(env, ri, value);
4165     hw_breakpoint_update(cpu, i);
4166 }
4167
4168 static void define_debug_regs(ARMCPU *cpu)
4169 {
4170     /* Define v7 and v8 architectural debug registers.
4171      * These are just dummy implementations for now.
4172      */
4173     int i;
4174     int wrps, brps, ctx_cmps;
4175     ARMCPRegInfo dbgdidr = {
4176         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4177         .access = PL0_R, .accessfn = access_tda,
4178         .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4179     };
4180
4181     /* Note that all these register fields hold "number of Xs minus 1". */
4182     brps = extract32(cpu->dbgdidr, 24, 4);
4183     wrps = extract32(cpu->dbgdidr, 28, 4);
4184     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4185
4186     assert(ctx_cmps <= brps);
4187
4188     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4189      * of the debug registers such as number of breakpoints;
4190      * check that if they both exist then they agree.
4191      */
4192     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4193         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4194         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4195         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4196     }
4197
4198     define_one_arm_cp_reg(cpu, &dbgdidr);
4199     define_arm_cp_regs(cpu, debug_cp_reginfo);
4200
4201     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4202         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4203     }
4204
4205     for (i = 0; i < brps + 1; i++) {
4206         ARMCPRegInfo dbgregs[] = {
4207             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4208               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4209               .access = PL1_RW, .accessfn = access_tda,
4210               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4211               .writefn = dbgbvr_write, .raw_writefn = raw_write
4212             },
4213             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4214               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4215               .access = PL1_RW, .accessfn = access_tda,
4216               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4217               .writefn = dbgbcr_write, .raw_writefn = raw_write
4218             },
4219             REGINFO_SENTINEL
4220         };
4221         define_arm_cp_regs(cpu, dbgregs);
4222     }
4223
4224     for (i = 0; i < wrps + 1; i++) {
4225         ARMCPRegInfo dbgregs[] = {
4226             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4227               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4228               .access = PL1_RW, .accessfn = access_tda,
4229               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4230               .writefn = dbgwvr_write, .raw_writefn = raw_write
4231             },
4232             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4233               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4234               .access = PL1_RW, .accessfn = access_tda,
4235               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4236               .writefn = dbgwcr_write, .raw_writefn = raw_write
4237             },
4238             REGINFO_SENTINEL
4239         };
4240         define_arm_cp_regs(cpu, dbgregs);
4241     }
4242 }
4243
4244 void register_cp_regs_for_features(ARMCPU *cpu)
4245 {
4246     /* Register all the coprocessor registers based on feature bits */
4247     CPUARMState *env = &cpu->env;
4248     if (arm_feature(env, ARM_FEATURE_M)) {
4249         /* M profile has no coprocessor registers */
4250         return;
4251     }
4252
4253     define_arm_cp_regs(cpu, cp_reginfo);
4254     if (!arm_feature(env, ARM_FEATURE_V8)) {
4255         /* Must go early as it is full of wildcards that may be
4256          * overridden by later definitions.
4257          */
4258         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4259     }
4260
4261     if (arm_feature(env, ARM_FEATURE_V6)) {
4262         /* The ID registers all have impdef reset values */
4263         ARMCPRegInfo v6_idregs[] = {
4264             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4265               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4266               .access = PL1_R, .type = ARM_CP_CONST,
4267               .resetvalue = cpu->id_pfr0 },
4268             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4269               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4270               .access = PL1_R, .type = ARM_CP_CONST,
4271               .resetvalue = cpu->id_pfr1 },
4272             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4273               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4274               .access = PL1_R, .type = ARM_CP_CONST,
4275               .resetvalue = cpu->id_dfr0 },
4276             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4277               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4278               .access = PL1_R, .type = ARM_CP_CONST,
4279               .resetvalue = cpu->id_afr0 },
4280             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4281               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4282               .access = PL1_R, .type = ARM_CP_CONST,
4283               .resetvalue = cpu->id_mmfr0 },
4284             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4285               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4286               .access = PL1_R, .type = ARM_CP_CONST,
4287               .resetvalue = cpu->id_mmfr1 },
4288             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4289               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4290               .access = PL1_R, .type = ARM_CP_CONST,
4291               .resetvalue = cpu->id_mmfr2 },
4292             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4293               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4294               .access = PL1_R, .type = ARM_CP_CONST,
4295               .resetvalue = cpu->id_mmfr3 },
4296             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4297               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4298               .access = PL1_R, .type = ARM_CP_CONST,
4299               .resetvalue = cpu->id_isar0 },
4300             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4301               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4302               .access = PL1_R, .type = ARM_CP_CONST,
4303               .resetvalue = cpu->id_isar1 },
4304             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4305               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4306               .access = PL1_R, .type = ARM_CP_CONST,
4307               .resetvalue = cpu->id_isar2 },
4308             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4309               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4310               .access = PL1_R, .type = ARM_CP_CONST,
4311               .resetvalue = cpu->id_isar3 },
4312             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4313               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4314               .access = PL1_R, .type = ARM_CP_CONST,
4315               .resetvalue = cpu->id_isar4 },
4316             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4317               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4318               .access = PL1_R, .type = ARM_CP_CONST,
4319               .resetvalue = cpu->id_isar5 },
4320             { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4321               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4322               .access = PL1_R, .type = ARM_CP_CONST,
4323               .resetvalue = cpu->id_mmfr4 },
4324             /* 7 is as yet unallocated and must RAZ */
4325             { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
4326               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4327               .access = PL1_R, .type = ARM_CP_CONST,
4328               .resetvalue = 0 },
4329             REGINFO_SENTINEL
4330         };
4331         define_arm_cp_regs(cpu, v6_idregs);
4332         define_arm_cp_regs(cpu, v6_cp_reginfo);
4333     } else {
4334         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4335     }
4336     if (arm_feature(env, ARM_FEATURE_V6K)) {
4337         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4338     }
4339     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4340         !arm_feature(env, ARM_FEATURE_MPU)) {
4341         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4342     }
4343     if (arm_feature(env, ARM_FEATURE_V7)) {
4344         /* v7 performance monitor control register: same implementor
4345          * field as main ID register, and we implement only the cycle
4346          * count register.
4347          */
4348 #ifndef CONFIG_USER_ONLY
4349         ARMCPRegInfo pmcr = {
4350             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4351             .access = PL0_RW,
4352             .type = ARM_CP_IO | ARM_CP_ALIAS,
4353             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4354             .accessfn = pmreg_access, .writefn = pmcr_write,
4355             .raw_writefn = raw_write,
4356         };
4357         ARMCPRegInfo pmcr64 = {
4358             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4359             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4360             .access = PL0_RW, .accessfn = pmreg_access,
4361             .type = ARM_CP_IO,
4362             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4363             .resetvalue = cpu->midr & 0xff000000,
4364             .writefn = pmcr_write, .raw_writefn = raw_write,
4365         };
4366         define_one_arm_cp_reg(cpu, &pmcr);
4367         define_one_arm_cp_reg(cpu, &pmcr64);
4368 #endif
4369         ARMCPRegInfo clidr = {
4370             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4371             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4372             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4373         };
4374         define_one_arm_cp_reg(cpu, &clidr);
4375         define_arm_cp_regs(cpu, v7_cp_reginfo);
4376         define_debug_regs(cpu);
4377     } else {
4378         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4379     }
4380     if (arm_feature(env, ARM_FEATURE_V8)) {
4381         /* AArch64 ID registers, which all have impdef reset values.
4382          * Note that within the ID register ranges the unused slots
4383          * must all RAZ, not UNDEF; future architecture versions may
4384          * define new registers here.
4385          */
4386         ARMCPRegInfo v8_idregs[] = {
4387             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4388               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4389               .access = PL1_R, .type = ARM_CP_CONST,
4390               .resetvalue = cpu->id_aa64pfr0 },
4391             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4392               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4393               .access = PL1_R, .type = ARM_CP_CONST,
4394               .resetvalue = cpu->id_aa64pfr1},
4395             { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4396               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
4397               .access = PL1_R, .type = ARM_CP_CONST,
4398               .resetvalue = 0 },
4399             { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4400               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
4401               .access = PL1_R, .type = ARM_CP_CONST,
4402               .resetvalue = 0 },
4403             { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4404               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
4405               .access = PL1_R, .type = ARM_CP_CONST,
4406               .resetvalue = 0 },
4407             { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4408               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
4409               .access = PL1_R, .type = ARM_CP_CONST,
4410               .resetvalue = 0 },
4411             { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4412               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
4413               .access = PL1_R, .type = ARM_CP_CONST,
4414               .resetvalue = 0 },
4415             { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4416               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
4417               .access = PL1_R, .type = ARM_CP_CONST,
4418               .resetvalue = 0 },
4419             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4420               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4421               .access = PL1_R, .type = ARM_CP_CONST,
4422               /* We mask out the PMUVer field, because we don't currently
4423                * implement the PMU. Not advertising it prevents the guest
4424                * from trying to use it and getting UNDEFs on registers we
4425                * don't implement.
4426                */
4427               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4428             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4429               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4430               .access = PL1_R, .type = ARM_CP_CONST,
4431               .resetvalue = cpu->id_aa64dfr1 },
4432             { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4433               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
4434               .access = PL1_R, .type = ARM_CP_CONST,
4435               .resetvalue = 0 },
4436             { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4437               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
4438               .access = PL1_R, .type = ARM_CP_CONST,
4439               .resetvalue = 0 },
4440             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4441               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4442               .access = PL1_R, .type = ARM_CP_CONST,
4443               .resetvalue = cpu->id_aa64afr0 },
4444             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4445               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4446               .access = PL1_R, .type = ARM_CP_CONST,
4447               .resetvalue = cpu->id_aa64afr1 },
4448             { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4449               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
4450               .access = PL1_R, .type = ARM_CP_CONST,
4451               .resetvalue = 0 },
4452             { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4453               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
4454               .access = PL1_R, .type = ARM_CP_CONST,
4455               .resetvalue = 0 },
4456             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4457               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4458               .access = PL1_R, .type = ARM_CP_CONST,
4459               .resetvalue = cpu->id_aa64isar0 },
4460             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4461               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4462               .access = PL1_R, .type = ARM_CP_CONST,
4463               .resetvalue = cpu->id_aa64isar1 },
4464             { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4465               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
4466               .access = PL1_R, .type = ARM_CP_CONST,
4467               .resetvalue = 0 },
4468             { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4469               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
4470               .access = PL1_R, .type = ARM_CP_CONST,
4471               .resetvalue = 0 },
4472             { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4473               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
4474               .access = PL1_R, .type = ARM_CP_CONST,
4475               .resetvalue = 0 },
4476             { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4477               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
4478               .access = PL1_R, .type = ARM_CP_CONST,
4479               .resetvalue = 0 },
4480             { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4481               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
4482               .access = PL1_R, .type = ARM_CP_CONST,
4483               .resetvalue = 0 },
4484             { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4485               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
4486               .access = PL1_R, .type = ARM_CP_CONST,
4487               .resetvalue = 0 },
4488             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4489               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4490               .access = PL1_R, .type = ARM_CP_CONST,
4491               .resetvalue = cpu->id_aa64mmfr0 },
4492             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4493               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4494               .access = PL1_R, .type = ARM_CP_CONST,
4495               .resetvalue = cpu->id_aa64mmfr1 },
4496             { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4497               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
4498               .access = PL1_R, .type = ARM_CP_CONST,
4499               .resetvalue = 0 },
4500             { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4501               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
4502               .access = PL1_R, .type = ARM_CP_CONST,
4503               .resetvalue = 0 },
4504             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4505               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
4506               .access = PL1_R, .type = ARM_CP_CONST,
4507               .resetvalue = 0 },
4508             { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4509               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
4510               .access = PL1_R, .type = ARM_CP_CONST,
4511               .resetvalue = 0 },
4512             { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4513               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
4514               .access = PL1_R, .type = ARM_CP_CONST,
4515               .resetvalue = 0 },
4516             { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4517               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
4518               .access = PL1_R, .type = ARM_CP_CONST,
4519               .resetvalue = 0 },
4520             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4521               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4522               .access = PL1_R, .type = ARM_CP_CONST,
4523               .resetvalue = cpu->mvfr0 },
4524             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4525               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4526               .access = PL1_R, .type = ARM_CP_CONST,
4527               .resetvalue = cpu->mvfr1 },
4528             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4529               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4530               .access = PL1_R, .type = ARM_CP_CONST,
4531               .resetvalue = cpu->mvfr2 },
4532             { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4533               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
4534               .access = PL1_R, .type = ARM_CP_CONST,
4535               .resetvalue = 0 },
4536             { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4537               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
4538               .access = PL1_R, .type = ARM_CP_CONST,
4539               .resetvalue = 0 },
4540             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4541               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
4542               .access = PL1_R, .type = ARM_CP_CONST,
4543               .resetvalue = 0 },
4544             { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4545               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
4546               .access = PL1_R, .type = ARM_CP_CONST,
4547               .resetvalue = 0 },
4548             { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4549               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
4550               .access = PL1_R, .type = ARM_CP_CONST,
4551               .resetvalue = 0 },
4552             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
4553               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
4554               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4555               .resetvalue = cpu->pmceid0 },
4556             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
4557               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
4558               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4559               .resetvalue = cpu->pmceid0 },
4560             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
4561               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
4562               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4563               .resetvalue = cpu->pmceid1 },
4564             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
4565               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
4566               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4567               .resetvalue = cpu->pmceid1 },
4568             REGINFO_SENTINEL
4569         };
4570         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4571         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4572             !arm_feature(env, ARM_FEATURE_EL2)) {
4573             ARMCPRegInfo rvbar = {
4574                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4575                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4576                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4577             };
4578             define_one_arm_cp_reg(cpu, &rvbar);
4579         }
4580         define_arm_cp_regs(cpu, v8_idregs);
4581         define_arm_cp_regs(cpu, v8_cp_reginfo);
4582     }
4583     if (arm_feature(env, ARM_FEATURE_EL2)) {
4584         uint64_t vmpidr_def = mpidr_read_val(env);
4585         ARMCPRegInfo vpidr_regs[] = {
4586             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4587               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4588               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4589               .resetvalue = cpu->midr,
4590               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4591             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4592               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4593               .access = PL2_RW, .resetvalue = cpu->midr,
4594               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4595             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4596               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4597               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4598               .resetvalue = vmpidr_def,
4599               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4600             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4601               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4602               .access = PL2_RW,
4603               .resetvalue = vmpidr_def,
4604               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4605             REGINFO_SENTINEL
4606         };
4607         define_arm_cp_regs(cpu, vpidr_regs);
4608         define_arm_cp_regs(cpu, el2_cp_reginfo);
4609         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4610         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4611             ARMCPRegInfo rvbar = {
4612                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4613                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4614                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4615             };
4616             define_one_arm_cp_reg(cpu, &rvbar);
4617         }
4618     } else {
4619         /* If EL2 is missing but higher ELs are enabled, we need to
4620          * register the no_el2 reginfos.
4621          */
4622         if (arm_feature(env, ARM_FEATURE_EL3)) {
4623             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4624              * of MIDR_EL1 and MPIDR_EL1.
4625              */
4626             ARMCPRegInfo vpidr_regs[] = {
4627                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4628                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4629                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4630                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4631                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4632                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4633                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4634                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4635                   .type = ARM_CP_NO_RAW,
4636                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4637                 REGINFO_SENTINEL
4638             };
4639             define_arm_cp_regs(cpu, vpidr_regs);
4640             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4641         }
4642     }
4643     if (arm_feature(env, ARM_FEATURE_EL3)) {
4644         define_arm_cp_regs(cpu, el3_cp_reginfo);
4645         ARMCPRegInfo el3_regs[] = {
4646             { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4647               .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4648               .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
4649             { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
4650               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
4651               .access = PL3_RW,
4652               .raw_writefn = raw_write, .writefn = sctlr_write,
4653               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
4654               .resetvalue = cpu->reset_sctlr },
4655             REGINFO_SENTINEL
4656         };
4657
4658         define_arm_cp_regs(cpu, el3_regs);
4659     }
4660     /* The behaviour of NSACR is sufficiently various that we don't
4661      * try to describe it in a single reginfo:
4662      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
4663      *     reads as constant 0xc00 from NS EL1 and NS EL2
4664      *  if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4665      *  if v7 without EL3, register doesn't exist
4666      *  if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4667      */
4668     if (arm_feature(env, ARM_FEATURE_EL3)) {
4669         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4670             ARMCPRegInfo nsacr = {
4671                 .name = "NSACR", .type = ARM_CP_CONST,
4672                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4673                 .access = PL1_RW, .accessfn = nsacr_access,
4674                 .resetvalue = 0xc00
4675             };
4676             define_one_arm_cp_reg(cpu, &nsacr);
4677         } else {
4678             ARMCPRegInfo nsacr = {
4679                 .name = "NSACR",
4680                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4681                 .access = PL3_RW | PL1_R,
4682                 .resetvalue = 0,
4683                 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4684             };
4685             define_one_arm_cp_reg(cpu, &nsacr);
4686         }
4687     } else {
4688         if (arm_feature(env, ARM_FEATURE_V8)) {
4689             ARMCPRegInfo nsacr = {
4690                 .name = "NSACR", .type = ARM_CP_CONST,
4691                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4692                 .access = PL1_R,
4693                 .resetvalue = 0xc00
4694             };
4695             define_one_arm_cp_reg(cpu, &nsacr);
4696         }
4697     }
4698
4699     if (arm_feature(env, ARM_FEATURE_MPU)) {
4700         if (arm_feature(env, ARM_FEATURE_V6)) {
4701             /* PMSAv6 not implemented */
4702             assert(arm_feature(env, ARM_FEATURE_V7));
4703             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4704             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4705         } else {
4706             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4707         }
4708     } else {
4709         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4710         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4711     }
4712     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4713         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4714     }
4715     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4716         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4717     }
4718     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4719         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4720     }
4721     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4722         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4723     }
4724     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4725         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4726     }
4727     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4728         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4729     }
4730     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4731         define_arm_cp_regs(cpu, omap_cp_reginfo);
4732     }
4733     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4734         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4735     }
4736     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4737         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4738     }
4739     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4740         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4741     }
4742     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4743         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4744     }
4745     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4746      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4747      * be read-only (ie write causes UNDEF exception).
4748      */
4749     {
4750         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4751             /* Pre-v8 MIDR space.
4752              * Note that the MIDR isn't a simple constant register because
4753              * of the TI925 behaviour where writes to another register can
4754              * cause the MIDR value to change.
4755              *
4756              * Unimplemented registers in the c15 0 0 0 space default to
4757              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4758              * and friends override accordingly.
4759              */
4760             { .name = "MIDR",
4761               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4762               .access = PL1_R, .resetvalue = cpu->midr,
4763               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4764               .readfn = midr_read,
4765               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4766               .type = ARM_CP_OVERRIDE },
4767             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4768             { .name = "DUMMY",
4769               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4770               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4771             { .name = "DUMMY",
4772               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4773               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4774             { .name = "DUMMY",
4775               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4776               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4777             { .name = "DUMMY",
4778               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4779               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4780             { .name = "DUMMY",
4781               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4782               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4783             REGINFO_SENTINEL
4784         };
4785         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4786             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4787               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4788               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4789               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4790               .readfn = midr_read },
4791             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4792             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4793               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4794               .access = PL1_R, .resetvalue = cpu->midr },
4795             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4796               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4797               .access = PL1_R, .resetvalue = cpu->midr },
4798             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4799               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4800               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4801             REGINFO_SENTINEL
4802         };
4803         ARMCPRegInfo id_cp_reginfo[] = {
4804             /* These are common to v8 and pre-v8 */
4805             { .name = "CTR",
4806               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4807               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4808             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4809               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4810               .access = PL0_R, .accessfn = ctr_el0_access,
4811               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4812             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4813             { .name = "TCMTR",
4814               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4815               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4816             REGINFO_SENTINEL
4817         };
4818         /* TLBTR is specific to VMSA */
4819         ARMCPRegInfo id_tlbtr_reginfo = {
4820               .name = "TLBTR",
4821               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4822               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4823         };
4824         /* MPUIR is specific to PMSA V6+ */
4825         ARMCPRegInfo id_mpuir_reginfo = {
4826               .name = "MPUIR",
4827               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4828               .access = PL1_R, .type = ARM_CP_CONST,
4829               .resetvalue = cpu->pmsav7_dregion << 8
4830         };
4831         ARMCPRegInfo crn0_wi_reginfo = {
4832             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4833             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4834             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4835         };
4836         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4837             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4838             ARMCPRegInfo *r;
4839             /* Register the blanket "writes ignored" value first to cover the
4840              * whole space. Then update the specific ID registers to allow write
4841              * access, so that they ignore writes rather than causing them to
4842              * UNDEF.
4843              */
4844             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4845             for (r = id_pre_v8_midr_cp_reginfo;
4846                  r->type != ARM_CP_SENTINEL; r++) {
4847                 r->access = PL1_RW;
4848             }
4849             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4850                 r->access = PL1_RW;
4851             }
4852             id_tlbtr_reginfo.access = PL1_RW;
4853             id_tlbtr_reginfo.access = PL1_RW;
4854         }
4855         if (arm_feature(env, ARM_FEATURE_V8)) {
4856             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4857         } else {
4858             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4859         }
4860         define_arm_cp_regs(cpu, id_cp_reginfo);
4861         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4862             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4863         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4864             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4865         }
4866     }
4867
4868     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4869         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4870     }
4871
4872     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4873         ARMCPRegInfo auxcr_reginfo[] = {
4874             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4875               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4876               .access = PL1_RW, .type = ARM_CP_CONST,
4877               .resetvalue = cpu->reset_auxcr },
4878             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4879               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4880               .access = PL2_RW, .type = ARM_CP_CONST,
4881               .resetvalue = 0 },
4882             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4883               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4884               .access = PL3_RW, .type = ARM_CP_CONST,
4885               .resetvalue = 0 },
4886             REGINFO_SENTINEL
4887         };
4888         define_arm_cp_regs(cpu, auxcr_reginfo);
4889     }
4890
4891     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4892         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4893             /* 32 bit view is [31:18] 0...0 [43:32]. */
4894             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4895                 | extract64(cpu->reset_cbar, 32, 12);
4896             ARMCPRegInfo cbar_reginfo[] = {
4897                 { .name = "CBAR",
4898                   .type = ARM_CP_CONST,
4899                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4900                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4901                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4902                   .type = ARM_CP_CONST,
4903                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4904                   .access = PL1_R, .resetvalue = cbar32 },
4905                 REGINFO_SENTINEL
4906             };
4907             /* We don't implement a r/w 64 bit CBAR currently */
4908             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4909             define_arm_cp_regs(cpu, cbar_reginfo);
4910         } else {
4911             ARMCPRegInfo cbar = {
4912                 .name = "CBAR",
4913                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4914                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4915                 .fieldoffset = offsetof(CPUARMState,
4916                                         cp15.c15_config_base_address)
4917             };
4918             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4919                 cbar.access = PL1_R;
4920                 cbar.fieldoffset = 0;
4921                 cbar.type = ARM_CP_CONST;
4922             }
4923             define_one_arm_cp_reg(cpu, &cbar);
4924         }
4925     }
4926
4927     /* Generic registers whose values depend on the implementation */
4928     {
4929         ARMCPRegInfo sctlr = {
4930             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4931             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4932             .access = PL1_RW,
4933             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4934                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4935             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4936             .raw_writefn = raw_write,
4937         };
4938         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4939             /* Normally we would always end the TB on an SCTLR write, but Linux
4940              * arch/arm/mach-pxa/sleep.S expects two instructions following
4941              * an MMU enable to execute from cache.  Imitate this behaviour.
4942              */
4943             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4944         }
4945         define_one_arm_cp_reg(cpu, &sctlr);
4946     }
4947 }
4948
4949 ARMCPU *cpu_arm_init(const char *cpu_model)
4950 {
4951     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4952 }
4953
4954 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4955 {
4956     CPUState *cs = CPU(cpu);
4957     CPUARMState *env = &cpu->env;
4958
4959     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4960         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4961                                  aarch64_fpu_gdb_set_reg,
4962                                  34, "aarch64-fpu.xml", 0);
4963     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4964         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4965                                  51, "arm-neon.xml", 0);
4966     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4967         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4968                                  35, "arm-vfp3.xml", 0);
4969     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4970         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4971                                  19, "arm-vfp.xml", 0);
4972     }
4973 }
4974
4975 /* Sort alphabetically by type name, except for "any". */
4976 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4977 {
4978     ObjectClass *class_a = (ObjectClass *)a;
4979     ObjectClass *class_b = (ObjectClass *)b;
4980     const char *name_a, *name_b;
4981
4982     name_a = object_class_get_name(class_a);
4983     name_b = object_class_get_name(class_b);
4984     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4985         return 1;
4986     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4987         return -1;
4988     } else {
4989         return strcmp(name_a, name_b);
4990     }
4991 }
4992
4993 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4994 {
4995     ObjectClass *oc = data;
4996     CPUListState *s = user_data;
4997     const char *typename;
4998     char *name;
4999
5000     typename = object_class_get_name(oc);
5001     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
5002     (*s->cpu_fprintf)(s->file, "  %s\n",
5003                       name);
5004     g_free(name);
5005 }
5006
5007 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5008 {
5009     CPUListState s = {
5010         .file = f,
5011         .cpu_fprintf = cpu_fprintf,
5012     };
5013     GSList *list;
5014
5015     list = object_class_get_list(TYPE_ARM_CPU, false);
5016     list = g_slist_sort(list, arm_cpu_list_compare);
5017     (*cpu_fprintf)(f, "Available CPUs:\n");
5018     g_slist_foreach(list, arm_cpu_list_entry, &s);
5019     g_slist_free(list);
5020 #ifdef CONFIG_KVM
5021     /* The 'host' CPU type is dynamically registered only if KVM is
5022      * enabled, so we have to special-case it here:
5023      */
5024     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
5025 #endif
5026 }
5027
5028 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5029 {
5030     ObjectClass *oc = data;
5031     CpuDefinitionInfoList **cpu_list = user_data;
5032     CpuDefinitionInfoList *entry;
5033     CpuDefinitionInfo *info;
5034     const char *typename;
5035
5036     typename = object_class_get_name(oc);
5037     info = g_malloc0(sizeof(*info));
5038     info->name = g_strndup(typename,
5039                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
5040
5041     entry = g_malloc0(sizeof(*entry));
5042     entry->value = info;
5043     entry->next = *cpu_list;
5044     *cpu_list = entry;
5045 }
5046
5047 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5048 {
5049     CpuDefinitionInfoList *cpu_list = NULL;
5050     GSList *list;
5051
5052     list = object_class_get_list(TYPE_ARM_CPU, false);
5053     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5054     g_slist_free(list);
5055
5056     return cpu_list;
5057 }
5058
5059 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5060                                    void *opaque, int state, int secstate,
5061                                    int crm, int opc1, int opc2)
5062 {
5063     /* Private utility function for define_one_arm_cp_reg_with_opaque():
5064      * add a single reginfo struct to the hash table.
5065      */
5066     uint32_t *key = g_new(uint32_t, 1);
5067     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5068     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5069     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5070
5071     /* Reset the secure state to the specific incoming state.  This is
5072      * necessary as the register may have been defined with both states.
5073      */
5074     r2->secure = secstate;
5075
5076     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5077         /* Register is banked (using both entries in array).
5078          * Overwriting fieldoffset as the array is only used to define
5079          * banked registers but later only fieldoffset is used.
5080          */
5081         r2->fieldoffset = r->bank_fieldoffsets[ns];
5082     }
5083
5084     if (state == ARM_CP_STATE_AA32) {
5085         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5086             /* If the register is banked then we don't need to migrate or
5087              * reset the 32-bit instance in certain cases:
5088              *
5089              * 1) If the register has both 32-bit and 64-bit instances then we
5090              *    can count on the 64-bit instance taking care of the
5091              *    non-secure bank.
5092              * 2) If ARMv8 is enabled then we can count on a 64-bit version
5093              *    taking care of the secure bank.  This requires that separate
5094              *    32 and 64-bit definitions are provided.
5095              */
5096             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5097                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5098                 r2->type |= ARM_CP_ALIAS;
5099             }
5100         } else if ((secstate != r->secure) && !ns) {
5101             /* The register is not banked so we only want to allow migration of
5102              * the non-secure instance.
5103              */
5104             r2->type |= ARM_CP_ALIAS;
5105         }
5106
5107         if (r->state == ARM_CP_STATE_BOTH) {
5108             /* We assume it is a cp15 register if the .cp field is left unset.
5109              */
5110             if (r2->cp == 0) {
5111                 r2->cp = 15;
5112             }
5113
5114 #ifdef HOST_WORDS_BIGENDIAN
5115             if (r2->fieldoffset) {
5116                 r2->fieldoffset += sizeof(uint32_t);
5117             }
5118 #endif
5119         }
5120     }
5121     if (state == ARM_CP_STATE_AA64) {
5122         /* To allow abbreviation of ARMCPRegInfo
5123          * definitions, we treat cp == 0 as equivalent to
5124          * the value for "standard guest-visible sysreg".
5125          * STATE_BOTH definitions are also always "standard
5126          * sysreg" in their AArch64 view (the .cp value may
5127          * be non-zero for the benefit of the AArch32 view).
5128          */
5129         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5130             r2->cp = CP_REG_ARM64_SYSREG_CP;
5131         }
5132         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5133                                   r2->opc0, opc1, opc2);
5134     } else {
5135         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5136     }
5137     if (opaque) {
5138         r2->opaque = opaque;
5139     }
5140     /* reginfo passed to helpers is correct for the actual access,
5141      * and is never ARM_CP_STATE_BOTH:
5142      */
5143     r2->state = state;
5144     /* Make sure reginfo passed to helpers for wildcarded regs
5145      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5146      */
5147     r2->crm = crm;
5148     r2->opc1 = opc1;
5149     r2->opc2 = opc2;
5150     /* By convention, for wildcarded registers only the first
5151      * entry is used for migration; the others are marked as
5152      * ALIAS so we don't try to transfer the register
5153      * multiple times. Special registers (ie NOP/WFI) are
5154      * never migratable and not even raw-accessible.
5155      */
5156     if ((r->type & ARM_CP_SPECIAL)) {
5157         r2->type |= ARM_CP_NO_RAW;
5158     }
5159     if (((r->crm == CP_ANY) && crm != 0) ||
5160         ((r->opc1 == CP_ANY) && opc1 != 0) ||
5161         ((r->opc2 == CP_ANY) && opc2 != 0)) {
5162         r2->type |= ARM_CP_ALIAS;
5163     }
5164
5165     /* Check that raw accesses are either forbidden or handled. Note that
5166      * we can't assert this earlier because the setup of fieldoffset for
5167      * banked registers has to be done first.
5168      */
5169     if (!(r2->type & ARM_CP_NO_RAW)) {
5170         assert(!raw_accessors_invalid(r2));
5171     }
5172
5173     /* Overriding of an existing definition must be explicitly
5174      * requested.
5175      */
5176     if (!(r->type & ARM_CP_OVERRIDE)) {
5177         ARMCPRegInfo *oldreg;
5178         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5179         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5180             fprintf(stderr, "Register redefined: cp=%d %d bit "
5181                     "crn=%d crm=%d opc1=%d opc2=%d, "
5182                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5183                     r2->crn, r2->crm, r2->opc1, r2->opc2,
5184                     oldreg->name, r2->name);
5185             g_assert_not_reached();
5186         }
5187     }
5188     g_hash_table_insert(cpu->cp_regs, key, r2);
5189 }
5190
5191
5192 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5193                                        const ARMCPRegInfo *r, void *opaque)
5194 {
5195     /* Define implementations of coprocessor registers.
5196      * We store these in a hashtable because typically
5197      * there are less than 150 registers in a space which
5198      * is 16*16*16*8*8 = 262144 in size.
5199      * Wildcarding is supported for the crm, opc1 and opc2 fields.
5200      * If a register is defined twice then the second definition is
5201      * used, so this can be used to define some generic registers and
5202      * then override them with implementation specific variations.
5203      * At least one of the original and the second definition should
5204      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5205      * against accidental use.
5206      *
5207      * The state field defines whether the register is to be
5208      * visible in the AArch32 or AArch64 execution state. If the
5209      * state is set to ARM_CP_STATE_BOTH then we synthesise a
5210      * reginfo structure for the AArch32 view, which sees the lower
5211      * 32 bits of the 64 bit register.
5212      *
5213      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5214      * be wildcarded. AArch64 registers are always considered to be 64
5215      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5216      * the register, if any.
5217      */
5218     int crm, opc1, opc2, state;
5219     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5220     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5221     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5222     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5223     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5224     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5225     /* 64 bit registers have only CRm and Opc1 fields */
5226     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5227     /* op0 only exists in the AArch64 encodings */
5228     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5229     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5230     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5231     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5232      * encodes a minimum access level for the register. We roll this
5233      * runtime check into our general permission check code, so check
5234      * here that the reginfo's specified permissions are strict enough
5235      * to encompass the generic architectural permission check.
5236      */
5237     if (r->state != ARM_CP_STATE_AA32) {
5238         int mask = 0;
5239         switch (r->opc1) {
5240         case 0: case 1: case 2:
5241             /* min_EL EL1 */
5242             mask = PL1_RW;
5243             break;
5244         case 3:
5245             /* min_EL EL0 */
5246             mask = PL0_RW;
5247             break;
5248         case 4:
5249             /* min_EL EL2 */
5250             mask = PL2_RW;
5251             break;
5252         case 5:
5253             /* unallocated encoding, so not possible */
5254             assert(false);
5255             break;
5256         case 6:
5257             /* min_EL EL3 */
5258             mask = PL3_RW;
5259             break;
5260         case 7:
5261             /* min_EL EL1, secure mode only (we don't check the latter) */
5262             mask = PL1_RW;
5263             break;
5264         default:
5265             /* broken reginfo with out-of-range opc1 */
5266             assert(false);
5267             break;
5268         }
5269         /* assert our permissions are not too lax (stricter is fine) */
5270         assert((r->access & ~mask) == 0);
5271     }
5272
5273     /* Check that the register definition has enough info to handle
5274      * reads and writes if they are permitted.
5275      */
5276     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5277         if (r->access & PL3_R) {
5278             assert((r->fieldoffset ||
5279                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5280                    r->readfn);
5281         }
5282         if (r->access & PL3_W) {
5283             assert((r->fieldoffset ||
5284                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5285                    r->writefn);
5286         }
5287     }
5288     /* Bad type field probably means missing sentinel at end of reg list */
5289     assert(cptype_valid(r->type));
5290     for (crm = crmmin; crm <= crmmax; crm++) {
5291         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5292             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5293                 for (state = ARM_CP_STATE_AA32;
5294                      state <= ARM_CP_STATE_AA64; state++) {
5295                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5296                         continue;
5297                     }
5298                     if (state == ARM_CP_STATE_AA32) {
5299                         /* Under AArch32 CP registers can be common
5300                          * (same for secure and non-secure world) or banked.
5301                          */
5302                         switch (r->secure) {
5303                         case ARM_CP_SECSTATE_S:
5304                         case ARM_CP_SECSTATE_NS:
5305                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5306                                                    r->secure, crm, opc1, opc2);
5307                             break;
5308                         default:
5309                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5310                                                    ARM_CP_SECSTATE_S,
5311                                                    crm, opc1, opc2);
5312                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5313                                                    ARM_CP_SECSTATE_NS,
5314                                                    crm, opc1, opc2);
5315                             break;
5316                         }
5317                     } else {
5318                         /* AArch64 registers get mapped to non-secure instance
5319                          * of AArch32 */
5320                         add_cpreg_to_hashtable(cpu, r, opaque, state,
5321                                                ARM_CP_SECSTATE_NS,
5322                                                crm, opc1, opc2);
5323                     }
5324                 }
5325             }
5326         }
5327     }
5328 }
5329
5330 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5331                                     const ARMCPRegInfo *regs, void *opaque)
5332 {
5333     /* Define a whole list of registers */
5334     const ARMCPRegInfo *r;
5335     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5336         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5337     }
5338 }
5339
5340 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5341 {
5342     return g_hash_table_lookup(cpregs, &encoded_cp);
5343 }
5344
5345 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5346                          uint64_t value)
5347 {
5348     /* Helper coprocessor write function for write-ignore registers */
5349 }
5350
5351 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5352 {
5353     /* Helper coprocessor write function for read-as-zero registers */
5354     return 0;
5355 }
5356
5357 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5358 {
5359     /* Helper coprocessor reset function for do-nothing-on-reset registers */
5360 }
5361
5362 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
5363 {
5364     /* Return true if it is not valid for us to switch to
5365      * this CPU mode (ie all the UNPREDICTABLE cases in
5366      * the ARM ARM CPSRWriteByInstr pseudocode).
5367      */
5368
5369     /* Changes to or from Hyp via MSR and CPS are illegal. */
5370     if (write_type == CPSRWriteByInstr &&
5371         ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
5372          mode == ARM_CPU_MODE_HYP)) {
5373         return 1;
5374     }
5375
5376     switch (mode) {
5377     case ARM_CPU_MODE_USR:
5378         return 0;
5379     case ARM_CPU_MODE_SYS:
5380     case ARM_CPU_MODE_SVC:
5381     case ARM_CPU_MODE_ABT:
5382     case ARM_CPU_MODE_UND:
5383     case ARM_CPU_MODE_IRQ:
5384     case ARM_CPU_MODE_FIQ:
5385         /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5386          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5387          */
5388         /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5389          * and CPS are treated as illegal mode changes.
5390          */
5391         if (write_type == CPSRWriteByInstr &&
5392             (env->cp15.hcr_el2 & HCR_TGE) &&
5393             (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
5394             !arm_is_secure_below_el3(env)) {
5395             return 1;
5396         }
5397         return 0;
5398     case ARM_CPU_MODE_HYP:
5399         return !arm_feature(env, ARM_FEATURE_EL2)
5400             || arm_current_el(env) < 2 || arm_is_secure(env);
5401     case ARM_CPU_MODE_MON:
5402         return arm_current_el(env) < 3;
5403     default:
5404         return 1;
5405     }
5406 }
5407
5408 uint32_t cpsr_read(CPUARMState *env)
5409 {
5410     int ZF;
5411     ZF = (env->ZF == 0);
5412     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5413         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5414         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5415         | ((env->condexec_bits & 0xfc) << 8)
5416         | (env->GE << 16) | (env->daif & CPSR_AIF);
5417 }
5418
5419 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
5420                 CPSRWriteType write_type)
5421 {
5422     uint32_t changed_daif;
5423
5424     if (mask & CPSR_NZCV) {
5425         env->ZF = (~val) & CPSR_Z;
5426         env->NF = val;
5427         env->CF = (val >> 29) & 1;
5428         env->VF = (val << 3) & 0x80000000;
5429     }
5430     if (mask & CPSR_Q)
5431         env->QF = ((val & CPSR_Q) != 0);
5432     if (mask & CPSR_T)
5433         env->thumb = ((val & CPSR_T) != 0);
5434     if (mask & CPSR_IT_0_1) {
5435         env->condexec_bits &= ~3;
5436         env->condexec_bits |= (val >> 25) & 3;
5437     }
5438     if (mask & CPSR_IT_2_7) {
5439         env->condexec_bits &= 3;
5440         env->condexec_bits |= (val >> 8) & 0xfc;
5441     }
5442     if (mask & CPSR_GE) {
5443         env->GE = (val >> 16) & 0xf;
5444     }
5445
5446     /* In a V7 implementation that includes the security extensions but does
5447      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5448      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5449      * bits respectively.
5450      *
5451      * In a V8 implementation, it is permitted for privileged software to
5452      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5453      */
5454     if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
5455         arm_feature(env, ARM_FEATURE_EL3) &&
5456         !arm_feature(env, ARM_FEATURE_EL2) &&
5457         !arm_is_secure(env)) {
5458
5459         changed_daif = (env->daif ^ val) & mask;
5460
5461         if (changed_daif & CPSR_A) {
5462             /* Check to see if we are allowed to change the masking of async
5463              * abort exceptions from a non-secure state.
5464              */
5465             if (!(env->cp15.scr_el3 & SCR_AW)) {
5466                 qemu_log_mask(LOG_GUEST_ERROR,
5467                               "Ignoring attempt to switch CPSR_A flag from "
5468                               "non-secure world with SCR.AW bit clear\n");
5469                 mask &= ~CPSR_A;
5470             }
5471         }
5472
5473         if (changed_daif & CPSR_F) {
5474             /* Check to see if we are allowed to change the masking of FIQ
5475              * exceptions from a non-secure state.
5476              */
5477             if (!(env->cp15.scr_el3 & SCR_FW)) {
5478                 qemu_log_mask(LOG_GUEST_ERROR,
5479                               "Ignoring attempt to switch CPSR_F flag from "
5480                               "non-secure world with SCR.FW bit clear\n");
5481                 mask &= ~CPSR_F;
5482             }
5483
5484             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5485              * If this bit is set software is not allowed to mask
5486              * FIQs, but is allowed to set CPSR_F to 0.
5487              */
5488             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5489                 (val & CPSR_F)) {
5490                 qemu_log_mask(LOG_GUEST_ERROR,
5491                               "Ignoring attempt to enable CPSR_F flag "
5492                               "(non-maskable FIQ [NMFI] support enabled)\n");
5493                 mask &= ~CPSR_F;
5494             }
5495         }
5496     }
5497
5498     env->daif &= ~(CPSR_AIF & mask);
5499     env->daif |= val & CPSR_AIF & mask;
5500
5501     if (write_type != CPSRWriteRaw &&
5502         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
5503         if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
5504             /* Note that we can only get here in USR mode if this is a
5505              * gdb stub write; for this case we follow the architectural
5506              * behaviour for guest writes in USR mode of ignoring an attempt
5507              * to switch mode. (Those are caught by translate.c for writes
5508              * triggered by guest instructions.)
5509              */
5510             mask &= ~CPSR_M;
5511         } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
5512             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5513              * v7, and has defined behaviour in v8:
5514              *  + leave CPSR.M untouched
5515              *  + allow changes to the other CPSR fields
5516              *  + set PSTATE.IL
5517              * For user changes via the GDB stub, we don't set PSTATE.IL,
5518              * as this would be unnecessarily harsh for a user error.
5519              */
5520             mask &= ~CPSR_M;
5521             if (write_type != CPSRWriteByGDBStub &&
5522                 arm_feature(env, ARM_FEATURE_V8)) {
5523                 mask |= CPSR_IL;
5524                 val |= CPSR_IL;
5525             }
5526         } else {
5527             switch_mode(env, val & CPSR_M);
5528         }
5529     }
5530     mask &= ~CACHED_CPSR_BITS;
5531     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5532 }
5533
5534 /* Sign/zero extend */
5535 uint32_t HELPER(sxtb16)(uint32_t x)
5536 {
5537     uint32_t res;
5538     res = (uint16_t)(int8_t)x;
5539     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5540     return res;
5541 }
5542
5543 uint32_t HELPER(uxtb16)(uint32_t x)
5544 {
5545     uint32_t res;
5546     res = (uint16_t)(uint8_t)x;
5547     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5548     return res;
5549 }
5550
5551 uint32_t HELPER(clz)(uint32_t x)
5552 {
5553     return clz32(x);
5554 }
5555
5556 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5557 {
5558     if (den == 0)
5559       return 0;
5560     if (num == INT_MIN && den == -1)
5561       return INT_MIN;
5562     return num / den;
5563 }
5564
5565 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5566 {
5567     if (den == 0)
5568       return 0;
5569     return num / den;
5570 }
5571
5572 uint32_t HELPER(rbit)(uint32_t x)
5573 {
5574     return revbit32(x);
5575 }
5576
5577 #if defined(CONFIG_USER_ONLY)
5578
5579 /* These should probably raise undefined insn exceptions.  */
5580 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5581 {
5582     ARMCPU *cpu = arm_env_get_cpu(env);
5583
5584     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5585 }
5586
5587 uint32_t QEMU_NORETURN HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5588 {
5589     ARMCPU *cpu = arm_env_get_cpu(env);
5590
5591     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5592 }
5593
5594 void switch_mode(CPUARMState *env, int mode)
5595 {
5596     ARMCPU *cpu = arm_env_get_cpu(env);
5597
5598     if (mode != ARM_CPU_MODE_USR) {
5599         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5600     }
5601 }
5602
5603 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5604                                  uint32_t cur_el, bool secure)
5605 {
5606     return 1;
5607 }
5608
5609 void aarch64_sync_64_to_32(CPUARMState *env)
5610 {
5611     g_assert_not_reached();
5612 }
5613
5614 #else
5615
5616 void switch_mode(CPUARMState *env, int mode)
5617 {
5618     int old_mode;
5619     int i;
5620
5621     old_mode = env->uncached_cpsr & CPSR_M;
5622     if (mode == old_mode)
5623         return;
5624
5625     if (old_mode == ARM_CPU_MODE_FIQ) {
5626         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5627         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5628     } else if (mode == ARM_CPU_MODE_FIQ) {
5629         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5630         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5631     }
5632
5633     i = bank_number(old_mode);
5634     env->banked_r13[i] = env->regs[13];
5635     env->banked_r14[i] = env->regs[14];
5636     env->banked_spsr[i] = env->spsr;
5637
5638     i = bank_number(mode);
5639     env->regs[13] = env->banked_r13[i];
5640     env->regs[14] = env->banked_r14[i];
5641     env->spsr = env->banked_spsr[i];
5642 }
5643
5644 /* Physical Interrupt Target EL Lookup Table
5645  *
5646  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5647  *
5648  * The below multi-dimensional table is used for looking up the target
5649  * exception level given numerous condition criteria.  Specifically, the
5650  * target EL is based on SCR and HCR routing controls as well as the
5651  * currently executing EL and secure state.
5652  *
5653  *    Dimensions:
5654  *    target_el_table[2][2][2][2][2][4]
5655  *                    |  |  |  |  |  +--- Current EL
5656  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5657  *                    |  |  |  +--------- HCR mask override
5658  *                    |  |  +------------ SCR exec state control
5659  *                    |  +--------------- SCR mask override
5660  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5661  *
5662  *    The table values are as such:
5663  *    0-3 = EL0-EL3
5664  *     -1 = Cannot occur
5665  *
5666  * The ARM ARM target EL table includes entries indicating that an "exception
5667  * is not taken".  The two cases where this is applicable are:
5668  *    1) An exception is taken from EL3 but the SCR does not have the exception
5669  *    routed to EL3.
5670  *    2) An exception is taken from EL2 but the HCR does not have the exception
5671  *    routed to EL2.
5672  * In these two cases, the below table contain a target of EL1.  This value is
5673  * returned as it is expected that the consumer of the table data will check
5674  * for "target EL >= current EL" to ensure the exception is not taken.
5675  *
5676  *            SCR     HCR
5677  *         64  EA     AMO                 From
5678  *        BIT IRQ     IMO      Non-secure         Secure
5679  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5680  */
5681 static const int8_t target_el_table[2][2][2][2][2][4] = {
5682     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5683        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5684       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5685        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5686      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5687        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5688       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5689        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5690     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5691        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5692       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5693        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5694      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5695        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5696       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5697        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5698 };
5699
5700 /*
5701  * Determine the target EL for physical exceptions
5702  */
5703 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5704                                  uint32_t cur_el, bool secure)
5705 {
5706     CPUARMState *env = cs->env_ptr;
5707     int rw;
5708     int scr;
5709     int hcr;
5710     int target_el;
5711     /* Is the highest EL AArch64? */
5712     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5713
5714     if (arm_feature(env, ARM_FEATURE_EL3)) {
5715         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5716     } else {
5717         /* Either EL2 is the highest EL (and so the EL2 register width
5718          * is given by is64); or there is no EL2 or EL3, in which case
5719          * the value of 'rw' does not affect the table lookup anyway.
5720          */
5721         rw = is64;
5722     }
5723
5724     switch (excp_idx) {
5725     case EXCP_IRQ:
5726         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5727         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5728         break;
5729     case EXCP_FIQ:
5730         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5731         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5732         break;
5733     default:
5734         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5735         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5736         break;
5737     };
5738
5739     /* If HCR.TGE is set then HCR is treated as being 1 */
5740     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5741
5742     /* Perform a table-lookup for the target EL given the current state */
5743     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5744
5745     assert(target_el > 0);
5746
5747     return target_el;
5748 }
5749
5750 static void v7m_push(CPUARMState *env, uint32_t val)
5751 {
5752     CPUState *cs = CPU(arm_env_get_cpu(env));
5753
5754     env->regs[13] -= 4;
5755     stl_phys(cs->as, env->regs[13], val);
5756 }
5757
5758 static uint32_t v7m_pop(CPUARMState *env)
5759 {
5760     CPUState *cs = CPU(arm_env_get_cpu(env));
5761     uint32_t val;
5762
5763     val = ldl_phys(cs->as, env->regs[13]);
5764     env->regs[13] += 4;
5765     return val;
5766 }
5767
5768 /* Switch to V7M main or process stack pointer.  */
5769 static void switch_v7m_sp(CPUARMState *env, int process)
5770 {
5771     uint32_t tmp;
5772     if (env->v7m.current_sp != process) {
5773         tmp = env->v7m.other_sp;
5774         env->v7m.other_sp = env->regs[13];
5775         env->regs[13] = tmp;
5776         env->v7m.current_sp = process;
5777     }
5778 }
5779
5780 static void do_v7m_exception_exit(CPUARMState *env)
5781 {
5782     uint32_t type;
5783     uint32_t xpsr;
5784
5785     type = env->regs[15];
5786     if (env->v7m.exception != 0)
5787         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5788
5789     /* Switch to the target stack.  */
5790     switch_v7m_sp(env, (type & 4) != 0);
5791     /* Pop registers.  */
5792     env->regs[0] = v7m_pop(env);
5793     env->regs[1] = v7m_pop(env);
5794     env->regs[2] = v7m_pop(env);
5795     env->regs[3] = v7m_pop(env);
5796     env->regs[12] = v7m_pop(env);
5797     env->regs[14] = v7m_pop(env);
5798     env->regs[15] = v7m_pop(env);
5799     if (env->regs[15] & 1) {
5800         qemu_log_mask(LOG_GUEST_ERROR,
5801                       "M profile return from interrupt with misaligned "
5802                       "PC is UNPREDICTABLE\n");
5803         /* Actual hardware seems to ignore the lsbit, and there are several
5804          * RTOSes out there which incorrectly assume the r15 in the stack
5805          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5806          */
5807         env->regs[15] &= ~1U;
5808     }
5809     xpsr = v7m_pop(env);
5810     xpsr_write(env, xpsr, 0xfffffdff);
5811     /* Undo stack alignment.  */
5812     if (xpsr & 0x200)
5813         env->regs[13] |= 4;
5814     /* ??? The exception return type specifies Thread/Handler mode.  However
5815        this is also implied by the xPSR value. Not sure what to do
5816        if there is a mismatch.  */
5817     /* ??? Likewise for mismatches between the CONTROL register and the stack
5818        pointer.  */
5819 }
5820
5821 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5822 {
5823     ARMCPU *cpu = ARM_CPU(cs);
5824     CPUARMState *env = &cpu->env;
5825     uint32_t xpsr = xpsr_read(env);
5826     uint32_t lr;
5827     uint32_t addr;
5828
5829     arm_log_exception(cs->exception_index);
5830
5831     lr = 0xfffffff1;
5832     if (env->v7m.current_sp)
5833         lr |= 4;
5834     if (env->v7m.exception == 0)
5835         lr |= 8;
5836
5837     /* For exceptions we just mark as pending on the NVIC, and let that
5838        handle it.  */
5839     /* TODO: Need to escalate if the current priority is higher than the
5840        one we're raising.  */
5841     switch (cs->exception_index) {
5842     case EXCP_UDEF:
5843         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5844         return;
5845     case EXCP_SWI:
5846         /* The PC already points to the next instruction.  */
5847         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5848         return;
5849     case EXCP_PREFETCH_ABORT:
5850     case EXCP_DATA_ABORT:
5851         /* TODO: if we implemented the MPU registers, this is where we
5852          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5853          */
5854         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5855         return;
5856     case EXCP_BKPT:
5857         if (semihosting_enabled()) {
5858             int nr;
5859             nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
5860             if (nr == 0xab) {
5861                 env->regs[15] += 2;
5862                 qemu_log_mask(CPU_LOG_INT,
5863                               "...handling as semihosting call 0x%x\n",
5864                               env->regs[0]);
5865                 env->regs[0] = do_arm_semihosting(env);
5866                 return;
5867             }
5868         }
5869         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5870         return;
5871     case EXCP_IRQ:
5872         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5873         break;
5874     case EXCP_EXCEPTION_EXIT:
5875         do_v7m_exception_exit(env);
5876         return;
5877     default:
5878         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5879         return; /* Never happens.  Keep compiler happy.  */
5880     }
5881
5882     /* Align stack pointer.  */
5883     /* ??? Should only do this if Configuration Control Register
5884        STACKALIGN bit is set.  */
5885     if (env->regs[13] & 4) {
5886         env->regs[13] -= 4;
5887         xpsr |= 0x200;
5888     }
5889     /* Switch to the handler mode.  */
5890     v7m_push(env, xpsr);
5891     v7m_push(env, env->regs[15]);
5892     v7m_push(env, env->regs[14]);
5893     v7m_push(env, env->regs[12]);
5894     v7m_push(env, env->regs[3]);
5895     v7m_push(env, env->regs[2]);
5896     v7m_push(env, env->regs[1]);
5897     v7m_push(env, env->regs[0]);
5898     switch_v7m_sp(env, 0);
5899     /* Clear IT bits */
5900     env->condexec_bits = 0;
5901     env->regs[14] = lr;
5902     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5903     env->regs[15] = addr & 0xfffffffe;
5904     env->thumb = addr & 1;
5905 }
5906
5907 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5908  * register set.  This is necessary when switching between AArch32 and AArch64
5909  * execution state.
5910  */
5911 void aarch64_sync_32_to_64(CPUARMState *env)
5912 {
5913     int i;
5914     uint32_t mode = env->uncached_cpsr & CPSR_M;
5915
5916     /* We can blanket copy R[0:7] to X[0:7] */
5917     for (i = 0; i < 8; i++) {
5918         env->xregs[i] = env->regs[i];
5919     }
5920
5921     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5922      * Otherwise, they come from the banked user regs.
5923      */
5924     if (mode == ARM_CPU_MODE_FIQ) {
5925         for (i = 8; i < 13; i++) {
5926             env->xregs[i] = env->usr_regs[i - 8];
5927         }
5928     } else {
5929         for (i = 8; i < 13; i++) {
5930             env->xregs[i] = env->regs[i];
5931         }
5932     }
5933
5934     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5935      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5936      * from the mode banked register.
5937      */
5938     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5939         env->xregs[13] = env->regs[13];
5940         env->xregs[14] = env->regs[14];
5941     } else {
5942         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5943         /* HYP is an exception in that it is copied from r14 */
5944         if (mode == ARM_CPU_MODE_HYP) {
5945             env->xregs[14] = env->regs[14];
5946         } else {
5947             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5948         }
5949     }
5950
5951     if (mode == ARM_CPU_MODE_HYP) {
5952         env->xregs[15] = env->regs[13];
5953     } else {
5954         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5955     }
5956
5957     if (mode == ARM_CPU_MODE_IRQ) {
5958         env->xregs[16] = env->regs[14];
5959         env->xregs[17] = env->regs[13];
5960     } else {
5961         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5962         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5963     }
5964
5965     if (mode == ARM_CPU_MODE_SVC) {
5966         env->xregs[18] = env->regs[14];
5967         env->xregs[19] = env->regs[13];
5968     } else {
5969         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5970         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5971     }
5972
5973     if (mode == ARM_CPU_MODE_ABT) {
5974         env->xregs[20] = env->regs[14];
5975         env->xregs[21] = env->regs[13];
5976     } else {
5977         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5978         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5979     }
5980
5981     if (mode == ARM_CPU_MODE_UND) {
5982         env->xregs[22] = env->regs[14];
5983         env->xregs[23] = env->regs[13];
5984     } else {
5985         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5986         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5987     }
5988
5989     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5990      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5991      * FIQ bank for r8-r14.
5992      */
5993     if (mode == ARM_CPU_MODE_FIQ) {
5994         for (i = 24; i < 31; i++) {
5995             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5996         }
5997     } else {
5998         for (i = 24; i < 29; i++) {
5999             env->xregs[i] = env->fiq_regs[i - 24];
6000         }
6001         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
6002         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
6003     }
6004
6005     env->pc = env->regs[15];
6006 }
6007
6008 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6009  * register set.  This is necessary when switching between AArch32 and AArch64
6010  * execution state.
6011  */
6012 void aarch64_sync_64_to_32(CPUARMState *env)
6013 {
6014     int i;
6015     uint32_t mode = env->uncached_cpsr & CPSR_M;
6016
6017     /* We can blanket copy X[0:7] to R[0:7] */
6018     for (i = 0; i < 8; i++) {
6019         env->regs[i] = env->xregs[i];
6020     }
6021
6022     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6023      * Otherwise, we copy x8-x12 into the banked user regs.
6024      */
6025     if (mode == ARM_CPU_MODE_FIQ) {
6026         for (i = 8; i < 13; i++) {
6027             env->usr_regs[i - 8] = env->xregs[i];
6028         }
6029     } else {
6030         for (i = 8; i < 13; i++) {
6031             env->regs[i] = env->xregs[i];
6032         }
6033     }
6034
6035     /* Registers r13 & r14 depend on the current mode.
6036      * If we are in a given mode, we copy the corresponding x registers to r13
6037      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
6038      * for the mode.
6039      */
6040     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6041         env->regs[13] = env->xregs[13];
6042         env->regs[14] = env->xregs[14];
6043     } else {
6044         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
6045
6046         /* HYP is an exception in that it does not have its own banked r14 but
6047          * shares the USR r14
6048          */
6049         if (mode == ARM_CPU_MODE_HYP) {
6050             env->regs[14] = env->xregs[14];
6051         } else {
6052             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
6053         }
6054     }
6055
6056     if (mode == ARM_CPU_MODE_HYP) {
6057         env->regs[13] = env->xregs[15];
6058     } else {
6059         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
6060     }
6061
6062     if (mode == ARM_CPU_MODE_IRQ) {
6063         env->regs[14] = env->xregs[16];
6064         env->regs[13] = env->xregs[17];
6065     } else {
6066         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
6067         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
6068     }
6069
6070     if (mode == ARM_CPU_MODE_SVC) {
6071         env->regs[14] = env->xregs[18];
6072         env->regs[13] = env->xregs[19];
6073     } else {
6074         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
6075         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
6076     }
6077
6078     if (mode == ARM_CPU_MODE_ABT) {
6079         env->regs[14] = env->xregs[20];
6080         env->regs[13] = env->xregs[21];
6081     } else {
6082         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
6083         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
6084     }
6085
6086     if (mode == ARM_CPU_MODE_UND) {
6087         env->regs[14] = env->xregs[22];
6088         env->regs[13] = env->xregs[23];
6089     } else {
6090         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
6091         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
6092     }
6093
6094     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
6095      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
6096      * FIQ bank for r8-r14.
6097      */
6098     if (mode == ARM_CPU_MODE_FIQ) {
6099         for (i = 24; i < 31; i++) {
6100             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
6101         }
6102     } else {
6103         for (i = 24; i < 29; i++) {
6104             env->fiq_regs[i - 24] = env->xregs[i];
6105         }
6106         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
6107         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
6108     }
6109
6110     env->regs[15] = env->pc;
6111 }
6112
6113 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
6114 {
6115     ARMCPU *cpu = ARM_CPU(cs);
6116     CPUARMState *env = &cpu->env;
6117     uint32_t addr;
6118     uint32_t mask;
6119     int new_mode;
6120     uint32_t offset;
6121     uint32_t moe;
6122
6123     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6124     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
6125     case EC_BREAKPOINT:
6126     case EC_BREAKPOINT_SAME_EL:
6127         moe = 1;
6128         break;
6129     case EC_WATCHPOINT:
6130     case EC_WATCHPOINT_SAME_EL:
6131         moe = 10;
6132         break;
6133     case EC_AA32_BKPT:
6134         moe = 3;
6135         break;
6136     case EC_VECTORCATCH:
6137         moe = 5;
6138         break;
6139     default:
6140         moe = 0;
6141         break;
6142     }
6143
6144     if (moe) {
6145         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
6146     }
6147
6148     /* TODO: Vectored interrupt controller.  */
6149     switch (cs->exception_index) {
6150     case EXCP_UDEF:
6151         new_mode = ARM_CPU_MODE_UND;
6152         addr = 0x04;
6153         mask = CPSR_I;
6154         if (env->thumb)
6155             offset = 2;
6156         else
6157             offset = 4;
6158         break;
6159     case EXCP_SWI:
6160         new_mode = ARM_CPU_MODE_SVC;
6161         addr = 0x08;
6162         mask = CPSR_I;
6163         /* The PC already points to the next instruction.  */
6164         offset = 0;
6165         break;
6166     case EXCP_BKPT:
6167         env->exception.fsr = 2;
6168         /* Fall through to prefetch abort.  */
6169     case EXCP_PREFETCH_ABORT:
6170         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
6171         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
6172         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
6173                       env->exception.fsr, (uint32_t)env->exception.vaddress);
6174         new_mode = ARM_CPU_MODE_ABT;
6175         addr = 0x0c;
6176         mask = CPSR_A | CPSR_I;
6177         offset = 4;
6178         break;
6179     case EXCP_DATA_ABORT:
6180         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
6181         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
6182         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
6183                       env->exception.fsr,
6184                       (uint32_t)env->exception.vaddress);
6185         new_mode = ARM_CPU_MODE_ABT;
6186         addr = 0x10;
6187         mask = CPSR_A | CPSR_I;
6188         offset = 8;
6189         break;
6190     case EXCP_IRQ:
6191         new_mode = ARM_CPU_MODE_IRQ;
6192         addr = 0x18;
6193         /* Disable IRQ and imprecise data aborts.  */
6194         mask = CPSR_A | CPSR_I;
6195         offset = 4;
6196         if (env->cp15.scr_el3 & SCR_IRQ) {
6197             /* IRQ routed to monitor mode */
6198             new_mode = ARM_CPU_MODE_MON;
6199             mask |= CPSR_F;
6200         }
6201         break;
6202     case EXCP_FIQ:
6203         new_mode = ARM_CPU_MODE_FIQ;
6204         addr = 0x1c;
6205         /* Disable FIQ, IRQ and imprecise data aborts.  */
6206         mask = CPSR_A | CPSR_I | CPSR_F;
6207         if (env->cp15.scr_el3 & SCR_FIQ) {
6208             /* FIQ routed to monitor mode */
6209             new_mode = ARM_CPU_MODE_MON;
6210         }
6211         offset = 4;
6212         break;
6213     case EXCP_SMC:
6214         new_mode = ARM_CPU_MODE_MON;
6215         addr = 0x08;
6216         mask = CPSR_A | CPSR_I | CPSR_F;
6217         offset = 0;
6218         break;
6219     default:
6220         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6221         return; /* Never happens.  Keep compiler happy.  */
6222     }
6223
6224     if (new_mode == ARM_CPU_MODE_MON) {
6225         addr += env->cp15.mvbar;
6226     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
6227         /* High vectors. When enabled, base address cannot be remapped. */
6228         addr += 0xffff0000;
6229     } else {
6230         /* ARM v7 architectures provide a vector base address register to remap
6231          * the interrupt vector table.
6232          * This register is only followed in non-monitor mode, and is banked.
6233          * Note: only bits 31:5 are valid.
6234          */
6235         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
6236     }
6237
6238     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
6239         env->cp15.scr_el3 &= ~SCR_NS;
6240     }
6241
6242     switch_mode (env, new_mode);
6243     /* For exceptions taken to AArch32 we must clear the SS bit in both
6244      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6245      */
6246     env->uncached_cpsr &= ~PSTATE_SS;
6247     env->spsr = cpsr_read(env);
6248     /* Clear IT bits.  */
6249     env->condexec_bits = 0;
6250     /* Switch to the new mode, and to the correct instruction set.  */
6251     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
6252     /* Set new mode endianness */
6253     env->uncached_cpsr &= ~CPSR_E;
6254     if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
6255         env->uncached_cpsr |= ~CPSR_E;
6256     }
6257     env->daif |= mask;
6258     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6259      * and we should just guard the thumb mode on V4 */
6260     if (arm_feature(env, ARM_FEATURE_V4T)) {
6261         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
6262     }
6263     env->regs[14] = env->regs[15] + offset;
6264     env->regs[15] = addr;
6265 }
6266
6267 /* Handle exception entry to a target EL which is using AArch64 */
6268 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
6269 {
6270     ARMCPU *cpu = ARM_CPU(cs);
6271     CPUARMState *env = &cpu->env;
6272     unsigned int new_el = env->exception.target_el;
6273     target_ulong addr = env->cp15.vbar_el[new_el];
6274     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
6275
6276     if (arm_current_el(env) < new_el) {
6277         /* Entry vector offset depends on whether the implemented EL
6278          * immediately lower than the target level is using AArch32 or AArch64
6279          */
6280         bool is_aa64;
6281
6282         switch (new_el) {
6283         case 3:
6284             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
6285             break;
6286         case 2:
6287             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
6288             break;
6289         case 1:
6290             is_aa64 = is_a64(env);
6291             break;
6292         default:
6293             g_assert_not_reached();
6294         }
6295
6296         if (is_aa64) {
6297             addr += 0x400;
6298         } else {
6299             addr += 0x600;
6300         }
6301     } else if (pstate_read(env) & PSTATE_SP) {
6302         addr += 0x200;
6303     }
6304
6305     switch (cs->exception_index) {
6306     case EXCP_PREFETCH_ABORT:
6307     case EXCP_DATA_ABORT:
6308         env->cp15.far_el[new_el] = env->exception.vaddress;
6309         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
6310                       env->cp15.far_el[new_el]);
6311         /* fall through */
6312     case EXCP_BKPT:
6313     case EXCP_UDEF:
6314     case EXCP_SWI:
6315     case EXCP_HVC:
6316     case EXCP_HYP_TRAP:
6317     case EXCP_SMC:
6318         env->cp15.esr_el[new_el] = env->exception.syndrome;
6319         break;
6320     case EXCP_IRQ:
6321     case EXCP_VIRQ:
6322         addr += 0x80;
6323         break;
6324     case EXCP_FIQ:
6325     case EXCP_VFIQ:
6326         addr += 0x100;
6327         break;
6328     case EXCP_SEMIHOST:
6329         qemu_log_mask(CPU_LOG_INT,
6330                       "...handling as semihosting call 0x%" PRIx64 "\n",
6331                       env->xregs[0]);
6332         env->xregs[0] = do_arm_semihosting(env);
6333         return;
6334     default:
6335         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6336     }
6337
6338     if (is_a64(env)) {
6339         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
6340         aarch64_save_sp(env, arm_current_el(env));
6341         env->elr_el[new_el] = env->pc;
6342     } else {
6343         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
6344         if (!env->thumb) {
6345             env->cp15.esr_el[new_el] |= 1 << 25;
6346         }
6347         env->elr_el[new_el] = env->regs[15];
6348
6349         aarch64_sync_32_to_64(env);
6350
6351         env->condexec_bits = 0;
6352     }
6353     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
6354                   env->elr_el[new_el]);
6355
6356     pstate_write(env, PSTATE_DAIF | new_mode);
6357     env->aarch64 = 1;
6358     aarch64_restore_sp(env, new_el);
6359
6360     env->pc = addr;
6361
6362     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
6363                   new_el, env->pc, pstate_read(env));
6364 }
6365
6366 static inline bool check_for_semihosting(CPUState *cs)
6367 {
6368     /* Check whether this exception is a semihosting call; if so
6369      * then handle it and return true; otherwise return false.
6370      */
6371     ARMCPU *cpu = ARM_CPU(cs);
6372     CPUARMState *env = &cpu->env;
6373
6374     if (is_a64(env)) {
6375         if (cs->exception_index == EXCP_SEMIHOST) {
6376             /* This is always the 64-bit semihosting exception.
6377              * The "is this usermode" and "is semihosting enabled"
6378              * checks have been done at translate time.
6379              */
6380             qemu_log_mask(CPU_LOG_INT,
6381                           "...handling as semihosting call 0x%" PRIx64 "\n",
6382                           env->xregs[0]);
6383             env->xregs[0] = do_arm_semihosting(env);
6384             return true;
6385         }
6386         return false;
6387     } else {
6388         uint32_t imm;
6389
6390         /* Only intercept calls from privileged modes, to provide some
6391          * semblance of security.
6392          */
6393         if (!semihosting_enabled() ||
6394             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6395             return false;
6396         }
6397
6398         switch (cs->exception_index) {
6399         case EXCP_SWI:
6400             /* Check for semihosting interrupt.  */
6401             if (env->thumb) {
6402                 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
6403                     & 0xff;
6404                 if (imm == 0xab) {
6405                     break;
6406                 }
6407             } else {
6408                 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
6409                     & 0xffffff;
6410                 if (imm == 0x123456) {
6411                     break;
6412                 }
6413             }
6414             return false;
6415         case EXCP_BKPT:
6416             /* See if this is a semihosting syscall.  */
6417             if (env->thumb) {
6418                 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
6419                     & 0xff;
6420                 if (imm == 0xab) {
6421                     env->regs[15] += 2;
6422                     break;
6423                 }
6424             }
6425             return false;
6426         default:
6427             return false;
6428         }
6429
6430         qemu_log_mask(CPU_LOG_INT,
6431                       "...handling as semihosting call 0x%x\n",
6432                       env->regs[0]);
6433         env->regs[0] = do_arm_semihosting(env);
6434         return true;
6435     }
6436 }
6437
6438 /* Handle a CPU exception for A and R profile CPUs.
6439  * Do any appropriate logging, handle PSCI calls, and then hand off
6440  * to the AArch64-entry or AArch32-entry function depending on the
6441  * target exception level's register width.
6442  */
6443 void arm_cpu_do_interrupt(CPUState *cs)
6444 {
6445     ARMCPU *cpu = ARM_CPU(cs);
6446     CPUARMState *env = &cpu->env;
6447     unsigned int new_el = env->exception.target_el;
6448
6449     assert(!IS_M(env));
6450
6451     arm_log_exception(cs->exception_index);
6452     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6453                   new_el);
6454     if (qemu_loglevel_mask(CPU_LOG_INT)
6455         && !excp_is_internal(cs->exception_index)) {
6456         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6457                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6458                       env->exception.syndrome);
6459     }
6460
6461     if (arm_is_psci_call(cpu, cs->exception_index)) {
6462         arm_handle_psci_call(cpu);
6463         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6464         return;
6465     }
6466
6467     /* Semihosting semantics depend on the register width of the
6468      * code that caused the exception, not the target exception level,
6469      * so must be handled here.
6470      */
6471     if (check_for_semihosting(cs)) {
6472         return;
6473     }
6474
6475     assert(!excp_is_internal(cs->exception_index));
6476     if (arm_el_is_aa64(env, new_el)) {
6477         arm_cpu_do_interrupt_aarch64(cs);
6478     } else {
6479         arm_cpu_do_interrupt_aarch32(cs);
6480     }
6481
6482     if (!kvm_enabled()) {
6483         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6484     }
6485 }
6486
6487 /* Return the exception level which controls this address translation regime */
6488 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6489 {
6490     switch (mmu_idx) {
6491     case ARMMMUIdx_S2NS:
6492     case ARMMMUIdx_S1E2:
6493         return 2;
6494     case ARMMMUIdx_S1E3:
6495         return 3;
6496     case ARMMMUIdx_S1SE0:
6497         return arm_el_is_aa64(env, 3) ? 1 : 3;
6498     case ARMMMUIdx_S1SE1:
6499     case ARMMMUIdx_S1NSE0:
6500     case ARMMMUIdx_S1NSE1:
6501         return 1;
6502     default:
6503         g_assert_not_reached();
6504     }
6505 }
6506
6507 /* Return true if this address translation regime is secure */
6508 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6509 {
6510     switch (mmu_idx) {
6511     case ARMMMUIdx_S12NSE0:
6512     case ARMMMUIdx_S12NSE1:
6513     case ARMMMUIdx_S1NSE0:
6514     case ARMMMUIdx_S1NSE1:
6515     case ARMMMUIdx_S1E2:
6516     case ARMMMUIdx_S2NS:
6517         return false;
6518     case ARMMMUIdx_S1E3:
6519     case ARMMMUIdx_S1SE0:
6520     case ARMMMUIdx_S1SE1:
6521         return true;
6522     default:
6523         g_assert_not_reached();
6524     }
6525 }
6526
6527 /* Return the SCTLR value which controls this address translation regime */
6528 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6529 {
6530     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6531 }
6532
6533 /* Return true if the specified stage of address translation is disabled */
6534 static inline bool regime_translation_disabled(CPUARMState *env,
6535                                                ARMMMUIdx mmu_idx)
6536 {
6537     if (mmu_idx == ARMMMUIdx_S2NS) {
6538         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6539     }
6540     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6541 }
6542
6543 static inline bool regime_translation_big_endian(CPUARMState *env,
6544                                                  ARMMMUIdx mmu_idx)
6545 {
6546     return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
6547 }
6548
6549 /* Return the TCR controlling this translation regime */
6550 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6551 {
6552     if (mmu_idx == ARMMMUIdx_S2NS) {
6553         return &env->cp15.vtcr_el2;
6554     }
6555     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6556 }
6557
6558 /* Return the TTBR associated with this translation regime */
6559 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6560                                    int ttbrn)
6561 {
6562     if (mmu_idx == ARMMMUIdx_S2NS) {
6563         return env->cp15.vttbr_el2;
6564     }
6565     if (ttbrn == 0) {
6566         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6567     } else {
6568         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6569     }
6570 }
6571
6572 /* Return true if the translation regime is using LPAE format page tables */
6573 static inline bool regime_using_lpae_format(CPUARMState *env,
6574                                             ARMMMUIdx mmu_idx)
6575 {
6576     int el = regime_el(env, mmu_idx);
6577     if (el == 2 || arm_el_is_aa64(env, el)) {
6578         return true;
6579     }
6580     if (arm_feature(env, ARM_FEATURE_LPAE)
6581         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6582         return true;
6583     }
6584     return false;
6585 }
6586
6587 /* Returns true if the stage 1 translation regime is using LPAE format page
6588  * tables. Used when raising alignment exceptions, whose FSR changes depending
6589  * on whether the long or short descriptor format is in use. */
6590 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6591 {
6592     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6593         mmu_idx += ARMMMUIdx_S1NSE0;
6594     }
6595
6596     return regime_using_lpae_format(env, mmu_idx);
6597 }
6598
6599 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6600 {
6601     switch (mmu_idx) {
6602     case ARMMMUIdx_S1SE0:
6603     case ARMMMUIdx_S1NSE0:
6604         return true;
6605     default:
6606         return false;
6607     case ARMMMUIdx_S12NSE0:
6608     case ARMMMUIdx_S12NSE1:
6609         g_assert_not_reached();
6610     }
6611 }
6612
6613 /* Translate section/page access permissions to page
6614  * R/W protection flags
6615  *
6616  * @env:         CPUARMState
6617  * @mmu_idx:     MMU index indicating required translation regime
6618  * @ap:          The 3-bit access permissions (AP[2:0])
6619  * @domain_prot: The 2-bit domain access permissions
6620  */
6621 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6622                                 int ap, int domain_prot)
6623 {
6624     bool is_user = regime_is_user(env, mmu_idx);
6625
6626     if (domain_prot == 3) {
6627         return PAGE_READ | PAGE_WRITE;
6628     }
6629
6630     switch (ap) {
6631     case 0:
6632         if (arm_feature(env, ARM_FEATURE_V7)) {
6633             return 0;
6634         }
6635         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6636         case SCTLR_S:
6637             return is_user ? 0 : PAGE_READ;
6638         case SCTLR_R:
6639             return PAGE_READ;
6640         default:
6641             return 0;
6642         }
6643     case 1:
6644         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6645     case 2:
6646         if (is_user) {
6647             return PAGE_READ;
6648         } else {
6649             return PAGE_READ | PAGE_WRITE;
6650         }
6651     case 3:
6652         return PAGE_READ | PAGE_WRITE;
6653     case 4: /* Reserved.  */
6654         return 0;
6655     case 5:
6656         return is_user ? 0 : PAGE_READ;
6657     case 6:
6658         return PAGE_READ;
6659     case 7:
6660         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6661             return 0;
6662         }
6663         return PAGE_READ;
6664     default:
6665         g_assert_not_reached();
6666     }
6667 }
6668
6669 /* Translate section/page access permissions to page
6670  * R/W protection flags.
6671  *
6672  * @ap:      The 2-bit simple AP (AP[2:1])
6673  * @is_user: TRUE if accessing from PL0
6674  */
6675 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6676 {
6677     switch (ap) {
6678     case 0:
6679         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6680     case 1:
6681         return PAGE_READ | PAGE_WRITE;
6682     case 2:
6683         return is_user ? 0 : PAGE_READ;
6684     case 3:
6685         return PAGE_READ;
6686     default:
6687         g_assert_not_reached();
6688     }
6689 }
6690
6691 static inline int
6692 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6693 {
6694     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6695 }
6696
6697 /* Translate S2 section/page access permissions to protection flags
6698  *
6699  * @env:     CPUARMState
6700  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6701  * @xn:      XN (execute-never) bit
6702  */
6703 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6704 {
6705     int prot = 0;
6706
6707     if (s2ap & 1) {
6708         prot |= PAGE_READ;
6709     }
6710     if (s2ap & 2) {
6711         prot |= PAGE_WRITE;
6712     }
6713     if (!xn) {
6714         if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
6715             prot |= PAGE_EXEC;
6716         }
6717     }
6718     return prot;
6719 }
6720
6721 /* Translate section/page access permissions to protection flags
6722  *
6723  * @env:     CPUARMState
6724  * @mmu_idx: MMU index indicating required translation regime
6725  * @is_aa64: TRUE if AArch64
6726  * @ap:      The 2-bit simple AP (AP[2:1])
6727  * @ns:      NS (non-secure) bit
6728  * @xn:      XN (execute-never) bit
6729  * @pxn:     PXN (privileged execute-never) bit
6730  */
6731 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6732                       int ap, int ns, int xn, int pxn)
6733 {
6734     bool is_user = regime_is_user(env, mmu_idx);
6735     int prot_rw, user_rw;
6736     bool have_wxn;
6737     int wxn = 0;
6738
6739     assert(mmu_idx != ARMMMUIdx_S2NS);
6740
6741     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6742     if (is_user) {
6743         prot_rw = user_rw;
6744     } else {
6745         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6746     }
6747
6748     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6749         return prot_rw;
6750     }
6751
6752     /* TODO have_wxn should be replaced with
6753      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6754      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6755      * compatible processors have EL2, which is required for [U]WXN.
6756      */
6757     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6758
6759     if (have_wxn) {
6760         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6761     }
6762
6763     if (is_aa64) {
6764         switch (regime_el(env, mmu_idx)) {
6765         case 1:
6766             if (!is_user) {
6767                 xn = pxn || (user_rw & PAGE_WRITE);
6768             }
6769             break;
6770         case 2:
6771         case 3:
6772             break;
6773         }
6774     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6775         switch (regime_el(env, mmu_idx)) {
6776         case 1:
6777         case 3:
6778             if (is_user) {
6779                 xn = xn || !(user_rw & PAGE_READ);
6780             } else {
6781                 int uwxn = 0;
6782                 if (have_wxn) {
6783                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6784                 }
6785                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6786                      (uwxn && (user_rw & PAGE_WRITE));
6787             }
6788             break;
6789         case 2:
6790             break;
6791         }
6792     } else {
6793         xn = wxn = 0;
6794     }
6795
6796     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6797         return prot_rw;
6798     }
6799     return prot_rw | PAGE_EXEC;
6800 }
6801
6802 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6803                                      uint32_t *table, uint32_t address)
6804 {
6805     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6806     TCR *tcr = regime_tcr(env, mmu_idx);
6807
6808     if (address & tcr->mask) {
6809         if (tcr->raw_tcr & TTBCR_PD1) {
6810             /* Translation table walk disabled for TTBR1 */
6811             return false;
6812         }
6813         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6814     } else {
6815         if (tcr->raw_tcr & TTBCR_PD0) {
6816             /* Translation table walk disabled for TTBR0 */
6817             return false;
6818         }
6819         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6820     }
6821     *table |= (address >> 18) & 0x3ffc;
6822     return true;
6823 }
6824
6825 /* Translate a S1 pagetable walk through S2 if needed.  */
6826 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6827                                hwaddr addr, MemTxAttrs txattrs,
6828                                uint32_t *fsr,
6829                                ARMMMUFaultInfo *fi)
6830 {
6831     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6832         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6833         target_ulong s2size;
6834         hwaddr s2pa;
6835         int s2prot;
6836         int ret;
6837
6838         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6839                                  &txattrs, &s2prot, &s2size, fsr, fi);
6840         if (ret) {
6841             fi->s2addr = addr;
6842             fi->stage2 = true;
6843             fi->s1ptw = true;
6844             return ~0;
6845         }
6846         addr = s2pa;
6847     }
6848     return addr;
6849 }
6850
6851 /* All loads done in the course of a page table walk go through here.
6852  * TODO: rather than ignoring errors from physical memory reads (which
6853  * are external aborts in ARM terminology) we should propagate this
6854  * error out so that we can turn it into a Data Abort if this walk
6855  * was being done for a CPU load/store or an address translation instruction
6856  * (but not if it was for a debug access).
6857  */
6858 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6859                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6860                             ARMMMUFaultInfo *fi)
6861 {
6862     ARMCPU *cpu = ARM_CPU(cs);
6863     CPUARMState *env = &cpu->env;
6864     MemTxAttrs attrs = {};
6865     AddressSpace *as;
6866
6867     attrs.secure = is_secure;
6868     as = arm_addressspace(cs, attrs);
6869     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6870     if (fi->s1ptw) {
6871         return 0;
6872     }
6873     if (regime_translation_big_endian(env, mmu_idx)) {
6874         return address_space_ldl_be(as, addr, attrs, NULL);
6875     } else {
6876         return address_space_ldl_le(as, addr, attrs, NULL);
6877     }
6878 }
6879
6880 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6881                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6882                             ARMMMUFaultInfo *fi)
6883 {
6884     ARMCPU *cpu = ARM_CPU(cs);
6885     CPUARMState *env = &cpu->env;
6886     MemTxAttrs attrs = {};
6887     AddressSpace *as;
6888
6889     attrs.secure = is_secure;
6890     as = arm_addressspace(cs, attrs);
6891     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6892     if (fi->s1ptw) {
6893         return 0;
6894     }
6895     if (regime_translation_big_endian(env, mmu_idx)) {
6896         return address_space_ldq_be(as, addr, attrs, NULL);
6897     } else {
6898         return address_space_ldq_le(as, addr, attrs, NULL);
6899     }
6900 }
6901
6902 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6903                              int access_type, ARMMMUIdx mmu_idx,
6904                              hwaddr *phys_ptr, int *prot,
6905                              target_ulong *page_size, uint32_t *fsr,
6906                              ARMMMUFaultInfo *fi)
6907 {
6908     CPUState *cs = CPU(arm_env_get_cpu(env));
6909     int code;
6910     uint32_t table;
6911     uint32_t desc;
6912     int type;
6913     int ap;
6914     int domain = 0;
6915     int domain_prot;
6916     hwaddr phys_addr;
6917     uint32_t dacr;
6918
6919     /* Pagetable walk.  */
6920     /* Lookup l1 descriptor.  */
6921     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6922         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6923         code = 5;
6924         goto do_fault;
6925     }
6926     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6927                        mmu_idx, fsr, fi);
6928     type = (desc & 3);
6929     domain = (desc >> 5) & 0x0f;
6930     if (regime_el(env, mmu_idx) == 1) {
6931         dacr = env->cp15.dacr_ns;
6932     } else {
6933         dacr = env->cp15.dacr_s;
6934     }
6935     domain_prot = (dacr >> (domain * 2)) & 3;
6936     if (type == 0) {
6937         /* Section translation fault.  */
6938         code = 5;
6939         goto do_fault;
6940     }
6941     if (domain_prot == 0 || domain_prot == 2) {
6942         if (type == 2)
6943             code = 9; /* Section domain fault.  */
6944         else
6945             code = 11; /* Page domain fault.  */
6946         goto do_fault;
6947     }
6948     if (type == 2) {
6949         /* 1Mb section.  */
6950         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6951         ap = (desc >> 10) & 3;
6952         code = 13;
6953         *page_size = 1024 * 1024;
6954     } else {
6955         /* Lookup l2 entry.  */
6956         if (type == 1) {
6957             /* Coarse pagetable.  */
6958             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6959         } else {
6960             /* Fine pagetable.  */
6961             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6962         }
6963         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6964                            mmu_idx, fsr, fi);
6965         switch (desc & 3) {
6966         case 0: /* Page translation fault.  */
6967             code = 7;
6968             goto do_fault;
6969         case 1: /* 64k page.  */
6970             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6971             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6972             *page_size = 0x10000;
6973             break;
6974         case 2: /* 4k page.  */
6975             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6976             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6977             *page_size = 0x1000;
6978             break;
6979         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6980             if (type == 1) {
6981                 /* ARMv6/XScale extended small page format */
6982                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6983                     || arm_feature(env, ARM_FEATURE_V6)) {
6984                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6985                     *page_size = 0x1000;
6986                 } else {
6987                     /* UNPREDICTABLE in ARMv5; we choose to take a
6988                      * page translation fault.
6989                      */
6990                     code = 7;
6991                     goto do_fault;
6992                 }
6993             } else {
6994                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6995                 *page_size = 0x400;
6996             }
6997             ap = (desc >> 4) & 3;
6998             break;
6999         default:
7000             /* Never happens, but compiler isn't smart enough to tell.  */
7001             abort();
7002         }
7003         code = 15;
7004     }
7005     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7006     *prot |= *prot ? PAGE_EXEC : 0;
7007     if (!(*prot & (1 << access_type))) {
7008         /* Access permission fault.  */
7009         goto do_fault;
7010     }
7011     *phys_ptr = phys_addr;
7012     return false;
7013 do_fault:
7014     *fsr = code | (domain << 4);
7015     return true;
7016 }
7017
7018 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
7019                              int access_type, ARMMMUIdx mmu_idx,
7020                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7021                              target_ulong *page_size, uint32_t *fsr,
7022                              ARMMMUFaultInfo *fi)
7023 {
7024     CPUState *cs = CPU(arm_env_get_cpu(env));
7025     int code;
7026     uint32_t table;
7027     uint32_t desc;
7028     uint32_t xn;
7029     uint32_t pxn = 0;
7030     int type;
7031     int ap;
7032     int domain = 0;
7033     int domain_prot;
7034     hwaddr phys_addr;
7035     uint32_t dacr;
7036     bool ns;
7037
7038     /* Pagetable walk.  */
7039     /* Lookup l1 descriptor.  */
7040     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7041         /* Section translation fault if page walk is disabled by PD0 or PD1 */
7042         code = 5;
7043         goto do_fault;
7044     }
7045     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7046                        mmu_idx, fsr, fi);
7047     type = (desc & 3);
7048     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
7049         /* Section translation fault, or attempt to use the encoding
7050          * which is Reserved on implementations without PXN.
7051          */
7052         code = 5;
7053         goto do_fault;
7054     }
7055     if ((type == 1) || !(desc & (1 << 18))) {
7056         /* Page or Section.  */
7057         domain = (desc >> 5) & 0x0f;
7058     }
7059     if (regime_el(env, mmu_idx) == 1) {
7060         dacr = env->cp15.dacr_ns;
7061     } else {
7062         dacr = env->cp15.dacr_s;
7063     }
7064     domain_prot = (dacr >> (domain * 2)) & 3;
7065     if (domain_prot == 0 || domain_prot == 2) {
7066         if (type != 1) {
7067             code = 9; /* Section domain fault.  */
7068         } else {
7069             code = 11; /* Page domain fault.  */
7070         }
7071         goto do_fault;
7072     }
7073     if (type != 1) {
7074         if (desc & (1 << 18)) {
7075             /* Supersection.  */
7076             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
7077             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
7078             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
7079             *page_size = 0x1000000;
7080         } else {
7081             /* Section.  */
7082             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7083             *page_size = 0x100000;
7084         }
7085         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
7086         xn = desc & (1 << 4);
7087         pxn = desc & 1;
7088         code = 13;
7089         ns = extract32(desc, 19, 1);
7090     } else {
7091         if (arm_feature(env, ARM_FEATURE_PXN)) {
7092             pxn = (desc >> 2) & 1;
7093         }
7094         ns = extract32(desc, 3, 1);
7095         /* Lookup l2 entry.  */
7096         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7097         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7098                            mmu_idx, fsr, fi);
7099         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
7100         switch (desc & 3) {
7101         case 0: /* Page translation fault.  */
7102             code = 7;
7103             goto do_fault;
7104         case 1: /* 64k page.  */
7105             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7106             xn = desc & (1 << 15);
7107             *page_size = 0x10000;
7108             break;
7109         case 2: case 3: /* 4k page.  */
7110             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7111             xn = desc & 1;
7112             *page_size = 0x1000;
7113             break;
7114         default:
7115             /* Never happens, but compiler isn't smart enough to tell.  */
7116             abort();
7117         }
7118         code = 15;
7119     }
7120     if (domain_prot == 3) {
7121         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7122     } else {
7123         if (pxn && !regime_is_user(env, mmu_idx)) {
7124             xn = 1;
7125         }
7126         if (xn && access_type == 2)
7127             goto do_fault;
7128
7129         if (arm_feature(env, ARM_FEATURE_V6K) &&
7130                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
7131             /* The simplified model uses AP[0] as an access control bit.  */
7132             if ((ap & 1) == 0) {
7133                 /* Access flag fault.  */
7134                 code = (code == 15) ? 6 : 3;
7135                 goto do_fault;
7136             }
7137             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
7138         } else {
7139             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7140         }
7141         if (*prot && !xn) {
7142             *prot |= PAGE_EXEC;
7143         }
7144         if (!(*prot & (1 << access_type))) {
7145             /* Access permission fault.  */
7146             goto do_fault;
7147         }
7148     }
7149     if (ns) {
7150         /* The NS bit will (as required by the architecture) have no effect if
7151          * the CPU doesn't support TZ or this is a non-secure translation
7152          * regime, because the attribute will already be non-secure.
7153          */
7154         attrs->secure = false;
7155     }
7156     *phys_ptr = phys_addr;
7157     return false;
7158 do_fault:
7159     *fsr = code | (domain << 4);
7160     return true;
7161 }
7162
7163 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7164  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7165  */
7166 typedef enum {
7167     translation_fault = 1,
7168     access_fault = 2,
7169     permission_fault = 3,
7170 } MMUFaultType;
7171
7172 /*
7173  * check_s2_mmu_setup
7174  * @cpu:        ARMCPU
7175  * @is_aa64:    True if the translation regime is in AArch64 state
7176  * @startlevel: Suggested starting level
7177  * @inputsize:  Bitsize of IPAs
7178  * @stride:     Page-table stride (See the ARM ARM)
7179  *
7180  * Returns true if the suggested S2 translation parameters are OK and
7181  * false otherwise.
7182  */
7183 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
7184                                int inputsize, int stride)
7185 {
7186     const int grainsize = stride + 3;
7187     int startsizecheck;
7188
7189     /* Negative levels are never allowed.  */
7190     if (level < 0) {
7191         return false;
7192     }
7193
7194     startsizecheck = inputsize - ((3 - level) * stride + grainsize);
7195     if (startsizecheck < 1 || startsizecheck > stride + 4) {
7196         return false;
7197     }
7198
7199     if (is_aa64) {
7200         CPUARMState *env = &cpu->env;
7201         unsigned int pamax = arm_pamax(cpu);
7202
7203         switch (stride) {
7204         case 13: /* 64KB Pages.  */
7205             if (level == 0 || (level == 1 && pamax <= 42)) {
7206                 return false;
7207             }
7208             break;
7209         case 11: /* 16KB Pages.  */
7210             if (level == 0 || (level == 1 && pamax <= 40)) {
7211                 return false;
7212             }
7213             break;
7214         case 9: /* 4KB Pages.  */
7215             if (level == 0 && pamax <= 42) {
7216                 return false;
7217             }
7218             break;
7219         default:
7220             g_assert_not_reached();
7221         }
7222
7223         /* Inputsize checks.  */
7224         if (inputsize > pamax &&
7225             (arm_el_is_aa64(env, 1) || inputsize > 40)) {
7226             /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
7227             return false;
7228         }
7229     } else {
7230         /* AArch32 only supports 4KB pages. Assert on that.  */
7231         assert(stride == 9);
7232
7233         if (level == 0) {
7234             return false;
7235         }
7236     }
7237     return true;
7238 }
7239
7240 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
7241                                int access_type, ARMMMUIdx mmu_idx,
7242                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
7243                                target_ulong *page_size_ptr, uint32_t *fsr,
7244                                ARMMMUFaultInfo *fi)
7245 {
7246     ARMCPU *cpu = arm_env_get_cpu(env);
7247     CPUState *cs = CPU(cpu);
7248     /* Read an LPAE long-descriptor translation table. */
7249     MMUFaultType fault_type = translation_fault;
7250     uint32_t level;
7251     uint32_t epd = 0;
7252     int32_t t0sz, t1sz;
7253     uint32_t tg;
7254     uint64_t ttbr;
7255     int ttbr_select;
7256     hwaddr descaddr, indexmask, indexmask_grainsize;
7257     uint32_t tableattrs;
7258     target_ulong page_size;
7259     uint32_t attrs;
7260     int32_t stride = 9;
7261     int32_t va_size;
7262     int inputsize;
7263     int32_t tbi = 0;
7264     TCR *tcr = regime_tcr(env, mmu_idx);
7265     int ap, ns, xn, pxn;
7266     uint32_t el = regime_el(env, mmu_idx);
7267     bool ttbr1_valid = true;
7268     uint64_t descaddrmask;
7269
7270     /* TODO:
7271      * This code does not handle the different format TCR for VTCR_EL2.
7272      * This code also does not support shareability levels.
7273      * Attribute and permission bit handling should also be checked when adding
7274      * support for those page table walks.
7275      */
7276     if (arm_el_is_aa64(env, el)) {
7277         level = 0;
7278         va_size = 64;
7279         if (el > 1) {
7280             if (mmu_idx != ARMMMUIdx_S2NS) {
7281                 tbi = extract64(tcr->raw_tcr, 20, 1);
7282             }
7283         } else {
7284             if (extract64(address, 55, 1)) {
7285                 tbi = extract64(tcr->raw_tcr, 38, 1);
7286             } else {
7287                 tbi = extract64(tcr->raw_tcr, 37, 1);
7288             }
7289         }
7290         tbi *= 8;
7291
7292         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7293          * invalid.
7294          */
7295         if (el > 1) {
7296             ttbr1_valid = false;
7297         }
7298     } else {
7299         level = 1;
7300         va_size = 32;
7301         /* There is no TTBR1 for EL2 */
7302         if (el == 2) {
7303             ttbr1_valid = false;
7304         }
7305     }
7306
7307     /* Determine whether this address is in the region controlled by
7308      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7309      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7310      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7311      */
7312     if (va_size == 64) {
7313         /* AArch64 translation.  */
7314         t0sz = extract32(tcr->raw_tcr, 0, 6);
7315         t0sz = MIN(t0sz, 39);
7316         t0sz = MAX(t0sz, 16);
7317     } else if (mmu_idx != ARMMMUIdx_S2NS) {
7318         /* AArch32 stage 1 translation.  */
7319         t0sz = extract32(tcr->raw_tcr, 0, 3);
7320     } else {
7321         /* AArch32 stage 2 translation.  */
7322         bool sext = extract32(tcr->raw_tcr, 4, 1);
7323         bool sign = extract32(tcr->raw_tcr, 3, 1);
7324         t0sz = sextract32(tcr->raw_tcr, 0, 4);
7325
7326         /* If the sign-extend bit is not the same as t0sz[3], the result
7327          * is unpredictable. Flag this as a guest error.  */
7328         if (sign != sext) {
7329             qemu_log_mask(LOG_GUEST_ERROR,
7330                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
7331         }
7332     }
7333     t1sz = extract32(tcr->raw_tcr, 16, 6);
7334     if (va_size == 64) {
7335         t1sz = MIN(t1sz, 39);
7336         t1sz = MAX(t1sz, 16);
7337     }
7338     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
7339         /* there is a ttbr0 region and we are in it (high bits all zero) */
7340         ttbr_select = 0;
7341     } else if (ttbr1_valid && t1sz &&
7342                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
7343         /* there is a ttbr1 region and we are in it (high bits all one) */
7344         ttbr_select = 1;
7345     } else if (!t0sz) {
7346         /* ttbr0 region is "everything not in the ttbr1 region" */
7347         ttbr_select = 0;
7348     } else if (!t1sz && ttbr1_valid) {
7349         /* ttbr1 region is "everything not in the ttbr0 region" */
7350         ttbr_select = 1;
7351     } else {
7352         /* in the gap between the two regions, this is a Translation fault */
7353         fault_type = translation_fault;
7354         goto do_fault;
7355     }
7356
7357     /* Note that QEMU ignores shareability and cacheability attributes,
7358      * so we don't need to do anything with the SH, ORGN, IRGN fields
7359      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
7360      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7361      * implement any ASID-like capability so we can ignore it (instead
7362      * we will always flush the TLB any time the ASID is changed).
7363      */
7364     if (ttbr_select == 0) {
7365         ttbr = regime_ttbr(env, mmu_idx, 0);
7366         if (el < 2) {
7367             epd = extract32(tcr->raw_tcr, 7, 1);
7368         }
7369         inputsize = va_size - t0sz;
7370
7371         tg = extract32(tcr->raw_tcr, 14, 2);
7372         if (tg == 1) { /* 64KB pages */
7373             stride = 13;
7374         }
7375         if (tg == 2) { /* 16KB pages */
7376             stride = 11;
7377         }
7378     } else {
7379         /* We should only be here if TTBR1 is valid */
7380         assert(ttbr1_valid);
7381
7382         ttbr = regime_ttbr(env, mmu_idx, 1);
7383         epd = extract32(tcr->raw_tcr, 23, 1);
7384         inputsize = va_size - t1sz;
7385
7386         tg = extract32(tcr->raw_tcr, 30, 2);
7387         if (tg == 3)  { /* 64KB pages */
7388             stride = 13;
7389         }
7390         if (tg == 1) { /* 16KB pages */
7391             stride = 11;
7392         }
7393     }
7394
7395     /* Here we should have set up all the parameters for the translation:
7396      * va_size, inputsize, ttbr, epd, stride, tbi
7397      */
7398
7399     if (epd) {
7400         /* Translation table walk disabled => Translation fault on TLB miss
7401          * Note: This is always 0 on 64-bit EL2 and EL3.
7402          */
7403         goto do_fault;
7404     }
7405
7406     if (mmu_idx != ARMMMUIdx_S2NS) {
7407         /* The starting level depends on the virtual address size (which can
7408          * be up to 48 bits) and the translation granule size. It indicates
7409          * the number of strides (stride bits at a time) needed to
7410          * consume the bits of the input address. In the pseudocode this is:
7411          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
7412          * where their 'inputsize' is our 'inputsize', 'grainsize' is
7413          * our 'stride + 3' and 'stride' is our 'stride'.
7414          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7415          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7416          * = 4 - (inputsize - 4) / stride;
7417          */
7418         level = 4 - (inputsize - 4) / stride;
7419     } else {
7420         /* For stage 2 translations the starting level is specified by the
7421          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7422          */
7423         uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
7424         uint32_t startlevel;
7425         bool ok;
7426
7427         if (va_size == 32 || stride == 9) {
7428             /* AArch32 or 4KB pages */
7429             startlevel = 2 - sl0;
7430         } else {
7431             /* 16KB or 64KB pages */
7432             startlevel = 3 - sl0;
7433         }
7434
7435         /* Check that the starting level is valid. */
7436         ok = check_s2_mmu_setup(cpu, va_size == 64, startlevel,
7437                                 inputsize, stride);
7438         if (!ok) {
7439             fault_type = translation_fault;
7440             goto do_fault;
7441         }
7442         level = startlevel;
7443     }
7444
7445     indexmask_grainsize = (1ULL << (stride + 3)) - 1;
7446     indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
7447
7448     /* Now we can extract the actual base address from the TTBR */
7449     descaddr = extract64(ttbr, 0, 48);
7450     descaddr &= ~indexmask;
7451
7452     /* The address field in the descriptor goes up to bit 39 for ARMv7
7453      * but up to bit 47 for ARMv8, but we use the descaddrmask
7454      * up to bit 39 for AArch32, because we don't need other bits in that case
7455      * to construct next descriptor address (anyway they should be all zeroes).
7456      */
7457     descaddrmask = ((1ull << (va_size == 64 ? 48 : 40)) - 1) &
7458                    ~indexmask_grainsize;
7459
7460     /* Secure accesses start with the page table in secure memory and
7461      * can be downgraded to non-secure at any step. Non-secure accesses
7462      * remain non-secure. We implement this by just ORing in the NSTable/NS
7463      * bits at each step.
7464      */
7465     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7466     for (;;) {
7467         uint64_t descriptor;
7468         bool nstable;
7469
7470         descaddr |= (address >> (stride * (4 - level))) & indexmask;
7471         descaddr &= ~7ULL;
7472         nstable = extract32(tableattrs, 4, 1);
7473         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7474         if (fi->s1ptw) {
7475             goto do_fault;
7476         }
7477
7478         if (!(descriptor & 1) ||
7479             (!(descriptor & 2) && (level == 3))) {
7480             /* Invalid, or the Reserved level 3 encoding */
7481             goto do_fault;
7482         }
7483         descaddr = descriptor & descaddrmask;
7484
7485         if ((descriptor & 2) && (level < 3)) {
7486             /* Table entry. The top five bits are attributes which  may
7487              * propagate down through lower levels of the table (and
7488              * which are all arranged so that 0 means "no effect", so
7489              * we can gather them up by ORing in the bits at each level).
7490              */
7491             tableattrs |= extract64(descriptor, 59, 5);
7492             level++;
7493             indexmask = indexmask_grainsize;
7494             continue;
7495         }
7496         /* Block entry at level 1 or 2, or page entry at level 3.
7497          * These are basically the same thing, although the number
7498          * of bits we pull in from the vaddr varies.
7499          */
7500         page_size = (1ULL << ((stride * (4 - level)) + 3));
7501         descaddr |= (address & (page_size - 1));
7502         /* Extract attributes from the descriptor */
7503         attrs = extract64(descriptor, 2, 10)
7504             | (extract64(descriptor, 52, 12) << 10);
7505
7506         if (mmu_idx == ARMMMUIdx_S2NS) {
7507             /* Stage 2 table descriptors do not include any attribute fields */
7508             break;
7509         }
7510         /* Merge in attributes from table descriptors */
7511         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7512         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7513         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7514          * means "force PL1 access only", which means forcing AP[1] to 0.
7515          */
7516         if (extract32(tableattrs, 2, 1)) {
7517             attrs &= ~(1 << 4);
7518         }
7519         attrs |= nstable << 3; /* NS */
7520         break;
7521     }
7522     /* Here descaddr is the final physical address, and attributes
7523      * are all in attrs.
7524      */
7525     fault_type = access_fault;
7526     if ((attrs & (1 << 8)) == 0) {
7527         /* Access flag */
7528         goto do_fault;
7529     }
7530
7531     ap = extract32(attrs, 4, 2);
7532     xn = extract32(attrs, 12, 1);
7533
7534     if (mmu_idx == ARMMMUIdx_S2NS) {
7535         ns = true;
7536         *prot = get_S2prot(env, ap, xn);
7537     } else {
7538         ns = extract32(attrs, 3, 1);
7539         pxn = extract32(attrs, 11, 1);
7540         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7541     }
7542
7543     fault_type = permission_fault;
7544     if (!(*prot & (1 << access_type))) {
7545         goto do_fault;
7546     }
7547
7548     if (ns) {
7549         /* The NS bit will (as required by the architecture) have no effect if
7550          * the CPU doesn't support TZ or this is a non-secure translation
7551          * regime, because the attribute will already be non-secure.
7552          */
7553         txattrs->secure = false;
7554     }
7555     *phys_ptr = descaddr;
7556     *page_size_ptr = page_size;
7557     return false;
7558
7559 do_fault:
7560     /* Long-descriptor format IFSR/DFSR value */
7561     *fsr = (1 << 9) | (fault_type << 2) | level;
7562     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7563     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7564     return true;
7565 }
7566
7567 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7568                                                 ARMMMUIdx mmu_idx,
7569                                                 int32_t address, int *prot)
7570 {
7571     *prot = PAGE_READ | PAGE_WRITE;
7572     switch (address) {
7573     case 0xF0000000 ... 0xFFFFFFFF:
7574         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7575             *prot |= PAGE_EXEC;
7576         }
7577         break;
7578     case 0x00000000 ... 0x7FFFFFFF:
7579         *prot |= PAGE_EXEC;
7580         break;
7581     }
7582
7583 }
7584
7585 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7586                                  int access_type, ARMMMUIdx mmu_idx,
7587                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7588 {
7589     ARMCPU *cpu = arm_env_get_cpu(env);
7590     int n;
7591     bool is_user = regime_is_user(env, mmu_idx);
7592
7593     *phys_ptr = address;
7594     *prot = 0;
7595
7596     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7597         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7598     } else { /* MPU enabled */
7599         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7600             /* region search */
7601             uint32_t base = env->pmsav7.drbar[n];
7602             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7603             uint32_t rmask;
7604             bool srdis = false;
7605
7606             if (!(env->pmsav7.drsr[n] & 0x1)) {
7607                 continue;
7608             }
7609
7610             if (!rsize) {
7611                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7612                 continue;
7613             }
7614             rsize++;
7615             rmask = (1ull << rsize) - 1;
7616
7617             if (base & rmask) {
7618                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7619                               "to DRSR region size, mask = %" PRIx32,
7620                               base, rmask);
7621                 continue;
7622             }
7623
7624             if (address < base || address > base + rmask) {
7625                 continue;
7626             }
7627
7628             /* Region matched */
7629
7630             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7631                 int i, snd;
7632                 uint32_t srdis_mask;
7633
7634                 rsize -= 3; /* sub region size (power of 2) */
7635                 snd = ((address - base) >> rsize) & 0x7;
7636                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7637
7638                 srdis_mask = srdis ? 0x3 : 0x0;
7639                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7640                     /* This will check in groups of 2, 4 and then 8, whether
7641                      * the subregion bits are consistent. rsize is incremented
7642                      * back up to give the region size, considering consistent
7643                      * adjacent subregions as one region. Stop testing if rsize
7644                      * is already big enough for an entire QEMU page.
7645                      */
7646                     int snd_rounded = snd & ~(i - 1);
7647                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7648                                                      snd_rounded + 8, i);
7649                     if (srdis_mask ^ srdis_multi) {
7650                         break;
7651                     }
7652                     srdis_mask = (srdis_mask << i) | srdis_mask;
7653                     rsize++;
7654                 }
7655             }
7656             if (rsize < TARGET_PAGE_BITS) {
7657                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7658                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7659                               rsize, TARGET_PAGE_BITS);
7660                 continue;
7661             }
7662             if (srdis) {
7663                 continue;
7664             }
7665             break;
7666         }
7667
7668         if (n == -1) { /* no hits */
7669             if (cpu->pmsav7_dregion &&
7670                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7671                 /* background fault */
7672                 *fsr = 0;
7673                 return true;
7674             }
7675             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7676         } else { /* a MPU hit! */
7677             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7678
7679             if (is_user) { /* User mode AP bit decoding */
7680                 switch (ap) {
7681                 case 0:
7682                 case 1:
7683                 case 5:
7684                     break; /* no access */
7685                 case 3:
7686                     *prot |= PAGE_WRITE;
7687                     /* fall through */
7688                 case 2:
7689                 case 6:
7690                     *prot |= PAGE_READ | PAGE_EXEC;
7691                     break;
7692                 default:
7693                     qemu_log_mask(LOG_GUEST_ERROR,
7694                                   "Bad value for AP bits in DRACR %"
7695                                   PRIx32 "\n", ap);
7696                 }
7697             } else { /* Priv. mode AP bits decoding */
7698                 switch (ap) {
7699                 case 0:
7700                     break; /* no access */
7701                 case 1:
7702                 case 2:
7703                 case 3:
7704                     *prot |= PAGE_WRITE;
7705                     /* fall through */
7706                 case 5:
7707                 case 6:
7708                     *prot |= PAGE_READ | PAGE_EXEC;
7709                     break;
7710                 default:
7711                     qemu_log_mask(LOG_GUEST_ERROR,
7712                                   "Bad value for AP bits in DRACR %"
7713                                   PRIx32 "\n", ap);
7714                 }
7715             }
7716
7717             /* execute never */
7718             if (env->pmsav7.dracr[n] & (1 << 12)) {
7719                 *prot &= ~PAGE_EXEC;
7720             }
7721         }
7722     }
7723
7724     *fsr = 0x00d; /* Permission fault */
7725     return !(*prot & (1 << access_type));
7726 }
7727
7728 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7729                                  int access_type, ARMMMUIdx mmu_idx,
7730                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7731 {
7732     int n;
7733     uint32_t mask;
7734     uint32_t base;
7735     bool is_user = regime_is_user(env, mmu_idx);
7736
7737     *phys_ptr = address;
7738     for (n = 7; n >= 0; n--) {
7739         base = env->cp15.c6_region[n];
7740         if ((base & 1) == 0) {
7741             continue;
7742         }
7743         mask = 1 << ((base >> 1) & 0x1f);
7744         /* Keep this shift separate from the above to avoid an
7745            (undefined) << 32.  */
7746         mask = (mask << 1) - 1;
7747         if (((base ^ address) & ~mask) == 0) {
7748             break;
7749         }
7750     }
7751     if (n < 0) {
7752         *fsr = 2;
7753         return true;
7754     }
7755
7756     if (access_type == 2) {
7757         mask = env->cp15.pmsav5_insn_ap;
7758     } else {
7759         mask = env->cp15.pmsav5_data_ap;
7760     }
7761     mask = (mask >> (n * 4)) & 0xf;
7762     switch (mask) {
7763     case 0:
7764         *fsr = 1;
7765         return true;
7766     case 1:
7767         if (is_user) {
7768             *fsr = 1;
7769             return true;
7770         }
7771         *prot = PAGE_READ | PAGE_WRITE;
7772         break;
7773     case 2:
7774         *prot = PAGE_READ;
7775         if (!is_user) {
7776             *prot |= PAGE_WRITE;
7777         }
7778         break;
7779     case 3:
7780         *prot = PAGE_READ | PAGE_WRITE;
7781         break;
7782     case 5:
7783         if (is_user) {
7784             *fsr = 1;
7785             return true;
7786         }
7787         *prot = PAGE_READ;
7788         break;
7789     case 6:
7790         *prot = PAGE_READ;
7791         break;
7792     default:
7793         /* Bad permission.  */
7794         *fsr = 1;
7795         return true;
7796     }
7797     *prot |= PAGE_EXEC;
7798     return false;
7799 }
7800
7801 /* get_phys_addr - get the physical address for this virtual address
7802  *
7803  * Find the physical address corresponding to the given virtual address,
7804  * by doing a translation table walk on MMU based systems or using the
7805  * MPU state on MPU based systems.
7806  *
7807  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7808  * prot and page_size may not be filled in, and the populated fsr value provides
7809  * information on why the translation aborted, in the format of a
7810  * DFSR/IFSR fault register, with the following caveats:
7811  *  * we honour the short vs long DFSR format differences.
7812  *  * the WnR bit is never set (the caller must do this).
7813  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7814  *    value.
7815  *
7816  * @env: CPUARMState
7817  * @address: virtual address to get physical address for
7818  * @access_type: 0 for read, 1 for write, 2 for execute
7819  * @mmu_idx: MMU index indicating required translation regime
7820  * @phys_ptr: set to the physical address corresponding to the virtual address
7821  * @attrs: set to the memory transaction attributes to use
7822  * @prot: set to the permissions for the page containing phys_ptr
7823  * @page_size: set to the size of the page containing phys_ptr
7824  * @fsr: set to the DFSR/IFSR value on failure
7825  */
7826 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7827                           int access_type, ARMMMUIdx mmu_idx,
7828                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7829                           target_ulong *page_size, uint32_t *fsr,
7830                           ARMMMUFaultInfo *fi)
7831 {
7832     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7833         /* Call ourselves recursively to do the stage 1 and then stage 2
7834          * translations.
7835          */
7836         if (arm_feature(env, ARM_FEATURE_EL2)) {
7837             hwaddr ipa;
7838             int s2_prot;
7839             int ret;
7840
7841             ret = get_phys_addr(env, address, access_type,
7842                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7843                                 prot, page_size, fsr, fi);
7844
7845             /* If S1 fails or S2 is disabled, return early.  */
7846             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7847                 *phys_ptr = ipa;
7848                 return ret;
7849             }
7850
7851             /* S1 is done. Now do S2 translation.  */
7852             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7853                                      phys_ptr, attrs, &s2_prot,
7854                                      page_size, fsr, fi);
7855             fi->s2addr = ipa;
7856             /* Combine the S1 and S2 perms.  */
7857             *prot &= s2_prot;
7858             return ret;
7859         } else {
7860             /*
7861              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7862              */
7863             mmu_idx += ARMMMUIdx_S1NSE0;
7864         }
7865     }
7866
7867     /* The page table entries may downgrade secure to non-secure, but
7868      * cannot upgrade an non-secure translation regime's attributes
7869      * to secure.
7870      */
7871     attrs->secure = regime_is_secure(env, mmu_idx);
7872     attrs->user = regime_is_user(env, mmu_idx);
7873
7874     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7875      * In v7 and earlier it affects all stage 1 translations.
7876      */
7877     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7878         && !arm_feature(env, ARM_FEATURE_V8)) {
7879         if (regime_el(env, mmu_idx) == 3) {
7880             address += env->cp15.fcseidr_s;
7881         } else {
7882             address += env->cp15.fcseidr_ns;
7883         }
7884     }
7885
7886     /* pmsav7 has special handling for when MPU is disabled so call it before
7887      * the common MMU/MPU disabled check below.
7888      */
7889     if (arm_feature(env, ARM_FEATURE_MPU) &&
7890         arm_feature(env, ARM_FEATURE_V7)) {
7891         *page_size = TARGET_PAGE_SIZE;
7892         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7893                                     phys_ptr, prot, fsr);
7894     }
7895
7896     if (regime_translation_disabled(env, mmu_idx)) {
7897         /* MMU/MPU disabled.  */
7898         *phys_ptr = address;
7899         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7900         *page_size = TARGET_PAGE_SIZE;
7901         return 0;
7902     }
7903
7904     if (arm_feature(env, ARM_FEATURE_MPU)) {
7905         /* Pre-v7 MPU */
7906         *page_size = TARGET_PAGE_SIZE;
7907         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7908                                     phys_ptr, prot, fsr);
7909     }
7910
7911     if (regime_using_lpae_format(env, mmu_idx)) {
7912         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7913                                   attrs, prot, page_size, fsr, fi);
7914     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7915         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7916                                 attrs, prot, page_size, fsr, fi);
7917     } else {
7918         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7919                                 prot, page_size, fsr, fi);
7920     }
7921 }
7922
7923 /* Walk the page table and (if the mapping exists) add the page
7924  * to the TLB. Return false on success, or true on failure. Populate
7925  * fsr with ARM DFSR/IFSR fault register format value on failure.
7926  */
7927 bool arm_tlb_fill(CPUState *cs, vaddr address,
7928                   int access_type, int mmu_idx, uint32_t *fsr,
7929                   ARMMMUFaultInfo *fi)
7930 {
7931     ARMCPU *cpu = ARM_CPU(cs);
7932     CPUARMState *env = &cpu->env;
7933     hwaddr phys_addr;
7934     target_ulong page_size;
7935     int prot;
7936     int ret;
7937     MemTxAttrs attrs = {};
7938
7939     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7940                         &attrs, &prot, &page_size, fsr, fi);
7941     if (!ret) {
7942         /* Map a single [sub]page.  */
7943         phys_addr &= TARGET_PAGE_MASK;
7944         address &= TARGET_PAGE_MASK;
7945         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7946                                 prot, mmu_idx, page_size);
7947         return 0;
7948     }
7949
7950     return ret;
7951 }
7952
7953 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7954                                          MemTxAttrs *attrs)
7955 {
7956     ARMCPU *cpu = ARM_CPU(cs);
7957     CPUARMState *env = &cpu->env;
7958     hwaddr phys_addr;
7959     target_ulong page_size;
7960     int prot;
7961     bool ret;
7962     uint32_t fsr;
7963     ARMMMUFaultInfo fi = {};
7964
7965     *attrs = (MemTxAttrs) {};
7966
7967     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7968                         attrs, &prot, &page_size, &fsr, &fi);
7969
7970     if (ret) {
7971         return -1;
7972     }
7973     return phys_addr;
7974 }
7975
7976 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7977 {
7978     ARMCPU *cpu = arm_env_get_cpu(env);
7979
7980     switch (reg) {
7981     case 0: /* APSR */
7982         return xpsr_read(env) & 0xf8000000;
7983     case 1: /* IAPSR */
7984         return xpsr_read(env) & 0xf80001ff;
7985     case 2: /* EAPSR */
7986         return xpsr_read(env) & 0xff00fc00;
7987     case 3: /* xPSR */
7988         return xpsr_read(env) & 0xff00fdff;
7989     case 5: /* IPSR */
7990         return xpsr_read(env) & 0x000001ff;
7991     case 6: /* EPSR */
7992         return xpsr_read(env) & 0x0700fc00;
7993     case 7: /* IEPSR */
7994         return xpsr_read(env) & 0x0700edff;
7995     case 8: /* MSP */
7996         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7997     case 9: /* PSP */
7998         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7999     case 16: /* PRIMASK */
8000         return (env->daif & PSTATE_I) != 0;
8001     case 17: /* BASEPRI */
8002     case 18: /* BASEPRI_MAX */
8003         return env->v7m.basepri;
8004     case 19: /* FAULTMASK */
8005         return (env->daif & PSTATE_F) != 0;
8006     case 20: /* CONTROL */
8007         return env->v7m.control;
8008     default:
8009         /* ??? For debugging only.  */
8010         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
8011         return 0;
8012     }
8013 }
8014
8015 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
8016 {
8017     ARMCPU *cpu = arm_env_get_cpu(env);
8018
8019     switch (reg) {
8020     case 0: /* APSR */
8021         xpsr_write(env, val, 0xf8000000);
8022         break;
8023     case 1: /* IAPSR */
8024         xpsr_write(env, val, 0xf8000000);
8025         break;
8026     case 2: /* EAPSR */
8027         xpsr_write(env, val, 0xfe00fc00);
8028         break;
8029     case 3: /* xPSR */
8030         xpsr_write(env, val, 0xfe00fc00);
8031         break;
8032     case 5: /* IPSR */
8033         /* IPSR bits are readonly.  */
8034         break;
8035     case 6: /* EPSR */
8036         xpsr_write(env, val, 0x0600fc00);
8037         break;
8038     case 7: /* IEPSR */
8039         xpsr_write(env, val, 0x0600fc00);
8040         break;
8041     case 8: /* MSP */
8042         if (env->v7m.current_sp)
8043             env->v7m.other_sp = val;
8044         else
8045             env->regs[13] = val;
8046         break;
8047     case 9: /* PSP */
8048         if (env->v7m.current_sp)
8049             env->regs[13] = val;
8050         else
8051             env->v7m.other_sp = val;
8052         break;
8053     case 16: /* PRIMASK */
8054         if (val & 1) {
8055             env->daif |= PSTATE_I;
8056         } else {
8057             env->daif &= ~PSTATE_I;
8058         }
8059         break;
8060     case 17: /* BASEPRI */
8061         env->v7m.basepri = val & 0xff;
8062         break;
8063     case 18: /* BASEPRI_MAX */
8064         val &= 0xff;
8065         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
8066             env->v7m.basepri = val;
8067         break;
8068     case 19: /* FAULTMASK */
8069         if (val & 1) {
8070             env->daif |= PSTATE_F;
8071         } else {
8072             env->daif &= ~PSTATE_F;
8073         }
8074         break;
8075     case 20: /* CONTROL */
8076         env->v7m.control = val & 3;
8077         switch_v7m_sp(env, (val & 2) != 0);
8078         break;
8079     default:
8080         /* ??? For debugging only.  */
8081         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
8082         return;
8083     }
8084 }
8085
8086 #endif
8087
8088 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
8089 {
8090     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8091      * Note that we do not implement the (architecturally mandated)
8092      * alignment fault for attempts to use this on Device memory
8093      * (which matches the usual QEMU behaviour of not implementing either
8094      * alignment faults or any memory attribute handling).
8095      */
8096
8097     ARMCPU *cpu = arm_env_get_cpu(env);
8098     uint64_t blocklen = 4 << cpu->dcz_blocksize;
8099     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
8100
8101 #ifndef CONFIG_USER_ONLY
8102     {
8103         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8104          * the block size so we might have to do more than one TLB lookup.
8105          * We know that in fact for any v8 CPU the page size is at least 4K
8106          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8107          * 1K as an artefact of legacy v5 subpage support being present in the
8108          * same QEMU executable.
8109          */
8110         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
8111         void *hostaddr[maxidx];
8112         int try, i;
8113         unsigned mmu_idx = cpu_mmu_index(env, false);
8114         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
8115
8116         for (try = 0; try < 2; try++) {
8117
8118             for (i = 0; i < maxidx; i++) {
8119                 hostaddr[i] = tlb_vaddr_to_host(env,
8120                                                 vaddr + TARGET_PAGE_SIZE * i,
8121                                                 1, mmu_idx);
8122                 if (!hostaddr[i]) {
8123                     break;
8124                 }
8125             }
8126             if (i == maxidx) {
8127                 /* If it's all in the TLB it's fair game for just writing to;
8128                  * we know we don't need to update dirty status, etc.
8129                  */
8130                 for (i = 0; i < maxidx - 1; i++) {
8131                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
8132                 }
8133                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
8134                 return;
8135             }
8136             /* OK, try a store and see if we can populate the tlb. This
8137              * might cause an exception if the memory isn't writable,
8138              * in which case we will longjmp out of here. We must for
8139              * this purpose use the actual register value passed to us
8140              * so that we get the fault address right.
8141              */
8142             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
8143             /* Now we can populate the other TLB entries, if any */
8144             for (i = 0; i < maxidx; i++) {
8145                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
8146                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
8147                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
8148                 }
8149             }
8150         }
8151
8152         /* Slow path (probably attempt to do this to an I/O device or
8153          * similar, or clearing of a block of code we have translations
8154          * cached for). Just do a series of byte writes as the architecture
8155          * demands. It's not worth trying to use a cpu_physical_memory_map(),
8156          * memset(), unmap() sequence here because:
8157          *  + we'd need to account for the blocksize being larger than a page
8158          *  + the direct-RAM access case is almost always going to be dealt
8159          *    with in the fastpath code above, so there's no speed benefit
8160          *  + we would have to deal with the map returning NULL because the
8161          *    bounce buffer was in use
8162          */
8163         for (i = 0; i < blocklen; i++) {
8164             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
8165         }
8166     }
8167 #else
8168     memset(g2h(vaddr), 0, blocklen);
8169 #endif
8170 }
8171
8172 /* Note that signed overflow is undefined in C.  The following routines are
8173    careful to use unsigned types where modulo arithmetic is required.
8174    Failure to do so _will_ break on newer gcc.  */
8175
8176 /* Signed saturating arithmetic.  */
8177
8178 /* Perform 16-bit signed saturating addition.  */
8179 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
8180 {
8181     uint16_t res;
8182
8183     res = a + b;
8184     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
8185         if (a & 0x8000)
8186             res = 0x8000;
8187         else
8188             res = 0x7fff;
8189     }
8190     return res;
8191 }
8192
8193 /* Perform 8-bit signed saturating addition.  */
8194 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
8195 {
8196     uint8_t res;
8197
8198     res = a + b;
8199     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
8200         if (a & 0x80)
8201             res = 0x80;
8202         else
8203             res = 0x7f;
8204     }
8205     return res;
8206 }
8207
8208 /* Perform 16-bit signed saturating subtraction.  */
8209 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
8210 {
8211     uint16_t res;
8212
8213     res = a - b;
8214     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
8215         if (a & 0x8000)
8216             res = 0x8000;
8217         else
8218             res = 0x7fff;
8219     }
8220     return res;
8221 }
8222
8223 /* Perform 8-bit signed saturating subtraction.  */
8224 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
8225 {
8226     uint8_t res;
8227
8228     res = a - b;
8229     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
8230         if (a & 0x80)
8231             res = 0x80;
8232         else
8233             res = 0x7f;
8234     }
8235     return res;
8236 }
8237
8238 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
8239 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
8240 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
8241 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
8242 #define PFX q
8243
8244 #include "op_addsub.h"
8245
8246 /* Unsigned saturating arithmetic.  */
8247 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
8248 {
8249     uint16_t res;
8250     res = a + b;
8251     if (res < a)
8252         res = 0xffff;
8253     return res;
8254 }
8255
8256 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
8257 {
8258     if (a > b)
8259         return a - b;
8260     else
8261         return 0;
8262 }
8263
8264 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
8265 {
8266     uint8_t res;
8267     res = a + b;
8268     if (res < a)
8269         res = 0xff;
8270     return res;
8271 }
8272
8273 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
8274 {
8275     if (a > b)
8276         return a - b;
8277     else
8278         return 0;
8279 }
8280
8281 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8282 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8283 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
8284 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
8285 #define PFX uq
8286
8287 #include "op_addsub.h"
8288
8289 /* Signed modulo arithmetic.  */
8290 #define SARITH16(a, b, n, op) do { \
8291     int32_t sum; \
8292     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8293     RESULT(sum, n, 16); \
8294     if (sum >= 0) \
8295         ge |= 3 << (n * 2); \
8296     } while(0)
8297
8298 #define SARITH8(a, b, n, op) do { \
8299     int32_t sum; \
8300     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8301     RESULT(sum, n, 8); \
8302     if (sum >= 0) \
8303         ge |= 1 << n; \
8304     } while(0)
8305
8306
8307 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8308 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8309 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
8310 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
8311 #define PFX s
8312 #define ARITH_GE
8313
8314 #include "op_addsub.h"
8315
8316 /* Unsigned modulo arithmetic.  */
8317 #define ADD16(a, b, n) do { \
8318     uint32_t sum; \
8319     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8320     RESULT(sum, n, 16); \
8321     if ((sum >> 16) == 1) \
8322         ge |= 3 << (n * 2); \
8323     } while(0)
8324
8325 #define ADD8(a, b, n) do { \
8326     uint32_t sum; \
8327     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8328     RESULT(sum, n, 8); \
8329     if ((sum >> 8) == 1) \
8330         ge |= 1 << n; \
8331     } while(0)
8332
8333 #define SUB16(a, b, n) do { \
8334     uint32_t sum; \
8335     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8336     RESULT(sum, n, 16); \
8337     if ((sum >> 16) == 0) \
8338         ge |= 3 << (n * 2); \
8339     } while(0)
8340
8341 #define SUB8(a, b, n) do { \
8342     uint32_t sum; \
8343     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8344     RESULT(sum, n, 8); \
8345     if ((sum >> 8) == 0) \
8346         ge |= 1 << n; \
8347     } while(0)
8348
8349 #define PFX u
8350 #define ARITH_GE
8351
8352 #include "op_addsub.h"
8353
8354 /* Halved signed arithmetic.  */
8355 #define ADD16(a, b, n) \
8356   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8357 #define SUB16(a, b, n) \
8358   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8359 #define ADD8(a, b, n) \
8360   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8361 #define SUB8(a, b, n) \
8362   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8363 #define PFX sh
8364
8365 #include "op_addsub.h"
8366
8367 /* Halved unsigned arithmetic.  */
8368 #define ADD16(a, b, n) \
8369   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8370 #define SUB16(a, b, n) \
8371   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8372 #define ADD8(a, b, n) \
8373   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8374 #define SUB8(a, b, n) \
8375   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8376 #define PFX uh
8377
8378 #include "op_addsub.h"
8379
8380 static inline uint8_t do_usad(uint8_t a, uint8_t b)
8381 {
8382     if (a > b)
8383         return a - b;
8384     else
8385         return b - a;
8386 }
8387
8388 /* Unsigned sum of absolute byte differences.  */
8389 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
8390 {
8391     uint32_t sum;
8392     sum = do_usad(a, b);
8393     sum += do_usad(a >> 8, b >> 8);
8394     sum += do_usad(a >> 16, b >>16);
8395     sum += do_usad(a >> 24, b >> 24);
8396     return sum;
8397 }
8398
8399 /* For ARMv6 SEL instruction.  */
8400 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8401 {
8402     uint32_t mask;
8403
8404     mask = 0;
8405     if (flags & 1)
8406         mask |= 0xff;
8407     if (flags & 2)
8408         mask |= 0xff00;
8409     if (flags & 4)
8410         mask |= 0xff0000;
8411     if (flags & 8)
8412         mask |= 0xff000000;
8413     return (a & mask) | (b & ~mask);
8414 }
8415
8416 /* VFP support.  We follow the convention used for VFP instructions:
8417    Single precision routines have a "s" suffix, double precision a
8418    "d" suffix.  */
8419
8420 /* Convert host exception flags to vfp form.  */
8421 static inline int vfp_exceptbits_from_host(int host_bits)
8422 {
8423     int target_bits = 0;
8424
8425     if (host_bits & float_flag_invalid)
8426         target_bits |= 1;
8427     if (host_bits & float_flag_divbyzero)
8428         target_bits |= 2;
8429     if (host_bits & float_flag_overflow)
8430         target_bits |= 4;
8431     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8432         target_bits |= 8;
8433     if (host_bits & float_flag_inexact)
8434         target_bits |= 0x10;
8435     if (host_bits & float_flag_input_denormal)
8436         target_bits |= 0x80;
8437     return target_bits;
8438 }
8439
8440 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8441 {
8442     int i;
8443     uint32_t fpscr;
8444
8445     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8446             | (env->vfp.vec_len << 16)
8447             | (env->vfp.vec_stride << 20);
8448     i = get_float_exception_flags(&env->vfp.fp_status);
8449     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8450     fpscr |= vfp_exceptbits_from_host(i);
8451     return fpscr;
8452 }
8453
8454 uint32_t vfp_get_fpscr(CPUARMState *env)
8455 {
8456     return HELPER(vfp_get_fpscr)(env);
8457 }
8458
8459 /* Convert vfp exception flags to target form.  */
8460 static inline int vfp_exceptbits_to_host(int target_bits)
8461 {
8462     int host_bits = 0;
8463
8464     if (target_bits & 1)
8465         host_bits |= float_flag_invalid;
8466     if (target_bits & 2)
8467         host_bits |= float_flag_divbyzero;
8468     if (target_bits & 4)
8469         host_bits |= float_flag_overflow;
8470     if (target_bits & 8)
8471         host_bits |= float_flag_underflow;
8472     if (target_bits & 0x10)
8473         host_bits |= float_flag_inexact;
8474     if (target_bits & 0x80)
8475         host_bits |= float_flag_input_denormal;
8476     return host_bits;
8477 }
8478
8479 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8480 {
8481     int i;
8482     uint32_t changed;
8483
8484     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8485     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8486     env->vfp.vec_len = (val >> 16) & 7;
8487     env->vfp.vec_stride = (val >> 20) & 3;
8488
8489     changed ^= val;
8490     if (changed & (3 << 22)) {
8491         i = (val >> 22) & 3;
8492         switch (i) {
8493         case FPROUNDING_TIEEVEN:
8494             i = float_round_nearest_even;
8495             break;
8496         case FPROUNDING_POSINF:
8497             i = float_round_up;
8498             break;
8499         case FPROUNDING_NEGINF:
8500             i = float_round_down;
8501             break;
8502         case FPROUNDING_ZERO:
8503             i = float_round_to_zero;
8504             break;
8505         }
8506         set_float_rounding_mode(i, &env->vfp.fp_status);
8507     }
8508     if (changed & (1 << 24)) {
8509         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8510         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8511     }
8512     if (changed & (1 << 25))
8513         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8514
8515     i = vfp_exceptbits_to_host(val);
8516     set_float_exception_flags(i, &env->vfp.fp_status);
8517     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8518 }
8519
8520 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8521 {
8522     HELPER(vfp_set_fpscr)(env, val);
8523 }
8524
8525 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8526
8527 #define VFP_BINOP(name) \
8528 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8529 { \
8530     float_status *fpst = fpstp; \
8531     return float32_ ## name(a, b, fpst); \
8532 } \
8533 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8534 { \
8535     float_status *fpst = fpstp; \
8536     return float64_ ## name(a, b, fpst); \
8537 }
8538 VFP_BINOP(add)
8539 VFP_BINOP(sub)
8540 VFP_BINOP(mul)
8541 VFP_BINOP(div)
8542 VFP_BINOP(min)
8543 VFP_BINOP(max)
8544 VFP_BINOP(minnum)
8545 VFP_BINOP(maxnum)
8546 #undef VFP_BINOP
8547
8548 float32 VFP_HELPER(neg, s)(float32 a)
8549 {
8550     return float32_chs(a);
8551 }
8552
8553 float64 VFP_HELPER(neg, d)(float64 a)
8554 {
8555     return float64_chs(a);
8556 }
8557
8558 float32 VFP_HELPER(abs, s)(float32 a)
8559 {
8560     return float32_abs(a);
8561 }
8562
8563 float64 VFP_HELPER(abs, d)(float64 a)
8564 {
8565     return float64_abs(a);
8566 }
8567
8568 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8569 {
8570     return float32_sqrt(a, &env->vfp.fp_status);
8571 }
8572
8573 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8574 {
8575     return float64_sqrt(a, &env->vfp.fp_status);
8576 }
8577
8578 /* XXX: check quiet/signaling case */
8579 #define DO_VFP_cmp(p, type) \
8580 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8581 { \
8582     uint32_t flags; \
8583     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8584     case 0: flags = 0x6; break; \
8585     case -1: flags = 0x8; break; \
8586     case 1: flags = 0x2; break; \
8587     default: case 2: flags = 0x3; break; \
8588     } \
8589     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8590         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8591 } \
8592 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8593 { \
8594     uint32_t flags; \
8595     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8596     case 0: flags = 0x6; break; \
8597     case -1: flags = 0x8; break; \
8598     case 1: flags = 0x2; break; \
8599     default: case 2: flags = 0x3; break; \
8600     } \
8601     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8602         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8603 }
8604 DO_VFP_cmp(s, float32)
8605 DO_VFP_cmp(d, float64)
8606 #undef DO_VFP_cmp
8607
8608 /* Integer to float and float to integer conversions */
8609
8610 #define CONV_ITOF(name, fsz, sign) \
8611     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8612 { \
8613     float_status *fpst = fpstp; \
8614     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8615 }
8616
8617 #define CONV_FTOI(name, fsz, sign, round) \
8618 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8619 { \
8620     float_status *fpst = fpstp; \
8621     if (float##fsz##_is_any_nan(x)) { \
8622         float_raise(float_flag_invalid, fpst); \
8623         return 0; \
8624     } \
8625     return float##fsz##_to_##sign##int32##round(x, fpst); \
8626 }
8627
8628 #define FLOAT_CONVS(name, p, fsz, sign) \
8629 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8630 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8631 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8632
8633 FLOAT_CONVS(si, s, 32, )
8634 FLOAT_CONVS(si, d, 64, )
8635 FLOAT_CONVS(ui, s, 32, u)
8636 FLOAT_CONVS(ui, d, 64, u)
8637
8638 #undef CONV_ITOF
8639 #undef CONV_FTOI
8640 #undef FLOAT_CONVS
8641
8642 /* floating point conversion */
8643 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8644 {
8645     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8646     /* ARM requires that S<->D conversion of any kind of NaN generates
8647      * a quiet NaN by forcing the most significant frac bit to 1.
8648      */
8649     return float64_maybe_silence_nan(r);
8650 }
8651
8652 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8653 {
8654     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8655     /* ARM requires that S<->D conversion of any kind of NaN generates
8656      * a quiet NaN by forcing the most significant frac bit to 1.
8657      */
8658     return float32_maybe_silence_nan(r);
8659 }
8660
8661 /* VFP3 fixed point conversion.  */
8662 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8663 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8664                                      void *fpstp) \
8665 { \
8666     float_status *fpst = fpstp; \
8667     float##fsz tmp; \
8668     tmp = itype##_to_##float##fsz(x, fpst); \
8669     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8670 }
8671
8672 /* Notice that we want only input-denormal exception flags from the
8673  * scalbn operation: the other possible flags (overflow+inexact if
8674  * we overflow to infinity, output-denormal) aren't correct for the
8675  * complete scale-and-convert operation.
8676  */
8677 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8678 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8679                                              uint32_t shift, \
8680                                              void *fpstp) \
8681 { \
8682     float_status *fpst = fpstp; \
8683     int old_exc_flags = get_float_exception_flags(fpst); \
8684     float##fsz tmp; \
8685     if (float##fsz##_is_any_nan(x)) { \
8686         float_raise(float_flag_invalid, fpst); \
8687         return 0; \
8688     } \
8689     tmp = float##fsz##_scalbn(x, shift, fpst); \
8690     old_exc_flags |= get_float_exception_flags(fpst) \
8691         & float_flag_input_denormal; \
8692     set_float_exception_flags(old_exc_flags, fpst); \
8693     return float##fsz##_to_##itype##round(tmp, fpst); \
8694 }
8695
8696 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8697 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8698 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8699 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8700
8701 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8702 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8703 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8704
8705 VFP_CONV_FIX(sh, d, 64, 64, int16)
8706 VFP_CONV_FIX(sl, d, 64, 64, int32)
8707 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8708 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8709 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8710 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8711 VFP_CONV_FIX(sh, s, 32, 32, int16)
8712 VFP_CONV_FIX(sl, s, 32, 32, int32)
8713 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8714 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8715 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8716 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8717 #undef VFP_CONV_FIX
8718 #undef VFP_CONV_FIX_FLOAT
8719 #undef VFP_CONV_FLOAT_FIX_ROUND
8720
8721 /* Set the current fp rounding mode and return the old one.
8722  * The argument is a softfloat float_round_ value.
8723  */
8724 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8725 {
8726     float_status *fp_status = &env->vfp.fp_status;
8727
8728     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8729     set_float_rounding_mode(rmode, fp_status);
8730
8731     return prev_rmode;
8732 }
8733
8734 /* Set the current fp rounding mode in the standard fp status and return
8735  * the old one. This is for NEON instructions that need to change the
8736  * rounding mode but wish to use the standard FPSCR values for everything
8737  * else. Always set the rounding mode back to the correct value after
8738  * modifying it.
8739  * The argument is a softfloat float_round_ value.
8740  */
8741 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8742 {
8743     float_status *fp_status = &env->vfp.standard_fp_status;
8744
8745     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8746     set_float_rounding_mode(rmode, fp_status);
8747
8748     return prev_rmode;
8749 }
8750
8751 /* Half precision conversions.  */
8752 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8753 {
8754     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8755     float32 r = float16_to_float32(make_float16(a), ieee, s);
8756     if (ieee) {
8757         return float32_maybe_silence_nan(r);
8758     }
8759     return r;
8760 }
8761
8762 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8763 {
8764     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8765     float16 r = float32_to_float16(a, ieee, s);
8766     if (ieee) {
8767         r = float16_maybe_silence_nan(r);
8768     }
8769     return float16_val(r);
8770 }
8771
8772 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8773 {
8774     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8775 }
8776
8777 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8778 {
8779     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8780 }
8781
8782 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8783 {
8784     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8785 }
8786
8787 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8788 {
8789     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8790 }
8791
8792 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8793 {
8794     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8795     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8796     if (ieee) {
8797         return float64_maybe_silence_nan(r);
8798     }
8799     return r;
8800 }
8801
8802 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8803 {
8804     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8805     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8806     if (ieee) {
8807         r = float16_maybe_silence_nan(r);
8808     }
8809     return float16_val(r);
8810 }
8811
8812 #define float32_two make_float32(0x40000000)
8813 #define float32_three make_float32(0x40400000)
8814 #define float32_one_point_five make_float32(0x3fc00000)
8815
8816 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8817 {
8818     float_status *s = &env->vfp.standard_fp_status;
8819     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8820         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8821         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8822             float_raise(float_flag_input_denormal, s);
8823         }
8824         return float32_two;
8825     }
8826     return float32_sub(float32_two, float32_mul(a, b, s), s);
8827 }
8828
8829 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8830 {
8831     float_status *s = &env->vfp.standard_fp_status;
8832     float32 product;
8833     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8834         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8835         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8836             float_raise(float_flag_input_denormal, s);
8837         }
8838         return float32_one_point_five;
8839     }
8840     product = float32_mul(a, b, s);
8841     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8842 }
8843
8844 /* NEON helpers.  */
8845
8846 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8847  * int->float conversions at run-time.  */
8848 #define float64_256 make_float64(0x4070000000000000LL)
8849 #define float64_512 make_float64(0x4080000000000000LL)
8850 #define float32_maxnorm make_float32(0x7f7fffff)
8851 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8852
8853 /* Reciprocal functions
8854  *
8855  * The algorithm that must be used to calculate the estimate
8856  * is specified by the ARM ARM, see FPRecipEstimate()
8857  */
8858
8859 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8860 {
8861     /* These calculations mustn't set any fp exception flags,
8862      * so we use a local copy of the fp_status.
8863      */
8864     float_status dummy_status = *real_fp_status;
8865     float_status *s = &dummy_status;
8866     /* q = (int)(a * 512.0) */
8867     float64 q = float64_mul(float64_512, a, s);
8868     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8869
8870     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8871     q = int64_to_float64(q_int, s);
8872     q = float64_add(q, float64_half, s);
8873     q = float64_div(q, float64_512, s);
8874     q = float64_div(float64_one, q, s);
8875
8876     /* s = (int)(256.0 * r + 0.5) */
8877     q = float64_mul(q, float64_256, s);
8878     q = float64_add(q, float64_half, s);
8879     q_int = float64_to_int64_round_to_zero(q, s);
8880
8881     /* return (double)s / 256.0 */
8882     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8883 }
8884
8885 /* Common wrapper to call recip_estimate */
8886 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8887 {
8888     uint64_t val64 = float64_val(num);
8889     uint64_t frac = extract64(val64, 0, 52);
8890     int64_t exp = extract64(val64, 52, 11);
8891     uint64_t sbit;
8892     float64 scaled, estimate;
8893
8894     /* Generate the scaled number for the estimate function */
8895     if (exp == 0) {
8896         if (extract64(frac, 51, 1) == 0) {
8897             exp = -1;
8898             frac = extract64(frac, 0, 50) << 2;
8899         } else {
8900             frac = extract64(frac, 0, 51) << 1;
8901         }
8902     }
8903
8904     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8905     scaled = make_float64((0x3feULL << 52)
8906                           | extract64(frac, 44, 8) << 44);
8907
8908     estimate = recip_estimate(scaled, fpst);
8909
8910     /* Build new result */
8911     val64 = float64_val(estimate);
8912     sbit = 0x8000000000000000ULL & val64;
8913     exp = off - exp;
8914     frac = extract64(val64, 0, 52);
8915
8916     if (exp == 0) {
8917         frac = 1ULL << 51 | extract64(frac, 1, 51);
8918     } else if (exp == -1) {
8919         frac = 1ULL << 50 | extract64(frac, 2, 50);
8920         exp = 0;
8921     }
8922
8923     return make_float64(sbit | (exp << 52) | frac);
8924 }
8925
8926 static bool round_to_inf(float_status *fpst, bool sign_bit)
8927 {
8928     switch (fpst->float_rounding_mode) {
8929     case float_round_nearest_even: /* Round to Nearest */
8930         return true;
8931     case float_round_up: /* Round to +Inf */
8932         return !sign_bit;
8933     case float_round_down: /* Round to -Inf */
8934         return sign_bit;
8935     case float_round_to_zero: /* Round to Zero */
8936         return false;
8937     }
8938
8939     g_assert_not_reached();
8940 }
8941
8942 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8943 {
8944     float_status *fpst = fpstp;
8945     float32 f32 = float32_squash_input_denormal(input, fpst);
8946     uint32_t f32_val = float32_val(f32);
8947     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8948     int32_t f32_exp = extract32(f32_val, 23, 8);
8949     uint32_t f32_frac = extract32(f32_val, 0, 23);
8950     float64 f64, r64;
8951     uint64_t r64_val;
8952     int64_t r64_exp;
8953     uint64_t r64_frac;
8954
8955     if (float32_is_any_nan(f32)) {
8956         float32 nan = f32;
8957         if (float32_is_signaling_nan(f32)) {
8958             float_raise(float_flag_invalid, fpst);
8959             nan = float32_maybe_silence_nan(f32);
8960         }
8961         if (fpst->default_nan_mode) {
8962             nan =  float32_default_nan;
8963         }
8964         return nan;
8965     } else if (float32_is_infinity(f32)) {
8966         return float32_set_sign(float32_zero, float32_is_neg(f32));
8967     } else if (float32_is_zero(f32)) {
8968         float_raise(float_flag_divbyzero, fpst);
8969         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8970     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8971         /* Abs(value) < 2.0^-128 */
8972         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8973         if (round_to_inf(fpst, f32_sbit)) {
8974             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8975         } else {
8976             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8977         }
8978     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8979         float_raise(float_flag_underflow, fpst);
8980         return float32_set_sign(float32_zero, float32_is_neg(f32));
8981     }
8982
8983
8984     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8985     r64 = call_recip_estimate(f64, 253, fpst);
8986     r64_val = float64_val(r64);
8987     r64_exp = extract64(r64_val, 52, 11);
8988     r64_frac = extract64(r64_val, 0, 52);
8989
8990     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8991     return make_float32(f32_sbit |
8992                         (r64_exp & 0xff) << 23 |
8993                         extract64(r64_frac, 29, 24));
8994 }
8995
8996 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8997 {
8998     float_status *fpst = fpstp;
8999     float64 f64 = float64_squash_input_denormal(input, fpst);
9000     uint64_t f64_val = float64_val(f64);
9001     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
9002     int64_t f64_exp = extract64(f64_val, 52, 11);
9003     float64 r64;
9004     uint64_t r64_val;
9005     int64_t r64_exp;
9006     uint64_t r64_frac;
9007
9008     /* Deal with any special cases */
9009     if (float64_is_any_nan(f64)) {
9010         float64 nan = f64;
9011         if (float64_is_signaling_nan(f64)) {
9012             float_raise(float_flag_invalid, fpst);
9013             nan = float64_maybe_silence_nan(f64);
9014         }
9015         if (fpst->default_nan_mode) {
9016             nan =  float64_default_nan;
9017         }
9018         return nan;
9019     } else if (float64_is_infinity(f64)) {
9020         return float64_set_sign(float64_zero, float64_is_neg(f64));
9021     } else if (float64_is_zero(f64)) {
9022         float_raise(float_flag_divbyzero, fpst);
9023         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9024     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
9025         /* Abs(value) < 2.0^-1024 */
9026         float_raise(float_flag_overflow | float_flag_inexact, fpst);
9027         if (round_to_inf(fpst, f64_sbit)) {
9028             return float64_set_sign(float64_infinity, float64_is_neg(f64));
9029         } else {
9030             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
9031         }
9032     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
9033         float_raise(float_flag_underflow, fpst);
9034         return float64_set_sign(float64_zero, float64_is_neg(f64));
9035     }
9036
9037     r64 = call_recip_estimate(f64, 2045, fpst);
9038     r64_val = float64_val(r64);
9039     r64_exp = extract64(r64_val, 52, 11);
9040     r64_frac = extract64(r64_val, 0, 52);
9041
9042     /* result = sign : result_exp<10:0> : fraction<51:0> */
9043     return make_float64(f64_sbit |
9044                         ((r64_exp & 0x7ff) << 52) |
9045                         r64_frac);
9046 }
9047
9048 /* The algorithm that must be used to calculate the estimate
9049  * is specified by the ARM ARM.
9050  */
9051 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
9052 {
9053     /* These calculations mustn't set any fp exception flags,
9054      * so we use a local copy of the fp_status.
9055      */
9056     float_status dummy_status = *real_fp_status;
9057     float_status *s = &dummy_status;
9058     float64 q;
9059     int64_t q_int;
9060
9061     if (float64_lt(a, float64_half, s)) {
9062         /* range 0.25 <= a < 0.5 */
9063
9064         /* a in units of 1/512 rounded down */
9065         /* q0 = (int)(a * 512.0);  */
9066         q = float64_mul(float64_512, a, s);
9067         q_int = float64_to_int64_round_to_zero(q, s);
9068
9069         /* reciprocal root r */
9070         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
9071         q = int64_to_float64(q_int, s);
9072         q = float64_add(q, float64_half, s);
9073         q = float64_div(q, float64_512, s);
9074         q = float64_sqrt(q, s);
9075         q = float64_div(float64_one, q, s);
9076     } else {
9077         /* range 0.5 <= a < 1.0 */
9078
9079         /* a in units of 1/256 rounded down */
9080         /* q1 = (int)(a * 256.0); */
9081         q = float64_mul(float64_256, a, s);
9082         int64_t q_int = float64_to_int64_round_to_zero(q, s);
9083
9084         /* reciprocal root r */
9085         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9086         q = int64_to_float64(q_int, s);
9087         q = float64_add(q, float64_half, s);
9088         q = float64_div(q, float64_256, s);
9089         q = float64_sqrt(q, s);
9090         q = float64_div(float64_one, q, s);
9091     }
9092     /* r in units of 1/256 rounded to nearest */
9093     /* s = (int)(256.0 * r + 0.5); */
9094
9095     q = float64_mul(q, float64_256,s );
9096     q = float64_add(q, float64_half, s);
9097     q_int = float64_to_int64_round_to_zero(q, s);
9098
9099     /* return (double)s / 256.0;*/
9100     return float64_div(int64_to_float64(q_int, s), float64_256, s);
9101 }
9102
9103 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
9104 {
9105     float_status *s = fpstp;
9106     float32 f32 = float32_squash_input_denormal(input, s);
9107     uint32_t val = float32_val(f32);
9108     uint32_t f32_sbit = 0x80000000 & val;
9109     int32_t f32_exp = extract32(val, 23, 8);
9110     uint32_t f32_frac = extract32(val, 0, 23);
9111     uint64_t f64_frac;
9112     uint64_t val64;
9113     int result_exp;
9114     float64 f64;
9115
9116     if (float32_is_any_nan(f32)) {
9117         float32 nan = f32;
9118         if (float32_is_signaling_nan(f32)) {
9119             float_raise(float_flag_invalid, s);
9120             nan = float32_maybe_silence_nan(f32);
9121         }
9122         if (s->default_nan_mode) {
9123             nan =  float32_default_nan;
9124         }
9125         return nan;
9126     } else if (float32_is_zero(f32)) {
9127         float_raise(float_flag_divbyzero, s);
9128         return float32_set_sign(float32_infinity, float32_is_neg(f32));
9129     } else if (float32_is_neg(f32)) {
9130         float_raise(float_flag_invalid, s);
9131         return float32_default_nan;
9132     } else if (float32_is_infinity(f32)) {
9133         return float32_zero;
9134     }
9135
9136     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9137      * preserving the parity of the exponent.  */
9138
9139     f64_frac = ((uint64_t) f32_frac) << 29;
9140     if (f32_exp == 0) {
9141         while (extract64(f64_frac, 51, 1) == 0) {
9142             f64_frac = f64_frac << 1;
9143             f32_exp = f32_exp-1;
9144         }
9145         f64_frac = extract64(f64_frac, 0, 51) << 1;
9146     }
9147
9148     if (extract64(f32_exp, 0, 1) == 0) {
9149         f64 = make_float64(((uint64_t) f32_sbit) << 32
9150                            | (0x3feULL << 52)
9151                            | f64_frac);
9152     } else {
9153         f64 = make_float64(((uint64_t) f32_sbit) << 32
9154                            | (0x3fdULL << 52)
9155                            | f64_frac);
9156     }
9157
9158     result_exp = (380 - f32_exp) / 2;
9159
9160     f64 = recip_sqrt_estimate(f64, s);
9161
9162     val64 = float64_val(f64);
9163
9164     val = ((result_exp & 0xff) << 23)
9165         | ((val64 >> 29)  & 0x7fffff);
9166     return make_float32(val);
9167 }
9168
9169 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
9170 {
9171     float_status *s = fpstp;
9172     float64 f64 = float64_squash_input_denormal(input, s);
9173     uint64_t val = float64_val(f64);
9174     uint64_t f64_sbit = 0x8000000000000000ULL & val;
9175     int64_t f64_exp = extract64(val, 52, 11);
9176     uint64_t f64_frac = extract64(val, 0, 52);
9177     int64_t result_exp;
9178     uint64_t result_frac;
9179
9180     if (float64_is_any_nan(f64)) {
9181         float64 nan = f64;
9182         if (float64_is_signaling_nan(f64)) {
9183             float_raise(float_flag_invalid, s);
9184             nan = float64_maybe_silence_nan(f64);
9185         }
9186         if (s->default_nan_mode) {
9187             nan =  float64_default_nan;
9188         }
9189         return nan;
9190     } else if (float64_is_zero(f64)) {
9191         float_raise(float_flag_divbyzero, s);
9192         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9193     } else if (float64_is_neg(f64)) {
9194         float_raise(float_flag_invalid, s);
9195         return float64_default_nan;
9196     } else if (float64_is_infinity(f64)) {
9197         return float64_zero;
9198     }
9199
9200     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9201      * preserving the parity of the exponent.  */
9202
9203     if (f64_exp == 0) {
9204         while (extract64(f64_frac, 51, 1) == 0) {
9205             f64_frac = f64_frac << 1;
9206             f64_exp = f64_exp - 1;
9207         }
9208         f64_frac = extract64(f64_frac, 0, 51) << 1;
9209     }
9210
9211     if (extract64(f64_exp, 0, 1) == 0) {
9212         f64 = make_float64(f64_sbit
9213                            | (0x3feULL << 52)
9214                            | f64_frac);
9215     } else {
9216         f64 = make_float64(f64_sbit
9217                            | (0x3fdULL << 52)
9218                            | f64_frac);
9219     }
9220
9221     result_exp = (3068 - f64_exp) / 2;
9222
9223     f64 = recip_sqrt_estimate(f64, s);
9224
9225     result_frac = extract64(float64_val(f64), 0, 52);
9226
9227     return make_float64(f64_sbit |
9228                         ((result_exp & 0x7ff) << 52) |
9229                         result_frac);
9230 }
9231
9232 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
9233 {
9234     float_status *s = fpstp;
9235     float64 f64;
9236
9237     if ((a & 0x80000000) == 0) {
9238         return 0xffffffff;
9239     }
9240
9241     f64 = make_float64((0x3feULL << 52)
9242                        | ((int64_t)(a & 0x7fffffff) << 21));
9243
9244     f64 = recip_estimate(f64, s);
9245
9246     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9247 }
9248
9249 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
9250 {
9251     float_status *fpst = fpstp;
9252     float64 f64;
9253
9254     if ((a & 0xc0000000) == 0) {
9255         return 0xffffffff;
9256     }
9257
9258     if (a & 0x80000000) {
9259         f64 = make_float64((0x3feULL << 52)
9260                            | ((uint64_t)(a & 0x7fffffff) << 21));
9261     } else { /* bits 31-30 == '01' */
9262         f64 = make_float64((0x3fdULL << 52)
9263                            | ((uint64_t)(a & 0x3fffffff) << 22));
9264     }
9265
9266     f64 = recip_sqrt_estimate(f64, fpst);
9267
9268     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9269 }
9270
9271 /* VFPv4 fused multiply-accumulate */
9272 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
9273 {
9274     float_status *fpst = fpstp;
9275     return float32_muladd(a, b, c, 0, fpst);
9276 }
9277
9278 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
9279 {
9280     float_status *fpst = fpstp;
9281     return float64_muladd(a, b, c, 0, fpst);
9282 }
9283
9284 /* ARMv8 round to integral */
9285 float32 HELPER(rints_exact)(float32 x, void *fp_status)
9286 {
9287     return float32_round_to_int(x, fp_status);
9288 }
9289
9290 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
9291 {
9292     return float64_round_to_int(x, fp_status);
9293 }
9294
9295 float32 HELPER(rints)(float32 x, void *fp_status)
9296 {
9297     int old_flags = get_float_exception_flags(fp_status), new_flags;
9298     float32 ret;
9299
9300     ret = float32_round_to_int(x, fp_status);
9301
9302     /* Suppress any inexact exceptions the conversion produced */
9303     if (!(old_flags & float_flag_inexact)) {
9304         new_flags = get_float_exception_flags(fp_status);
9305         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9306     }
9307
9308     return ret;
9309 }
9310
9311 float64 HELPER(rintd)(float64 x, void *fp_status)
9312 {
9313     int old_flags = get_float_exception_flags(fp_status), new_flags;
9314     float64 ret;
9315
9316     ret = float64_round_to_int(x, fp_status);
9317
9318     new_flags = get_float_exception_flags(fp_status);
9319
9320     /* Suppress any inexact exceptions the conversion produced */
9321     if (!(old_flags & float_flag_inexact)) {
9322         new_flags = get_float_exception_flags(fp_status);
9323         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9324     }
9325
9326     return ret;
9327 }
9328
9329 /* Convert ARM rounding mode to softfloat */
9330 int arm_rmode_to_sf(int rmode)
9331 {
9332     switch (rmode) {
9333     case FPROUNDING_TIEAWAY:
9334         rmode = float_round_ties_away;
9335         break;
9336     case FPROUNDING_ODD:
9337         /* FIXME: add support for TIEAWAY and ODD */
9338         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
9339                       rmode);
9340     case FPROUNDING_TIEEVEN:
9341     default:
9342         rmode = float_round_nearest_even;
9343         break;
9344     case FPROUNDING_POSINF:
9345         rmode = float_round_up;
9346         break;
9347     case FPROUNDING_NEGINF:
9348         rmode = float_round_down;
9349         break;
9350     case FPROUNDING_ZERO:
9351         rmode = float_round_to_zero;
9352         break;
9353     }
9354     return rmode;
9355 }
9356
9357 /* CRC helpers.
9358  * The upper bytes of val (above the number specified by 'bytes') must have
9359  * been zeroed out by the caller.
9360  */
9361 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
9362 {
9363     uint8_t buf[4];
9364
9365     stl_le_p(buf, val);
9366
9367     /* zlib crc32 converts the accumulator and output to one's complement.  */
9368     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
9369 }
9370
9371 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
9372 {
9373     uint8_t buf[4];
9374
9375     stl_le_p(buf, val);
9376
9377     /* Linux crc32c converts the output to one's complement.  */
9378     return crc32c(acc, buf, bytes) ^ 0xffffffff;
9379 }