2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "kvm-consts.h"
25 #if defined(TARGET_AARCH64)
26 /* AArch64 definitions */
27 # define TARGET_LONG_BITS 64
29 # define TARGET_LONG_BITS 32
32 #define TARGET_IS_BIENDIAN 1
34 #define CPUArchState struct CPUARMState
36 #include "qemu-common.h"
37 #include "exec/cpu-defs.h"
39 #include "fpu/softfloat.h"
41 #define EXCP_UDEF 1 /* undefined instruction */
42 #define EXCP_SWI 2 /* software interrupt */
43 #define EXCP_PREFETCH_ABORT 3
44 #define EXCP_DATA_ABORT 4
48 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
49 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
51 #define EXCP_HVC 11 /* HyperVisor Call */
52 #define EXCP_HYP_TRAP 12
53 #define EXCP_SMC 13 /* Secure Monitor Call */
56 #define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
58 #define ARMV7M_EXCP_RESET 1
59 #define ARMV7M_EXCP_NMI 2
60 #define ARMV7M_EXCP_HARD 3
61 #define ARMV7M_EXCP_MEM 4
62 #define ARMV7M_EXCP_BUS 5
63 #define ARMV7M_EXCP_USAGE 6
64 #define ARMV7M_EXCP_SVC 11
65 #define ARMV7M_EXCP_DEBUG 12
66 #define ARMV7M_EXCP_PENDSV 14
67 #define ARMV7M_EXCP_SYSTICK 15
69 /* ARM-specific interrupt pending bits. */
70 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
71 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
72 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
74 /* The usual mapping for an AArch64 system register to its AArch32
75 * counterpart is for the 32 bit world to have access to the lower
76 * half only (with writes leaving the upper half untouched). It's
77 * therefore useful to be able to pass TCG the offset of the least
78 * significant half of a uint64_t struct member.
80 #ifdef HOST_WORDS_BIGENDIAN
81 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
82 #define offsetofhigh32(S, M) offsetof(S, M)
84 #define offsetoflow32(S, M) offsetof(S, M)
85 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
88 /* Meanings of the ARMCPU object's four inbound GPIO lines */
91 #define ARM_CPU_VIRQ 2
92 #define ARM_CPU_VFIQ 3
96 #define NB_MMU_MODES 7
97 #define TARGET_INSN_START_EXTRA_WORDS 1
99 /* We currently assume float and double are IEEE single and double
100 precision respectively.
101 Doing runtime conversions is tricky because VFP registers may contain
102 integer values (eg. as the result of a FTOSI instruction).
103 s<2n> maps to the least significant half of d<n>
104 s<2n+1> maps to the most significant half of d<n>
107 /* CPU state for each instance of a generic timer (in cp15 c14) */
108 typedef struct ARMGenericTimer
{
109 uint64_t cval
; /* Timer CompareValue register */
110 uint64_t ctl
; /* Timer Control register */
113 #define GTIMER_PHYS 0
114 #define GTIMER_VIRT 1
117 #define NUM_GTIMERS 4
125 typedef struct CPUARMState
{
126 /* Regs for current mode. */
129 /* 32/64 switch only happens when taking and returning from
130 * exceptions so the overlap semantics are taken care of then
131 * instead of having a complicated union.
133 /* Regs for A64 mode. */
136 /* PSTATE isn't an architectural register for ARMv8. However, it is
137 * convenient for us to assemble the underlying state into a 32 bit format
138 * identical to the architectural format used for the SPSR. (This is also
139 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
140 * 'pstate' register are.) Of the PSTATE bits:
141 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
142 * semantics as for AArch32, as described in the comments on each field)
143 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
144 * DAIF (exception masks) are kept in env->daif
145 * all other bits are stored in their correct places in env->pstate
148 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
150 /* Frequently accessed CPSR bits are stored separately for efficiency.
151 This contains all the other bits. Use cpsr_{read,write} to access
153 uint32_t uncached_cpsr
;
156 /* Banked registers. */
157 uint64_t banked_spsr
[8];
158 uint32_t banked_r13
[8];
159 uint32_t banked_r14
[8];
161 /* These hold r8-r12. */
162 uint32_t usr_regs
[5];
163 uint32_t fiq_regs
[5];
165 /* cpsr flag cache for faster execution */
166 uint32_t CF
; /* 0 or 1 */
167 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
168 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
169 uint32_t ZF
; /* Z set if zero. */
170 uint32_t QF
; /* 0 or 1 */
171 uint32_t GE
; /* cpsr[19:16] */
172 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
173 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
174 uint64_t daif
; /* exception masks, in the bits they are in PSTATE */
176 uint64_t elr_el
[4]; /* AArch64 exception link regs */
177 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
179 /* System control coprocessor (cp15) */
182 union { /* Cache size selection */
184 uint64_t _unused_csselr0
;
186 uint64_t _unused_csselr1
;
189 uint64_t csselr_el
[4];
191 union { /* System control register. */
193 uint64_t _unused_sctlr
;
198 uint64_t sctlr_el
[4];
200 uint64_t cpacr_el1
; /* Architectural feature access control register */
201 uint64_t cptr_el
[4]; /* ARMv8 feature trap registers */
202 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
203 uint64_t sder
; /* Secure debug enable register. */
204 uint32_t nsacr
; /* Non-secure access control register. */
205 union { /* MMU translation table base 0. */
207 uint64_t _unused_ttbr0_0
;
209 uint64_t _unused_ttbr0_1
;
212 uint64_t ttbr0_el
[4];
214 union { /* MMU translation table base 1. */
216 uint64_t _unused_ttbr1_0
;
218 uint64_t _unused_ttbr1_1
;
221 uint64_t ttbr1_el
[4];
223 uint64_t vttbr_el2
; /* Virtualization Translation Table Base. */
224 /* MMU translation table base control. */
226 TCR vtcr_el2
; /* Virtualization Translation Control. */
227 uint32_t c2_data
; /* MPU data cacheable bits. */
228 uint32_t c2_insn
; /* MPU instruction cacheable bits. */
229 union { /* MMU domain access control register
230 * MPU write buffer control.
240 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
241 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
242 uint64_t hcr_el2
; /* Hypervisor configuration register */
243 uint64_t scr_el3
; /* Secure configuration register. */
244 union { /* Fault status registers. */
255 uint64_t _unused_dfsr
;
262 uint32_t c6_region
[8]; /* MPU base/size registers. */
263 union { /* Fault address registers. */
265 uint64_t _unused_far0
;
266 #ifdef HOST_WORDS_BIGENDIAN
277 uint64_t _unused_far3
;
282 union { /* Translation result. */
284 uint64_t _unused_par_0
;
286 uint64_t _unused_par_1
;
294 uint32_t c9_insn
; /* Cache lockdown registers. */
296 uint64_t c9_pmcr
; /* performance monitor control register */
297 uint64_t c9_pmcnten
; /* perf monitor counter enables */
298 uint32_t c9_pmovsr
; /* perf monitor overflow status */
299 uint32_t c9_pmxevtyper
; /* perf monitor event type */
300 uint32_t c9_pmuserenr
; /* perf monitor user enable */
301 uint32_t c9_pminten
; /* perf monitor interrupt enables */
302 union { /* Memory attribute redirection */
304 #ifdef HOST_WORDS_BIGENDIAN
305 uint64_t _unused_mair_0
;
308 uint64_t _unused_mair_1
;
312 uint64_t _unused_mair_0
;
315 uint64_t _unused_mair_1
;
322 union { /* vector base address register */
324 uint64_t _unused_vbar
;
331 uint32_t mvbar
; /* (monitor) vector base address register */
332 struct { /* FCSE PID. */
336 union { /* Context ID. */
338 uint64_t _unused_contextidr_0
;
339 uint64_t contextidr_ns
;
340 uint64_t _unused_contextidr_1
;
341 uint64_t contextidr_s
;
343 uint64_t contextidr_el
[4];
345 union { /* User RW Thread register. */
347 uint64_t tpidrurw_ns
;
348 uint64_t tpidrprw_ns
;
352 uint64_t tpidr_el
[4];
354 /* The secure banks of these registers don't map anywhere */
359 union { /* User RO Thread register. */
360 uint64_t tpidruro_ns
;
361 uint64_t tpidrro_el
[1];
363 uint64_t c14_cntfrq
; /* Counter Frequency register */
364 uint64_t c14_cntkctl
; /* Timer Control register */
365 uint32_t cnthctl_el2
; /* Counter/Timer Hyp Control register */
366 uint64_t cntvoff_el2
; /* Counter Virtual Offset register */
367 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
368 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
369 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
370 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
371 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
372 uint32_t c15_threadid
; /* TI debugger thread-ID. */
373 uint32_t c15_config_base_address
; /* SCU base address. */
374 uint32_t c15_diagnostic
; /* diagnostic register */
375 uint32_t c15_power_diagnostic
;
376 uint32_t c15_power_control
; /* power control */
377 uint64_t dbgbvr
[16]; /* breakpoint value registers */
378 uint64_t dbgbcr
[16]; /* breakpoint control registers */
379 uint64_t dbgwvr
[16]; /* watchpoint value registers */
380 uint64_t dbgwcr
[16]; /* watchpoint control registers */
382 uint64_t oslsr_el1
; /* OS Lock Status */
385 /* If the counter is enabled, this stores the last time the counter
386 * was reset. Otherwise it stores the counter value
389 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
390 uint64_t vpidr_el2
; /* Virtualization Processor ID Register */
391 uint64_t vmpidr_el2
; /* Virtualization Multiprocessor ID Register */
403 /* Information associated with an exception about to be taken:
404 * code which raises an exception must set cs->exception_index and
405 * the relevant parts of this structure; the cpu_do_interrupt function
406 * will then set the guest-visible registers as part of the exception
410 uint32_t syndrome
; /* AArch64 format syndrome register */
411 uint32_t fsr
; /* AArch32 format fault status register info */
412 uint64_t vaddress
; /* virtual addr associated with exception, if any */
413 uint32_t target_el
; /* EL the exception should be targeted for */
414 /* If we implement EL2 we will also need to store information
415 * about the intermediate physical address for stage 2 faults.
419 /* Thumb-2 EE state. */
423 /* VFP coprocessor state. */
425 /* VFP/Neon register state. Note that the mapping between S, D and Q
426 * views of the register bank differs between AArch64 and AArch32:
428 * Qn = regs[2n+1]:regs[2n]
430 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
431 * (and regs[32] to regs[63] are inaccessible)
433 * Qn = regs[2n+1]:regs[2n]
435 * Sn = regs[2n] bits 31..0
436 * This corresponds to the architecturally defined mapping between
437 * the two execution states, and means we do not need to explicitly
438 * map these registers when changing states.
443 /* We store these fpcsr fields separately for convenience. */
447 /* scratch space when Tn are not sufficient. */
450 /* fp_status is the "normal" fp status. standard_fp_status retains
451 * values corresponding to the ARM "Standard FPSCR Value", ie
452 * default-NaN, flush-to-zero, round-to-nearest and is used by
453 * any operations (generally Neon) which the architecture defines
454 * as controlled by the standard FPSCR value rather than the FPSCR.
456 * To avoid having to transfer exception bits around, we simply
457 * say that the FPSCR cumulative exception flags are the logical
458 * OR of the flags in the two fp statuses. This relies on the
459 * only thing which needs to read the exception flags being
460 * an explicit FPSCR read.
462 float_status fp_status
;
463 float_status standard_fp_status
;
465 uint64_t exclusive_addr
;
466 uint64_t exclusive_val
;
467 uint64_t exclusive_high
;
468 #if defined(CONFIG_USER_ONLY)
469 uint64_t exclusive_test
;
470 uint32_t exclusive_info
;
473 /* iwMMXt coprocessor state. */
481 #if defined(CONFIG_USER_ONLY)
482 /* For usermode syscall translation. */
486 struct CPUBreakpoint
*cpu_breakpoint
[16];
487 struct CPUWatchpoint
*cpu_watchpoint
[16];
491 /* These fields after the common ones so they are preserved on reset. */
493 /* Internal CPU feature flags. */
504 const struct arm_boot_info
*boot_info
;
509 ARMCPU
*cpu_arm_init(const char *cpu_model
);
510 int cpu_arm_exec(CPUState
*cpu
);
511 target_ulong
do_arm_semihosting(CPUARMState
*env
);
512 void aarch64_sync_32_to_64(CPUARMState
*env
);
513 void aarch64_sync_64_to_32(CPUARMState
*env
);
515 static inline bool is_a64(CPUARMState
*env
)
520 /* you can call this signal handler from your SIGBUS and SIGSEGV
521 signal handlers to inform the virtual CPU of exceptions. non zero
522 is returned if the signal was handled by the virtual CPU. */
523 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
530 * Synchronises the counter in the PMCCNTR. This must always be called twice,
531 * once before any action that might affect the timer and again afterwards.
532 * The function is used to swap the state of the register if required.
533 * This only happens when not in user mode (!CONFIG_USER_ONLY)
535 void pmccntr_sync(CPUARMState
*env
);
537 /* SCTLR bit meanings. Several bits have been reused in newer
538 * versions of the architecture; in that case we define constants
539 * for both old and new bit meanings. Code which tests against those
540 * bits should probably check or otherwise arrange that the CPU
541 * is the architectural version it expects.
543 #define SCTLR_M (1U << 0)
544 #define SCTLR_A (1U << 1)
545 #define SCTLR_C (1U << 2)
546 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
547 #define SCTLR_SA (1U << 3)
548 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
549 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
550 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
551 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
552 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
553 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
554 #define SCTLR_ITD (1U << 7) /* v8 onward */
555 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
556 #define SCTLR_SED (1U << 8) /* v8 onward */
557 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
558 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
559 #define SCTLR_F (1U << 10) /* up to v6 */
560 #define SCTLR_SW (1U << 10) /* v7 onward */
561 #define SCTLR_Z (1U << 11)
562 #define SCTLR_I (1U << 12)
563 #define SCTLR_V (1U << 13)
564 #define SCTLR_RR (1U << 14) /* up to v7 */
565 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
566 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
567 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
568 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
569 #define SCTLR_nTWI (1U << 16) /* v8 onward */
570 #define SCTLR_HA (1U << 17)
571 #define SCTLR_BR (1U << 17) /* PMSA only */
572 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
573 #define SCTLR_nTWE (1U << 18) /* v8 onward */
574 #define SCTLR_WXN (1U << 19)
575 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
576 #define SCTLR_UWXN (1U << 20) /* v7 onward */
577 #define SCTLR_FI (1U << 21)
578 #define SCTLR_U (1U << 22)
579 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
580 #define SCTLR_VE (1U << 24) /* up to v7 */
581 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
582 #define SCTLR_EE (1U << 25)
583 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
584 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
585 #define SCTLR_NMFI (1U << 27)
586 #define SCTLR_TRE (1U << 28)
587 #define SCTLR_AFE (1U << 29)
588 #define SCTLR_TE (1U << 30)
590 #define CPTR_TCPAC (1U << 31)
591 #define CPTR_TTA (1U << 20)
592 #define CPTR_TFP (1U << 10)
594 #define MDCR_EPMAD (1U << 21)
595 #define MDCR_EDAD (1U << 20)
596 #define MDCR_SPME (1U << 17)
597 #define MDCR_SDD (1U << 16)
598 #define MDCR_SPD (3U << 14)
599 #define MDCR_TDRA (1U << 11)
600 #define MDCR_TDOSA (1U << 10)
601 #define MDCR_TDA (1U << 9)
602 #define MDCR_TDE (1U << 8)
603 #define MDCR_HPME (1U << 7)
604 #define MDCR_TPM (1U << 6)
605 #define MDCR_TPMCR (1U << 5)
607 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
608 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
610 #define CPSR_M (0x1fU)
611 #define CPSR_T (1U << 5)
612 #define CPSR_F (1U << 6)
613 #define CPSR_I (1U << 7)
614 #define CPSR_A (1U << 8)
615 #define CPSR_E (1U << 9)
616 #define CPSR_IT_2_7 (0xfc00U)
617 #define CPSR_GE (0xfU << 16)
618 #define CPSR_IL (1U << 20)
619 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
620 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
621 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
622 * where it is live state but not accessible to the AArch32 code.
624 #define CPSR_RESERVED (0x7U << 21)
625 #define CPSR_J (1U << 24)
626 #define CPSR_IT_0_1 (3U << 25)
627 #define CPSR_Q (1U << 27)
628 #define CPSR_V (1U << 28)
629 #define CPSR_C (1U << 29)
630 #define CPSR_Z (1U << 30)
631 #define CPSR_N (1U << 31)
632 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
633 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
635 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
636 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
638 /* Bits writable in user mode. */
639 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
640 /* Execution state bits. MRS read as zero, MSR writes ignored. */
641 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
642 /* Mask of bits which may be set by exception return copying them from SPSR */
643 #define CPSR_ERET_MASK (~CPSR_RESERVED)
645 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
646 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
647 #define TTBCR_PD0 (1U << 4)
648 #define TTBCR_PD1 (1U << 5)
649 #define TTBCR_EPD0 (1U << 7)
650 #define TTBCR_IRGN0 (3U << 8)
651 #define TTBCR_ORGN0 (3U << 10)
652 #define TTBCR_SH0 (3U << 12)
653 #define TTBCR_T1SZ (3U << 16)
654 #define TTBCR_A1 (1U << 22)
655 #define TTBCR_EPD1 (1U << 23)
656 #define TTBCR_IRGN1 (3U << 24)
657 #define TTBCR_ORGN1 (3U << 26)
658 #define TTBCR_SH1 (1U << 28)
659 #define TTBCR_EAE (1U << 31)
661 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
662 * Only these are valid when in AArch64 mode; in
663 * AArch32 mode SPSRs are basically CPSR-format.
665 #define PSTATE_SP (1U)
666 #define PSTATE_M (0xFU)
667 #define PSTATE_nRW (1U << 4)
668 #define PSTATE_F (1U << 6)
669 #define PSTATE_I (1U << 7)
670 #define PSTATE_A (1U << 8)
671 #define PSTATE_D (1U << 9)
672 #define PSTATE_IL (1U << 20)
673 #define PSTATE_SS (1U << 21)
674 #define PSTATE_V (1U << 28)
675 #define PSTATE_C (1U << 29)
676 #define PSTATE_Z (1U << 30)
677 #define PSTATE_N (1U << 31)
678 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
679 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
680 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
681 /* Mode values for AArch64 */
682 #define PSTATE_MODE_EL3h 13
683 #define PSTATE_MODE_EL3t 12
684 #define PSTATE_MODE_EL2h 9
685 #define PSTATE_MODE_EL2t 8
686 #define PSTATE_MODE_EL1h 5
687 #define PSTATE_MODE_EL1t 4
688 #define PSTATE_MODE_EL0t 0
690 /* Map EL and handler into a PSTATE_MODE. */
691 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
693 return (el
<< 2) | handler
;
696 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
697 * interprocessing, so we don't attempt to sync with the cpsr state used by
698 * the 32 bit decoder.
700 static inline uint32_t pstate_read(CPUARMState
*env
)
705 return (env
->NF
& 0x80000000) | (ZF
<< 30)
706 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
707 | env
->pstate
| env
->daif
;
710 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
712 env
->ZF
= (~val
) & PSTATE_Z
;
714 env
->CF
= (val
>> 29) & 1;
715 env
->VF
= (val
<< 3) & 0x80000000;
716 env
->daif
= val
& PSTATE_DAIF
;
717 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
720 /* Return the current CPSR value. */
721 uint32_t cpsr_read(CPUARMState
*env
);
723 typedef enum CPSRWriteType
{
724 CPSRWriteByInstr
= 0, /* from guest MSR or CPS */
725 CPSRWriteExceptionReturn
= 1, /* from guest exception return insn */
726 CPSRWriteRaw
= 2, /* trust values, do not switch reg banks */
727 CPSRWriteByGDBStub
= 3, /* from the GDB stub */
730 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
731 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
732 CPSRWriteType write_type
);
734 /* Return the current xPSR value. */
735 static inline uint32_t xpsr_read(CPUARMState
*env
)
739 return (env
->NF
& 0x80000000) | (ZF
<< 30)
740 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
741 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
742 | ((env
->condexec_bits
& 0xfc) << 8)
743 | env
->v7m
.exception
;
746 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
747 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
749 if (mask
& CPSR_NZCV
) {
750 env
->ZF
= (~val
) & CPSR_Z
;
752 env
->CF
= (val
>> 29) & 1;
753 env
->VF
= (val
<< 3) & 0x80000000;
756 env
->QF
= ((val
& CPSR_Q
) != 0);
757 if (mask
& (1 << 24))
758 env
->thumb
= ((val
& (1 << 24)) != 0);
759 if (mask
& CPSR_IT_0_1
) {
760 env
->condexec_bits
&= ~3;
761 env
->condexec_bits
|= (val
>> 25) & 3;
763 if (mask
& CPSR_IT_2_7
) {
764 env
->condexec_bits
&= 3;
765 env
->condexec_bits
|= (val
>> 8) & 0xfc;
768 env
->v7m
.exception
= val
& 0x1ff;
772 #define HCR_VM (1ULL << 0)
773 #define HCR_SWIO (1ULL << 1)
774 #define HCR_PTW (1ULL << 2)
775 #define HCR_FMO (1ULL << 3)
776 #define HCR_IMO (1ULL << 4)
777 #define HCR_AMO (1ULL << 5)
778 #define HCR_VF (1ULL << 6)
779 #define HCR_VI (1ULL << 7)
780 #define HCR_VSE (1ULL << 8)
781 #define HCR_FB (1ULL << 9)
782 #define HCR_BSU_MASK (3ULL << 10)
783 #define HCR_DC (1ULL << 12)
784 #define HCR_TWI (1ULL << 13)
785 #define HCR_TWE (1ULL << 14)
786 #define HCR_TID0 (1ULL << 15)
787 #define HCR_TID1 (1ULL << 16)
788 #define HCR_TID2 (1ULL << 17)
789 #define HCR_TID3 (1ULL << 18)
790 #define HCR_TSC (1ULL << 19)
791 #define HCR_TIDCP (1ULL << 20)
792 #define HCR_TACR (1ULL << 21)
793 #define HCR_TSW (1ULL << 22)
794 #define HCR_TPC (1ULL << 23)
795 #define HCR_TPU (1ULL << 24)
796 #define HCR_TTLB (1ULL << 25)
797 #define HCR_TVM (1ULL << 26)
798 #define HCR_TGE (1ULL << 27)
799 #define HCR_TDZ (1ULL << 28)
800 #define HCR_HCD (1ULL << 29)
801 #define HCR_TRVM (1ULL << 30)
802 #define HCR_RW (1ULL << 31)
803 #define HCR_CD (1ULL << 32)
804 #define HCR_ID (1ULL << 33)
805 #define HCR_MASK ((1ULL << 34) - 1)
807 #define SCR_NS (1U << 0)
808 #define SCR_IRQ (1U << 1)
809 #define SCR_FIQ (1U << 2)
810 #define SCR_EA (1U << 3)
811 #define SCR_FW (1U << 4)
812 #define SCR_AW (1U << 5)
813 #define SCR_NET (1U << 6)
814 #define SCR_SMD (1U << 7)
815 #define SCR_HCE (1U << 8)
816 #define SCR_SIF (1U << 9)
817 #define SCR_RW (1U << 10)
818 #define SCR_ST (1U << 11)
819 #define SCR_TWI (1U << 12)
820 #define SCR_TWE (1U << 13)
821 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
822 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
824 /* Return the current FPSCR value. */
825 uint32_t vfp_get_fpscr(CPUARMState
*env
);
826 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
828 /* For A64 the FPSCR is split into two logically distinct registers,
829 * FPCR and FPSR. However since they still use non-overlapping bits
830 * we store the underlying state in fpscr and just mask on read/write.
832 #define FPSR_MASK 0xf800009f
833 #define FPCR_MASK 0x07f79f00
834 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
836 return vfp_get_fpscr(env
) & FPSR_MASK
;
839 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
841 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
842 vfp_set_fpscr(env
, new_fpscr
);
845 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
847 return vfp_get_fpscr(env
) & FPCR_MASK
;
850 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
852 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
853 vfp_set_fpscr(env
, new_fpscr
);
857 ARM_CPU_MODE_USR
= 0x10,
858 ARM_CPU_MODE_FIQ
= 0x11,
859 ARM_CPU_MODE_IRQ
= 0x12,
860 ARM_CPU_MODE_SVC
= 0x13,
861 ARM_CPU_MODE_MON
= 0x16,
862 ARM_CPU_MODE_ABT
= 0x17,
863 ARM_CPU_MODE_HYP
= 0x1a,
864 ARM_CPU_MODE_UND
= 0x1b,
865 ARM_CPU_MODE_SYS
= 0x1f
868 /* VFP system registers. */
869 #define ARM_VFP_FPSID 0
870 #define ARM_VFP_FPSCR 1
871 #define ARM_VFP_MVFR2 5
872 #define ARM_VFP_MVFR1 6
873 #define ARM_VFP_MVFR0 7
874 #define ARM_VFP_FPEXC 8
875 #define ARM_VFP_FPINST 9
876 #define ARM_VFP_FPINST2 10
878 /* iwMMXt coprocessor control registers. */
879 #define ARM_IWMMXT_wCID 0
880 #define ARM_IWMMXT_wCon 1
881 #define ARM_IWMMXT_wCSSF 2
882 #define ARM_IWMMXT_wCASF 3
883 #define ARM_IWMMXT_wCGR0 8
884 #define ARM_IWMMXT_wCGR1 9
885 #define ARM_IWMMXT_wCGR2 10
886 #define ARM_IWMMXT_wCGR3 11
888 /* If adding a feature bit which corresponds to a Linux ELF
889 * HWCAP bit, remember to update the feature-bit-to-hwcap
890 * mapping in linux-user/elfload.c:get_elf_hwcap().
893 ARM_FEATURE_VFP
, /* Vector Floating-point. */
894 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
895 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
896 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
900 //~ See http://lists.nongnu.org/archive/html/qemu-devel/2009-05/msg01570.html
901 //~ ARM_FEATURE_THUMB, /* TODO: still unused. */
902 //~ ARM_FEATURE_THUMB1 = ARM_FEATURE_THUMB, /* TODO: still unused. */
904 ARM_FEATURE_MPU
, /* Only has Memory Protection Unit, not full MMU. */
906 ARM_FEATURE_VFP_FP16
,
908 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
909 ARM_FEATURE_M
, /* Microcontroller profile. */
910 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
911 // TODO: long multiply instructions (M variant), standard for v4 and v5.
912 // TODO: enhanced dsp instructions (E variant).
914 ARM_FEATURE_THUMB2EE
,
915 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
918 ARM_FEATURE_STRONGARM
,
919 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
920 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
921 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
922 ARM_FEATURE_GENERIC_TIMER
,
923 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
924 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
925 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
926 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
927 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
928 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
929 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
930 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
932 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
933 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
934 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
935 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
936 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
937 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
938 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
939 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
940 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
941 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
942 ARM_FEATURE_THUMB_DSP
, /* DSP insns supported in the Thumb encodings */
945 static inline int arm_feature(CPUARMState
*env
, int feature
)
947 return (env
->features
& (1ULL << feature
)) != 0;
950 #if !defined(CONFIG_USER_ONLY)
951 /* Return true if exception levels below EL3 are in secure state,
952 * or would be following an exception return to that level.
953 * Unlike arm_is_secure() (which is always a question about the
954 * _current_ state of the CPU) this doesn't care about the current
957 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
959 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
960 return !(env
->cp15
.scr_el3
& SCR_NS
);
962 /* If EL3 is not supported then the secure state is implementation
963 * defined, in which case QEMU defaults to non-secure.
969 /* Return true if the processor is in secure state */
970 static inline bool arm_is_secure(CPUARMState
*env
)
972 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
973 if (is_a64(env
) && extract32(env
->pstate
, 2, 2) == 3) {
974 /* CPU currently in AArch64 state and EL3 */
976 } else if (!is_a64(env
) &&
977 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
978 /* CPU currently in AArch32 state and monitor mode */
982 return arm_is_secure_below_el3(env
);
986 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
991 static inline bool arm_is_secure(CPUARMState
*env
)
997 /* Return true if the specified exception level is running in AArch64 state. */
998 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
1000 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1001 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1003 assert(el
>= 1 && el
<= 3);
1004 bool aa64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
1006 /* The highest exception level is always at the maximum supported
1007 * register width, and then lower levels have a register width controlled
1008 * by bits in the SCR or HCR registers.
1014 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1015 aa64
= aa64
&& (env
->cp15
.scr_el3
& SCR_RW
);
1022 if (arm_feature(env
, ARM_FEATURE_EL2
) && !arm_is_secure_below_el3(env
)) {
1023 aa64
= aa64
&& (env
->cp15
.hcr_el2
& HCR_RW
);
1029 /* Function for determing whether guest cp register reads and writes should
1030 * access the secure or non-secure bank of a cp register. When EL3 is
1031 * operating in AArch32 state, the NS-bit determines whether the secure
1032 * instance of a cp register should be used. When EL3 is AArch64 (or if
1033 * it doesn't exist at all) then there is no register banking, and all
1034 * accesses are to the non-secure version.
1036 static inline bool access_secure_reg(CPUARMState
*env
)
1038 bool ret
= (arm_feature(env
, ARM_FEATURE_EL3
) &&
1039 !arm_el_is_aa64(env
, 3) &&
1040 !(env
->cp15
.scr_el3
& SCR_NS
));
1045 /* Macros for accessing a specified CP register bank */
1046 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1047 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1049 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1052 (_env)->cp15._regname##_s = (_val); \
1054 (_env)->cp15._regname##_ns = (_val); \
1058 /* Macros for automatically accessing a specific CP register bank depending on
1059 * the current secure state of the system. These macros are not intended for
1060 * supporting instruction translation reads/writes as these are dependent
1061 * solely on the SCR.NS bit and not the mode.
1063 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1064 A32_BANKED_REG_GET((_env), _regname, \
1065 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1067 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1068 A32_BANKED_REG_SET((_env), _regname, \
1069 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1072 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1073 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
1074 uint32_t cur_el
, bool secure
);
1076 /* Interface between CPU and Interrupt controller. */
1077 void armv7m_nvic_set_pending(void *opaque
, int irq
);
1078 int armv7m_nvic_acknowledge_irq(void *opaque
);
1079 void armv7m_nvic_complete_irq(void *opaque
, int irq
);
1081 /* Interface for defining coprocessor registers.
1082 * Registers are defined in tables of arm_cp_reginfo structs
1083 * which are passed to define_arm_cp_regs().
1086 /* When looking up a coprocessor register we look for it
1087 * via an integer which encodes all of:
1088 * coprocessor number
1089 * Crn, Crm, opc1, opc2 fields
1090 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1091 * or via MRRC/MCRR?)
1092 * non-secure/secure bank (AArch32 only)
1093 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1094 * (In this case crn and opc2 should be zero.)
1095 * For AArch64, there is no 32/64 bit size distinction;
1096 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1097 * and 4 bit CRn and CRm. The encoding patterns are chosen
1098 * to be easy to convert to and from the KVM encodings, and also
1099 * so that the hashtable can contain both AArch32 and AArch64
1100 * registers (to allow for interprocessing where we might run
1101 * 32 bit code on a 64 bit core).
1103 /* This bit is private to our hashtable cpreg; in KVM register
1104 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1105 * in the upper bits of the 64 bit ID.
1107 #define CP_REG_AA64_SHIFT 28
1108 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1110 /* To enable banking of coprocessor registers depending on ns-bit we
1111 * add a bit to distinguish between secure and non-secure cpregs in the
1114 #define CP_REG_NS_SHIFT 29
1115 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1117 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1118 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1119 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1121 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1122 (CP_REG_AA64_MASK | \
1123 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1124 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1125 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1126 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1127 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1128 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1130 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1131 * version used as a key for the coprocessor register hashtable
1133 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
1135 uint32_t cpregid
= kvmid
;
1136 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
1137 cpregid
|= CP_REG_AA64_MASK
;
1139 if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
1140 cpregid
|= (1 << 15);
1143 /* KVM is always non-secure so add the NS flag on AArch32 register
1146 cpregid
|= 1 << CP_REG_NS_SHIFT
;
1151 /* Convert a truncated 32 bit hashtable key into the full
1152 * 64 bit KVM register ID.
1154 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
1158 if (cpregid
& CP_REG_AA64_MASK
) {
1159 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
1160 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
1162 kvmid
= cpregid
& ~(1 << 15);
1163 if (cpregid
& (1 << 15)) {
1164 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
1166 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
1172 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1173 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1174 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1175 * TCG can assume the value to be constant (ie load at translate time)
1176 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1177 * indicates that the TB should not be ended after a write to this register
1178 * (the default is that the TB ends after cp writes). OVERRIDE permits
1179 * a register definition to override a previous definition for the
1180 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1181 * old must have the OVERRIDE bit set.
1182 * ALIAS indicates that this register is an alias view of some underlying
1183 * state which is also visible via another register, and that the other
1184 * register is handling migration and reset; registers marked ALIAS will not be
1185 * migrated but may have their state set by syncing of register state from KVM.
1186 * NO_RAW indicates that this register has no underlying state and does not
1187 * support raw access for state saving/loading; it will not be used for either
1188 * migration or KVM state synchronization. (Typically this is for "registers"
1189 * which are actually used as instructions for cache maintenance and so on.)
1190 * IO indicates that this register does I/O and therefore its accesses
1191 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1192 * registers which implement clocks or timers require this.
1194 #define ARM_CP_SPECIAL 1
1195 #define ARM_CP_CONST 2
1196 #define ARM_CP_64BIT 4
1197 #define ARM_CP_SUPPRESS_TB_END 8
1198 #define ARM_CP_OVERRIDE 16
1199 #define ARM_CP_ALIAS 32
1200 #define ARM_CP_IO 64
1201 #define ARM_CP_NO_RAW 128
1202 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1203 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1204 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1205 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1206 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1207 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1208 /* Used only as a terminator for ARMCPRegInfo lists */
1209 #define ARM_CP_SENTINEL 0xffff
1210 /* Mask of only the flag bits in a type field */
1211 #define ARM_CP_FLAG_MASK 0xff
1213 /* Valid values for ARMCPRegInfo state field, indicating which of
1214 * the AArch32 and AArch64 execution states this register is visible in.
1215 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1216 * If the reginfo is declared to be visible in both states then a second
1217 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1218 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1219 * Note that we rely on the values of these enums as we iterate through
1220 * the various states in some places.
1223 ARM_CP_STATE_AA32
= 0,
1224 ARM_CP_STATE_AA64
= 1,
1225 ARM_CP_STATE_BOTH
= 2,
1228 /* ARM CP register secure state flags. These flags identify security state
1229 * attributes for a given CP register entry.
1230 * The existence of both or neither secure and non-secure flags indicates that
1231 * the register has both a secure and non-secure hash entry. A single one of
1232 * these flags causes the register to only be hashed for the specified
1234 * Although definitions may have any combination of the S/NS bits, each
1235 * registered entry will only have one to identify whether the entry is secure
1239 ARM_CP_SECSTATE_S
= (1 << 0), /* bit[0]: Secure state register */
1240 ARM_CP_SECSTATE_NS
= (1 << 1), /* bit[1]: Non-secure state register */
1243 /* Return true if cptype is a valid type field. This is used to try to
1244 * catch errors where the sentinel has been accidentally left off the end
1245 * of a list of registers.
1247 static inline bool cptype_valid(int cptype
)
1249 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
1250 || ((cptype
& ARM_CP_SPECIAL
) &&
1251 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
1255 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1256 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1257 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1258 * (ie any of the privileged modes in Secure state, or Monitor mode).
1259 * If a register is accessible in one privilege level it's always accessible
1260 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1261 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1262 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1263 * terminology a little and call this PL3.
1264 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1265 * with the ELx exception levels.
1267 * If access permissions for a register are more complex than can be
1268 * described with these bits, then use a laxer set of restrictions, and
1269 * do the more restrictive/complex check inside a helper function.
1273 #define PL2_R (0x20 | PL3_R)
1274 #define PL2_W (0x10 | PL3_W)
1275 #define PL1_R (0x08 | PL2_R)
1276 #define PL1_W (0x04 | PL2_W)
1277 #define PL0_R (0x02 | PL1_R)
1278 #define PL0_W (0x01 | PL1_W)
1280 #define PL3_RW (PL3_R | PL3_W)
1281 #define PL2_RW (PL2_R | PL2_W)
1282 #define PL1_RW (PL1_R | PL1_W)
1283 #define PL0_RW (PL0_R | PL0_W)
1285 /* Return the highest implemented Exception Level */
1286 static inline int arm_highest_el(CPUARMState
*env
)
1288 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1291 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1297 /* Return the current Exception Level (as per ARMv8; note that this differs
1298 * from the ARMv7 Privilege Level).
1300 static inline int arm_current_el(CPUARMState
*env
)
1302 if (arm_feature(env
, ARM_FEATURE_M
)) {
1303 return !((env
->v7m
.exception
== 0) && (env
->v7m
.control
& 1));
1307 return extract32(env
->pstate
, 2, 2);
1310 switch (env
->uncached_cpsr
& 0x1f) {
1311 case ARM_CPU_MODE_USR
:
1313 case ARM_CPU_MODE_HYP
:
1315 case ARM_CPU_MODE_MON
:
1318 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1319 /* If EL3 is 32-bit then all secure privileged modes run in
1329 typedef struct ARMCPRegInfo ARMCPRegInfo
;
1331 typedef enum CPAccessResult
{
1332 /* Access is permitted */
1334 /* Access fails due to a configurable trap or enable which would
1335 * result in a categorized exception syndrome giving information about
1336 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1337 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1338 * PL1 if in EL0, otherwise to the current EL).
1341 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1342 * Note that this is not a catch-all case -- the set of cases which may
1343 * result in this failure is specifically defined by the architecture.
1345 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
1346 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1347 CP_ACCESS_TRAP_EL2
= 3,
1348 CP_ACCESS_TRAP_EL3
= 4,
1349 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1350 CP_ACCESS_TRAP_UNCATEGORIZED_EL2
= 5,
1351 CP_ACCESS_TRAP_UNCATEGORIZED_EL3
= 6,
1352 /* Access fails and results in an exception syndrome for an FP access,
1353 * trapped directly to EL2 or EL3
1355 CP_ACCESS_TRAP_FP_EL2
= 7,
1356 CP_ACCESS_TRAP_FP_EL3
= 8,
1359 /* Access functions for coprocessor registers. These cannot fail and
1360 * may not raise exceptions.
1362 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1363 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
1365 /* Access permission check functions for coprocessor registers. */
1366 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
,
1367 const ARMCPRegInfo
*opaque
,
1369 /* Hook function for register reset */
1370 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1374 /* Definition of an ARM coprocessor register */
1375 struct ARMCPRegInfo
{
1376 /* Name of register (useful mainly for debugging, need not be unique) */
1378 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1379 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1380 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1381 * will be decoded to this register. The register read and write
1382 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1383 * used by the program, so it is possible to register a wildcard and
1384 * then behave differently on read/write if necessary.
1385 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1386 * must both be zero.
1387 * For AArch64-visible registers, opc0 is also used.
1388 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1389 * way to distinguish (for KVM's benefit) guest-visible system registers
1390 * from demuxed ones provided to preserve the "no side effects on
1391 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1392 * visible (to match KVM's encoding); cp==0 will be converted to
1393 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1401 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1403 /* Register type: ARM_CP_* bits/values */
1405 /* Access rights: PL*_[RW] */
1407 /* Security state: ARM_CP_SECSTATE_* bits/values */
1409 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1410 * this register was defined: can be used to hand data through to the
1411 * register read/write functions, since they are passed the ARMCPRegInfo*.
1414 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1415 * fieldoffset is non-zero, the reset value of the register.
1417 uint64_t resetvalue
;
1418 /* Offset of the field in CPUARMState for this register.
1420 * This is not needed if either:
1421 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1422 * 2. both readfn and writefn are specified
1424 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1426 /* Offsets of the secure and non-secure fields in CPUARMState for the
1427 * register if it is banked. These fields are only used during the static
1428 * registration of a register. During hashing the bank associated
1429 * with a given security state is copied to fieldoffset which is used from
1432 * It is expected that register definitions use either fieldoffset or
1433 * bank_fieldoffsets in the definition but not both. It is also expected
1434 * that both bank offsets are set when defining a banked register. This
1435 * use indicates that a register is banked.
1437 ptrdiff_t bank_fieldoffsets
[2];
1439 /* Function for making any access checks for this register in addition to
1440 * those specified by the 'access' permissions bits. If NULL, no extra
1441 * checks required. The access check is performed at runtime, not at
1444 CPAccessFn
*accessfn
;
1445 /* Function for handling reads of this register. If NULL, then reads
1446 * will be done by loading from the offset into CPUARMState specified
1450 /* Function for handling writes of this register. If NULL, then writes
1451 * will be done by writing to the offset into CPUARMState specified
1455 /* Function for doing a "raw" read; used when we need to copy
1456 * coprocessor state to the kernel for KVM or out for
1457 * migration. This only needs to be provided if there is also a
1458 * readfn and it has side effects (for instance clear-on-read bits).
1460 CPReadFn
*raw_readfn
;
1461 /* Function for doing a "raw" write; used when we need to copy KVM
1462 * kernel coprocessor state into userspace, or for inbound
1463 * migration. This only needs to be provided if there is also a
1464 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1465 * or similar behaviour.
1467 CPWriteFn
*raw_writefn
;
1468 /* Function for resetting the register. If NULL, then reset will be done
1469 * by writing resetvalue to the field specified in fieldoffset. If
1470 * fieldoffset is 0 then no reset will be done.
1475 /* Macros which are lvalues for the field in CPUARMState for the
1478 #define CPREG_FIELD32(env, ri) \
1479 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1480 #define CPREG_FIELD64(env, ri) \
1481 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1483 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1485 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1486 const ARMCPRegInfo
*regs
, void *opaque
);
1487 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1488 const ARMCPRegInfo
*regs
, void *opaque
);
1489 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1491 define_arm_cp_regs_with_opaque(cpu
, regs
, NULL
);
1493 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
1495 define_one_arm_cp_reg_with_opaque(cpu
, regs
, NULL
);
1497 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
1499 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1500 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1502 /* CPReadFn that can be used for read-as-zero behaviour */
1503 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1505 /* CPResetFn that does nothing, for use if no reset is required even
1506 * if fieldoffset is non zero.
1508 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1510 /* Return true if this reginfo struct's field in the cpu state struct
1513 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
1515 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
1518 static inline bool cp_access_ok(int current_el
,
1519 const ARMCPRegInfo
*ri
, int isread
)
1521 return (ri
->access
>> ((current_el
* 2) + isread
)) & 1;
1524 /* Raw read of a coprocessor register (as needed for migration, etc) */
1525 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
1528 * write_list_to_cpustate
1531 * For each register listed in the ARMCPU cpreg_indexes list, write
1532 * its value from the cpreg_values list into the ARMCPUState structure.
1533 * This updates TCG's working data structures from KVM data or
1534 * from incoming migration state.
1536 * Returns: true if all register values were updated correctly,
1537 * false if some register was unknown or could not be written.
1538 * Note that we do not stop early on failure -- we will attempt
1539 * writing all registers in the list.
1541 bool write_list_to_cpustate(ARMCPU
*cpu
);
1544 * write_cpustate_to_list:
1547 * For each register listed in the ARMCPU cpreg_indexes list, write
1548 * its value from the ARMCPUState structure into the cpreg_values list.
1549 * This is used to copy info from TCG's working data structures into
1550 * KVM or for outbound migration.
1552 * Returns: true if all register values were read correctly,
1553 * false if some register was unknown or could not be read.
1554 * Note that we do not stop early on failure -- we will attempt
1555 * reading all registers in the list.
1557 bool write_cpustate_to_list(ARMCPU
*cpu
);
1559 /* Does the core conform to the "MicroController" profile. e.g. Cortex-M3.
1560 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1561 conventional cores (ie. Application or Realtime profile). */
1563 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1565 #define ARM_CPUID_TI915T 0x54029152
1566 #define ARM_CPUID_TI925T 0x54029252
1568 #if defined(CONFIG_USER_ONLY)
1569 #define TARGET_PAGE_BITS 12
1571 /* The ARM MMU allows 1k pages. */
1572 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1573 architecture revisions. Maybe a configure option to disable them. */
1574 #define TARGET_PAGE_BITS 10
1577 #if defined(TARGET_AARCH64)
1578 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1579 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1581 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1582 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1585 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
1586 unsigned int target_el
)
1588 CPUARMState
*env
= cs
->env_ptr
;
1589 unsigned int cur_el
= arm_current_el(env
);
1590 bool secure
= arm_is_secure(env
);
1591 bool pstate_unmasked
;
1592 int8_t unmasked
= 0;
1594 /* Don't take exceptions if they target a lower EL.
1595 * This check should catch any exceptions that would not be taken but left
1598 if (cur_el
> target_el
) {
1604 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
1608 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
1612 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_FMO
)) {
1613 /* VFIQs are only taken when hypervized and non-secure. */
1616 return !(env
->daif
& PSTATE_F
);
1618 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_IMO
)) {
1619 /* VIRQs are only taken when hypervized and non-secure. */
1622 return !(env
->daif
& PSTATE_I
);
1624 g_assert_not_reached();
1627 /* Use the target EL, current execution state and SCR/HCR settings to
1628 * determine whether the corresponding CPSR bit is used to mask the
1631 if ((target_el
> cur_el
) && (target_el
!= 1)) {
1632 /* Exceptions targeting a higher EL may not be maskable */
1633 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
1634 /* 64-bit masking rules are simple: exceptions to EL3
1635 * can't be masked, and exceptions to EL2 can only be
1636 * masked from Secure state. The HCR and SCR settings
1637 * don't affect the masking logic, only the interrupt routing.
1639 if (target_el
== 3 || !secure
) {
1643 /* The old 32-bit-only environment has a more complicated
1644 * masking setup. HCR and SCR bits not only affect interrupt
1645 * routing but also change the behaviour of masking.
1651 /* If FIQs are routed to EL3 or EL2 then there are cases where
1652 * we override the CPSR.F in determining if the exception is
1653 * masked or not. If neither of these are set then we fall back
1654 * to the CPSR.F setting otherwise we further assess the state
1657 hcr
= (env
->cp15
.hcr_el2
& HCR_FMO
);
1658 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
1660 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
1661 * CPSR.F bit masks FIQ interrupts when taken in non-secure
1662 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
1663 * when non-secure but only when FIQs are only routed to EL3.
1665 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
1668 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
1669 * we may override the CPSR.I masking when in non-secure state.
1670 * The SCR.IRQ setting has already been taken into consideration
1671 * when setting the target EL, so it does not have a further
1674 hcr
= (env
->cp15
.hcr_el2
& HCR_IMO
);
1678 g_assert_not_reached();
1681 if ((scr
|| hcr
) && !secure
) {
1687 /* The PSTATE bits only mask the interrupt if we have not overriden the
1690 return unmasked
|| pstate_unmasked
;
1693 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1695 #define cpu_exec cpu_arm_exec
1696 #define cpu_signal_handler cpu_arm_signal_handler
1697 #define cpu_list arm_cpu_list
1699 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
1702 * + NonSecure EL1 & 0 stage 1
1703 * + NonSecure EL1 & 0 stage 2
1705 * + Secure EL1 & EL0
1708 * + NonSecure PL1 & 0 stage 1
1709 * + NonSecure PL1 & 0 stage 2
1711 * + Secure PL0 & PL1
1712 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1714 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1715 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
1716 * may differ in access permissions even if the VA->PA map is the same
1717 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
1718 * translation, which means that we have one mmu_idx that deals with two
1719 * concatenated translation regimes [this sort of combined s1+2 TLB is
1720 * architecturally permitted]
1721 * 3. we don't need to allocate an mmu_idx to translations that we won't be
1722 * handling via the TLB. The only way to do a stage 1 translation without
1723 * the immediate stage 2 translation is via the ATS or AT system insns,
1724 * which can be slow-pathed and always do a page table walk.
1725 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
1726 * translation regimes, because they map reasonably well to each other
1727 * and they can't both be active at the same time.
1728 * This gives us the following list of mmu_idx values:
1730 * NS EL0 (aka NS PL0) stage 1+2
1731 * NS EL1 (aka NS PL1) stage 1+2
1732 * NS EL2 (aka NS PL2)
1735 * S EL1 (not used if EL3 is 32 bit)
1738 * (The last of these is an mmu_idx because we want to be able to use the TLB
1739 * for the accesses done as part of a stage 1 page table walk, rather than
1740 * having to walk the stage 2 page table over and over.)
1742 * Our enumeration includes at the end some entries which are not "true"
1743 * mmu_idx values in that they don't have corresponding TLBs and are only
1744 * valid for doing slow path page table walks.
1746 * The constant names here are patterned after the general style of the names
1747 * of the AT/ATS operations.
1748 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
1750 typedef enum ARMMMUIdx
{
1751 ARMMMUIdx_S12NSE0
= 0,
1752 ARMMMUIdx_S12NSE1
= 1,
1755 ARMMMUIdx_S1SE0
= 4,
1756 ARMMMUIdx_S1SE1
= 5,
1758 /* Indexes below here don't have TLBs and are used only for AT system
1759 * instructions or for the first stage of an S12 page table walk.
1761 ARMMMUIdx_S1NSE0
= 7,
1762 ARMMMUIdx_S1NSE1
= 8,
1765 #define MMU_USER_IDX 0
1767 /* Return the exception level we're running at if this is our mmu_idx */
1768 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
1770 assert(mmu_idx
< ARMMMUIdx_S2NS
);
1774 /* Determine the current mmu_idx to use for normal loads/stores */
1775 static inline int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
1777 int el
= arm_current_el(env
);
1779 if (el
< 2 && arm_is_secure_below_el3(env
)) {
1780 return ARMMMUIdx_S1SE0
+ el
;
1785 /* Indexes used when registering address spaces with cpu_address_space_init */
1786 typedef enum ARMASIdx
{
1791 /* Return the Exception Level targeted by debug exceptions. */
1792 static inline int arm_debug_target_el(CPUARMState
*env
)
1794 bool secure
= arm_is_secure(env
);
1795 bool route_to_el2
= false;
1797 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
) {
1798 route_to_el2
= env
->cp15
.hcr_el2
& HCR_TGE
||
1799 env
->cp15
.mdcr_el2
& (1 << 8);
1804 } else if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1805 !arm_el_is_aa64(env
, 3) && secure
) {
1812 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
1814 if (arm_is_secure(env
)) {
1815 /* MDCR_EL3.SDD disables debug events from Secure state */
1816 if (extract32(env
->cp15
.mdcr_el3
, 16, 1) != 0
1817 || arm_current_el(env
) == 3) {
1822 if (arm_current_el(env
) == arm_debug_target_el(env
)) {
1823 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
1824 || (env
->daif
& PSTATE_D
)) {
1831 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
1833 int el
= arm_current_el(env
);
1835 if (el
== 0 && arm_el_is_aa64(env
, 1)) {
1836 return aa64_generate_debug_exceptions(env
);
1839 if (arm_is_secure(env
)) {
1842 if (el
== 0 && (env
->cp15
.sder
& 1)) {
1843 /* SDER.SUIDEN means debug exceptions from Secure EL0
1844 * are always enabled. Otherwise they are controlled by
1845 * SDCR.SPD like those from other Secure ELs.
1850 spd
= extract32(env
->cp15
.mdcr_el3
, 14, 2);
1853 /* SPD == 0b01 is reserved, but behaves as 0b00. */
1855 /* For 0b00 we return true if external secure invasive debug
1856 * is enabled. On real hardware this is controlled by external
1857 * signals to the core. QEMU always permits debug, and behaves
1858 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
1871 /* Return true if debugging exceptions are currently enabled.
1872 * This corresponds to what in ARM ARM pseudocode would be
1873 * if UsingAArch32() then
1874 * return AArch32.GenerateDebugExceptions()
1876 * return AArch64.GenerateDebugExceptions()
1877 * We choose to push the if() down into this function for clarity,
1878 * since the pseudocode has it at all callsites except for the one in
1879 * CheckSoftwareStep(), where it is elided because both branches would
1880 * always return the same value.
1882 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1883 * don't yet implement those exception levels or their associated trap bits.
1885 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
1888 return aa64_generate_debug_exceptions(env
);
1890 return aa32_generate_debug_exceptions(env
);
1894 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1895 * implicitly means this always returns false in pre-v8 CPUs.)
1897 static inline bool arm_singlestep_active(CPUARMState
*env
)
1899 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
1900 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
1901 && arm_generate_debug_exceptions(env
);
1904 static inline bool arm_sctlr_b(CPUARMState
*env
)
1907 /* We need not implement SCTLR.ITD in user-mode emulation, so
1908 * let linux-user ignore the fact that it conflicts with SCTLR_B.
1909 * This lets people run BE32 binaries with "-cpu any".
1911 #ifndef CONFIG_USER_ONLY
1912 !arm_feature(env
, ARM_FEATURE_V7
) &&
1914 (env
->cp15
.sctlr_el
[1] & SCTLR_B
) != 0;
1917 /* Return true if the processor is in big-endian mode. */
1918 static bool arm_cpu_data_is_big_endian(CPUARMState
*env
)
1922 /* In 32bit endianness is determined by looking at CPSR's E bit */
1925 #ifdef CONFIG_USER_ONLY
1926 /* In system mode, BE32 is modelled in line with the
1927 * architecture (as word-invariant big-endianness), where loads
1928 * and stores are done little endian but from addresses which
1929 * are adjusted by XORing with the appropriate constant. So the
1930 * endianness to use for the raw data access is not affected by
1932 * In user mode, however, we model BE32 as byte-invariant
1933 * big-endianness (because user-only code cannot tell the
1934 * difference), and so we need to use a data access endianness
1935 * that depends on SCTLR.B.
1939 ((env
->uncached_cpsr
& CPSR_E
) ? 1 : 0);
1942 cur_el
= arm_current_el(env
);
1945 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
1948 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
1951 #include "exec/cpu-all.h"
1953 /* Bit usage in the TB flags field: bit 31 indicates whether we are
1954 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
1955 * We put flags which are shared between 32 and 64 bit mode at the top
1956 * of the word, and flags which apply to only one mode at the bottom.
1958 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1959 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1960 #define ARM_TBFLAG_MMUIDX_SHIFT 28
1961 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
1962 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
1963 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1964 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
1965 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1966 /* Target EL if we take a floating-point-disabled exception */
1967 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
1968 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
1970 /* Bit usage when in AArch32 state: */
1971 #define ARM_TBFLAG_THUMB_SHIFT 0
1972 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1973 #define ARM_TBFLAG_VECLEN_SHIFT 1
1974 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1975 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1976 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1977 #define ARM_TBFLAG_VFPEN_SHIFT 7
1978 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1979 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
1980 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1981 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
1982 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
1983 /* We store the bottom two bits of the CPAR as TB flags and handle
1984 * checks on the other bits at runtime
1986 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
1987 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1988 /* Indicates whether cp register reads and writes by guest code should access
1989 * the secure or nonsecure bank of banked registers; note that this is not
1990 * the same thing as the current security state of the processor!
1992 #define ARM_TBFLAG_NS_SHIFT 19
1993 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
1994 #define ARM_TBFLAG_BE_DATA_SHIFT 20
1995 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
1997 /* Bit usage when in AArch64 state: currently we have no A64 specific bits */
1999 /* some convenience accessor macros */
2000 #define ARM_TBFLAG_AARCH64_STATE(F) \
2001 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2002 #define ARM_TBFLAG_MMUIDX(F) \
2003 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2004 #define ARM_TBFLAG_SS_ACTIVE(F) \
2005 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2006 #define ARM_TBFLAG_PSTATE_SS(F) \
2007 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2008 #define ARM_TBFLAG_FPEXC_EL(F) \
2009 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2010 #define ARM_TBFLAG_THUMB(F) \
2011 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2012 #define ARM_TBFLAG_VECLEN(F) \
2013 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2014 #define ARM_TBFLAG_VECSTRIDE(F) \
2015 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2016 #define ARM_TBFLAG_VFPEN(F) \
2017 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2018 #define ARM_TBFLAG_CONDEXEC(F) \
2019 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2020 #define ARM_TBFLAG_SCTLR_B(F) \
2021 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2022 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2023 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2024 #define ARM_TBFLAG_NS(F) \
2025 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2026 #define ARM_TBFLAG_BE_DATA(F) \
2027 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2029 static inline bool bswap_code(bool sctlr_b
)
2031 #ifdef CONFIG_USER_ONLY
2032 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
2033 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
2034 * would also end up as a mixed-endian mode with BE code, LE data.
2037 #ifdef TARGET_WORDS_BIGENDIAN
2042 /* All code access in ARM is little endian, and there are no loaders
2043 * doing swaps that need to be reversed
2049 /* Return the exception level to which FP-disabled exceptions should
2050 * be taken, or 0 if FP is enabled.
2052 static inline int fp_exception_el(CPUARMState
*env
)
2055 int cur_el
= arm_current_el(env
);
2057 /* CPACR and the CPTR registers don't exist before v6, so FP is
2060 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
2064 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
2065 * 0, 2 : trap EL0 and EL1/PL1 accesses
2066 * 1 : trap only EL0 accesses
2067 * 3 : trap no accesses
2069 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
2073 if (cur_el
== 0 || cur_el
== 1) {
2074 /* Trap to PL1, which might be EL1 or EL3 */
2075 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
2080 if (cur_el
== 3 && !is_a64(env
)) {
2081 /* Secure PL1 running at EL3 */
2094 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
2095 * check because zero bits in the registers mean "don't trap".
2098 /* CPTR_EL2 : present in v7VE or v8 */
2099 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
2100 && !arm_is_secure_below_el3(env
)) {
2101 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
2105 /* CPTR_EL3 : present in v8 */
2106 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
2107 /* Trap all FP ops to EL3 */
2114 #ifdef CONFIG_USER_ONLY
2115 /* get_user and put_user respectively return and expect data according
2116 * to TARGET_WORDS_BIGENDIAN, but ldrex/strex emulation needs to take
2117 * into account CPSR.E.
2119 * TARGET_WORDS_BIGENDIAN CPSR.E need swap?
2124 * BE32/BE yes 1 0 no
2125 * (BE32/LE) yes 1 1 yes
2127 * Officially, BE32 with CPSR.E=1 has "unpredictable" results. We
2128 * implement it as big-endian code, little-endian data.
2130 static inline bool arm_cpu_bswap_data(CPUARMState
*env
)
2133 #ifdef TARGET_WORDS_BIGENDIAN
2137 arm_cpu_data_is_big_endian(env
);
2141 static inline void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
2142 target_ulong
*cs_base
, uint32_t *flags
)
2146 *flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
2148 *pc
= env
->regs
[15];
2149 *flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
2150 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
2151 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
2152 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
2153 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
2154 if (!(access_secure_reg(env
))) {
2155 *flags
|= ARM_TBFLAG_NS_MASK
;
2157 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
2158 || arm_el_is_aa64(env
, 1)) {
2159 *flags
|= ARM_TBFLAG_VFPEN_MASK
;
2161 *flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
2162 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
2165 *flags
|= (cpu_mmu_index(env
, false) << ARM_TBFLAG_MMUIDX_SHIFT
);
2166 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
2167 * states defined in the ARM ARM for software singlestep:
2168 * SS_ACTIVE PSTATE.SS State
2169 * 0 x Inactive (the TB flag for SS is always 0)
2170 * 1 0 Active-pending
2171 * 1 1 Active-not-pending
2173 if (arm_singlestep_active(env
)) {
2174 *flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
2176 if (env
->pstate
& PSTATE_SS
) {
2177 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
2180 if (env
->uncached_cpsr
& PSTATE_SS
) {
2181 *flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
2185 if (arm_cpu_data_is_big_endian(env
)) {
2186 *flags
|= ARM_TBFLAG_BE_DATA_MASK
;
2188 *flags
|= fp_exception_el(env
) << ARM_TBFLAG_FPEXC_EL_SHIFT
;
2193 #include "exec/exec-all.h"
2196 QEMU_PSCI_CONDUIT_DISABLED
= 0,
2197 QEMU_PSCI_CONDUIT_SMC
= 1,
2198 QEMU_PSCI_CONDUIT_HVC
= 2,
2201 #ifndef CONFIG_USER_ONLY
2202 /* Return the address space index to use for a memory access */
2203 static inline int arm_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2205 return attrs
.secure
? ARMASIdx_S
: ARMASIdx_NS
;
2208 /* Return the AddressSpace to use for a memory access
2209 * (which depends on whether the access is S or NS, and whether
2210 * the board gave us a separate AddressSpace for S accesses).
2212 static inline AddressSpace
*arm_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2214 return cpu_get_address_space(cs
, arm_asidx_from_attrs(cs
, attrs
));