2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "hw/arm/arm.h"
20 #include "hw/intc/armv7m_nvic.h"
21 #include "target/arm/cpu.h"
22 #include "exec/exec-all.h"
26 /* IRQ number counting:
28 * the num-irq property counts the number of external IRQ lines
30 * NVICState::num_irq counts the total number of exceptions
31 * (external IRQs, the 15 internal exceptions including reset,
32 * and one for the unused exception number 0).
34 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
36 * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
38 * Iterating through all exceptions should typically be done with
39 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
41 * The external qemu_irq lines are the NVIC's external IRQ lines,
42 * so line 0 is exception 16.
44 * In the terminology of the architecture manual, "interrupts" are
45 * a subcategory of exception referring to the external interrupts
46 * (which are exception numbers NVIC_FIRST_IRQ and upward).
47 * For historical reasons QEMU tends to use "interrupt" and
48 * "exception" more or less interchangeably.
50 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
53 /* Effective running priority of the CPU when no exception is active
54 * (higher than the highest possible priority value)
56 #define NVIC_NOEXC_PRIO 0x100
57 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
58 #define NVIC_NS_PRIO_LIMIT 0x80
60 static const uint8_t nvic_id
[] = {
61 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
64 static int nvic_pending_prio(NVICState
*s
)
66 /* return the group priority of the current pending interrupt,
67 * or NVIC_NOEXC_PRIO if no interrupt is pending
69 return s
->vectpending_prio
;
72 /* Return the value of the ISCR RETTOBASE bit:
73 * 1 if there is exactly one active exception
74 * 0 if there is more than one active exception
75 * UNKNOWN if there are no active exceptions (we choose 1,
76 * which matches the choice Cortex-M3 is documented as making).
78 * NB: some versions of the documentation talk about this
79 * counting "active exceptions other than the one shown by IPSR";
80 * this is only different in the obscure corner case where guest
81 * code has manually deactivated an exception and is about
82 * to fail an exception-return integrity check. The definition
83 * above is the one from the v8M ARM ARM and is also in line
84 * with the behaviour documented for the Cortex-M3.
86 static bool nvic_rettobase(NVICState
*s
)
89 bool check_sec
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
91 for (irq
= ARMV7M_EXCP_RESET
; irq
< s
->num_irq
; irq
++) {
92 if (s
->vectors
[irq
].active
||
93 (check_sec
&& irq
< NVIC_INTERNAL_VECTORS
&&
94 s
->sec_vectors
[irq
].active
)) {
105 /* Return the value of the ISCR ISRPENDING bit:
106 * 1 if an external interrupt is pending
107 * 0 if no external interrupt is pending
109 static bool nvic_isrpending(NVICState
*s
)
113 /* We can shortcut if the highest priority pending interrupt
114 * happens to be external or if there is nothing pending.
116 if (s
->vectpending
> NVIC_FIRST_IRQ
) {
119 if (s
->vectpending
== 0) {
123 for (irq
= NVIC_FIRST_IRQ
; irq
< s
->num_irq
; irq
++) {
124 if (s
->vectors
[irq
].pending
) {
131 static bool exc_is_banked(int exc
)
133 /* Return true if this is one of the limited set of exceptions which
134 * are banked (and thus have state in sec_vectors[])
136 return exc
== ARMV7M_EXCP_HARD
||
137 exc
== ARMV7M_EXCP_MEM
||
138 exc
== ARMV7M_EXCP_USAGE
||
139 exc
== ARMV7M_EXCP_SVC
||
140 exc
== ARMV7M_EXCP_PENDSV
||
141 exc
== ARMV7M_EXCP_SYSTICK
;
144 /* Return a mask word which clears the subpriority bits from
145 * a priority value for an M-profile exception, leaving only
146 * the group priority.
148 static inline uint32_t nvic_gprio_mask(NVICState
*s
, bool secure
)
150 return ~0U << (s
->prigroup
[secure
] + 1);
153 static bool exc_targets_secure(NVICState
*s
, int exc
)
155 /* Return true if this non-banked exception targets Secure state. */
156 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
160 if (exc
>= NVIC_FIRST_IRQ
) {
161 return !s
->itns
[exc
];
164 /* Function shouldn't be called for banked exceptions. */
165 assert(!exc_is_banked(exc
));
168 case ARMV7M_EXCP_NMI
:
169 case ARMV7M_EXCP_BUS
:
170 return !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
171 case ARMV7M_EXCP_SECURE
:
173 case ARMV7M_EXCP_DEBUG
:
174 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
177 /* reset, and reserved (unused) low exception numbers.
178 * We'll get called by code that loops through all the exception
179 * numbers, but it doesn't matter what we return here as these
180 * non-existent exceptions will never be pended or active.
186 static int exc_group_prio(NVICState
*s
, int rawprio
, bool targets_secure
)
188 /* Return the group priority for this exception, given its raw
189 * (group-and-subgroup) priority value and whether it is targeting
190 * secure state or not.
195 rawprio
&= nvic_gprio_mask(s
, targets_secure
);
196 /* AIRCR.PRIS causes us to squash all NS priorities into the
197 * lower half of the total range
199 if (!targets_secure
&&
200 (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
)) {
201 rawprio
= (rawprio
>> 1) + NVIC_NS_PRIO_LIMIT
;
206 /* Recompute vectpending and exception_prio for a CPU which implements
207 * the Security extension
209 static void nvic_recompute_state_secure(NVICState
*s
)
212 int pend_prio
= NVIC_NOEXC_PRIO
;
213 int active_prio
= NVIC_NOEXC_PRIO
;
215 bool pending_is_s_banked
= false;
217 /* R_CQRV: precedence is by:
218 * - lowest group priority; if both the same then
219 * - lowest subpriority; if both the same then
220 * - lowest exception number; if both the same (ie banked) then
221 * - secure exception takes precedence
222 * Compare pseudocode RawExecutionPriority.
223 * Annoyingly, now we have two prigroup values (for S and NS)
224 * we can't do the loop comparison on raw priority values.
226 for (i
= 1; i
< s
->num_irq
; i
++) {
227 for (bank
= M_REG_S
; bank
>= M_REG_NS
; bank
--) {
232 if (bank
== M_REG_S
) {
233 if (!exc_is_banked(i
)) {
236 vec
= &s
->sec_vectors
[i
];
237 targets_secure
= true;
239 vec
= &s
->vectors
[i
];
240 targets_secure
= !exc_is_banked(i
) && exc_targets_secure(s
, i
);
243 prio
= exc_group_prio(s
, vec
->prio
, targets_secure
);
244 if (vec
->enabled
&& vec
->pending
&& prio
< pend_prio
) {
247 pending_is_s_banked
= (bank
== M_REG_S
);
249 if (vec
->active
&& prio
< active_prio
) {
255 s
->vectpending_is_s_banked
= pending_is_s_banked
;
256 s
->vectpending
= pend_irq
;
257 s
->vectpending_prio
= pend_prio
;
258 s
->exception_prio
= active_prio
;
260 trace_nvic_recompute_state_secure(s
->vectpending
,
261 s
->vectpending_is_s_banked
,
266 /* Recompute vectpending and exception_prio */
267 static void nvic_recompute_state(NVICState
*s
)
270 int pend_prio
= NVIC_NOEXC_PRIO
;
271 int active_prio
= NVIC_NOEXC_PRIO
;
274 /* In theory we could write one function that handled both
275 * the "security extension present" and "not present"; however
276 * the security related changes significantly complicate the
277 * recomputation just by themselves and mixing both cases together
278 * would be even worse, so we retain a separate non-secure-only
279 * version for CPUs which don't implement the security extension.
281 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
282 nvic_recompute_state_secure(s
);
286 for (i
= 1; i
< s
->num_irq
; i
++) {
287 VecInfo
*vec
= &s
->vectors
[i
];
289 if (vec
->enabled
&& vec
->pending
&& vec
->prio
< pend_prio
) {
290 pend_prio
= vec
->prio
;
293 if (vec
->active
&& vec
->prio
< active_prio
) {
294 active_prio
= vec
->prio
;
298 if (active_prio
> 0) {
299 active_prio
&= nvic_gprio_mask(s
, false);
303 pend_prio
&= nvic_gprio_mask(s
, false);
306 s
->vectpending
= pend_irq
;
307 s
->vectpending_prio
= pend_prio
;
308 s
->exception_prio
= active_prio
;
310 trace_nvic_recompute_state(s
->vectpending
,
315 /* Return the current execution priority of the CPU
316 * (equivalent to the pseudocode ExecutionPriority function).
317 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
319 static inline int nvic_exec_prio(NVICState
*s
)
321 CPUARMState
*env
= &s
->cpu
->env
;
322 int running
= NVIC_NOEXC_PRIO
;
324 if (env
->v7m
.basepri
[M_REG_NS
] > 0) {
325 running
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_NS
], M_REG_NS
);
328 if (env
->v7m
.basepri
[M_REG_S
] > 0) {
329 int basepri
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_S
], M_REG_S
);
330 if (running
> basepri
) {
335 if (env
->v7m
.primask
[M_REG_NS
]) {
336 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
337 if (running
> NVIC_NS_PRIO_LIMIT
) {
338 running
= NVIC_NS_PRIO_LIMIT
;
345 if (env
->v7m
.primask
[M_REG_S
]) {
349 if (env
->v7m
.faultmask
[M_REG_NS
]) {
350 if (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
353 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
354 if (running
> NVIC_NS_PRIO_LIMIT
) {
355 running
= NVIC_NS_PRIO_LIMIT
;
363 if (env
->v7m
.faultmask
[M_REG_S
]) {
364 running
= (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) ? -3 : -1;
367 /* consider priority of active handler */
368 return MIN(running
, s
->exception_prio
);
371 bool armv7m_nvic_neg_prio_requested(void *opaque
, bool secure
)
373 /* Return true if the requested execution priority is negative
374 * for the specified security state, ie that security state
375 * has an active NMI or HardFault or has set its FAULTMASK.
376 * Note that this is not the same as whether the execution
377 * priority is actually negative (for instance AIRCR.PRIS may
378 * mean we don't allow FAULTMASK_NS to actually make the execution
379 * priority negative). Compare pseudocode IsReqExcPriNeg().
381 NVICState
*s
= opaque
;
383 if (s
->cpu
->env
.v7m
.faultmask
[secure
]) {
387 if (secure
? s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
:
388 s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
392 if (s
->vectors
[ARMV7M_EXCP_NMI
].active
&&
393 exc_targets_secure(s
, ARMV7M_EXCP_NMI
) == secure
) {
400 bool armv7m_nvic_can_take_pending_exception(void *opaque
)
402 NVICState
*s
= opaque
;
404 return nvic_exec_prio(s
) > nvic_pending_prio(s
);
407 int armv7m_nvic_raw_execution_priority(void *opaque
)
409 NVICState
*s
= opaque
;
411 return s
->exception_prio
;
414 /* caller must call nvic_irq_update() after this.
415 * secure indicates the bank to use for banked exceptions (we assert if
416 * we are passed secure=true for a non-banked exception).
418 static void set_prio(NVICState
*s
, unsigned irq
, bool secure
, uint8_t prio
)
420 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
421 assert(irq
< s
->num_irq
);
423 prio
&= MAKE_64BIT_MASK(8 - s
->num_prio_bits
, s
->num_prio_bits
);
426 assert(exc_is_banked(irq
));
427 s
->sec_vectors
[irq
].prio
= prio
;
429 s
->vectors
[irq
].prio
= prio
;
432 trace_nvic_set_prio(irq
, secure
, prio
);
435 /* Return the current raw priority register value.
436 * secure indicates the bank to use for banked exceptions (we assert if
437 * we are passed secure=true for a non-banked exception).
439 static int get_prio(NVICState
*s
, unsigned irq
, bool secure
)
441 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
442 assert(irq
< s
->num_irq
);
445 assert(exc_is_banked(irq
));
446 return s
->sec_vectors
[irq
].prio
;
448 return s
->vectors
[irq
].prio
;
452 /* Recompute state and assert irq line accordingly.
453 * Must be called after changes to:
454 * vec->active, vec->enabled, vec->pending or vec->prio for any vector
457 static void nvic_irq_update(NVICState
*s
)
462 nvic_recompute_state(s
);
463 pend_prio
= nvic_pending_prio(s
);
465 /* Raise NVIC output if this IRQ would be taken, except that we
466 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
467 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
468 * to those CPU registers don't cause us to recalculate the NVIC
471 lvl
= (pend_prio
< s
->exception_prio
);
472 trace_nvic_irq_update(s
->vectpending
, pend_prio
, s
->exception_prio
, lvl
);
473 qemu_set_irq(s
->excpout
, lvl
);
477 * armv7m_nvic_clear_pending: mark the specified exception as not pending
479 * @irq: the exception number to mark as not pending
480 * @secure: false for non-banked exceptions or for the nonsecure
481 * version of a banked exception, true for the secure version of a banked
484 * Marks the specified exception as not pending. Note that we will assert()
485 * if @secure is true and @irq does not specify one of the fixed set
486 * of architecturally banked exceptions.
488 static void armv7m_nvic_clear_pending(void *opaque
, int irq
, bool secure
)
490 NVICState
*s
= (NVICState
*)opaque
;
493 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
496 assert(exc_is_banked(irq
));
497 vec
= &s
->sec_vectors
[irq
];
499 vec
= &s
->vectors
[irq
];
501 trace_nvic_clear_pending(irq
, secure
, vec
->enabled
, vec
->prio
);
508 static void do_armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
,
511 /* Pend an exception, including possibly escalating it to HardFault.
513 * This function handles both "normal" pending of interrupts and
514 * exceptions, and also derived exceptions (ones which occur as
515 * a result of trying to take some other exception).
517 * If derived == true, the caller guarantees that we are part way through
518 * trying to take an exception (but have not yet called
519 * armv7m_nvic_acknowledge_irq() to make it active), and so:
520 * - s->vectpending is the "original exception" we were trying to take
521 * - irq is the "derived exception"
522 * - nvic_exec_prio(s) gives the priority before exception entry
523 * Here we handle the prioritization logic which the pseudocode puts
524 * in the DerivedLateArrival() function.
527 NVICState
*s
= (NVICState
*)opaque
;
528 bool banked
= exc_is_banked(irq
);
532 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
533 assert(!secure
|| banked
);
535 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
537 targets_secure
= banked
? secure
: exc_targets_secure(s
, irq
);
539 trace_nvic_set_pending(irq
, secure
, targets_secure
,
540 derived
, vec
->enabled
, vec
->prio
);
543 /* Derived exceptions are always synchronous. */
544 assert(irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
);
546 if (irq
== ARMV7M_EXCP_DEBUG
&&
547 exc_group_prio(s
, vec
->prio
, secure
) >= nvic_exec_prio(s
)) {
548 /* DebugMonitorFault, but its priority is lower than the
549 * preempted exception priority: just ignore it.
554 if (irq
== ARMV7M_EXCP_HARD
&& vec
->prio
>= s
->vectpending_prio
) {
555 /* If this is a terminal exception (one which means we cannot
556 * take the original exception, like a failure to read its
557 * vector table entry), then we must take the derived exception.
558 * If the derived exception can't take priority over the
559 * original exception, then we go into Lockup.
561 * For QEMU, we rely on the fact that a derived exception is
562 * terminal if and only if it's reported to us as HardFault,
563 * which saves having to have an extra argument is_terminal
564 * that we'd only use in one place.
566 cpu_abort(&s
->cpu
->parent_obj
,
567 "Lockup: can't take terminal derived exception "
568 "(original exception priority %d)\n",
569 s
->vectpending_prio
);
571 /* We now continue with the same code as for a normal pending
572 * exception, which will cause us to pend the derived exception.
573 * We'll then take either the original or the derived exception
574 * based on which is higher priority by the usual mechanism
575 * for selecting the highest priority pending interrupt.
579 if (irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
) {
580 /* If a synchronous exception is pending then it may be
581 * escalated to HardFault if:
582 * * it is equal or lower priority to current execution
584 * (ie we need to take it immediately but we can't do so).
585 * Asynchronous exceptions (and interrupts) simply remain pending.
587 * For QEMU, we don't have any imprecise (asynchronous) faults,
588 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
590 * Debug exceptions are awkward because only Debug exceptions
591 * resulting from the BKPT instruction should be escalated,
592 * but we don't currently implement any Debug exceptions other
593 * than those that result from BKPT, so we treat all debug exceptions
594 * as needing escalation.
596 * This all means we can identify whether to escalate based only on
597 * the exception number and don't (yet) need the caller to explicitly
598 * tell us whether this exception is synchronous or not.
600 int running
= nvic_exec_prio(s
);
601 bool escalate
= false;
603 if (exc_group_prio(s
, vec
->prio
, secure
) >= running
) {
604 trace_nvic_escalate_prio(irq
, vec
->prio
, running
);
606 } else if (!vec
->enabled
) {
607 trace_nvic_escalate_disabled(irq
);
613 /* We need to escalate this exception to a synchronous HardFault.
614 * If BFHFNMINS is set then we escalate to the banked HF for
615 * the target security state of the original exception; otherwise
616 * we take a Secure HardFault.
618 irq
= ARMV7M_EXCP_HARD
;
619 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
) &&
621 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))) {
622 vec
= &s
->sec_vectors
[irq
];
624 vec
= &s
->vectors
[irq
];
626 if (running
<= vec
->prio
) {
627 /* We want to escalate to HardFault but we can't take the
628 * synchronous HardFault at this point either. This is a
629 * Lockup condition due to a guest bug. We don't model
630 * Lockup, so report via cpu_abort() instead.
632 cpu_abort(&s
->cpu
->parent_obj
,
633 "Lockup: can't escalate %d to HardFault "
634 "(current priority %d)\n", irq
, running
);
637 /* HF may be banked but there is only one shared HFSR */
638 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
648 void armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
)
650 do_armv7m_nvic_set_pending(opaque
, irq
, secure
, false);
653 void armv7m_nvic_set_pending_derived(void *opaque
, int irq
, bool secure
)
655 do_armv7m_nvic_set_pending(opaque
, irq
, secure
, true);
658 /* Make pending IRQ active. */
659 void armv7m_nvic_acknowledge_irq(void *opaque
)
661 NVICState
*s
= (NVICState
*)opaque
;
662 CPUARMState
*env
= &s
->cpu
->env
;
663 const int pending
= s
->vectpending
;
664 const int running
= nvic_exec_prio(s
);
667 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
669 if (s
->vectpending_is_s_banked
) {
670 vec
= &s
->sec_vectors
[pending
];
672 vec
= &s
->vectors
[pending
];
675 assert(vec
->enabled
);
676 assert(vec
->pending
);
678 assert(s
->vectpending_prio
< running
);
680 trace_nvic_acknowledge_irq(pending
, s
->vectpending_prio
);
685 write_v7m_exception(env
, s
->vectpending
);
690 void armv7m_nvic_get_pending_irq_info(void *opaque
,
691 int *pirq
, bool *ptargets_secure
)
693 NVICState
*s
= (NVICState
*)opaque
;
694 const int pending
= s
->vectpending
;
697 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
699 if (s
->vectpending_is_s_banked
) {
700 targets_secure
= true;
702 targets_secure
= !exc_is_banked(pending
) &&
703 exc_targets_secure(s
, pending
);
706 trace_nvic_get_pending_irq_info(pending
, targets_secure
);
708 *ptargets_secure
= targets_secure
;
712 int armv7m_nvic_complete_irq(void *opaque
, int irq
, bool secure
)
714 NVICState
*s
= (NVICState
*)opaque
;
718 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
720 if (secure
&& exc_is_banked(irq
)) {
721 vec
= &s
->sec_vectors
[irq
];
723 vec
= &s
->vectors
[irq
];
726 trace_nvic_complete_irq(irq
, secure
);
729 /* Tell the caller this was an illegal exception return */
733 ret
= nvic_rettobase(s
);
737 /* Re-pend the exception if it's still held high; only
738 * happens for extenal IRQs
740 assert(irq
>= NVIC_FIRST_IRQ
);
749 /* callback when external interrupt line is changed */
750 static void set_irq_level(void *opaque
, int n
, int level
)
752 NVICState
*s
= opaque
;
757 assert(n
>= NVIC_FIRST_IRQ
&& n
< s
->num_irq
);
759 trace_nvic_set_irq_level(n
, level
);
761 /* The pending status of an external interrupt is
762 * latched on rising edge and exception handler return.
764 * Pulsing the IRQ will always run the handler
765 * once, and the handler will re-run until the
766 * level is low when the handler completes.
768 vec
= &s
->vectors
[n
];
769 if (level
!= vec
->level
) {
772 armv7m_nvic_set_pending(s
, n
, false);
777 /* callback when external NMI line is changed */
778 static void nvic_nmi_trigger(void *opaque
, int n
, int level
)
780 NVICState
*s
= opaque
;
782 trace_nvic_set_nmi_level(level
);
785 * The architecture doesn't specify whether NMI should share
786 * the normal-interrupt behaviour of being resampled on
787 * exception handler return. We choose not to, so just
788 * set NMI pending here and don't track the current level.
791 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
795 static uint32_t nvic_readl(NVICState
*s
, uint32_t offset
, MemTxAttrs attrs
)
797 ARMCPU
*cpu
= s
->cpu
;
801 case 4: /* Interrupt Control Type. */
802 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
805 return ((s
->num_irq
- NVIC_FIRST_IRQ
) / 32) - 1;
806 case 0xc: /* CPPWR */
807 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
810 /* We make the IMPDEF choice that nothing can ever go into a
811 * non-retentive power state, which allows us to RAZ/WI this.
814 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
816 int startvec
= 8 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
819 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
826 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
827 if (s
->itns
[startvec
+ i
]) {
833 case 0xd00: /* CPUID Base. */
835 case 0xd04: /* Interrupt Control State (ICSR) */
837 val
= cpu
->env
.v7m
.exception
;
839 val
|= (s
->vectpending
& 0xff) << 12;
840 /* ISRPENDING - set if any external IRQ is pending */
841 if (nvic_isrpending(s
)) {
844 /* RETTOBASE - set if only one handler is active */
845 if (nvic_rettobase(s
)) {
850 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
854 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
859 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
863 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
868 if ((attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))
869 && s
->vectors
[ARMV7M_EXCP_NMI
].pending
) {
872 /* ISRPREEMPT: RES0 when halting debug not implemented */
873 /* STTNS: RES0 for the Main Extension */
875 case 0xd08: /* Vector Table Offset. */
876 return cpu
->env
.v7m
.vecbase
[attrs
.secure
];
877 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
878 val
= 0xfa050000 | (s
->prigroup
[attrs
.secure
] << 8);
880 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
881 val
|= cpu
->env
.v7m
.aircr
;
883 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
884 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
885 * security isn't supported then BFHFNMINS is RAO (and
886 * the bit in env.v7m.aircr is always set).
888 val
|= cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
;
892 case 0xd10: /* System Control. */
893 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
896 return cpu
->env
.v7m
.scr
[attrs
.secure
];
897 case 0xd14: /* Configuration Control. */
898 /* The BFHFNMIGN bit is the only non-banked bit; we
899 * keep it in the non-secure copy of the register.
901 val
= cpu
->env
.v7m
.ccr
[attrs
.secure
];
902 val
|= cpu
->env
.v7m
.ccr
[M_REG_NS
] & R_V7M_CCR_BFHFNMIGN_MASK
;
904 case 0xd24: /* System Handler Control and State (SHCSR) */
905 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
910 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
) {
913 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
) {
916 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
) {
919 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
) {
922 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
) {
925 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
928 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
) {
931 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
) {
934 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
) {
937 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
) {
940 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
943 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
) {
946 /* SecureFault is not banked but is always RAZ/WI to NS */
947 if (s
->vectors
[ARMV7M_EXCP_SECURE
].active
) {
950 if (s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
) {
953 if (s
->vectors
[ARMV7M_EXCP_SECURE
].pending
) {
957 if (s
->vectors
[ARMV7M_EXCP_MEM
].active
) {
960 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
961 /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
962 if (s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
965 if (s
->vectors
[ARMV7M_EXCP_HARD
].pending
) {
969 if (s
->vectors
[ARMV7M_EXCP_USAGE
].active
) {
972 if (s
->vectors
[ARMV7M_EXCP_SVC
].active
) {
975 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].active
) {
978 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
981 if (s
->vectors
[ARMV7M_EXCP_USAGE
].pending
) {
984 if (s
->vectors
[ARMV7M_EXCP_MEM
].pending
) {
987 if (s
->vectors
[ARMV7M_EXCP_SVC
].pending
) {
990 if (s
->vectors
[ARMV7M_EXCP_MEM
].enabled
) {
993 if (s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
997 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
998 if (s
->vectors
[ARMV7M_EXCP_BUS
].active
) {
1001 if (s
->vectors
[ARMV7M_EXCP_BUS
].pending
) {
1004 if (s
->vectors
[ARMV7M_EXCP_BUS
].enabled
) {
1007 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
1008 s
->vectors
[ARMV7M_EXCP_NMI
].active
) {
1009 /* NMIACT is not present in v7M */
1014 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1015 if (s
->vectors
[ARMV7M_EXCP_DEBUG
].active
) {
1019 case 0xd2c: /* Hard Fault Status. */
1020 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1023 return cpu
->env
.v7m
.hfsr
;
1024 case 0xd30: /* Debug Fault Status. */
1025 return cpu
->env
.v7m
.dfsr
;
1026 case 0xd34: /* MMFAR MemManage Fault Address */
1027 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1030 return cpu
->env
.v7m
.mmfar
[attrs
.secure
];
1031 case 0xd38: /* Bus Fault Address. */
1032 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1035 return cpu
->env
.v7m
.bfar
;
1036 case 0xd3c: /* Aux Fault Status. */
1037 /* TODO: Implement fault status registers. */
1038 qemu_log_mask(LOG_UNIMP
,
1039 "Aux Fault status registers unimplemented\n");
1041 case 0xd40: /* PFR0. */
1042 return cpu
->id_pfr0
;
1043 case 0xd44: /* PFR1. */
1044 return cpu
->id_pfr1
;
1045 case 0xd48: /* DFR0. */
1046 return cpu
->id_dfr0
;
1047 case 0xd4c: /* AFR0. */
1048 return cpu
->id_afr0
;
1049 case 0xd50: /* MMFR0. */
1050 return cpu
->id_mmfr0
;
1051 case 0xd54: /* MMFR1. */
1052 return cpu
->id_mmfr1
;
1053 case 0xd58: /* MMFR2. */
1054 return cpu
->id_mmfr2
;
1055 case 0xd5c: /* MMFR3. */
1056 return cpu
->id_mmfr3
;
1057 case 0xd60: /* ISAR0. */
1058 return cpu
->isar
.id_isar0
;
1059 case 0xd64: /* ISAR1. */
1060 return cpu
->isar
.id_isar1
;
1061 case 0xd68: /* ISAR2. */
1062 return cpu
->isar
.id_isar2
;
1063 case 0xd6c: /* ISAR3. */
1064 return cpu
->isar
.id_isar3
;
1065 case 0xd70: /* ISAR4. */
1066 return cpu
->isar
.id_isar4
;
1067 case 0xd74: /* ISAR5. */
1068 return cpu
->isar
.id_isar5
;
1069 case 0xd78: /* CLIDR */
1071 case 0xd7c: /* CTR */
1073 case 0xd80: /* CSSIDR */
1075 int idx
= cpu
->env
.v7m
.csselr
[attrs
.secure
] & R_V7M_CSSELR_INDEX_MASK
;
1076 return cpu
->ccsidr
[idx
];
1078 case 0xd84: /* CSSELR */
1079 return cpu
->env
.v7m
.csselr
[attrs
.secure
];
1080 case 0xd88: /* CPACR */
1081 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1084 return cpu
->env
.v7m
.cpacr
[attrs
.secure
];
1085 case 0xd8c: /* NSACR */
1086 if (!attrs
.secure
|| !arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1089 return cpu
->env
.v7m
.nsacr
;
1090 /* TODO: Implement debug registers. */
1091 case 0xd90: /* MPU_TYPE */
1092 /* Unified MPU; if the MPU is not present this value is zero */
1093 return cpu
->pmsav7_dregion
<< 8;
1095 case 0xd94: /* MPU_CTRL */
1096 return cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
];
1097 case 0xd98: /* MPU_RNR */
1098 return cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1099 case 0xd9c: /* MPU_RBAR */
1100 case 0xda4: /* MPU_RBAR_A1 */
1101 case 0xdac: /* MPU_RBAR_A2 */
1102 case 0xdb4: /* MPU_RBAR_A3 */
1104 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1106 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1107 /* PMSAv8M handling of the aliases is different from v7M:
1108 * aliases A1, A2, A3 override the low two bits of the region
1109 * number in MPU_RNR, and there is no 'region' field in the
1112 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1114 region
= deposit32(region
, 0, 2, aliasno
);
1116 if (region
>= cpu
->pmsav7_dregion
) {
1119 return cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
];
1122 if (region
>= cpu
->pmsav7_dregion
) {
1125 return (cpu
->env
.pmsav7
.drbar
[region
] & ~0x1f) | (region
& 0xf);
1127 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1128 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1129 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1130 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1132 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1134 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1135 /* PMSAv8M handling of the aliases is different from v7M:
1136 * aliases A1, A2, A3 override the low two bits of the region
1137 * number in MPU_RNR.
1139 int aliasno
= (offset
- 0xda0) / 8; /* 0..3 */
1141 region
= deposit32(region
, 0, 2, aliasno
);
1143 if (region
>= cpu
->pmsav7_dregion
) {
1146 return cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
];
1149 if (region
>= cpu
->pmsav7_dregion
) {
1152 return ((cpu
->env
.pmsav7
.dracr
[region
] & 0xffff) << 16) |
1153 (cpu
->env
.pmsav7
.drsr
[region
] & 0xffff);
1155 case 0xdc0: /* MPU_MAIR0 */
1156 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1159 return cpu
->env
.pmsav8
.mair0
[attrs
.secure
];
1160 case 0xdc4: /* MPU_MAIR1 */
1161 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1164 return cpu
->env
.pmsav8
.mair1
[attrs
.secure
];
1165 case 0xdd0: /* SAU_CTRL */
1166 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1169 if (!attrs
.secure
) {
1172 return cpu
->env
.sau
.ctrl
;
1173 case 0xdd4: /* SAU_TYPE */
1174 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1177 if (!attrs
.secure
) {
1180 return cpu
->sau_sregion
;
1181 case 0xdd8: /* SAU_RNR */
1182 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1185 if (!attrs
.secure
) {
1188 return cpu
->env
.sau
.rnr
;
1189 case 0xddc: /* SAU_RBAR */
1191 int region
= cpu
->env
.sau
.rnr
;
1193 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1196 if (!attrs
.secure
) {
1199 if (region
>= cpu
->sau_sregion
) {
1202 return cpu
->env
.sau
.rbar
[region
];
1204 case 0xde0: /* SAU_RLAR */
1206 int region
= cpu
->env
.sau
.rnr
;
1208 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1211 if (!attrs
.secure
) {
1214 if (region
>= cpu
->sau_sregion
) {
1217 return cpu
->env
.sau
.rlar
[region
];
1219 case 0xde4: /* SFSR */
1220 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1223 if (!attrs
.secure
) {
1226 return cpu
->env
.v7m
.sfsr
;
1227 case 0xde8: /* SFAR */
1228 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1231 if (!attrs
.secure
) {
1234 return cpu
->env
.v7m
.sfar
;
1235 case 0xf34: /* FPCCR */
1236 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1240 return cpu
->env
.v7m
.fpccr
[M_REG_S
];
1243 * NS can read LSPEN, CLRONRET and MONRDY. It can read
1244 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0;
1245 * other non-banked bits RAZ.
1246 * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set.
1248 uint32_t value
= cpu
->env
.v7m
.fpccr
[M_REG_S
];
1249 uint32_t mask
= R_V7M_FPCCR_LSPEN_MASK
|
1250 R_V7M_FPCCR_CLRONRET_MASK
|
1251 R_V7M_FPCCR_MONRDY_MASK
;
1253 if (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1254 mask
|= R_V7M_FPCCR_BFRDY_MASK
| R_V7M_FPCCR_HFRDY_MASK
;
1259 value
|= cpu
->env
.v7m
.fpccr
[M_REG_NS
];
1262 case 0xf38: /* FPCAR */
1263 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1266 return cpu
->env
.v7m
.fpcar
[attrs
.secure
];
1267 case 0xf3c: /* FPDSCR */
1268 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1271 return cpu
->env
.v7m
.fpdscr
[attrs
.secure
];
1272 case 0xf40: /* MVFR0 */
1273 return cpu
->isar
.mvfr0
;
1274 case 0xf44: /* MVFR1 */
1275 return cpu
->isar
.mvfr1
;
1276 case 0xf48: /* MVFR2 */
1277 return cpu
->isar
.mvfr2
;
1280 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
1285 static void nvic_writel(NVICState
*s
, uint32_t offset
, uint32_t value
,
1288 ARMCPU
*cpu
= s
->cpu
;
1291 case 0xc: /* CPPWR */
1292 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1295 /* Make the IMPDEF choice to RAZ/WI this. */
1297 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
1299 int startvec
= 8 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
1302 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1305 if (!attrs
.secure
) {
1308 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
1309 s
->itns
[startvec
+ i
] = (value
>> i
) & 1;
1314 case 0xd04: /* Interrupt Control State (ICSR) */
1315 if (attrs
.secure
|| cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1316 if (value
& (1 << 31)) {
1317 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
1318 } else if (value
& (1 << 30) &&
1319 arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1320 /* PENDNMICLR didn't exist in v7M */
1321 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_NMI
, false);
1324 if (value
& (1 << 28)) {
1325 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1326 } else if (value
& (1 << 27)) {
1327 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1329 if (value
& (1 << 26)) {
1330 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1331 } else if (value
& (1 << 25)) {
1332 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1335 case 0xd08: /* Vector Table Offset. */
1336 cpu
->env
.v7m
.vecbase
[attrs
.secure
] = value
& 0xffffff80;
1338 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
1339 if ((value
>> R_V7M_AIRCR_VECTKEY_SHIFT
) == 0x05fa) {
1340 if (value
& R_V7M_AIRCR_SYSRESETREQ_MASK
) {
1342 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_SYSRESETREQS_MASK
)) {
1343 qemu_irq_pulse(s
->sysresetreq
);
1346 if (value
& R_V7M_AIRCR_VECTCLRACTIVE_MASK
) {
1347 qemu_log_mask(LOG_GUEST_ERROR
,
1348 "Setting VECTCLRACTIVE when not in DEBUG mode "
1349 "is UNPREDICTABLE\n");
1351 if (value
& R_V7M_AIRCR_VECTRESET_MASK
) {
1352 /* NB: this bit is RES0 in v8M */
1353 qemu_log_mask(LOG_GUEST_ERROR
,
1354 "Setting VECTRESET when not in DEBUG mode "
1355 "is UNPREDICTABLE\n");
1357 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1358 s
->prigroup
[attrs
.secure
] =
1360 R_V7M_AIRCR_PRIGROUP_SHIFT
,
1361 R_V7M_AIRCR_PRIGROUP_LENGTH
);
1364 /* These bits are only writable by secure */
1365 cpu
->env
.v7m
.aircr
= value
&
1366 (R_V7M_AIRCR_SYSRESETREQS_MASK
|
1367 R_V7M_AIRCR_BFHFNMINS_MASK
|
1368 R_V7M_AIRCR_PRIS_MASK
);
1369 /* BFHFNMINS changes the priority of Secure HardFault, and
1370 * allows a pending Non-secure HardFault to preempt (which
1371 * we implement by marking it enabled).
1373 if (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1374 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -3;
1375 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1377 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1378 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
1384 case 0xd10: /* System Control. */
1385 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1388 /* We don't implement deep-sleep so these bits are RAZ/WI.
1389 * The other bits in the register are banked.
1390 * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which
1391 * is architecturally permitted.
1393 value
&= ~(R_V7M_SCR_SLEEPDEEP_MASK
| R_V7M_SCR_SLEEPDEEPS_MASK
);
1394 cpu
->env
.v7m
.scr
[attrs
.secure
] = value
;
1396 case 0xd14: /* Configuration Control. */
1397 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1401 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
1402 value
&= (R_V7M_CCR_STKALIGN_MASK
|
1403 R_V7M_CCR_BFHFNMIGN_MASK
|
1404 R_V7M_CCR_DIV_0_TRP_MASK
|
1405 R_V7M_CCR_UNALIGN_TRP_MASK
|
1406 R_V7M_CCR_USERSETMPEND_MASK
|
1407 R_V7M_CCR_NONBASETHRDENA_MASK
);
1409 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1410 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
1411 value
|= R_V7M_CCR_NONBASETHRDENA_MASK
1412 | R_V7M_CCR_STKALIGN_MASK
;
1415 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
1416 cpu
->env
.v7m
.ccr
[M_REG_NS
] =
1417 (cpu
->env
.v7m
.ccr
[M_REG_NS
] & ~R_V7M_CCR_BFHFNMIGN_MASK
)
1418 | (value
& R_V7M_CCR_BFHFNMIGN_MASK
);
1419 value
&= ~R_V7M_CCR_BFHFNMIGN_MASK
;
1422 cpu
->env
.v7m
.ccr
[attrs
.secure
] = value
;
1424 case 0xd24: /* System Handler Control and State (SHCSR) */
1425 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1429 s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1430 /* Secure HardFault active bit cannot be written */
1431 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1432 s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1433 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
=
1434 (value
& (1 << 10)) != 0;
1435 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
=
1436 (value
& (1 << 11)) != 0;
1437 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
=
1438 (value
& (1 << 12)) != 0;
1439 s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1440 s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1441 s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1442 s
->sec_vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1443 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
=
1444 (value
& (1 << 18)) != 0;
1445 s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1446 /* SecureFault not banked, but RAZ/WI to NS */
1447 s
->vectors
[ARMV7M_EXCP_SECURE
].active
= (value
& (1 << 4)) != 0;
1448 s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
= (value
& (1 << 19)) != 0;
1449 s
->vectors
[ARMV7M_EXCP_SECURE
].pending
= (value
& (1 << 20)) != 0;
1451 s
->vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1452 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1453 /* HARDFAULTPENDED is not present in v7M */
1454 s
->vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1456 s
->vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1457 s
->vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1458 s
->vectors
[ARMV7M_EXCP_PENDSV
].active
= (value
& (1 << 10)) != 0;
1459 s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
= (value
& (1 << 11)) != 0;
1460 s
->vectors
[ARMV7M_EXCP_USAGE
].pending
= (value
& (1 << 12)) != 0;
1461 s
->vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1462 s
->vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1463 s
->vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1464 s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
1466 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1467 s
->vectors
[ARMV7M_EXCP_BUS
].active
= (value
& (1 << 1)) != 0;
1468 s
->vectors
[ARMV7M_EXCP_BUS
].pending
= (value
& (1 << 14)) != 0;
1469 s
->vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1471 /* NMIACT can only be written if the write is of a zero, with
1472 * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
1474 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1475 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1476 (value
& (1 << 5)) == 0) {
1477 s
->vectors
[ARMV7M_EXCP_NMI
].active
= 0;
1479 /* HARDFAULTACT can only be written if the write is of a zero
1480 * to the non-secure HardFault state by the CPU in secure state.
1481 * The only case where we can be targeting the non-secure HF state
1482 * when in secure state is if this is a write via the NS alias
1483 * and BFHFNMINS is 1.
1485 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1486 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1487 (value
& (1 << 2)) == 0) {
1488 s
->vectors
[ARMV7M_EXCP_HARD
].active
= 0;
1491 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1492 s
->vectors
[ARMV7M_EXCP_DEBUG
].active
= (value
& (1 << 8)) != 0;
1495 case 0xd2c: /* Hard Fault Status. */
1496 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1499 cpu
->env
.v7m
.hfsr
&= ~value
; /* W1C */
1501 case 0xd30: /* Debug Fault Status. */
1502 cpu
->env
.v7m
.dfsr
&= ~value
; /* W1C */
1504 case 0xd34: /* Mem Manage Address. */
1505 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1508 cpu
->env
.v7m
.mmfar
[attrs
.secure
] = value
;
1510 case 0xd38: /* Bus Fault Address. */
1511 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1514 cpu
->env
.v7m
.bfar
= value
;
1516 case 0xd3c: /* Aux Fault Status. */
1517 qemu_log_mask(LOG_UNIMP
,
1518 "NVIC: Aux fault status registers unimplemented\n");
1520 case 0xd84: /* CSSELR */
1521 if (!arm_v7m_csselr_razwi(cpu
)) {
1522 cpu
->env
.v7m
.csselr
[attrs
.secure
] = value
& R_V7M_CSSELR_INDEX_MASK
;
1525 case 0xd88: /* CPACR */
1526 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1527 /* We implement only the Floating Point extension's CP10/CP11 */
1528 cpu
->env
.v7m
.cpacr
[attrs
.secure
] = value
& (0xf << 20);
1531 case 0xd8c: /* NSACR */
1532 if (attrs
.secure
&& arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1533 /* We implement only the Floating Point extension's CP10/CP11 */
1534 cpu
->env
.v7m
.nsacr
= value
& (3 << 10);
1537 case 0xd90: /* MPU_TYPE */
1539 case 0xd94: /* MPU_CTRL */
1541 (R_V7M_MPU_CTRL_HFNMIENA_MASK
| R_V7M_MPU_CTRL_ENABLE_MASK
))
1542 == R_V7M_MPU_CTRL_HFNMIENA_MASK
) {
1543 qemu_log_mask(LOG_GUEST_ERROR
, "MPU_CTRL: HFNMIENA and !ENABLE is "
1546 cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
]
1547 = value
& (R_V7M_MPU_CTRL_ENABLE_MASK
|
1548 R_V7M_MPU_CTRL_HFNMIENA_MASK
|
1549 R_V7M_MPU_CTRL_PRIVDEFENA_MASK
);
1550 tlb_flush(CPU(cpu
));
1552 case 0xd98: /* MPU_RNR */
1553 if (value
>= cpu
->pmsav7_dregion
) {
1554 qemu_log_mask(LOG_GUEST_ERROR
, "MPU region out of range %"
1555 PRIu32
"/%" PRIu32
"\n",
1556 value
, cpu
->pmsav7_dregion
);
1558 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = value
;
1561 case 0xd9c: /* MPU_RBAR */
1562 case 0xda4: /* MPU_RBAR_A1 */
1563 case 0xdac: /* MPU_RBAR_A2 */
1564 case 0xdb4: /* MPU_RBAR_A3 */
1568 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1569 /* PMSAv8M handling of the aliases is different from v7M:
1570 * aliases A1, A2, A3 override the low two bits of the region
1571 * number in MPU_RNR, and there is no 'region' field in the
1574 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1576 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1578 region
= deposit32(region
, 0, 2, aliasno
);
1580 if (region
>= cpu
->pmsav7_dregion
) {
1583 cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
] = value
;
1584 tlb_flush(CPU(cpu
));
1588 if (value
& (1 << 4)) {
1589 /* VALID bit means use the region number specified in this
1590 * value and also update MPU_RNR.REGION with that value.
1592 region
= extract32(value
, 0, 4);
1593 if (region
>= cpu
->pmsav7_dregion
) {
1594 qemu_log_mask(LOG_GUEST_ERROR
,
1595 "MPU region out of range %u/%" PRIu32
"\n",
1596 region
, cpu
->pmsav7_dregion
);
1599 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = region
;
1601 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1604 if (region
>= cpu
->pmsav7_dregion
) {
1608 cpu
->env
.pmsav7
.drbar
[region
] = value
& ~0x1f;
1609 tlb_flush(CPU(cpu
));
1612 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1613 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1614 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1615 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1617 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1619 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1620 /* PMSAv8M handling of the aliases is different from v7M:
1621 * aliases A1, A2, A3 override the low two bits of the region
1622 * number in MPU_RNR.
1624 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1626 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1628 region
= deposit32(region
, 0, 2, aliasno
);
1630 if (region
>= cpu
->pmsav7_dregion
) {
1633 cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
] = value
;
1634 tlb_flush(CPU(cpu
));
1638 if (region
>= cpu
->pmsav7_dregion
) {
1642 cpu
->env
.pmsav7
.drsr
[region
] = value
& 0xff3f;
1643 cpu
->env
.pmsav7
.dracr
[region
] = (value
>> 16) & 0x173f;
1644 tlb_flush(CPU(cpu
));
1647 case 0xdc0: /* MPU_MAIR0 */
1648 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1651 if (cpu
->pmsav7_dregion
) {
1652 /* Register is RES0 if no MPU regions are implemented */
1653 cpu
->env
.pmsav8
.mair0
[attrs
.secure
] = value
;
1655 /* We don't need to do anything else because memory attributes
1656 * only affect cacheability, and we don't implement caching.
1659 case 0xdc4: /* MPU_MAIR1 */
1660 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1663 if (cpu
->pmsav7_dregion
) {
1664 /* Register is RES0 if no MPU regions are implemented */
1665 cpu
->env
.pmsav8
.mair1
[attrs
.secure
] = value
;
1667 /* We don't need to do anything else because memory attributes
1668 * only affect cacheability, and we don't implement caching.
1671 case 0xdd0: /* SAU_CTRL */
1672 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1675 if (!attrs
.secure
) {
1678 cpu
->env
.sau
.ctrl
= value
& 3;
1680 case 0xdd4: /* SAU_TYPE */
1681 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1685 case 0xdd8: /* SAU_RNR */
1686 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1689 if (!attrs
.secure
) {
1692 if (value
>= cpu
->sau_sregion
) {
1693 qemu_log_mask(LOG_GUEST_ERROR
, "SAU region out of range %"
1694 PRIu32
"/%" PRIu32
"\n",
1695 value
, cpu
->sau_sregion
);
1697 cpu
->env
.sau
.rnr
= value
;
1700 case 0xddc: /* SAU_RBAR */
1702 int region
= cpu
->env
.sau
.rnr
;
1704 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1707 if (!attrs
.secure
) {
1710 if (region
>= cpu
->sau_sregion
) {
1713 cpu
->env
.sau
.rbar
[region
] = value
& ~0x1f;
1714 tlb_flush(CPU(cpu
));
1717 case 0xde0: /* SAU_RLAR */
1719 int region
= cpu
->env
.sau
.rnr
;
1721 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1724 if (!attrs
.secure
) {
1727 if (region
>= cpu
->sau_sregion
) {
1730 cpu
->env
.sau
.rlar
[region
] = value
& ~0x1c;
1731 tlb_flush(CPU(cpu
));
1734 case 0xde4: /* SFSR */
1735 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1738 if (!attrs
.secure
) {
1741 cpu
->env
.v7m
.sfsr
&= ~value
; /* W1C */
1743 case 0xde8: /* SFAR */
1744 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1747 if (!attrs
.secure
) {
1750 cpu
->env
.v7m
.sfsr
= value
;
1752 case 0xf00: /* Software Triggered Interrupt Register */
1754 int excnum
= (value
& 0x1ff) + NVIC_FIRST_IRQ
;
1756 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1760 if (excnum
< s
->num_irq
) {
1761 armv7m_nvic_set_pending(s
, excnum
, false);
1765 case 0xf34: /* FPCCR */
1766 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1767 /* Not all bits here are banked. */
1770 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1771 /* Don't allow setting of bits not present in v7M */
1772 value
&= (R_V7M_FPCCR_LSPACT_MASK
|
1773 R_V7M_FPCCR_USER_MASK
|
1774 R_V7M_FPCCR_THREAD_MASK
|
1775 R_V7M_FPCCR_HFRDY_MASK
|
1776 R_V7M_FPCCR_MMRDY_MASK
|
1777 R_V7M_FPCCR_BFRDY_MASK
|
1778 R_V7M_FPCCR_MONRDY_MASK
|
1779 R_V7M_FPCCR_LSPEN_MASK
|
1780 R_V7M_FPCCR_ASPEN_MASK
);
1782 value
&= ~R_V7M_FPCCR_RES0_MASK
;
1784 if (!attrs
.secure
) {
1785 /* Some non-banked bits are configurably writable by NS */
1786 fpccr_s
= cpu
->env
.v7m
.fpccr
[M_REG_S
];
1787 if (!(fpccr_s
& R_V7M_FPCCR_LSPENS_MASK
)) {
1788 uint32_t lspen
= FIELD_EX32(value
, V7M_FPCCR
, LSPEN
);
1789 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, LSPEN
, lspen
);
1791 if (!(fpccr_s
& R_V7M_FPCCR_CLRONRETS_MASK
)) {
1792 uint32_t cor
= FIELD_EX32(value
, V7M_FPCCR
, CLRONRET
);
1793 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, CLRONRET
, cor
);
1795 if ((s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1796 uint32_t hfrdy
= FIELD_EX32(value
, V7M_FPCCR
, HFRDY
);
1797 uint32_t bfrdy
= FIELD_EX32(value
, V7M_FPCCR
, BFRDY
);
1798 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, HFRDY
, hfrdy
);
1799 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, BFRDY
, bfrdy
);
1801 /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */
1803 uint32_t monrdy
= FIELD_EX32(value
, V7M_FPCCR
, MONRDY
);
1804 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, MONRDY
, monrdy
);
1808 * All other non-banked bits are RAZ/WI from NS; write
1809 * just the banked bits to fpccr[M_REG_NS].
1811 value
&= R_V7M_FPCCR_BANKED_MASK
;
1812 cpu
->env
.v7m
.fpccr
[M_REG_NS
] = value
;
1816 cpu
->env
.v7m
.fpccr
[M_REG_S
] = fpccr_s
;
1819 case 0xf38: /* FPCAR */
1820 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1822 cpu
->env
.v7m
.fpcar
[attrs
.secure
] = value
;
1825 case 0xf3c: /* FPDSCR */
1826 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1827 value
&= 0x07c00000;
1828 cpu
->env
.v7m
.fpdscr
[attrs
.secure
] = value
;
1831 case 0xf50: /* ICIALLU */
1832 case 0xf58: /* ICIMVAU */
1833 case 0xf5c: /* DCIMVAC */
1834 case 0xf60: /* DCISW */
1835 case 0xf64: /* DCCMVAU */
1836 case 0xf68: /* DCCMVAC */
1837 case 0xf6c: /* DCCSW */
1838 case 0xf70: /* DCCIMVAC */
1839 case 0xf74: /* DCCISW */
1840 case 0xf78: /* BPIALL */
1841 /* Cache and branch predictor maintenance: for QEMU these always NOP */
1845 qemu_log_mask(LOG_GUEST_ERROR
,
1846 "NVIC: Bad write offset 0x%x\n", offset
);
1850 static bool nvic_user_access_ok(NVICState
*s
, hwaddr offset
, MemTxAttrs attrs
)
1852 /* Return true if unprivileged access to this register is permitted. */
1854 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
1855 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
1856 * controls access even though the CPU is in Secure state (I_QDKX).
1858 return s
->cpu
->env
.v7m
.ccr
[attrs
.secure
] & R_V7M_CCR_USERSETMPEND_MASK
;
1860 /* All other user accesses cause a BusFault unconditionally */
1865 static int shpr_bank(NVICState
*s
, int exc
, MemTxAttrs attrs
)
1867 /* Behaviour for the SHPR register field for this exception:
1868 * return M_REG_NS to use the nonsecure vector (including for
1869 * non-banked exceptions), M_REG_S for the secure version of
1870 * a banked exception, and -1 if this field should RAZ/WI.
1873 case ARMV7M_EXCP_MEM
:
1874 case ARMV7M_EXCP_USAGE
:
1875 case ARMV7M_EXCP_SVC
:
1876 case ARMV7M_EXCP_PENDSV
:
1877 case ARMV7M_EXCP_SYSTICK
:
1878 /* Banked exceptions */
1879 return attrs
.secure
;
1880 case ARMV7M_EXCP_BUS
:
1881 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
1882 if (!attrs
.secure
&&
1883 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1887 case ARMV7M_EXCP_SECURE
:
1888 /* Not banked, RAZ/WI from nonsecure */
1889 if (!attrs
.secure
) {
1893 case ARMV7M_EXCP_DEBUG
:
1894 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
1901 /* Not reachable due to decode of SHPR register addresses */
1902 g_assert_not_reached();
1906 static MemTxResult
nvic_sysreg_read(void *opaque
, hwaddr addr
,
1907 uint64_t *data
, unsigned size
,
1910 NVICState
*s
= (NVICState
*)opaque
;
1911 uint32_t offset
= addr
;
1912 unsigned i
, startvec
, end
;
1915 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
1916 /* Generate BusFault for unprivileged accesses */
1921 /* reads of set and clear both return the status */
1922 case 0x100 ... 0x13f: /* NVIC Set enable */
1925 case 0x180 ... 0x1bf: /* NVIC Clear enable */
1927 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
; /* vector # */
1929 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1930 if (s
->vectors
[startvec
+ i
].enabled
&&
1931 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1936 case 0x200 ... 0x23f: /* NVIC Set pend */
1939 case 0x280 ... 0x2bf: /* NVIC Clear pend */
1941 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
1942 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1943 if (s
->vectors
[startvec
+ i
].pending
&&
1944 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1949 case 0x300 ... 0x33f: /* NVIC Active */
1952 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_V7
)) {
1956 startvec
= 8 * (offset
- 0x300) + NVIC_FIRST_IRQ
; /* vector # */
1958 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1959 if (s
->vectors
[startvec
+ i
].active
&&
1960 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1965 case 0x400 ... 0x5ef: /* NVIC Priority */
1967 startvec
= offset
- 0x400 + NVIC_FIRST_IRQ
; /* vector # */
1969 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
1970 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
1971 val
|= s
->vectors
[startvec
+ i
].prio
<< (8 * i
);
1975 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
1976 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1981 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
1983 for (i
= 0; i
< size
; i
++) {
1984 unsigned hdlidx
= (offset
- 0xd14) + i
;
1985 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
1990 val
= deposit32(val
, i
* 8, 8, get_prio(s
, hdlidx
, sbank
));
1993 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
1994 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1998 /* The BFSR bits [15:8] are shared between security states
1999 * and we store them in the NS copy
2001 val
= s
->cpu
->env
.v7m
.cfsr
[attrs
.secure
];
2002 val
|= s
->cpu
->env
.v7m
.cfsr
[M_REG_NS
] & R_V7M_CFSR_BFSR_MASK
;
2003 val
= extract32(val
, (offset
- 0xd28) * 8, size
* 8);
2005 case 0xfe0 ... 0xfff: /* ID. */
2009 val
= nvic_id
[(offset
- 0xfe0) >> 2];
2014 val
= nvic_readl(s
, offset
, attrs
);
2016 qemu_log_mask(LOG_GUEST_ERROR
,
2017 "NVIC: Bad read of size %d at offset 0x%x\n",
2023 trace_nvic_sysreg_read(addr
, val
, size
);
2028 static MemTxResult
nvic_sysreg_write(void *opaque
, hwaddr addr
,
2029 uint64_t value
, unsigned size
,
2032 NVICState
*s
= (NVICState
*)opaque
;
2033 uint32_t offset
= addr
;
2034 unsigned i
, startvec
, end
;
2035 unsigned setval
= 0;
2037 trace_nvic_sysreg_write(addr
, value
, size
);
2039 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
2040 /* Generate BusFault for unprivileged accesses */
2045 case 0x100 ... 0x13f: /* NVIC Set enable */
2049 case 0x180 ... 0x1bf: /* NVIC Clear enable */
2050 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
;
2052 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2053 if (value
& (1 << i
) &&
2054 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2055 s
->vectors
[startvec
+ i
].enabled
= setval
;
2060 case 0x200 ... 0x23f: /* NVIC Set pend */
2061 /* the special logic in armv7m_nvic_set_pending()
2062 * is not needed since IRQs are never escalated
2067 case 0x280 ... 0x2bf: /* NVIC Clear pend */
2068 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
2070 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2071 if (value
& (1 << i
) &&
2072 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2073 s
->vectors
[startvec
+ i
].pending
= setval
;
2078 case 0x300 ... 0x33f: /* NVIC Active */
2079 return MEMTX_OK
; /* R/O */
2080 case 0x400 ... 0x5ef: /* NVIC Priority */
2081 startvec
= (offset
- 0x400) + NVIC_FIRST_IRQ
; /* vector # */
2083 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
2084 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
2085 set_prio(s
, startvec
+ i
, false, (value
>> (i
* 8)) & 0xff);
2090 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
2091 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2095 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
2096 for (i
= 0; i
< size
; i
++) {
2097 unsigned hdlidx
= (offset
- 0xd14) + i
;
2098 int newprio
= extract32(value
, i
* 8, 8);
2099 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
2104 set_prio(s
, hdlidx
, sbank
, newprio
);
2108 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
2109 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2112 /* All bits are W1C, so construct 32 bit value with 0s in
2113 * the parts not written by the access size
2115 value
<<= ((offset
- 0xd28) * 8);
2117 s
->cpu
->env
.v7m
.cfsr
[attrs
.secure
] &= ~value
;
2119 /* The BFSR bits [15:8] are shared between security states
2120 * and we store them in the NS copy.
2122 s
->cpu
->env
.v7m
.cfsr
[M_REG_NS
] &= ~(value
& R_V7M_CFSR_BFSR_MASK
);
2127 nvic_writel(s
, offset
, value
, attrs
);
2130 qemu_log_mask(LOG_GUEST_ERROR
,
2131 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
2132 /* This is UNPREDICTABLE; treat as RAZ/WI */
2136 static const MemoryRegionOps nvic_sysreg_ops
= {
2137 .read_with_attrs
= nvic_sysreg_read
,
2138 .write_with_attrs
= nvic_sysreg_write
,
2139 .endianness
= DEVICE_NATIVE_ENDIAN
,
2142 static MemTxResult
nvic_sysreg_ns_write(void *opaque
, hwaddr addr
,
2143 uint64_t value
, unsigned size
,
2146 MemoryRegion
*mr
= opaque
;
2149 /* S accesses to the alias act like NS accesses to the real region */
2151 return memory_region_dispatch_write(mr
, addr
, value
, size
, attrs
);
2153 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
2161 static MemTxResult
nvic_sysreg_ns_read(void *opaque
, hwaddr addr
,
2162 uint64_t *data
, unsigned size
,
2165 MemoryRegion
*mr
= opaque
;
2168 /* S accesses to the alias act like NS accesses to the real region */
2170 return memory_region_dispatch_read(mr
, addr
, data
, size
, attrs
);
2172 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
2181 static const MemoryRegionOps nvic_sysreg_ns_ops
= {
2182 .read_with_attrs
= nvic_sysreg_ns_read
,
2183 .write_with_attrs
= nvic_sysreg_ns_write
,
2184 .endianness
= DEVICE_NATIVE_ENDIAN
,
2187 static MemTxResult
nvic_systick_write(void *opaque
, hwaddr addr
,
2188 uint64_t value
, unsigned size
,
2191 NVICState
*s
= opaque
;
2194 /* Direct the access to the correct systick */
2195 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->systick
[attrs
.secure
]), 0);
2196 return memory_region_dispatch_write(mr
, addr
, value
, size
, attrs
);
2199 static MemTxResult
nvic_systick_read(void *opaque
, hwaddr addr
,
2200 uint64_t *data
, unsigned size
,
2203 NVICState
*s
= opaque
;
2206 /* Direct the access to the correct systick */
2207 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->systick
[attrs
.secure
]), 0);
2208 return memory_region_dispatch_read(mr
, addr
, data
, size
, attrs
);
2211 static const MemoryRegionOps nvic_systick_ops
= {
2212 .read_with_attrs
= nvic_systick_read
,
2213 .write_with_attrs
= nvic_systick_write
,
2214 .endianness
= DEVICE_NATIVE_ENDIAN
,
2217 static int nvic_post_load(void *opaque
, int version_id
)
2219 NVICState
*s
= opaque
;
2223 /* Check for out of range priority settings */
2224 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
2226 if (s
->vectors
[ARMV7M_EXCP_RESET
].prio
!= resetprio
||
2227 s
->vectors
[ARMV7M_EXCP_NMI
].prio
!= -2 ||
2228 s
->vectors
[ARMV7M_EXCP_HARD
].prio
!= -1) {
2231 for (i
= ARMV7M_EXCP_MEM
; i
< s
->num_irq
; i
++) {
2232 if (s
->vectors
[i
].prio
& ~0xff) {
2237 nvic_recompute_state(s
);
2242 static const VMStateDescription vmstate_VecInfo
= {
2243 .name
= "armv7m_nvic_info",
2245 .minimum_version_id
= 1,
2246 .fields
= (VMStateField
[]) {
2247 VMSTATE_INT16(prio
, VecInfo
),
2248 VMSTATE_UINT8(enabled
, VecInfo
),
2249 VMSTATE_UINT8(pending
, VecInfo
),
2250 VMSTATE_UINT8(active
, VecInfo
),
2251 VMSTATE_UINT8(level
, VecInfo
),
2252 VMSTATE_END_OF_LIST()
2256 static bool nvic_security_needed(void *opaque
)
2258 NVICState
*s
= opaque
;
2260 return arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
2263 static int nvic_security_post_load(void *opaque
, int version_id
)
2265 NVICState
*s
= opaque
;
2268 /* Check for out of range priority settings */
2269 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -1
2270 && s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -3) {
2271 /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
2272 * if the CPU state has been migrated yet; a mismatch won't
2273 * cause the emulation to blow up, though.
2277 for (i
= ARMV7M_EXCP_MEM
; i
< ARRAY_SIZE(s
->sec_vectors
); i
++) {
2278 if (s
->sec_vectors
[i
].prio
& ~0xff) {
2285 static const VMStateDescription vmstate_nvic_security
= {
2286 .name
= "armv7m_nvic/m-security",
2288 .minimum_version_id
= 1,
2289 .needed
= nvic_security_needed
,
2290 .post_load
= &nvic_security_post_load
,
2291 .fields
= (VMStateField
[]) {
2292 VMSTATE_STRUCT_ARRAY(sec_vectors
, NVICState
, NVIC_INTERNAL_VECTORS
, 1,
2293 vmstate_VecInfo
, VecInfo
),
2294 VMSTATE_UINT32(prigroup
[M_REG_S
], NVICState
),
2295 VMSTATE_BOOL_ARRAY(itns
, NVICState
, NVIC_MAX_VECTORS
),
2296 VMSTATE_END_OF_LIST()
2300 static const VMStateDescription vmstate_nvic
= {
2301 .name
= "armv7m_nvic",
2303 .minimum_version_id
= 4,
2304 .post_load
= &nvic_post_load
,
2305 .fields
= (VMStateField
[]) {
2306 VMSTATE_STRUCT_ARRAY(vectors
, NVICState
, NVIC_MAX_VECTORS
, 1,
2307 vmstate_VecInfo
, VecInfo
),
2308 VMSTATE_UINT32(prigroup
[M_REG_NS
], NVICState
),
2309 VMSTATE_END_OF_LIST()
2311 .subsections
= (const VMStateDescription
*[]) {
2312 &vmstate_nvic_security
,
2317 static Property props_nvic
[] = {
2318 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
2319 DEFINE_PROP_UINT32("num-irq", NVICState
, num_irq
, 64),
2320 DEFINE_PROP_END_OF_LIST()
2323 static void armv7m_nvic_reset(DeviceState
*dev
)
2326 NVICState
*s
= NVIC(dev
);
2328 memset(s
->vectors
, 0, sizeof(s
->vectors
));
2329 memset(s
->sec_vectors
, 0, sizeof(s
->sec_vectors
));
2330 s
->prigroup
[M_REG_NS
] = 0;
2331 s
->prigroup
[M_REG_S
] = 0;
2333 s
->vectors
[ARMV7M_EXCP_NMI
].enabled
= 1;
2334 /* MEM, BUS, and USAGE are enabled through
2335 * the System Handler Control register
2337 s
->vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
2338 s
->vectors
[ARMV7M_EXCP_DEBUG
].enabled
= 1;
2339 s
->vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
2340 s
->vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
2342 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
2343 s
->vectors
[ARMV7M_EXCP_RESET
].prio
= resetprio
;
2344 s
->vectors
[ARMV7M_EXCP_NMI
].prio
= -2;
2345 s
->vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
2347 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2348 s
->sec_vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
2349 s
->sec_vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
2350 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
2351 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
2353 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
2354 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
2355 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
2356 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
2358 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
2361 /* Strictly speaking the reset handler should be enabled.
2362 * However, we don't simulate soft resets through the NVIC,
2363 * and the reset vector should never be pended.
2364 * So we leave it disabled to catch logic errors.
2367 s
->exception_prio
= NVIC_NOEXC_PRIO
;
2369 s
->vectpending_is_s_banked
= false;
2370 s
->vectpending_prio
= NVIC_NOEXC_PRIO
;
2372 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2373 memset(s
->itns
, 0, sizeof(s
->itns
));
2375 /* This state is constant and not guest accessible in a non-security
2376 * NVIC; we set the bits to true to avoid having to do a feature
2377 * bit check in the NVIC enable/pend/etc register accessors.
2381 for (i
= NVIC_FIRST_IRQ
; i
< ARRAY_SIZE(s
->itns
); i
++) {
2387 static void nvic_systick_trigger(void *opaque
, int n
, int level
)
2389 NVICState
*s
= opaque
;
2392 /* SysTick just asked us to pend its exception.
2393 * (This is different from an external interrupt line's
2395 * n == 0 : NonSecure systick
2396 * n == 1 : Secure systick
2398 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, n
);
2402 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
2404 NVICState
*s
= NVIC(dev
);
2408 /* The armv7m container object will have set our CPU pointer */
2409 if (!s
->cpu
|| !arm_feature(&s
->cpu
->env
, ARM_FEATURE_M
)) {
2410 error_setg(errp
, "The NVIC can only be used with a Cortex-M CPU");
2414 if (s
->num_irq
> NVIC_MAX_IRQ
) {
2415 error_setg(errp
, "num-irq %d exceeds NVIC maximum", s
->num_irq
);
2419 qdev_init_gpio_in(dev
, set_irq_level
, s
->num_irq
);
2421 /* include space for internal exception vectors */
2422 s
->num_irq
+= NVIC_FIRST_IRQ
;
2424 s
->num_prio_bits
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V7
) ? 8 : 2;
2426 object_property_set_bool(OBJECT(&s
->systick
[M_REG_NS
]), true,
2429 error_propagate(errp
, err
);
2432 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->systick
[M_REG_NS
]), 0,
2433 qdev_get_gpio_in_named(dev
, "systick-trigger",
2436 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2437 /* We couldn't init the secure systick device in instance_init
2438 * as we didn't know then if the CPU had the security extensions;
2439 * so we have to do it here.
2441 object_initialize(&s
->systick
[M_REG_S
], sizeof(s
->systick
[M_REG_S
]),
2443 qdev_set_parent_bus(DEVICE(&s
->systick
[M_REG_S
]), sysbus_get_default());
2445 object_property_set_bool(OBJECT(&s
->systick
[M_REG_S
]), true,
2448 error_propagate(errp
, err
);
2451 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->systick
[M_REG_S
]), 0,
2452 qdev_get_gpio_in_named(dev
, "systick-trigger",
2456 /* The NVIC and System Control Space (SCS) starts at 0xe000e000
2457 * and looks like this:
2459 * 0x010 - 0xff - systick
2460 * 0x100..0x7ec - NVIC
2461 * 0x7f0..0xcff - Reserved
2462 * 0xd00..0xd3c - SCS registers
2463 * 0xd40..0xeff - Reserved or Not implemented
2466 * Some registers within this space are banked between security states.
2467 * In v8M there is a second range 0xe002e000..0xe002efff which is the
2468 * NonSecure alias SCS; secure accesses to this behave like NS accesses
2469 * to the main SCS range, and non-secure accesses (including when
2470 * the security extension is not implemented) are RAZ/WI.
2471 * Note that both the main SCS range and the alias range are defined
2472 * to be exempt from memory attribution (R_BLJT) and so the memory
2473 * transaction attribute always matches the current CPU security
2474 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
2475 * wrappers we change attrs.secure to indicate the NS access; so
2476 * generally code determining which banked register to use should
2477 * use attrs.secure; code determining actual behaviour of the system
2478 * should use env->v7m.secure.
2480 regionlen
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? 0x21000 : 0x1000;
2481 memory_region_init(&s
->container
, OBJECT(s
), "nvic", regionlen
);
2482 /* The system register region goes at the bottom of the priority
2483 * stack as it covers the whole page.
2485 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
2486 "nvic_sysregs", 0x1000);
2487 memory_region_add_subregion(&s
->container
, 0, &s
->sysregmem
);
2489 memory_region_init_io(&s
->systickmem
, OBJECT(s
),
2490 &nvic_systick_ops
, s
,
2491 "nvic_systick", 0xe0);
2493 memory_region_add_subregion_overlap(&s
->container
, 0x10,
2496 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
2497 memory_region_init_io(&s
->sysreg_ns_mem
, OBJECT(s
),
2498 &nvic_sysreg_ns_ops
, &s
->sysregmem
,
2499 "nvic_sysregs_ns", 0x1000);
2500 memory_region_add_subregion(&s
->container
, 0x20000, &s
->sysreg_ns_mem
);
2501 memory_region_init_io(&s
->systick_ns_mem
, OBJECT(s
),
2502 &nvic_sysreg_ns_ops
, &s
->systickmem
,
2503 "nvic_systick_ns", 0xe0);
2504 memory_region_add_subregion_overlap(&s
->container
, 0x20010,
2505 &s
->systick_ns_mem
, 1);
2508 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->container
);
2511 static void armv7m_nvic_instance_init(Object
*obj
)
2513 /* We have a different default value for the num-irq property
2514 * than our superclass. This function runs after qdev init
2515 * has set the defaults from the Property array and before
2516 * any user-specified property setting, so just modify the
2517 * value in the GICState struct.
2519 DeviceState
*dev
= DEVICE(obj
);
2520 NVICState
*nvic
= NVIC(obj
);
2521 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
2523 sysbus_init_child_obj(obj
, "systick-reg-ns", &nvic
->systick
[M_REG_NS
],
2524 sizeof(nvic
->systick
[M_REG_NS
]), TYPE_SYSTICK
);
2525 /* We can't initialize the secure systick here, as we don't know
2526 * yet if we need it.
2529 sysbus_init_irq(sbd
, &nvic
->excpout
);
2530 qdev_init_gpio_out_named(dev
, &nvic
->sysresetreq
, "SYSRESETREQ", 1);
2531 qdev_init_gpio_in_named(dev
, nvic_systick_trigger
, "systick-trigger",
2533 qdev_init_gpio_in_named(dev
, nvic_nmi_trigger
, "NMI", 1);
2536 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
2538 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2540 dc
->vmsd
= &vmstate_nvic
;
2541 dc
->props
= props_nvic
;
2542 dc
->reset
= armv7m_nvic_reset
;
2543 dc
->realize
= armv7m_nvic_realize
;
2546 static const TypeInfo armv7m_nvic_info
= {
2548 .parent
= TYPE_SYS_BUS_DEVICE
,
2549 .instance_init
= armv7m_nvic_instance_init
,
2550 .instance_size
= sizeof(NVICState
),
2551 .class_init
= armv7m_nvic_class_init
,
2552 .class_size
= sizeof(SysBusDeviceClass
),
2555 static void armv7m_nvic_register_types(void)
2557 type_register_static(&armv7m_nvic_info
);
2560 type_init(armv7m_nvic_register_types
)