hw/rdma/vmw/pvrdma_main.c

   1 /*
   2  * QEMU paravirtual RDMA
   3  *
   4  * Copyright (C) 2018 Oracle
   5  * Copyright (C) 2018 Red Hat Inc
   6  *
   7  * Authors:
   8  *     Yuval Shaia <yuval.shaia@oracle.com>
   9  *     Marcel Apfelbaum <marcel@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  *
  14  */
  15
  16 #include "qemu/osdep.h"
  17 #include "qapi/error.h"
  18 #include "qemu/module.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/pci/pci_ids.h"
  21 #include "hw/pci/msi.h"
  22 #include "hw/pci/msix.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/qdev-properties-system.h"
  25 #include "cpu.h"
  26 #include "trace.h"
  27 #include "monitor/monitor.h"
  28 #include "hw/rdma/rdma.h"
  29
  30 #include "../rdma_rm.h"
  31 #include "../rdma_backend.h"
  32 #include "../rdma_utils.h"
  33
  34 #include <infiniband/verbs.h>
  35 #include "pvrdma.h"
  36 #include "standard-headers/rdma/vmw_pvrdma-abi.h"
  37 #include "sysemu/runstate.h"
  38 #include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
  39 #include "pvrdma_qp_ops.h"
  40
  41 static Property pvrdma_dev_properties[] = {
  42     DEFINE_PROP_STRING("netdev", PVRDMADev, backend_eth_device_name),
  43     DEFINE_PROP_STRING("ibdev", PVRDMADev, backend_device_name),
  44     DEFINE_PROP_UINT8("ibport", PVRDMADev, backend_port_num, 1),
  45     DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
  46                        MAX_MR_SIZE),
  47     DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
  48     DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
  49     DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
  50     DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
  51     DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
  52                       MAX_QP_RD_ATOM),
  53     DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
  54                       dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
  55     DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
  56     DEFINE_PROP_INT32("dev-caps-max-srq", PVRDMADev, dev_attr.max_srq, MAX_SRQ),
  57     DEFINE_PROP_CHR("mad-chardev", PVRDMADev, mad_chr),
  58     DEFINE_PROP_END_OF_LIST(),
  59 };
  60
  61 static void pvrdma_print_statistics(Monitor *mon, RdmaProvider *obj)
  62 {
  63     PVRDMADev *dev = PVRDMA_DEV(obj);
  64     PCIDevice *pdev = PCI_DEVICE(dev);
  65
  66     monitor_printf(mon, "%s, %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
  67                    PCI_FUNC(pdev->devfn));
  68     monitor_printf(mon, "\tcommands         : %" PRId64 "\n",
  69                    dev->stats.commands);
  70     monitor_printf(mon, "\tregs_reads       : %" PRId64 "\n",
  71                    dev->stats.regs_reads);
  72     monitor_printf(mon, "\tregs_writes      : %" PRId64 "\n",
  73                    dev->stats.regs_writes);
  74     monitor_printf(mon, "\tuar_writes       : %" PRId64 "\n",
  75                    dev->stats.uar_writes);
  76     monitor_printf(mon, "\tinterrupts       : %" PRId64 "\n",
  77                    dev->stats.interrupts);
  78     rdma_dump_device_counters(mon, &dev->rdma_dev_res);
  79 }
  80
  81 static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
  82                           void *ring_state)
  83 {
  84     pvrdma_ring_free(ring);
  85     rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
  86 }
  87
  88 static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
  89                          const char *name, PCIDevice *pci_dev,
  90                          dma_addr_t dir_addr, uint32_t num_pages)
  91 {
  92     uint64_t *dir, *tbl;
  93     int rc = 0;
  94
  95     dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
  96     if (!dir) {
  97         rdma_error_report("Failed to map to page directory (ring %s)", name);
  98         rc = -ENOMEM;
  99         goto out;
 100     }
 101     tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
 102     if (!tbl) {
 103         rdma_error_report("Failed to map to page table (ring %s)", name);
 104         rc = -ENOMEM;
 105         goto out_free_dir;
 106     }
 107
 108     *ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
 109     if (!*ring_state) {
 110         rdma_error_report("Failed to map to ring state (ring %s)", name);
 111         rc = -ENOMEM;
 112         goto out_free_tbl;
 113     }
 114     /* RX ring is the second */
 115     (*ring_state)++;
 116     rc = pvrdma_ring_init(ring, name, pci_dev,
 117                           (struct pvrdma_ring *)*ring_state,
 118                           (num_pages - 1) * TARGET_PAGE_SIZE /
 119                           sizeof(struct pvrdma_cqne),
 120                           sizeof(struct pvrdma_cqne),
 121                           (dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
 122     if (rc) {
 123         rc = -ENOMEM;
 124         goto out_free_ring_state;
 125     }
 126
 127     goto out_free_tbl;
 128
 129 out_free_ring_state:
 130     rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
 131
 132 out_free_tbl:
 133     rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
 134
 135 out_free_dir:
 136     rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
 137
 138 out:
 139     return rc;
 140 }
 141
 142 static void free_dsr(PVRDMADev *dev)
 143 {
 144     PCIDevice *pci_dev = PCI_DEVICE(dev);
 145
 146     if (!dev->dsr_info.dsr) {
 147         return;
 148     }
 149
 150     free_dev_ring(pci_dev, &dev->dsr_info.async,
 151                   dev->dsr_info.async_ring_state);
 152
 153     free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
 154
 155     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
 156                          sizeof(union pvrdma_cmd_req));
 157
 158     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
 159                          sizeof(union pvrdma_cmd_resp));
 160
 161     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
 162                          sizeof(struct pvrdma_device_shared_region));
 163
 164     dev->dsr_info.dsr = NULL;
 165 }
 166
 167 static int load_dsr(PVRDMADev *dev)
 168 {
 169     int rc = 0;
 170     PCIDevice *pci_dev = PCI_DEVICE(dev);
 171     DSRInfo *dsr_info;
 172     struct pvrdma_device_shared_region *dsr;
 173
 174     free_dsr(dev);
 175
 176     /* Map to DSR */
 177     dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
 178                               sizeof(struct pvrdma_device_shared_region));
 179     if (!dev->dsr_info.dsr) {
 180         rdma_error_report("Failed to map to DSR");
 181         rc = -ENOMEM;
 182         goto out;
 183     }
 184
 185     /* Shortcuts */
 186     dsr_info = &dev->dsr_info;
 187     dsr = dsr_info->dsr;
 188
 189     /* Map to command slot */
 190     dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
 191                                      sizeof(union pvrdma_cmd_req));
 192     if (!dsr_info->req) {
 193         rdma_error_report("Failed to map to command slot address");
 194         rc = -ENOMEM;
 195         goto out_free_dsr;
 196     }
 197
 198     /* Map to response slot */
 199     dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
 200                                      sizeof(union pvrdma_cmd_resp));
 201     if (!dsr_info->rsp) {
 202         rdma_error_report("Failed to map to response slot address");
 203         rc = -ENOMEM;
 204         goto out_free_req;
 205     }
 206
 207     /* Map to CQ notification ring */
 208     rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
 209                        pci_dev, dsr->cq_ring_pages.pdir_dma,
 210                        dsr->cq_ring_pages.num_pages);
 211     if (rc) {
 212         rc = -ENOMEM;
 213         goto out_free_rsp;
 214     }
 215
 216     /* Map to event notification ring */
 217     rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
 218                        "dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
 219                        dsr->async_ring_pages.num_pages);
 220     if (rc) {
 221         rc = -ENOMEM;
 222         goto out_free_rsp;
 223     }
 224
 225     goto out;
 226
 227 out_free_rsp:
 228     rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
 229
 230 out_free_req:
 231     rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
 232
 233 out_free_dsr:
 234     rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
 235                        sizeof(struct pvrdma_device_shared_region));
 236     dsr_info->dsr = NULL;
 237
 238 out:
 239     return rc;
 240 }
 241
 242 static void init_dsr_dev_caps(PVRDMADev *dev)
 243 {
 244     struct pvrdma_device_shared_region *dsr;
 245
 246     if (dev->dsr_info.dsr == NULL) {
 247         rdma_error_report("Can't initialized DSR");
 248         return;
 249     }
 250
 251     dsr = dev->dsr_info.dsr;
 252     dsr->caps.fw_ver = PVRDMA_FW_VERSION;
 253     dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
 254     dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
 255     dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
 256     dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
 257     dsr->caps.max_qp = dev->dev_attr.max_qp;
 258     dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
 259     dsr->caps.max_sge = dev->dev_attr.max_sge;
 260     dsr->caps.max_cq = dev->dev_attr.max_cq;
 261     dsr->caps.max_cqe = dev->dev_attr.max_cqe;
 262     dsr->caps.max_mr = dev->dev_attr.max_mr;
 263     dsr->caps.max_pd = dev->dev_attr.max_pd;
 264     dsr->caps.max_ah = dev->dev_attr.max_ah;
 265     dsr->caps.max_srq = dev->dev_attr.max_srq;
 266     dsr->caps.max_srq_wr = dev->dev_attr.max_srq_wr;
 267     dsr->caps.max_srq_sge = dev->dev_attr.max_srq_sge;
 268     dsr->caps.gid_tbl_len = MAX_GIDS;
 269     dsr->caps.sys_image_guid = 0;
 270     dsr->caps.node_guid = dev->node_guid;
 271     dsr->caps.phys_port_cnt = MAX_PORTS;
 272     dsr->caps.max_pkeys = MAX_PKEYS;
 273 }
 274
 275 static void uninit_msix(PCIDevice *pdev, int used_vectors)
 276 {
 277     PVRDMADev *dev = PVRDMA_DEV(pdev);
 278     int i;
 279
 280     for (i = 0; i < used_vectors; i++) {
 281         msix_vector_unuse(pdev, i);
 282     }
 283
 284     msix_uninit(pdev, &dev->msix, &dev->msix);
 285 }
 286
 287 static int init_msix(PCIDevice *pdev)
 288 {
 289     PVRDMADev *dev = PVRDMA_DEV(pdev);
 290     int i;
 291     int rc;
 292
 293     rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
 294                    RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
 295                    RDMA_MSIX_PBA, 0, NULL);
 296
 297     if (rc < 0) {
 298         rdma_error_report("Failed to initialize MSI-X");
 299         return rc;
 300     }
 301
 302     for (i = 0; i < RDMA_MAX_INTRS; i++) {
 303         rc = msix_vector_use(PCI_DEVICE(dev), i);
 304         if (rc < 0) {
 305             rdma_error_report("Fail mark MSI-X vector %d", i);
 306             uninit_msix(pdev, i);
 307             return rc;
 308         }
 309     }
 310
 311     return 0;
 312 }
 313
 314 static void pvrdma_fini(PCIDevice *pdev)
 315 {
 316     PVRDMADev *dev = PVRDMA_DEV(pdev);
 317
 318     notifier_remove(&dev->shutdown_notifier);
 319
 320     pvrdma_qp_ops_fini();
 321
 322     rdma_backend_stop(&dev->backend_dev);
 323
 324     rdma_rm_fini(&dev->rdma_dev_res, &dev->backend_dev,
 325                  dev->backend_eth_device_name);
 326
 327     rdma_backend_fini(&dev->backend_dev);
 328
 329     free_dsr(dev);
 330
 331     if (msix_enabled(pdev)) {
 332         uninit_msix(pdev, RDMA_MAX_INTRS);
 333     }
 334
 335     rdma_info_report("Device %s %x.%x is down", pdev->name,
 336                      PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 337 }
 338
 339 static void pvrdma_stop(PVRDMADev *dev)
 340 {
 341     rdma_backend_stop(&dev->backend_dev);
 342 }
 343
 344 static void pvrdma_start(PVRDMADev *dev)
 345 {
 346     rdma_backend_start(&dev->backend_dev);
 347 }
 348
 349 static void activate_device(PVRDMADev *dev)
 350 {
 351     pvrdma_start(dev);
 352     set_reg_val(dev, PVRDMA_REG_ERR, 0);
 353 }
 354
 355 static int unquiesce_device(PVRDMADev *dev)
 356 {
 357     return 0;
 358 }
 359
 360 static void reset_device(PVRDMADev *dev)
 361 {
 362     pvrdma_stop(dev);
 363 }
 364
 365 static uint64_t pvrdma_regs_read(void *opaque, hwaddr addr, unsigned size)
 366 {
 367     PVRDMADev *dev = opaque;
 368     uint32_t val;
 369
 370     dev->stats.regs_reads++;
 371
 372     if (get_reg_val(dev, addr, &val)) {
 373         rdma_error_report("Failed to read REG value from address 0x%x",
 374                           (uint32_t)addr);
 375         return -EINVAL;
 376     }
 377
 378     trace_pvrdma_regs_read(addr, val);
 379
 380     return val;
 381 }
 382
 383 static void pvrdma_regs_write(void *opaque, hwaddr addr, uint64_t val,
 384                               unsigned size)
 385 {
 386     PVRDMADev *dev = opaque;
 387
 388     dev->stats.regs_writes++;
 389
 390     if (set_reg_val(dev, addr, val)) {
 391         rdma_error_report("Failed to set REG value, addr=0x%"PRIx64 ", val=0x%"PRIx64,
 392                           addr, val);
 393         return;
 394     }
 395
 396     switch (addr) {
 397     case PVRDMA_REG_DSRLOW:
 398         trace_pvrdma_regs_write(addr, val, "DSRLOW", "");
 399         dev->dsr_info.dma = val;
 400         break;
 401     case PVRDMA_REG_DSRHIGH:
 402         trace_pvrdma_regs_write(addr, val, "DSRHIGH", "");
 403         dev->dsr_info.dma |= val << 32;
 404         load_dsr(dev);
 405         init_dsr_dev_caps(dev);
 406         break;
 407     case PVRDMA_REG_CTL:
 408         switch (val) {
 409         case PVRDMA_DEVICE_CTL_ACTIVATE:
 410             trace_pvrdma_regs_write(addr, val, "CTL", "ACTIVATE");
 411             activate_device(dev);
 412             break;
 413         case PVRDMA_DEVICE_CTL_UNQUIESCE:
 414             trace_pvrdma_regs_write(addr, val, "CTL", "UNQUIESCE");
 415             unquiesce_device(dev);
 416             break;
 417         case PVRDMA_DEVICE_CTL_RESET:
 418             trace_pvrdma_regs_write(addr, val, "CTL", "URESET");
 419             reset_device(dev);
 420             break;
 421         }
 422         break;
 423     case PVRDMA_REG_IMR:
 424         trace_pvrdma_regs_write(addr, val, "INTR_MASK", "");
 425         dev->interrupt_mask = val;
 426         break;
 427     case PVRDMA_REG_REQUEST:
 428         if (val == 0) {
 429             trace_pvrdma_regs_write(addr, val, "REQUEST", "");
 430             pvrdma_exec_cmd(dev);
 431         }
 432         break;
 433     default:
 434         break;
 435     }
 436 }
 437
 438 static const MemoryRegionOps regs_ops = {
 439     .read = pvrdma_regs_read,
 440     .write = pvrdma_regs_write,
 441     .endianness = DEVICE_LITTLE_ENDIAN,
 442     .impl = {
 443         .min_access_size = sizeof(uint32_t),
 444         .max_access_size = sizeof(uint32_t),
 445     },
 446 };
 447
 448 static uint64_t pvrdma_uar_read(void *opaque, hwaddr addr, unsigned size)
 449 {
 450     return 0xffffffff;
 451 }
 452
 453 static void pvrdma_uar_write(void *opaque, hwaddr addr, uint64_t val,
 454                              unsigned size)
 455 {
 456     PVRDMADev *dev = opaque;
 457
 458     dev->stats.uar_writes++;
 459
 460     switch (addr & 0xFFF) { /* Mask with 0xFFF as each UC gets page */
 461     case PVRDMA_UAR_QP_OFFSET:
 462         if (val & PVRDMA_UAR_QP_SEND) {
 463             trace_pvrdma_uar_write(addr, val, "QP", "SEND",
 464                                    val & PVRDMA_UAR_HANDLE_MASK, 0);
 465             pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
 466         }
 467         if (val & PVRDMA_UAR_QP_RECV) {
 468             trace_pvrdma_uar_write(addr, val, "QP", "RECV",
 469                                    val & PVRDMA_UAR_HANDLE_MASK, 0);
 470             pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
 471         }
 472         break;
 473     case PVRDMA_UAR_CQ_OFFSET:
 474         if (val & PVRDMA_UAR_CQ_ARM) {
 475             trace_pvrdma_uar_write(addr, val, "CQ", "ARM",
 476                                    val & PVRDMA_UAR_HANDLE_MASK,
 477                                    !!(val & PVRDMA_UAR_CQ_ARM_SOL));
 478             rdma_rm_req_notify_cq(&dev->rdma_dev_res,
 479                                   val & PVRDMA_UAR_HANDLE_MASK,
 480                                   !!(val & PVRDMA_UAR_CQ_ARM_SOL));
 481         }
 482         if (val & PVRDMA_UAR_CQ_ARM_SOL) {
 483             trace_pvrdma_uar_write(addr, val, "CQ", "ARMSOL - not supported", 0,
 484                                    0);
 485         }
 486         if (val & PVRDMA_UAR_CQ_POLL) {
 487             trace_pvrdma_uar_write(addr, val, "CQ", "POLL",
 488                                    val & PVRDMA_UAR_HANDLE_MASK, 0);
 489             pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
 490         }
 491         break;
 492     case PVRDMA_UAR_SRQ_OFFSET:
 493         if (val & PVRDMA_UAR_SRQ_RECV) {
 494             trace_pvrdma_uar_write(addr, val, "QP", "SRQ",
 495                                    val & PVRDMA_UAR_HANDLE_MASK, 0);
 496             pvrdma_srq_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
 497         }
 498         break;
 499     default:
 500         rdma_error_report("Unsupported command, addr=0x%"PRIx64", val=0x%"PRIx64,
 501                           addr, val);
 502         break;
 503     }
 504 }
 505
 506 static const MemoryRegionOps uar_ops = {
 507     .read = pvrdma_uar_read,
 508     .write = pvrdma_uar_write,
 509     .endianness = DEVICE_LITTLE_ENDIAN,
 510     .impl = {
 511         .min_access_size = sizeof(uint32_t),
 512         .max_access_size = sizeof(uint32_t),
 513     },
 514 };
 515
 516 static void init_pci_config(PCIDevice *pdev)
 517 {
 518     pdev->config[PCI_INTERRUPT_PIN] = 1;
 519 }
 520
 521 static void init_bars(PCIDevice *pdev)
 522 {
 523     PVRDMADev *dev = PVRDMA_DEV(pdev);
 524
 525     /* BAR 0 - MSI-X */
 526     memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
 527                        RDMA_BAR0_MSIX_SIZE);
 528     pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 529                      &dev->msix);
 530
 531     /* BAR 1 - Registers */
 532     memset(&dev->regs_data, 0, sizeof(dev->regs_data));
 533     memory_region_init_io(&dev->regs, OBJECT(dev), &regs_ops, dev,
 534                           "pvrdma-regs", sizeof(dev->regs_data));
 535     pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 536                      &dev->regs);
 537
 538     /* BAR 2 - UAR */
 539     memset(&dev->uar_data, 0, sizeof(dev->uar_data));
 540     memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
 541                           sizeof(dev->uar_data));
 542     pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 543                      &dev->uar);
 544 }
 545
 546 static void init_regs(PCIDevice *pdev)
 547 {
 548     PVRDMADev *dev = PVRDMA_DEV(pdev);
 549
 550     set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
 551     set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
 552 }
 553
 554 static void init_dev_caps(PVRDMADev *dev)
 555 {
 556     size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
 557                           (TARGET_PAGE_SIZE / sizeof(uint64_t));
 558     size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
 559                        sizeof(struct pvrdma_rq_wqe_hdr));
 560
 561     dev->dev_attr.max_qp_wr = pg_tbl_bytes /
 562                               (wr_sz + sizeof(struct pvrdma_sge) *
 563                               dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
 564                               /* First page is ring state  ^^^^ */
 565
 566     dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
 567                             TARGET_PAGE_SIZE; /* First page is ring state */
 568
 569     dev->dev_attr.max_srq_wr = pg_tbl_bytes /
 570                                 ((sizeof(struct pvrdma_rq_wqe_hdr) +
 571                                 sizeof(struct pvrdma_sge)) *
 572                                 dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
 573 }
 574
 575 static int pvrdma_check_ram_shared(Object *obj, void *opaque)
 576 {
 577     bool *shared = opaque;
 578
 579     if (object_dynamic_cast(obj, "memory-backend-ram")) {
 580         *shared = object_property_get_bool(obj, "share", NULL);
 581     }
 582
 583     return 0;
 584 }
 585
 586 static void pvrdma_shutdown_notifier(Notifier *n, void *opaque)
 587 {
 588     PVRDMADev *dev = container_of(n, PVRDMADev, shutdown_notifier);
 589     PCIDevice *pci_dev = PCI_DEVICE(dev);
 590
 591     pvrdma_fini(pci_dev);
 592 }
 593
 594 static void pvrdma_realize(PCIDevice *pdev, Error **errp)
 595 {
 596     int rc = 0;
 597     PVRDMADev *dev = PVRDMA_DEV(pdev);
 598     Object *memdev_root;
 599     bool ram_shared = false;
 600     PCIDevice *func0;
 601
 602     rdma_info_report("Initializing device %s %x.%x", pdev->name,
 603                      PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 604
 605     if (TARGET_PAGE_SIZE != qemu_real_host_page_size) {
 606         error_setg(errp, "Target page size must be the same as host page size");
 607         return;
 608     }
 609
 610     func0 = pci_get_function_0(pdev);
 611     /* Break if not vmxnet3 device in slot 0 */
 612     if (strcmp(object_get_typename(OBJECT(func0)), TYPE_VMXNET3)) {
 613         error_setg(errp, "Device on %x.0 must be %s", PCI_SLOT(pdev->devfn),
 614                    TYPE_VMXNET3);
 615         return;
 616     }
 617     dev->func0 = VMXNET3(func0);
 618
 619     addrconf_addr_eui48((unsigned char *)&dev->node_guid,
 620                         (const char *)&dev->func0->conf.macaddr.a);
 621
 622     memdev_root = object_resolve_path("/objects", NULL);
 623     if (memdev_root) {
 624         object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
 625     }
 626     if (!ram_shared) {
 627         error_setg(errp, "Only shared memory backed ram is supported");
 628         return;
 629     }
 630
 631     dev->dsr_info.dsr = NULL;
 632
 633     init_pci_config(pdev);
 634
 635     init_bars(pdev);
 636
 637     init_regs(pdev);
 638
 639     rc = init_msix(pdev);
 640     if (rc) {
 641         goto out;
 642     }
 643
 644     rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
 645                            dev->backend_device_name, dev->backend_port_num,
 646                            &dev->dev_attr, &dev->mad_chr);
 647     if (rc) {
 648         goto out;
 649     }
 650
 651     init_dev_caps(dev);
 652
 653     rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr);
 654     if (rc) {
 655         goto out;
 656     }
 657
 658     rc = pvrdma_qp_ops_init();
 659     if (rc) {
 660         goto out;
 661     }
 662
 663     memset(&dev->stats, 0, sizeof(dev->stats));
 664
 665     dev->shutdown_notifier.notify = pvrdma_shutdown_notifier;
 666     qemu_register_shutdown_notifier(&dev->shutdown_notifier);
 667
 668 #ifdef LEGACY_RDMA_REG_MR
 669     rdma_info_report("Using legacy reg_mr");
 670 #else
 671     rdma_info_report("Using iova reg_mr");
 672 #endif
 673
 674 out:
 675     if (rc) {
 676         pvrdma_fini(pdev);
 677         error_append_hint(errp, "Device failed to load\n");
 678     }
 679 }
 680
 681 static void pvrdma_class_init(ObjectClass *klass, void *data)
 682 {
 683     DeviceClass *dc = DEVICE_CLASS(klass);
 684     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 685     RdmaProviderClass *ir = RDMA_PROVIDER_CLASS(klass);
 686
 687     k->realize = pvrdma_realize;
 688     k->vendor_id = PCI_VENDOR_ID_VMWARE;
 689     k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
 690     k->revision = 0x00;
 691     k->class_id = PCI_CLASS_NETWORK_OTHER;
 692
 693     dc->desc = "RDMA Device";
 694     device_class_set_props(dc, pvrdma_dev_properties);
 695     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 696
 697     ir->print_statistics = pvrdma_print_statistics;
 698 }
 699
 700 static const TypeInfo pvrdma_info = {
 701     .name = PVRDMA_HW_NAME,
 702     .parent = TYPE_PCI_DEVICE,
 703     .instance_size = sizeof(PVRDMADev),
 704     .class_init = pvrdma_class_init,
 705     .interfaces = (InterfaceInfo[]) {
 706         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 707         { INTERFACE_RDMA_PROVIDER },
 708         { }
 709     }
 710 };
 711
 712 static void register_types(void)
 713 {
 714     type_register_static(&pvrdma_info);
 715 }
 716
 717 type_init(register_types)