hw/ppc/ppc440_bamboo.c

   1 /*
   2  * QEMU PowerPC 440 Bamboo board emulation
   3  *
   4  * Copyright 2007 IBM Corporation.
   5  * Authors:
   6  *      Jerone Young <jyoung5@us.ibm.com>
   7  *      Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
   8  *      Hollis Blanchard <hollisb@us.ibm.com>
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/error-report.h"
  17 #include "qemu-common.h"
  18 #include "qemu/datadir.h"
  19 #include "qemu/error-report.h"
  20 #include "net/net.h"
  21 #include "hw/pci/pci.h"
  22 #include "hw/boards.h"
  23 #include "sysemu/kvm.h"
  24 #include "kvm_ppc.h"
  25 #include "sysemu/device_tree.h"
  26 #include "hw/loader.h"
  27 #include "elf.h"
  28 #include "exec/address-spaces.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/ppc/ppc.h"
  31 #include "ppc405.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/qtest.h"
  34 #include "sysemu/reset.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/intc/ppc-uic.h"
  37 #include "hw/qdev-properties.h"
  38 #include "qapi/error.h"
  39
  40 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
  41
  42 /* from u-boot */
  43 #define KERNEL_ADDR  0x1000000
  44 #define FDT_ADDR     0x1800000
  45 #define RAMDISK_ADDR 0x1900000
  46
  47 #define PPC440EP_PCI_CONFIG     0xeec00000
  48 #define PPC440EP_PCI_INTACK     0xeed00000
  49 #define PPC440EP_PCI_SPECIAL    0xeed00000
  50 #define PPC440EP_PCI_REGS       0xef400000
  51 #define PPC440EP_PCI_IO         0xe8000000
  52 #define PPC440EP_PCI_IOLEN      0x00010000
  53
  54 #define PPC440EP_SDRAM_NR_BANKS 4
  55
  56 static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
  57     256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
  58 };
  59
  60 static hwaddr entry;
  61
  62 static int bamboo_load_device_tree(hwaddr addr,
  63                                      uint32_t ramsize,
  64                                      hwaddr initrd_base,
  65                                      hwaddr initrd_size,
  66                                      const char *kernel_cmdline)
  67 {
  68     int ret = -1;
  69     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
  70     char *filename;
  71     int fdt_size;
  72     void *fdt;
  73     uint32_t tb_freq = 400000000;
  74     uint32_t clock_freq = 400000000;
  75
  76     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
  77     if (!filename) {
  78         return -1;
  79     }
  80     fdt = load_device_tree(filename, &fdt_size);
  81     g_free(filename);
  82     if (fdt == NULL) {
  83         return -1;
  84     }
  85
  86     /* Manipulate device tree in memory. */
  87
  88     ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
  89                            sizeof(mem_reg_property));
  90     if (ret < 0)
  91         fprintf(stderr, "couldn't set /memory/reg\n");
  92
  93     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
  94                                 initrd_base);
  95     if (ret < 0)
  96         fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
  97
  98     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
  99                                 (initrd_base + initrd_size));
 100     if (ret < 0)
 101         fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 102
 103     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 104                                   kernel_cmdline);
 105     if (ret < 0)
 106         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 107
 108     /* Copy data from the host device tree into the guest. Since the guest can
 109      * directly access the timebase without host involvement, we must expose
 110      * the correct frequencies. */
 111     if (kvm_enabled()) {
 112         tb_freq = kvmppc_get_tbfreq();
 113         clock_freq = kvmppc_get_clockfreq();
 114     }
 115
 116     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 117                           clock_freq);
 118     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 119                           tb_freq);
 120
 121     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 122     g_free(fdt);
 123     return 0;
 124 }
 125
 126 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 127 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 128                                      target_ulong va,
 129                                      hwaddr pa)
 130 {
 131     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 132
 133     tlb->attr = 0;
 134     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 135     tlb->size = 1U << 31; /* up to 0x80000000  */
 136     tlb->EPN = va & TARGET_PAGE_MASK;
 137     tlb->RPN = pa & TARGET_PAGE_MASK;
 138     tlb->PID = 0;
 139
 140     tlb = &env->tlb.tlbe[1];
 141     tlb->attr = 0;
 142     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 143     tlb->size = 1U << 31; /* up to 0xffffffff  */
 144     tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
 145     tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
 146     tlb->PID = 0;
 147 }
 148
 149 static void main_cpu_reset(void *opaque)
 150 {
 151     PowerPCCPU *cpu = opaque;
 152     CPUPPCState *env = &cpu->env;
 153
 154     cpu_reset(CPU(cpu));
 155     env->gpr[1] = (16 * MiB) - 8;
 156     env->gpr[3] = FDT_ADDR;
 157     env->nip = entry;
 158
 159     /* Create a mapping for the kernel.  */
 160     mmubooke_create_initial_mapping(env, 0, 0);
 161 }
 162
 163 static void bamboo_init(MachineState *machine)
 164 {
 165     const char *kernel_filename = machine->kernel_filename;
 166     const char *kernel_cmdline = machine->kernel_cmdline;
 167     const char *initrd_filename = machine->initrd_filename;
 168     unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
 169     MemoryRegion *address_space_mem = get_system_memory();
 170     MemoryRegion *isa = g_new(MemoryRegion, 1);
 171     MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
 172     hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
 173     hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
 174     PCIBus *pcibus;
 175     PowerPCCPU *cpu;
 176     CPUPPCState *env;
 177     target_long initrd_size = 0;
 178     DeviceState *dev;
 179     DeviceState *uicdev;
 180     SysBusDevice *uicsbd;
 181     int success;
 182     int i;
 183
 184     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 185     env = &cpu->env;
 186
 187     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 188         error_report("MMU model %i not supported by this machine",
 189                      env->mmu_model);
 190         exit(1);
 191     }
 192
 193     qemu_register_reset(main_cpu_reset, cpu);
 194     ppc_booke_timers_init(cpu, 400000000, 0);
 195     ppc_dcr_init(env, NULL, NULL);
 196
 197     /* interrupt controller */
 198     uicdev = qdev_new(TYPE_PPC_UIC);
 199     uicsbd = SYS_BUS_DEVICE(uicdev);
 200
 201     object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
 202                              &error_fatal);
 203     sysbus_realize_and_unref(uicsbd, &error_fatal);
 204
 205     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
 206                        ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
 207     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
 208                        ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
 209
 210     /* SDRAM controller */
 211     memset(ram_bases, 0, sizeof(ram_bases));
 212     memset(ram_sizes, 0, sizeof(ram_sizes));
 213     ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
 214                        ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
 215     /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
 216     ppc4xx_sdram_init(env,
 217                       qdev_get_gpio_in(uicdev, 14),
 218                       PPC440EP_SDRAM_NR_BANKS, ram_memories,
 219                       ram_bases, ram_sizes, 1);
 220
 221     /* PCI */
 222     dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
 223                                 PPC440EP_PCI_CONFIG,
 224                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]),
 225                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]),
 226                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]),
 227                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]),
 228                                 NULL);
 229     pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 230     if (!pcibus) {
 231         error_report("couldn't create PCI controller");
 232         exit(1);
 233     }
 234
 235     memory_region_init_alias(isa, NULL, "isa_mmio",
 236                              get_system_io(), 0, PPC440EP_PCI_IOLEN);
 237     memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
 238
 239     if (serial_hd(0) != NULL) {
 240         serial_mm_init(address_space_mem, 0xef600300, 0,
 241                        qdev_get_gpio_in(uicdev, 0),
 242                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
 243                        DEVICE_BIG_ENDIAN);
 244     }
 245     if (serial_hd(1) != NULL) {
 246         serial_mm_init(address_space_mem, 0xef600400, 0,
 247                        qdev_get_gpio_in(uicdev, 1),
 248                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
 249                        DEVICE_BIG_ENDIAN);
 250     }
 251
 252     if (pcibus) {
 253         /* Register network interfaces. */
 254         for (i = 0; i < nb_nics; i++) {
 255             /* There are no PCI NICs on the Bamboo board, but there are
 256              * PCI slots, so we can pick whatever default model we want. */
 257             pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
 258         }
 259     }
 260
 261     /* Load kernel. */
 262     if (kernel_filename) {
 263         hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
 264         success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
 265                               NULL, NULL);
 266         if (success < 0) {
 267             uint64_t elf_entry;
 268             success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
 269                                NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 270             entry = elf_entry;
 271         }
 272         /* XXX try again as binary */
 273         if (success < 0) {
 274             error_report("could not load kernel '%s'", kernel_filename);
 275             exit(1);
 276         }
 277     }
 278
 279     /* Load initrd. */
 280     if (initrd_filename) {
 281         initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
 282                                           machine->ram_size - RAMDISK_ADDR);
 283
 284         if (initrd_size < 0) {
 285             error_report("could not load ram disk '%s' at %x",
 286                          initrd_filename, RAMDISK_ADDR);
 287             exit(1);
 288         }
 289     }
 290
 291     /* If we're loading a kernel directly, we must load the device tree too. */
 292     if (kernel_filename) {
 293         if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
 294                                     initrd_size, kernel_cmdline) < 0) {
 295             error_report("couldn't load device tree");
 296             exit(1);
 297         }
 298     }
 299 }
 300
 301 static void bamboo_machine_init(MachineClass *mc)
 302 {
 303     mc->desc = "bamboo";
 304     mc->init = bamboo_init;
 305     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
 306     mc->default_ram_id = "ppc4xx.sdram";
 307 }
 308
 309 DEFINE_MACHINE("bamboo", bamboo_machine_init)