2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/i2c/ppc4xx_i2c.h"
33 #include "hw/char/serial.h"
34 #include "qemu/timer.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/sysemu.h"
38 #include "exec/address-spaces.h"
39 #include "hw/intc/ppc-uic.h"
40 #include "hw/qdev-properties.h"
41 #include "qapi/error.h"
46 //#define DEBUG_SERIAL
49 //#define DEBUG_CLOCKS
50 //#define DEBUG_CLOCKS_LL
52 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
55 CPUState *cs = env_cpu(env);
59 /* We put the bd structure at the top of memory */
60 if (bd->bi_memsize >= 0x01000000UL)
61 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
63 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
64 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
65 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
66 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
67 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
68 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
69 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
70 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
71 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
72 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
73 for (i = 0; i < 6; i++) {
74 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
76 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
77 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
78 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
79 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
80 for (i = 0; i < 4; i++) {
81 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
83 for (i = 0; i < 32; i++) {
84 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
86 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
87 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
88 for (i = 0; i < 6; i++) {
89 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
92 if (flags & 0x00000001) {
93 for (i = 0; i < 6; i++)
94 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
96 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
98 for (i = 0; i < 2; i++) {
99 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
106 /*****************************************************************************/
107 /* Shared peripherals */
109 /*****************************************************************************/
110 /* Peripheral local bus arbitrer */
120 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
121 struct ppc4xx_plb_t {
127 static uint32_t dcr_read_plb (void *opaque, int dcrn)
144 /* Avoid gcc warning */
152 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
159 /* We don't care about the actual parameters written as
160 * we don't manage any priorities on the bus
162 plb->acr = val & 0xF8000000;
174 static void ppc4xx_plb_reset (void *opaque)
179 plb->acr = 0x00000000;
180 plb->bear = 0x00000000;
181 plb->besr = 0x00000000;
184 void ppc4xx_plb_init(CPUPPCState *env)
188 plb = g_malloc0(sizeof(ppc4xx_plb_t));
189 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
190 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
191 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
192 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
193 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
194 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
195 qemu_register_reset(ppc4xx_plb_reset, plb);
198 /*****************************************************************************/
199 /* PLB to OPB bridge */
206 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
207 struct ppc4xx_pob_t {
213 static uint32_t dcr_read_pob (void *opaque, int dcrn)
230 /* Avoid gcc warning */
238 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
258 static void ppc4xx_pob_reset (void *opaque)
264 pob->bear = 0x00000000;
265 pob->besr0 = 0x0000000;
266 pob->besr1 = 0x0000000;
269 static void ppc4xx_pob_init(CPUPPCState *env)
273 pob = g_malloc0(sizeof(ppc4xx_pob_t));
274 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
275 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
276 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
277 qemu_register_reset(ppc4xx_pob_reset, pob);
280 /*****************************************************************************/
282 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
283 struct ppc4xx_opba_t {
289 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
295 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
313 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
319 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
325 opba->cr = value & 0xF8;
328 opba->pr = value & 0xFF;
334 static const MemoryRegionOps opba_ops = {
336 .write = opba_writeb,
337 .impl.min_access_size = 1,
338 .impl.max_access_size = 1,
339 .valid.min_access_size = 1,
340 .valid.max_access_size = 4,
341 .endianness = DEVICE_BIG_ENDIAN,
344 static void ppc4xx_opba_reset (void *opaque)
349 opba->cr = 0x00; /* No dynamic priorities - park disabled */
353 static void ppc4xx_opba_init(hwaddr base)
357 opba = g_malloc0(sizeof(ppc4xx_opba_t));
359 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
361 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
362 memory_region_add_subregion(get_system_memory(), base, &opba->io);
363 qemu_register_reset(ppc4xx_opba_reset, opba);
366 /*****************************************************************************/
367 /* Code decompression controller */
370 /*****************************************************************************/
371 /* Peripheral controller */
372 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
373 struct ppc4xx_ebc_t {
384 EBC0_CFGADDR = 0x012,
385 EBC0_CFGDATA = 0x013,
388 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
400 case 0x00: /* B0CR */
403 case 0x01: /* B1CR */
406 case 0x02: /* B2CR */
409 case 0x03: /* B3CR */
412 case 0x04: /* B4CR */
415 case 0x05: /* B5CR */
418 case 0x06: /* B6CR */
421 case 0x07: /* B7CR */
424 case 0x10: /* B0AP */
427 case 0x11: /* B1AP */
430 case 0x12: /* B2AP */
433 case 0x13: /* B3AP */
436 case 0x14: /* B4AP */
439 case 0x15: /* B5AP */
442 case 0x16: /* B6AP */
445 case 0x17: /* B7AP */
448 case 0x20: /* BEAR */
451 case 0x21: /* BESR0 */
454 case 0x22: /* BESR1 */
473 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
484 case 0x00: /* B0CR */
486 case 0x01: /* B1CR */
488 case 0x02: /* B2CR */
490 case 0x03: /* B3CR */
492 case 0x04: /* B4CR */
494 case 0x05: /* B5CR */
496 case 0x06: /* B6CR */
498 case 0x07: /* B7CR */
500 case 0x10: /* B0AP */
502 case 0x11: /* B1AP */
504 case 0x12: /* B2AP */
506 case 0x13: /* B3AP */
508 case 0x14: /* B4AP */
510 case 0x15: /* B5AP */
512 case 0x16: /* B6AP */
514 case 0x17: /* B7AP */
516 case 0x20: /* BEAR */
518 case 0x21: /* BESR0 */
520 case 0x22: /* BESR1 */
533 static void ebc_reset (void *opaque)
539 ebc->addr = 0x00000000;
540 ebc->bap[0] = 0x7F8FFE80;
541 ebc->bcr[0] = 0xFFE28000;
542 for (i = 0; i < 8; i++) {
543 ebc->bap[i] = 0x00000000;
544 ebc->bcr[i] = 0x00000000;
546 ebc->besr0 = 0x00000000;
547 ebc->besr1 = 0x00000000;
548 ebc->cfg = 0x80400000;
551 void ppc405_ebc_init(CPUPPCState *env)
555 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
556 qemu_register_reset(&ebc_reset, ebc);
557 ppc_dcr_register(env, EBC0_CFGADDR,
558 ebc, &dcr_read_ebc, &dcr_write_ebc);
559 ppc_dcr_register(env, EBC0_CFGDATA,
560 ebc, &dcr_read_ebc, &dcr_write_ebc);
563 /*****************************************************************************/
592 typedef struct ppc405_dma_t ppc405_dma_t;
593 struct ppc405_dma_t {
606 static uint32_t dcr_read_dma (void *opaque, int dcrn)
611 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
615 static void ppc405_dma_reset (void *opaque)
621 for (i = 0; i < 4; i++) {
622 dma->cr[i] = 0x00000000;
623 dma->ct[i] = 0x00000000;
624 dma->da[i] = 0x00000000;
625 dma->sa[i] = 0x00000000;
626 dma->sg[i] = 0x00000000;
628 dma->sr = 0x00000000;
629 dma->sgc = 0x00000000;
630 dma->slp = 0x7C000000;
631 dma->pol = 0x00000000;
634 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
638 dma = g_malloc0(sizeof(ppc405_dma_t));
639 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
640 qemu_register_reset(&ppc405_dma_reset, dma);
641 ppc_dcr_register(env, DMA0_CR0,
642 dma, &dcr_read_dma, &dcr_write_dma);
643 ppc_dcr_register(env, DMA0_CT0,
644 dma, &dcr_read_dma, &dcr_write_dma);
645 ppc_dcr_register(env, DMA0_DA0,
646 dma, &dcr_read_dma, &dcr_write_dma);
647 ppc_dcr_register(env, DMA0_SA0,
648 dma, &dcr_read_dma, &dcr_write_dma);
649 ppc_dcr_register(env, DMA0_SG0,
650 dma, &dcr_read_dma, &dcr_write_dma);
651 ppc_dcr_register(env, DMA0_CR1,
652 dma, &dcr_read_dma, &dcr_write_dma);
653 ppc_dcr_register(env, DMA0_CT1,
654 dma, &dcr_read_dma, &dcr_write_dma);
655 ppc_dcr_register(env, DMA0_DA1,
656 dma, &dcr_read_dma, &dcr_write_dma);
657 ppc_dcr_register(env, DMA0_SA1,
658 dma, &dcr_read_dma, &dcr_write_dma);
659 ppc_dcr_register(env, DMA0_SG1,
660 dma, &dcr_read_dma, &dcr_write_dma);
661 ppc_dcr_register(env, DMA0_CR2,
662 dma, &dcr_read_dma, &dcr_write_dma);
663 ppc_dcr_register(env, DMA0_CT2,
664 dma, &dcr_read_dma, &dcr_write_dma);
665 ppc_dcr_register(env, DMA0_DA2,
666 dma, &dcr_read_dma, &dcr_write_dma);
667 ppc_dcr_register(env, DMA0_SA2,
668 dma, &dcr_read_dma, &dcr_write_dma);
669 ppc_dcr_register(env, DMA0_SG2,
670 dma, &dcr_read_dma, &dcr_write_dma);
671 ppc_dcr_register(env, DMA0_CR3,
672 dma, &dcr_read_dma, &dcr_write_dma);
673 ppc_dcr_register(env, DMA0_CT3,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_DA3,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_SA3,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_SG3,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_SR,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SGC,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_SLP,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_POL,
688 dma, &dcr_read_dma, &dcr_write_dma);
691 /*****************************************************************************/
693 typedef struct ppc405_gpio_t ppc405_gpio_t;
694 struct ppc405_gpio_t {
709 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
712 printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size);
718 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
722 printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n",
723 __func__, addr, size, value);
727 static const MemoryRegionOps ppc405_gpio_ops = {
728 .read = ppc405_gpio_read,
729 .write = ppc405_gpio_write,
730 .endianness = DEVICE_NATIVE_ENDIAN,
733 static void ppc405_gpio_reset (void *opaque)
737 static void ppc405_gpio_init(hwaddr base)
741 gpio = g_malloc0(sizeof(ppc405_gpio_t));
743 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
745 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
746 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
747 qemu_register_reset(&ppc405_gpio_reset, gpio);
750 /*****************************************************************************/
754 OCM0_ISACNTL = 0x019,
756 OCM0_DSACNTL = 0x01B,
759 typedef struct ppc405_ocm_t ppc405_ocm_t;
760 struct ppc405_ocm_t {
762 MemoryRegion isarc_ram;
763 MemoryRegion dsarc_ram;
770 static void ocm_update_mappings (ppc405_ocm_t *ocm,
771 uint32_t isarc, uint32_t isacntl,
772 uint32_t dsarc, uint32_t dsacntl)
775 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
776 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
777 " (%08" PRIx32 " %08" PRIx32 ")\n",
778 isarc, isacntl, dsarc, dsacntl,
779 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
781 if (ocm->isarc != isarc ||
782 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
783 if (ocm->isacntl & 0x80000000) {
784 /* Unmap previously assigned memory region */
785 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
786 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
788 if (isacntl & 0x80000000) {
789 /* Map new instruction memory region */
791 printf("OCM map ISA %08" PRIx32 "\n", isarc);
793 memory_region_add_subregion(get_system_memory(), isarc,
797 if (ocm->dsarc != dsarc ||
798 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
799 if (ocm->dsacntl & 0x80000000) {
800 /* Beware not to unmap the region we just mapped */
801 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
802 /* Unmap previously assigned memory region */
804 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
806 memory_region_del_subregion(get_system_memory(),
810 if (dsacntl & 0x80000000) {
811 /* Beware not to remap the region we just mapped */
812 if (!(isacntl & 0x80000000) || dsarc != isarc) {
813 /* Map new data memory region */
815 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
817 memory_region_add_subregion(get_system_memory(), dsarc,
824 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
851 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
854 uint32_t isarc, dsarc, isacntl, dsacntl;
859 isacntl = ocm->isacntl;
860 dsacntl = ocm->dsacntl;
863 isarc = val & 0xFC000000;
866 isacntl = val & 0xC0000000;
869 isarc = val & 0xFC000000;
872 isacntl = val & 0xC0000000;
875 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
878 ocm->isacntl = isacntl;
879 ocm->dsacntl = dsacntl;
882 static void ocm_reset (void *opaque)
885 uint32_t isarc, dsarc, isacntl, dsacntl;
889 isacntl = 0x00000000;
891 dsacntl = 0x00000000;
892 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
895 ocm->isacntl = isacntl;
896 ocm->dsacntl = dsacntl;
899 static void ppc405_ocm_init(CPUPPCState *env)
903 ocm = g_malloc0(sizeof(ppc405_ocm_t));
904 /* XXX: Size is 4096 or 0x04000000 */
905 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
907 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
908 &ocm->isarc_ram, 0, 4 * KiB);
909 qemu_register_reset(&ocm_reset, ocm);
910 ppc_dcr_register(env, OCM0_ISARC,
911 ocm, &dcr_read_ocm, &dcr_write_ocm);
912 ppc_dcr_register(env, OCM0_ISACNTL,
913 ocm, &dcr_read_ocm, &dcr_write_ocm);
914 ppc_dcr_register(env, OCM0_DSARC,
915 ocm, &dcr_read_ocm, &dcr_write_ocm);
916 ppc_dcr_register(env, OCM0_DSACNTL,
917 ocm, &dcr_read_ocm, &dcr_write_ocm);
920 /*****************************************************************************/
921 /* General purpose timers */
922 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
923 struct ppc4xx_gpt_t {
938 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
944 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
949 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
955 for (i = 0; i < 5; i++) {
956 if (gpt->oe & mask) {
957 /* Output is enabled */
958 if (ppc4xx_gpt_compare(gpt, i)) {
959 /* Comparison is OK */
960 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
962 /* Comparison is KO */
963 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
970 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
976 for (i = 0; i < 5; i++) {
977 if (gpt->is & gpt->im & mask)
978 qemu_irq_raise(gpt->irqs[i]);
980 qemu_irq_lower(gpt->irqs[i]);
985 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
990 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
997 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1002 /* Time base counter */
1003 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1004 gpt->tb_freq, NANOSECONDS_PER_SECOND);
1015 /* Interrupt mask */
1020 /* Interrupt status */
1024 /* Interrupt enable */
1029 idx = (addr - 0x80) >> 2;
1030 ret = gpt->comp[idx];
1034 idx = (addr - 0xC0) >> 2;
1035 ret = gpt->mask[idx];
1045 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
1052 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1058 /* Time base counter */
1059 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
1060 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1061 ppc4xx_gpt_compute_timer(gpt);
1065 gpt->oe = value & 0xF8000000;
1066 ppc4xx_gpt_set_outputs(gpt);
1070 gpt->ol = value & 0xF8000000;
1071 ppc4xx_gpt_set_outputs(gpt);
1074 /* Interrupt mask */
1075 gpt->im = value & 0x0000F800;
1078 /* Interrupt status set */
1079 gpt->is |= value & 0x0000F800;
1080 ppc4xx_gpt_set_irqs(gpt);
1083 /* Interrupt status clear */
1084 gpt->is &= ~(value & 0x0000F800);
1085 ppc4xx_gpt_set_irqs(gpt);
1088 /* Interrupt enable */
1089 gpt->ie = value & 0x0000F800;
1090 ppc4xx_gpt_set_irqs(gpt);
1094 idx = (addr - 0x80) >> 2;
1095 gpt->comp[idx] = value & 0xF8000000;
1096 ppc4xx_gpt_compute_timer(gpt);
1100 idx = (addr - 0xC0) >> 2;
1101 gpt->mask[idx] = value & 0xF8000000;
1102 ppc4xx_gpt_compute_timer(gpt);
1107 static const MemoryRegionOps gpt_ops = {
1108 .read = ppc4xx_gpt_read,
1109 .write = ppc4xx_gpt_write,
1110 .valid.min_access_size = 4,
1111 .valid.max_access_size = 4,
1112 .endianness = DEVICE_NATIVE_ENDIAN,
1115 static void ppc4xx_gpt_cb (void *opaque)
1120 ppc4xx_gpt_set_irqs(gpt);
1121 ppc4xx_gpt_set_outputs(gpt);
1122 ppc4xx_gpt_compute_timer(gpt);
1125 static void ppc4xx_gpt_reset (void *opaque)
1131 timer_del(gpt->timer);
1132 gpt->oe = 0x00000000;
1133 gpt->ol = 0x00000000;
1134 gpt->im = 0x00000000;
1135 gpt->is = 0x00000000;
1136 gpt->ie = 0x00000000;
1137 for (i = 0; i < 5; i++) {
1138 gpt->comp[i] = 0x00000000;
1139 gpt->mask[i] = 0x00000000;
1143 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1148 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1149 for (i = 0; i < 5; i++) {
1150 gpt->irqs[i] = irqs[i];
1152 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1154 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1156 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1157 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1158 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1161 /*****************************************************************************/
1165 PPC405EP_CPC0_PLLMR0 = 0x0F0,
1166 PPC405EP_CPC0_BOOT = 0x0F1,
1167 PPC405EP_CPC0_EPCTL = 0x0F3,
1168 PPC405EP_CPC0_PLLMR1 = 0x0F4,
1169 PPC405EP_CPC0_UCR = 0x0F5,
1170 PPC405EP_CPC0_SRR = 0x0F6,
1171 PPC405EP_CPC0_JTAGID = 0x0F7,
1172 PPC405EP_CPC0_PCI = 0x0F9,
1174 PPC405EP_CPC0_ER = xxx,
1175 PPC405EP_CPC0_FR = xxx,
1176 PPC405EP_CPC0_SR = xxx,
1181 PPC405EP_CPU_CLK = 0,
1182 PPC405EP_PLB_CLK = 1,
1183 PPC405EP_OPB_CLK = 2,
1184 PPC405EP_EBC_CLK = 3,
1185 PPC405EP_MAL_CLK = 4,
1186 PPC405EP_PCI_CLK = 5,
1187 PPC405EP_UART0_CLK = 6,
1188 PPC405EP_UART1_CLK = 7,
1189 PPC405EP_CLK_NB = 8,
1192 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
1193 struct ppc405ep_cpc_t {
1195 clk_setup_t clk_setup[PPC405EP_CLK_NB];
1203 /* Clock and power management */
1209 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
1211 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
1212 uint32_t UART0_clk, UART1_clk;
1213 uint64_t VCO_out, PLL_out;
1217 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
1218 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
1219 #ifdef DEBUG_CLOCKS_LL
1220 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
1222 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
1223 #ifdef DEBUG_CLOCKS_LL
1224 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
1226 VCO_out = (uint64_t)cpc->sysclk * M * D;
1227 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
1228 /* Error - unlock the PLL */
1229 printf("VCO out of range %" PRIu64 "\n", VCO_out);
1231 cpc->pllmr[1] &= ~0x80000000;
1235 PLL_out = VCO_out / D;
1236 /* Pretend the PLL is locked */
1237 cpc->boot |= 0x00000001;
1242 PLL_out = cpc->sysclk;
1243 if (cpc->pllmr[1] & 0x40000000) {
1244 /* Pretend the PLL is not locked */
1245 cpc->boot &= ~0x00000001;
1248 /* Now, compute all other clocks */
1249 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
1250 #ifdef DEBUG_CLOCKS_LL
1251 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
1253 CPU_clk = PLL_out / D;
1254 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
1255 #ifdef DEBUG_CLOCKS_LL
1256 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
1258 PLB_clk = CPU_clk / D;
1259 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
1260 #ifdef DEBUG_CLOCKS_LL
1261 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
1263 OPB_clk = PLB_clk / D;
1264 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
1265 #ifdef DEBUG_CLOCKS_LL
1266 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
1268 EBC_clk = PLB_clk / D;
1269 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
1270 #ifdef DEBUG_CLOCKS_LL
1271 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
1273 MAL_clk = PLB_clk / D;
1274 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
1275 #ifdef DEBUG_CLOCKS_LL
1276 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
1278 PCI_clk = PLB_clk / D;
1279 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
1280 #ifdef DEBUG_CLOCKS_LL
1281 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
1283 UART0_clk = PLL_out / D;
1284 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
1285 #ifdef DEBUG_CLOCKS_LL
1286 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
1288 UART1_clk = PLL_out / D;
1290 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
1291 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
1292 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
1293 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
1294 " UART1 %" PRIu32 "\n",
1295 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
1296 UART0_clk, UART1_clk);
1298 /* Setup CPU clocks */
1299 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
1300 /* Setup PLB clock */
1301 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
1302 /* Setup OPB clock */
1303 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
1304 /* Setup external clock */
1305 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
1306 /* Setup MAL clock */
1307 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
1308 /* Setup PCI clock */
1309 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
1310 /* Setup UART0 clock */
1311 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
1312 /* Setup UART1 clock */
1313 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
1316 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
1318 ppc405ep_cpc_t *cpc;
1323 case PPC405EP_CPC0_BOOT:
1326 case PPC405EP_CPC0_EPCTL:
1329 case PPC405EP_CPC0_PLLMR0:
1330 ret = cpc->pllmr[0];
1332 case PPC405EP_CPC0_PLLMR1:
1333 ret = cpc->pllmr[1];
1335 case PPC405EP_CPC0_UCR:
1338 case PPC405EP_CPC0_SRR:
1341 case PPC405EP_CPC0_JTAGID:
1344 case PPC405EP_CPC0_PCI:
1348 /* Avoid gcc warning */
1356 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
1358 ppc405ep_cpc_t *cpc;
1362 case PPC405EP_CPC0_BOOT:
1363 /* Read-only register */
1365 case PPC405EP_CPC0_EPCTL:
1366 /* Don't care for now */
1367 cpc->epctl = val & 0xC00000F3;
1369 case PPC405EP_CPC0_PLLMR0:
1370 cpc->pllmr[0] = val & 0x00633333;
1371 ppc405ep_compute_clocks(cpc);
1373 case PPC405EP_CPC0_PLLMR1:
1374 cpc->pllmr[1] = val & 0xC0F73FFF;
1375 ppc405ep_compute_clocks(cpc);
1377 case PPC405EP_CPC0_UCR:
1378 /* UART control - don't care for now */
1379 cpc->ucr = val & 0x003F7F7F;
1381 case PPC405EP_CPC0_SRR:
1384 case PPC405EP_CPC0_JTAGID:
1387 case PPC405EP_CPC0_PCI:
1393 static void ppc405ep_cpc_reset (void *opaque)
1395 ppc405ep_cpc_t *cpc = opaque;
1397 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
1398 cpc->epctl = 0x00000000;
1399 cpc->pllmr[0] = 0x00011010;
1400 cpc->pllmr[1] = 0x40000000;
1401 cpc->ucr = 0x00000000;
1402 cpc->srr = 0x00040000;
1403 cpc->pci = 0x00000000;
1404 cpc->er = 0x00000000;
1405 cpc->fr = 0x00000000;
1406 cpc->sr = 0x00000000;
1407 ppc405ep_compute_clocks(cpc);
1410 /* XXX: sysclk should be between 25 and 100 MHz */
1411 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
1414 ppc405ep_cpc_t *cpc;
1416 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
1417 memcpy(cpc->clk_setup, clk_setup,
1418 PPC405EP_CLK_NB * sizeof(clk_setup_t));
1419 cpc->jtagid = 0x20267049;
1420 cpc->sysclk = sysclk;
1421 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
1422 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
1423 &dcr_read_epcpc, &dcr_write_epcpc);
1424 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
1425 &dcr_read_epcpc, &dcr_write_epcpc);
1426 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
1427 &dcr_read_epcpc, &dcr_write_epcpc);
1428 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
1429 &dcr_read_epcpc, &dcr_write_epcpc);
1430 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
1431 &dcr_read_epcpc, &dcr_write_epcpc);
1432 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
1433 &dcr_read_epcpc, &dcr_write_epcpc);
1434 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
1435 &dcr_read_epcpc, &dcr_write_epcpc);
1436 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
1437 &dcr_read_epcpc, &dcr_write_epcpc);
1439 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
1440 &dcr_read_epcpc, &dcr_write_epcpc);
1441 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
1442 &dcr_read_epcpc, &dcr_write_epcpc);
1443 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
1444 &dcr_read_epcpc, &dcr_write_epcpc);
1448 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
1449 MemoryRegion ram_memories[2],
1450 hwaddr ram_bases[2],
1451 hwaddr ram_sizes[2],
1452 uint32_t sysclk, DeviceState **uicdevp,
1455 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
1456 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
1459 DeviceState *uicdev;
1460 SysBusDevice *uicsbd;
1462 memset(clk_setup, 0, sizeof(clk_setup));
1464 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
1465 &clk_setup[PPC405EP_CPU_CLK],
1466 &tlb_clk_setup, sysclk);
1468 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
1469 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
1470 /* Internal devices init */
1471 /* Memory mapped devices registers */
1473 ppc4xx_plb_init(env);
1474 /* PLB to OPB bridge */
1475 ppc4xx_pob_init(env);
1477 ppc4xx_opba_init(0xef600600);
1478 /* Initialize timers */
1479 ppc_booke_timers_init(cpu, sysclk, 0);
1480 /* Universal interrupt controller */
1481 uicdev = qdev_new(TYPE_PPC_UIC);
1482 uicsbd = SYS_BUS_DEVICE(uicdev);
1484 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
1486 sysbus_realize_and_unref(uicsbd, &error_fatal);
1488 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
1489 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
1490 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
1491 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
1495 /* SDRAM controller */
1496 /* XXX 405EP has no ECC interrupt */
1497 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
1498 ram_bases, ram_sizes, do_init);
1499 /* External bus controller */
1500 ppc405_ebc_init(env);
1501 /* DMA controller */
1502 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
1503 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
1504 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
1505 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
1506 ppc405_dma_init(env, dma_irqs);
1507 /* IIC controller */
1508 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
1509 qdev_get_gpio_in(uicdev, 2));
1511 ppc405_gpio_init(0xef600700);
1513 if (serial_hd(0) != NULL) {
1514 serial_mm_init(address_space_mem, 0xef600300, 0,
1515 qdev_get_gpio_in(uicdev, 0),
1516 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
1519 if (serial_hd(1) != NULL) {
1520 serial_mm_init(address_space_mem, 0xef600400, 0,
1521 qdev_get_gpio_in(uicdev, 1),
1522 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
1526 ppc405_ocm_init(env);
1528 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
1529 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
1530 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
1531 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
1532 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
1533 ppc4xx_gpt_init(0xef600000, gpt_irqs);
1535 /* Uses UIC IRQs 3, 16, 18 */
1537 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
1538 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
1539 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
1540 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
1541 ppc4xx_mal_init(env, 4, 2, mal_irqs);
1543 /* Uses UIC IRQs 9, 15, 17 */
1545 ppc405ep_cpc_init(env, clk_setup, sysclk);