hw/arm/npcm7xx_boards.c

   1 /*
   2  * Machine definitions for boards featuring an NPCM7xx SoC.
   3  *
   4  * Copyright 2020 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16
  17 #include "qemu/osdep.h"
  18
  19 #include "exec/address-spaces.h"
  20 #include "hw/arm/npcm7xx.h"
  21 #include "hw/core/cpu.h"
  22 #include "hw/i2c/smbus_eeprom.h"
  23 #include "hw/loader.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "qemu/datadir.h"
  28 #include "qemu/units.h"
  29 #include "sysemu/sysemu.h"
  30
  31 #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
  32 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
  33
  34 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
  35
  36 static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
  37 {
  38     const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
  39     g_autofree char *filename = NULL;
  40     int ret;
  41
  42     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  43     if (!filename) {
  44         error_report("Could not find ROM image '%s'", bios_name);
  45         if (!machine->kernel_filename) {
  46             /* We can't boot without a bootrom or a kernel image. */
  47             exit(1);
  48         }
  49         return;
  50     }
  51     ret = load_image_mr(filename, &soc->irom);
  52     if (ret < 0) {
  53         error_report("Failed to load ROM image '%s'", filename);
  54         exit(1);
  55     }
  56 }
  57
  58 static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
  59                                   const char *flash_type, DriveInfo *dinfo)
  60 {
  61     DeviceState *flash;
  62     qemu_irq flash_cs;
  63
  64     flash = qdev_new(flash_type);
  65     if (dinfo) {
  66         qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
  67     }
  68     qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
  69
  70     flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
  71     qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
  72 }
  73
  74 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
  75 {
  76     memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
  77
  78     object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
  79                              &error_abort);
  80 }
  81
  82 static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
  83                                         uint32_t hw_straps)
  84 {
  85     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
  86     MachineClass *mc = MACHINE_CLASS(nmc);
  87     Object *obj;
  88
  89     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
  90         error_report("This board can only be used with %s",
  91                      mc->default_cpu_type);
  92         exit(1);
  93     }
  94
  95     obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
  96                                 &error_abort, NULL);
  97     object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
  98
  99     return NPCM7XX(obj);
 100 }
 101
 102 static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
 103 {
 104     g_assert(num < ARRAY_SIZE(soc->smbus));
 105     return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
 106 }
 107
 108 static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
 109                               uint32_t rsize)
 110 {
 111     I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
 112     I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
 113     DeviceState *dev = DEVICE(i2c_dev);
 114
 115     qdev_prop_set_uint32(dev, "rom-size", rsize);
 116     i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
 117 }
 118
 119 static void npcm750_evb_i2c_init(NPCM7xxState *soc)
 120 {
 121     /* lm75 temperature sensor on SVB, tmp105 is compatible */
 122     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48);
 123     /* lm75 temperature sensor on EB, tmp105 is compatible */
 124     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48);
 125     /* tmp100 temperature sensor on EB, tmp105 is compatible */
 126     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48);
 127     /* tmp100 temperature sensor on SVB, tmp105 is compatible */
 128     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
 129 }
 130
 131 static void quanta_gsj_i2c_init(NPCM7xxState *soc)
 132 {
 133     /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
 134     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c);
 135     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c);
 136     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
 137     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
 138
 139     at24c_eeprom_init(soc, 9, 0x55, 8192);
 140     at24c_eeprom_init(soc, 10, 0x55, 8192);
 141
 142     /* TODO: Add additional i2c devices. */
 143 }
 144
 145 static void npcm750_evb_init(MachineState *machine)
 146 {
 147     NPCM7xxState *soc;
 148
 149     soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
 150     npcm7xx_connect_dram(soc, machine->ram);
 151     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 152
 153     npcm7xx_load_bootrom(machine, soc);
 154     npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
 155     npcm750_evb_i2c_init(soc);
 156     npcm7xx_load_kernel(machine, soc);
 157 }
 158
 159 static void quanta_gsj_init(MachineState *machine)
 160 {
 161     NPCM7xxState *soc;
 162
 163     soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
 164     npcm7xx_connect_dram(soc, machine->ram);
 165     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 166
 167     npcm7xx_load_bootrom(machine, soc);
 168     npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
 169                           drive_get(IF_MTD, 0, 0));
 170     quanta_gsj_i2c_init(soc);
 171     npcm7xx_load_kernel(machine, soc);
 172 }
 173
 174 static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
 175 {
 176     NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
 177     MachineClass *mc = MACHINE_CLASS(nmc);
 178
 179     nmc->soc_type = type;
 180     mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
 181 }
 182
 183 static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
 184 {
 185     MachineClass *mc = MACHINE_CLASS(oc);
 186
 187     mc->no_floppy = 1;
 188     mc->no_cdrom = 1;
 189     mc->no_parallel = 1;
 190     mc->default_ram_id = "ram";
 191     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 192 }
 193
 194 /*
 195  * Schematics:
 196  * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
 197  */
 198 static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
 199 {
 200     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
 201     MachineClass *mc = MACHINE_CLASS(oc);
 202
 203     npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
 204
 205     mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)";
 206     mc->init = npcm750_evb_init;
 207     mc->default_ram_size = 512 * MiB;
 208 };
 209
 210 static void gsj_machine_class_init(ObjectClass *oc, void *data)
 211 {
 212     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
 213     MachineClass *mc = MACHINE_CLASS(oc);
 214
 215     npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
 216
 217     mc->desc = "Quanta GSJ (Cortex A9)";
 218     mc->init = quanta_gsj_init;
 219     mc->default_ram_size = 512 * MiB;
 220 };
 221
 222 static const TypeInfo npcm7xx_machine_types[] = {
 223     {
 224         .name           = TYPE_NPCM7XX_MACHINE,
 225         .parent         = TYPE_MACHINE,
 226         .instance_size  = sizeof(NPCM7xxMachine),
 227         .class_size     = sizeof(NPCM7xxMachineClass),
 228         .class_init     = npcm7xx_machine_class_init,
 229         .abstract       = true,
 230     }, {
 231         .name           = MACHINE_TYPE_NAME("npcm750-evb"),
 232         .parent         = TYPE_NPCM7XX_MACHINE,
 233         .class_init     = npcm750_evb_machine_class_init,
 234     }, {
 235         .name           = MACHINE_TYPE_NAME("quanta-gsj"),
 236         .parent         = TYPE_NPCM7XX_MACHINE,
 237         .class_init     = gsj_machine_class_init,
 238     },
 239 };
 240
 241 DEFINE_TYPES(npcm7xx_machine_types)