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pc: acpi: drop manual hole punching for GPE0 resources
[qemu/ar7.git] / target-mips / translate_init.c
blob9e8433a919139699f7a4a24ee0ebcf41b4d15a9f
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t MSAIR;
88 int32_t SEGBITS;
89 int32_t PABITS;
90 int32_t CP0_SRSConf0_rw_bitmask;
91 int32_t CP0_SRSConf0;
92 int32_t CP0_SRSConf1_rw_bitmask;
93 int32_t CP0_SRSConf1;
94 int32_t CP0_SRSConf2_rw_bitmask;
95 int32_t CP0_SRSConf2;
96 int32_t CP0_SRSConf3_rw_bitmask;
97 int32_t CP0_SRSConf3;
98 int32_t CP0_SRSConf4_rw_bitmask;
99 int32_t CP0_SRSConf4;
100 int32_t CP0_PageGrain_rw_bitmask;
101 int32_t CP0_PageGrain;
102 int insn_flags;
103 enum mips_mmu_types mmu_type;
104 };
105
106 /*****************************************************************************/
107 /* MIPS CPU definitions */
108 static const mips_def_t mips_defs[] =
109 {
110 {
111 .name = "4Kc",
112 .CP0_PRid = 0x00018000,
113 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
114 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
115 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
116 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
117 (0 << CP0C1_CA),
118 .CP0_Config2 = MIPS_CONFIG2,
119 .CP0_Config3 = MIPS_CONFIG3,
120 .CP0_LLAddr_rw_bitmask = 0,
121 .CP0_LLAddr_shift = 4,
122 .SYNCI_Step = 32,
123 .CCRes = 2,
124 .CP0_Status_rw_bitmask = 0x1278FF17,
125 .SEGBITS = 32,
126 .PABITS = 32,
127 .insn_flags = CPU_MIPS32,
128 .mmu_type = MMU_TYPE_R4000,
129 },
130 {
131 .name = "4Km",
132 .CP0_PRid = 0x00018300,
133 /* Config1 implemented, fixed mapping MMU,
134 no virtual icache, uncached coherency. */
135 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
136 .CP0_Config1 = MIPS_CONFIG1 |
137 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
138 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
139 (1 << CP0C1_CA),
140 .CP0_Config2 = MIPS_CONFIG2,
141 .CP0_Config3 = MIPS_CONFIG3,
142 .CP0_LLAddr_rw_bitmask = 0,
143 .CP0_LLAddr_shift = 4,
144 .SYNCI_Step = 32,
145 .CCRes = 2,
146 .CP0_Status_rw_bitmask = 0x1258FF17,
147 .SEGBITS = 32,
148 .PABITS = 32,
149 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
150 .mmu_type = MMU_TYPE_FMT,
151 },
152 {
153 .name = "4KEcR1",
154 .CP0_PRid = 0x00018400,
155 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
156 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
157 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
158 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
159 (0 << CP0C1_CA),
160 .CP0_Config2 = MIPS_CONFIG2,
161 .CP0_Config3 = MIPS_CONFIG3,
162 .CP0_LLAddr_rw_bitmask = 0,
163 .CP0_LLAddr_shift = 4,
164 .SYNCI_Step = 32,
165 .CCRes = 2,
166 .CP0_Status_rw_bitmask = 0x1278FF17,
167 .SEGBITS = 32,
168 .PABITS = 32,
169 .insn_flags = CPU_MIPS32,
170 .mmu_type = MMU_TYPE_R4000,
171 },
172 {
173 .name = "4KEmR1",
174 .CP0_PRid = 0x00018500,
175 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
176 .CP0_Config1 = MIPS_CONFIG1 |
177 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
178 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
179 (1 << CP0C1_CA),
180 .CP0_Config2 = MIPS_CONFIG2,
181 .CP0_Config3 = MIPS_CONFIG3,
182 .CP0_LLAddr_rw_bitmask = 0,
183 .CP0_LLAddr_shift = 4,
184 .SYNCI_Step = 32,
185 .CCRes = 2,
186 .CP0_Status_rw_bitmask = 0x1258FF17,
187 .SEGBITS = 32,
188 .PABITS = 32,
189 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
190 .mmu_type = MMU_TYPE_FMT,
191 },
192 {
193 .name = "4KEc",
194 .CP0_PRid = 0x00019000,
195 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
196 (MMU_TYPE_R4000 << CP0C0_MT),
197 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
198 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
199 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
200 (0 << CP0C1_CA),
201 .CP0_Config2 = MIPS_CONFIG2,
202 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
203 .CP0_LLAddr_rw_bitmask = 0,
204 .CP0_LLAddr_shift = 4,
205 .SYNCI_Step = 32,
206 .CCRes = 2,
207 .CP0_Status_rw_bitmask = 0x1278FF17,
208 .SEGBITS = 32,
209 .PABITS = 32,
210 .insn_flags = CPU_MIPS32R2,
211 .mmu_type = MMU_TYPE_R4000,
212 },
213 {
214 .name = "4KEm",
215 .CP0_PRid = 0x00019100,
216 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
217 (MMU_TYPE_FMT << CP0C0_MT),
218 .CP0_Config1 = MIPS_CONFIG1 |
219 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
220 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
221 (1 << CP0C1_CA),
222 .CP0_Config2 = MIPS_CONFIG2,
223 .CP0_Config3 = MIPS_CONFIG3,
224 .CP0_LLAddr_rw_bitmask = 0,
225 .CP0_LLAddr_shift = 4,
226 .SYNCI_Step = 32,
227 .CCRes = 2,
228 .CP0_Status_rw_bitmask = 0x1258FF17,
229 .SEGBITS = 32,
230 .PABITS = 32,
231 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
232 .mmu_type = MMU_TYPE_FMT,
233 },
234 {
235 .name = "24Kc",
236 .CP0_PRid = 0x00019300,
237 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
238 (MMU_TYPE_R4000 << CP0C0_MT),
239 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
240 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
241 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
242 (1 << CP0C1_CA),
243 .CP0_Config2 = MIPS_CONFIG2,
244 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
245 .CP0_LLAddr_rw_bitmask = 0,
246 .CP0_LLAddr_shift = 4,
247 .SYNCI_Step = 32,
248 .CCRes = 2,
249 /* No DSP implemented. */
250 .CP0_Status_rw_bitmask = 0x1278FF1F,
251 .SEGBITS = 32,
252 .PABITS = 32,
253 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
254 .mmu_type = MMU_TYPE_R4000,
255 },
256 {
257 .name = "24Kf",
258 .CP0_PRid = 0x00019300,
259 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
260 (MMU_TYPE_R4000 << CP0C0_MT),
261 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
262 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
263 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
264 (1 << CP0C1_CA),
265 .CP0_Config2 = MIPS_CONFIG2,
266 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
267 .CP0_LLAddr_rw_bitmask = 0,
268 .CP0_LLAddr_shift = 4,
269 .SYNCI_Step = 32,
270 .CCRes = 2,
271 /* No DSP implemented. */
272 .CP0_Status_rw_bitmask = 0x3678FF1F,
273 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
274 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
275 .SEGBITS = 32,
276 .PABITS = 32,
277 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
278 .mmu_type = MMU_TYPE_R4000,
279 },
280 {
281 .name = "34Kf",
282 .CP0_PRid = 0x00019500,
283 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
284 (MMU_TYPE_R4000 << CP0C0_MT),
285 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
286 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
287 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
288 (1 << CP0C1_CA),
289 .CP0_Config2 = MIPS_CONFIG2,
290 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
291 (1 << CP0C3_DSPP),
292 .CP0_LLAddr_rw_bitmask = 0,
293 .CP0_LLAddr_shift = 0,
294 .SYNCI_Step = 32,
295 .CCRes = 2,
296 .CP0_Status_rw_bitmask = 0x3778FF1F,
297 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
298 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
299 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
300 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
301 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
302 (0xff << CP0TCSt_TASID),
303 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
304 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
305 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
306 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
308 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
309 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
310 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
311 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
312 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
313 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
314 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
315 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
317 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
318 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
319 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
320 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
321 .SEGBITS = 32,
322 .PABITS = 32,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
324 .mmu_type = MMU_TYPE_R4000,
325 },
326 {
327 .name = "74Kf",
328 .CP0_PRid = 0x00019700,
329 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
330 (MMU_TYPE_R4000 << CP0C0_MT),
331 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
332 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
333 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
334 (1 << CP0C1_CA),
335 .CP0_Config2 = MIPS_CONFIG2,
336 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
337 (1 << CP0C3_VInt),
338 .CP0_LLAddr_rw_bitmask = 0,
339 .CP0_LLAddr_shift = 4,
340 .SYNCI_Step = 32,
341 .CCRes = 2,
342 .CP0_Status_rw_bitmask = 0x3778FF1F,
343 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
344 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
345 .SEGBITS = 32,
346 .PABITS = 32,
347 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
348 .mmu_type = MMU_TYPE_R4000,
349 },
350 {
351 .name = "M14K",
352 .CP0_PRid = 0x00019b00,
353 /* Config1 implemented, fixed mapping MMU,
354 no virtual icache, uncached coherency. */
355 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
356 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
357 .CP0_Config1 = MIPS_CONFIG1,
358 .CP0_Config2 = MIPS_CONFIG2,
359 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
360 .CP0_LLAddr_rw_bitmask = 0,
361 .CP0_LLAddr_shift = 4,
362 .SYNCI_Step = 32,
363 .CCRes = 2,
364 .CP0_Status_rw_bitmask = 0x1258FF17,
365 .SEGBITS = 32,
366 .PABITS = 32,
367 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
368 .mmu_type = MMU_TYPE_FMT,
369 },
370 {
371 .name = "M14Kc",
372 /* This is the TLB-based MMU core. */
373 .CP0_PRid = 0x00019c00,
374 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
375 (MMU_TYPE_R4000 << CP0C0_MT),
376 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
377 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
378 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
379 .CP0_Config2 = MIPS_CONFIG2,
380 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
381 .CP0_LLAddr_rw_bitmask = 0,
382 .CP0_LLAddr_shift = 4,
383 .SYNCI_Step = 32,
384 .CCRes = 2,
385 .CP0_Status_rw_bitmask = 0x1278FF17,
386 .SEGBITS = 32,
387 .PABITS = 32,
388 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
389 .mmu_type = MMU_TYPE_R4000,
390 },
391 {
392 /* A generic CPU providing MIPS32 Release 5 features.
393 FIXME: Eventually this should be replaced by a real CPU model. */
394 .name = "mips32r5-generic",
395 .CP0_PRid = 0x00019700,
396 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
397 (MMU_TYPE_R4000 << CP0C0_MT),
398 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
399 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
400 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
401 (1 << CP0C1_CA),
402 .CP0_Config2 = MIPS_CONFIG2,
403 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP),
404 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
405 .CP0_Config4_rw_bitmask = 0,
406 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
407 .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
408 (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
409 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
410 (0 << CP0C5_NFExists),
411 .CP0_LLAddr_rw_bitmask = 0,
412 .CP0_LLAddr_shift = 4,
413 .SYNCI_Step = 32,
414 .CCRes = 2,
415 .CP0_Status_rw_bitmask = 0x3778FF1F,
416 .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
417 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
418 (0x93 << FCR0_PRID),
419 .SEGBITS = 32,
420 .PABITS = 32,
421 .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
422 .mmu_type = MMU_TYPE_R4000,
423 },
424 #if defined(TARGET_MIPS64)
425 {
426 .name = "R4000",
427 .CP0_PRid = 0x00000400,
428 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
429 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
430 /* Note: Config1 is only used internally, the R4000 has only Config0. */
431 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
432 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
433 .CP0_LLAddr_shift = 4,
434 .SYNCI_Step = 16,
435 .CCRes = 2,
436 .CP0_Status_rw_bitmask = 0x3678FFFF,
437 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
438 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
439 .SEGBITS = 40,
440 .PABITS = 36,
441 .insn_flags = CPU_MIPS3,
442 .mmu_type = MMU_TYPE_R4000,
443 },
444 {
445 .name = "VR5432",
446 .CP0_PRid = 0x00005400,
447 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
448 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
449 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
450 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
451 .CP0_LLAddr_shift = 4,
452 .SYNCI_Step = 16,
453 .CCRes = 2,
454 .CP0_Status_rw_bitmask = 0x3678FFFF,
455 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
456 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
457 .SEGBITS = 40,
458 .PABITS = 32,
459 .insn_flags = CPU_VR54XX,
460 .mmu_type = MMU_TYPE_R4000,
461 },
462 {
463 .name = "5Kc",
464 .CP0_PRid = 0x00018100,
465 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
466 (MMU_TYPE_R4000 << CP0C0_MT),
467 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
468 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
469 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
470 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
471 .CP0_Config2 = MIPS_CONFIG2,
472 .CP0_Config3 = MIPS_CONFIG3,
473 .CP0_LLAddr_rw_bitmask = 0,
474 .CP0_LLAddr_shift = 4,
475 .SYNCI_Step = 32,
476 .CCRes = 2,
477 .CP0_Status_rw_bitmask = 0x12F8FFFF,
478 .SEGBITS = 42,
479 .PABITS = 36,
480 .insn_flags = CPU_MIPS64,
481 .mmu_type = MMU_TYPE_R4000,
482 },
483 {
484 .name = "5Kf",
485 .CP0_PRid = 0x00018100,
486 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
487 (MMU_TYPE_R4000 << CP0C0_MT),
488 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
489 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
490 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
491 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
492 .CP0_Config2 = MIPS_CONFIG2,
493 .CP0_Config3 = MIPS_CONFIG3,
494 .CP0_LLAddr_rw_bitmask = 0,
495 .CP0_LLAddr_shift = 4,
496 .SYNCI_Step = 32,
497 .CCRes = 2,
498 .CP0_Status_rw_bitmask = 0x36F8FFFF,
499 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
500 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
501 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
502 .SEGBITS = 42,
503 .PABITS = 36,
504 .insn_flags = CPU_MIPS64,
505 .mmu_type = MMU_TYPE_R4000,
506 },
507 {
508 .name = "20Kc",
509 /* We emulate a later version of the 20Kc, earlier ones had a broken
510 WAIT instruction. */
511 .CP0_PRid = 0x000182a0,
512 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
513 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
514 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
515 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
516 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
517 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
518 .CP0_Config2 = MIPS_CONFIG2,
519 .CP0_Config3 = MIPS_CONFIG3,
520 .CP0_LLAddr_rw_bitmask = 0,
521 .CP0_LLAddr_shift = 0,
522 .SYNCI_Step = 32,
523 .CCRes = 1,
524 .CP0_Status_rw_bitmask = 0x36FBFFFF,
525 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
526 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
527 (1 << FCR0_D) | (1 << FCR0_S) |
528 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
529 .SEGBITS = 40,
530 .PABITS = 36,
531 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
532 .mmu_type = MMU_TYPE_R4000,
533 },
534 {
535 /* A generic CPU providing MIPS64 Release 2 features.
536 FIXME: Eventually this should be replaced by a real CPU model. */
537 .name = "MIPS64R2-generic",
538 .CP0_PRid = 0x00010000,
539 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
540 (MMU_TYPE_R4000 << CP0C0_MT),
541 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
542 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
543 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
544 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
545 .CP0_Config2 = MIPS_CONFIG2,
546 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
547 .CP0_LLAddr_rw_bitmask = 0,
548 .CP0_LLAddr_shift = 0,
549 .SYNCI_Step = 32,
550 .CCRes = 2,
551 .CP0_Status_rw_bitmask = 0x36FBFFFF,
552 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
553 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
554 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
555 .SEGBITS = 42,
556 /* The architectural limit is 59, but we have hardcoded 36 bit
557 in some places...
558 .PABITS = 59, */ /* the architectural limit */
559 .PABITS = 36,
560 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
561 .mmu_type = MMU_TYPE_R4000,
562 },
563 {
564 .name = "5KEc",
565 .CP0_PRid = 0x00018900,
566 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
567 (MMU_TYPE_R4000 << CP0C0_MT),
568 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
569 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
570 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
571 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
572 .CP0_Config2 = MIPS_CONFIG2,
573 .CP0_Config3 = MIPS_CONFIG3,
574 .CP0_LLAddr_rw_bitmask = 0,
575 .CP0_LLAddr_shift = 4,
576 .SYNCI_Step = 32,
577 .CCRes = 2,
578 .CP0_Status_rw_bitmask = 0x12F8FFFF,
579 .SEGBITS = 42,
580 .PABITS = 36,
581 .insn_flags = CPU_MIPS64R2,
582 .mmu_type = MMU_TYPE_R4000,
583 },
584 {
585 .name = "5KEf",
586 .CP0_PRid = 0x00018900,
587 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
588 (MMU_TYPE_R4000 << CP0C0_MT),
589 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
590 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
591 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
592 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
593 .CP0_Config2 = MIPS_CONFIG2,
594 .CP0_Config3 = MIPS_CONFIG3,
595 .CP0_LLAddr_rw_bitmask = 0,
596 .CP0_LLAddr_shift = 4,
597 .SYNCI_Step = 32,
598 .CCRes = 2,
599 .CP0_Status_rw_bitmask = 0x36F8FFFF,
600 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
601 (1 << FCR0_D) | (1 << FCR0_S) |
602 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
603 .SEGBITS = 42,
604 .PABITS = 36,
605 .insn_flags = CPU_MIPS64R2,
606 .mmu_type = MMU_TYPE_R4000,
607 },
608 {
609 /* A generic CPU supporting MIPS64 Release 6 ISA.
610 FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
611 Eventually this should be replaced by a real CPU model. */
612 .name = "MIPS64R6-generic",
613 .CP0_PRid = 0x00010000,
614 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
615 (MMU_TYPE_R4000 << CP0C0_MT),
616 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
617 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
618 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
619 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
620 .CP0_Config2 = MIPS_CONFIG2,
621 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
622 (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
623 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
624 (3 << CP0C4_IE) | (1 << CP0C4_M),
625 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI),
626 .CP0_LLAddr_rw_bitmask = 0,
627 .CP0_LLAddr_shift = 0,
628 .SYNCI_Step = 32,
629 .CCRes = 2,
630 .CP0_Status_rw_bitmask = 0x30D8FFFF,
631 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
632 (1U << CP0PG_RIE),
633 .CP0_PageGrain_rw_bitmask = 0,
634 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
635 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
636 (0x0 << FCR0_REV),
637 .SEGBITS = 42,
638 /* The architectural limit is 59, but we have hardcoded 36 bit
639 in some places...
640 .PABITS = 59, */ /* the architectural limit */
641 .PABITS = 36,
642 .insn_flags = CPU_MIPS64R6,
643 .mmu_type = MMU_TYPE_R4000,
644 },
645 {
646 .name = "Loongson-2E",
647 .CP0_PRid = 0x6302,
648 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
649 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
650 (0x1<<5) | (0x1<<4) | (0x1<<1),
651 /* Note: Config1 is only used internally,
652 Loongson-2E has only Config0. */
653 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
654 .SYNCI_Step = 16,
655 .CCRes = 2,
656 .CP0_Status_rw_bitmask = 0x35D0FFFF,
657 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
658 .SEGBITS = 40,
659 .PABITS = 40,
660 .insn_flags = CPU_LOONGSON2E,
661 .mmu_type = MMU_TYPE_R4000,
662 },
663 {
664 .name = "Loongson-2F",
665 .CP0_PRid = 0x6303,
666 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
667 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
668 (0x1<<5) | (0x1<<4) | (0x1<<1),
669 /* Note: Config1 is only used internally,
670 Loongson-2F has only Config0. */
671 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
672 .SYNCI_Step = 16,
673 .CCRes = 2,
674 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
675 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
676 .SEGBITS = 40,
677 .PABITS = 40,
678 .insn_flags = CPU_LOONGSON2F,
679 .mmu_type = MMU_TYPE_R4000,
680 },
681 {
682 /* A generic CPU providing MIPS64 ASE DSP 2 features.
683 FIXME: Eventually this should be replaced by a real CPU model. */
684 .name = "mips64dspr2",
685 .CP0_PRid = 0x00010000,
686 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
687 (MMU_TYPE_R4000 << CP0C0_MT),
688 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
689 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
690 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
691 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
692 .CP0_Config2 = MIPS_CONFIG2,
693 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
694 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
695 .CP0_LLAddr_rw_bitmask = 0,
696 .CP0_LLAddr_shift = 0,
697 .SYNCI_Step = 32,
698 .CCRes = 2,
699 .CP0_Status_rw_bitmask = 0x37FBFFFF,
700 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
701 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
702 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
703 .SEGBITS = 42,
704 /* The architectural limit is 59, but we have hardcoded 36 bit
705 in some places...
706 .PABITS = 59, */ /* the architectural limit */
707 .PABITS = 36,
708 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
709 .mmu_type = MMU_TYPE_R4000,
710 },
711
712 #endif
713 };
714
715 static const mips_def_t *cpu_mips_find_by_name (const char *name)
716 {
717 int i;
718
719 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
720 if (strcasecmp(name, mips_defs[i].name) == 0) {
721 return &mips_defs[i];
722 }
723 }
724 return NULL;
725 }
726
727 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
728 {
729 int i;
730
731 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
732 (*cpu_fprintf)(f, "MIPS '%s'\n",
733 mips_defs[i].name);
734 }
735 }
736
737 #ifndef CONFIG_USER_ONLY
738 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
739 {
740 env->tlb->nb_tlb = 1;
741 env->tlb->map_address = &no_mmu_map_address;
742 }
743
744 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
745 {
746 env->tlb->nb_tlb = 1;
747 env->tlb->map_address = &fixed_mmu_map_address;
748 }
749
750 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
751 {
752 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
753 env->tlb->map_address = &r4k_map_address;
754 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
755 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
756 env->tlb->helper_tlbp = r4k_helper_tlbp;
757 env->tlb->helper_tlbr = r4k_helper_tlbr;
758 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
759 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
760 }
761
762 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
763 {
764 MIPSCPU *cpu = mips_env_get_cpu(env);
765
766 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
767
768 switch (def->mmu_type) {
769 case MMU_TYPE_NONE:
770 no_mmu_init(env, def);
771 break;
772 case MMU_TYPE_R4000:
773 r4k_mmu_init(env, def);
774 break;
775 case MMU_TYPE_FMT:
776 fixed_mmu_init(env, def);
777 break;
778 case MMU_TYPE_R3000:
779 case MMU_TYPE_R6000:
780 case MMU_TYPE_R8000:
781 default:
782 cpu_abort(CPU(cpu), "MMU type not supported\n");
783 }
784 }
785 #endif /* CONFIG_USER_ONLY */
786
787 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
788 {
789 int i;
790
791 for (i = 0; i < MIPS_FPU_MAX; i++)
792 env->fpus[i].fcr0 = def->CP1_fcr0;
793
794 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
795 }
796
797 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
798 {
799 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
800
801 /* MVPConf1 implemented, TLB sharable, no gating storage support,
802 programmable cache partitioning implemented, number of allocatable
803 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
804 implemented, 5 TCs implemented. */
805 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
806 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
807 // TODO: actually do 2 VPEs.
808 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
809 // (0x04 << CP0MVPC0_PTC);
810 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
811 (0x00 << CP0MVPC0_PTC);
812 #if !defined(CONFIG_USER_ONLY)
813 /* Usermode has no TLB support */
814 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
815 #endif
816
817 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
818 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
819 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
820 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
821 (0x1 << CP0MVPC1_PCP1);
822 }
823
824 static void msa_reset(CPUMIPSState *env)
825 {
826 #ifdef CONFIG_USER_ONLY
827 /* MSA access enabled */
828 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
829 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
830 #endif
831
832 /* MSA CSR:
833 - non-signaling floating point exception mode off (NX bit is 0)
834 - Cause, Enables, and Flags are all 0
835 - round to nearest / ties to even (RM bits are 0) */
836 env->active_tc.msacsr = 0;
837
838 /* tininess detected after rounding.*/
839 set_float_detect_tininess(float_tininess_after_rounding,
840 &env->active_tc.msa_fp_status);
841
842 /* clear float_status exception flags */
843 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
844
845 /* set float_status rounding mode */
846 set_float_rounding_mode(float_round_nearest_even,
847 &env->active_tc.msa_fp_status);
848
849 /* set float_status flush modes */
850 set_flush_to_zero(0, &env->active_tc.msa_fp_status);
851 set_flush_inputs_to_zero(0, &env->active_tc.msa_fp_status);
852
853 /* clear float_status nan mode */
854 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
855 }
AR7 emulation for QEMU