hw/arm/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/arm.h"
  24 #include "net/net.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/boards.h"
  28 #include "hw/block/flash.h"
  29 #include "sysemu/block-backend.h"
  30 #include "hw/loader.h"
  31 #include "hw/misc/zynq-xadc.h"
  32 #include "hw/ssi/ssi.h"
  33 #include "qemu/error-report.h"
  34 #include "hw/sd/sd.h"
  35
  36 #define NUM_SPI_FLASHES 4
  37 #define NUM_QSPI_FLASHES 2
  38 #define NUM_QSPI_BUSSES 2
  39
  40 #define FLASH_SIZE (64 * 1024 * 1024)
  41 #define FLASH_SECTOR_SIZE (128 * 1024)
  42
  43 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  44
  45 #define MPCORE_PERIPHBASE 0xF8F00000
  46 #define ZYNQ_BOARD_MIDR 0x413FC090
  47
  48 static const int dma_irqs[8] = {
  49     46, 47, 48, 49, 72, 73, 74, 75
  50 };
  51
  52 #define BOARD_SETUP_ADDR        0x100
  53
  54 #define SLCR_LOCK_OFFSET        0x004
  55 #define SLCR_UNLOCK_OFFSET      0x008
  56 #define SLCR_ARM_PLL_OFFSET     0x100
  57
  58 #define SLCR_XILINX_UNLOCK_KEY  0xdf0d
  59 #define SLCR_XILINX_LOCK_KEY    0x767b
  60
  61 #define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
  62                         extract32((x), 12,  4) << 16)
  63
  64 /* Write immediate val to address r0 + addr. r0 should contain base offset
  65  * of the SLCR block. Clobbers r1.
  66  */
  67
  68 #define SLCR_WRITE(addr, val) \
  69     0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
  70     0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
  71     0xe5801000 + (addr)
  72
  73 static void zynq_write_board_setup(ARMCPU *cpu,
  74                                    const struct arm_boot_info *info)
  75 {
  76     int n;
  77     uint32_t board_setup_blob[] = {
  78         0xe3a004f8, /* mov r0, #0xf8000000 */
  79         SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
  80         SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
  81         SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
  82         0xe12fff1e, /* bx lr */
  83     };
  84     for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
  85         board_setup_blob[n] = tswap32(board_setup_blob[n]);
  86     }
  87     rom_add_blob_fixed("board-setup", board_setup_blob,
  88                        sizeof(board_setup_blob), BOARD_SETUP_ADDR);
  89 }
  90
  91 static struct arm_boot_info zynq_binfo = {};
  92
  93 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  94 {
  95     DeviceState *dev;
  96     SysBusDevice *s;
  97
  98     dev = qdev_create(NULL, "cadence_gem");
  99     if (nd->used) {
 100         qemu_check_nic_model(nd, "cadence_gem");
 101         qdev_set_nic_properties(dev, nd);
 102     }
 103     qdev_init_nofail(dev);
 104     s = SYS_BUS_DEVICE(dev);
 105     sysbus_mmio_map(s, 0, base);
 106     sysbus_connect_irq(s, 0, irq);
 107 }
 108
 109 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
 110                                          bool is_qspi)
 111 {
 112     DeviceState *dev;
 113     SysBusDevice *busdev;
 114     SSIBus *spi;
 115     DeviceState *flash_dev;
 116     int i, j;
 117     int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
 118     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
 119
 120     dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
 121     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
 122     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
 123     qdev_prop_set_uint8(dev, "num-busses", num_busses);
 124     qdev_init_nofail(dev);
 125     busdev = SYS_BUS_DEVICE(dev);
 126     sysbus_mmio_map(busdev, 0, base_addr);
 127     if (is_qspi) {
 128         sysbus_mmio_map(busdev, 1, 0xFC000000);
 129     }
 130     sysbus_connect_irq(busdev, 0, irq);
 131
 132     for (i = 0; i < num_busses; ++i) {
 133         char bus_name[16];
 134         qemu_irq cs_line;
 135
 136         snprintf(bus_name, 16, "spi%d", i);
 137         spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
 138
 139         for (j = 0; j < num_ss; ++j) {
 140             flash_dev = ssi_create_slave(spi, "n25q128");
 141
 142             cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 143             sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
 144         }
 145     }
 146
 147 }
 148
 149 static void zynq_init(MachineState *machine)
 150 {
 151     ram_addr_t ram_size = machine->ram_size;
 152     const char *cpu_model = machine->cpu_model;
 153     const char *kernel_filename = machine->kernel_filename;
 154     const char *kernel_cmdline = machine->kernel_cmdline;
 155     const char *initrd_filename = machine->initrd_filename;
 156     ObjectClass *cpu_oc;
 157     ARMCPU *cpu;
 158     MemoryRegion *address_space_mem = get_system_memory();
 159     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
 160     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
 161     DeviceState *dev, *carddev;
 162     SysBusDevice *busdev;
 163     DriveInfo *di;
 164     BlockBackend *blk;
 165     qemu_irq pic[64];
 166     int n;
 167
 168     if (!cpu_model) {
 169         cpu_model = "cortex-a9";
 170     }
 171     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 172
 173     cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
 174
 175     /* By default A9 CPUs have EL3 enabled.  This board does not
 176      * currently support EL3 so the CPU EL3 property is disabled before
 177      * realization.
 178      */
 179     if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
 180         object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
 181     }
 182
 183     object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
 184                             &error_fatal);
 185     object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
 186                             &error_fatal);
 187     object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
 188
 189     /* max 2GB ram */
 190     if (ram_size > 0x80000000) {
 191         ram_size = 0x80000000;
 192     }
 193
 194     /* DDR remapped to address zero.  */
 195     memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
 196                                          ram_size);
 197     memory_region_add_subregion(address_space_mem, 0, ext_ram);
 198
 199     /* 256K of on-chip memory */
 200     memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
 201                            &error_fatal);
 202     vmstate_register_ram_global(ocm_ram);
 203     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 204
 205     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 206
 207     /* AMD */
 208     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
 209                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 210                           FLASH_SECTOR_SIZE,
 211                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
 212                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 213                               0);
 214
 215     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 216     qdev_init_nofail(dev);
 217     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 218
 219     dev = qdev_create(NULL, "a9mpcore_priv");
 220     qdev_prop_set_uint32(dev, "num-cpu", 1);
 221     qdev_init_nofail(dev);
 222     busdev = SYS_BUS_DEVICE(dev);
 223     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 224     sysbus_connect_irq(busdev, 0,
 225                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 226
 227     for (n = 0; n < 64; n++) {
 228         pic[n] = qdev_get_gpio_in(dev, n);
 229     }
 230
 231     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
 232     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
 233     zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
 234
 235     sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
 236     sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
 237
 238     sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
 239     sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
 240
 241     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 242             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 243     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 244             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 245
 246     gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
 247     gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
 248
 249     dev = qdev_create(NULL, "generic-sdhci");
 250     qdev_init_nofail(dev);
 251     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
 252     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
 253
 254     di = drive_get_next(IF_SD);
 255     blk = di ? blk_by_legacy_dinfo(di) : NULL;
 256     carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
 257     qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
 258     object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
 259
 260     dev = qdev_create(NULL, "generic-sdhci");
 261     qdev_init_nofail(dev);
 262     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
 263     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
 264
 265     di = drive_get_next(IF_SD);
 266     blk = di ? blk_by_legacy_dinfo(di) : NULL;
 267     carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
 268     qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
 269     object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
 270
 271     dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
 272     qdev_init_nofail(dev);
 273     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
 274     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
 275
 276     dev = qdev_create(NULL, "pl330");
 277     qdev_prop_set_uint8(dev, "num_chnls",  8);
 278     qdev_prop_set_uint8(dev, "num_periph_req",  4);
 279     qdev_prop_set_uint8(dev, "num_events",  16);
 280
 281     qdev_prop_set_uint8(dev, "data_width",  64);
 282     qdev_prop_set_uint8(dev, "wr_cap",  8);
 283     qdev_prop_set_uint8(dev, "wr_q_dep",  16);
 284     qdev_prop_set_uint8(dev, "rd_cap",  8);
 285     qdev_prop_set_uint8(dev, "rd_q_dep",  16);
 286     qdev_prop_set_uint16(dev, "data_buffer_dep",  256);
 287
 288     qdev_init_nofail(dev);
 289     busdev = SYS_BUS_DEVICE(dev);
 290     sysbus_mmio_map(busdev, 0, 0xF8003000);
 291     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
 292     for (n = 0; n < 8; ++n) { /* event irqs */
 293         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
 294     }
 295
 296     zynq_binfo.ram_size = ram_size;
 297     zynq_binfo.kernel_filename = kernel_filename;
 298     zynq_binfo.kernel_cmdline = kernel_cmdline;
 299     zynq_binfo.initrd_filename = initrd_filename;
 300     zynq_binfo.nb_cpus = 1;
 301     zynq_binfo.board_id = 0xd32;
 302     zynq_binfo.loader_start = 0;
 303     zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 304     zynq_binfo.write_board_setup = zynq_write_board_setup;
 305
 306     arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
 307 }
 308
 309 static void zynq_machine_init(MachineClass *mc)
 310 {
 311     mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
 312     mc->init = zynq_init;
 313     mc->block_default_type = IF_SCSI;
 314     mc->max_cpus = 1;
 315     mc->no_sdcard = 1;
 316 }
 317
 318 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)