hw/arm/s3c24xx_clkcon.c

   1 /* hw/s3c24xx_clkcon.c
   2  *
   3  * Samsung S3C24XX Clock control emulation
   4  *
   5  * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
   6  *
   7  * Copyright 2010, 2013 Stefan Weil
   8  *
   9  * This file is under the terms of the GNU General Public License Version 2.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/hw.h"
  14 #include "exec/address-spaces.h" /* get_system_memory */
  15
  16 #include "s3c24xx.h"
  17
  18 /* Lock time RW */
  19 #define S3C_REG_LOCKTIME 0
  20
  21 /* MPLL Control RW */
  22 #define S3C_REG_MPLLCON 1
  23
  24 /* UPLL Control RW */
  25 #define S3C_REG_UPLLCON 2
  26
  27 /* Clock Generator Control RW */
  28 #define S3C_REG_CLKCON 3
  29
  30 /* CLKCON IDLE */
  31 #define S3C_REG_CLKCON_IDLE (1<<2)
  32
  33 /* Slow Clock Control RW */
  34 #define S3C_REG_CLKSLOW 4
  35
  36 /* Clock divider control RW */
  37 #define S3C_REG_CLKDIVN 5
  38
  39 /* Clock controller state */
  40 struct s3c24xx_clkcon_state_s {
  41     MemoryRegion mmio;
  42     CPUARMState *cpu_env;
  43     uint32_t ref_freq; /* frequency of reference xtal or extclock */
  44     uint32_t clkcon_reg[7];
  45 };
  46
  47 static void s3c24xx_clkcon_write(void *opaque, hwaddr addr_,
  48                                  uint64_t value, unsigned size)
  49 {
  50     struct s3c24xx_clkcon_state_s *s = opaque;
  51     unsigned addr = (addr_ & 0x1F) >> 2;
  52     int idle_rising_edge = 0;
  53
  54     assert(addr < ARRAY_SIZE(s->clkcon_reg));
  55
  56     if (addr == S3C_REG_CLKCON) {
  57         if (!(s->clkcon_reg[addr] & S3C_REG_CLKCON_IDLE) &&
  58             (value & S3C_REG_CLKCON_IDLE))
  59             idle_rising_edge = 1;
  60     }
  61
  62     s->clkcon_reg[addr] = value;
  63
  64     if (idle_rising_edge) {
  65         cpu_interrupt(CPU(s), CPU_INTERRUPT_HALT);
  66     }
  67 }
  68
  69 static uint64_t s3c24xx_clkcon_read(void *opaque, hwaddr addr_,
  70                                     unsigned size)
  71 {
  72     struct s3c24xx_clkcon_state_s *s = opaque;
  73     unsigned addr = (addr_ & 0x1F) >> 2;
  74
  75     assert(addr < ARRAY_SIZE(s->clkcon_reg));
  76
  77     return s->clkcon_reg[addr];
  78 }
  79
  80 static const MemoryRegionOps s3c24xx_clkcon_ops = {
  81     .read = s3c24xx_clkcon_read,
  82     .write = s3c24xx_clkcon_write,
  83     .endianness = DEVICE_NATIVE_ENDIAN,
  84     .valid = {
  85         .min_access_size = 1,
  86         .max_access_size = 4
  87     }
  88 };
  89
  90 static void s3c24xx_clkcon_save(QEMUFile *f, void *opaque)
  91 {
  92     struct s3c24xx_clkcon_state_s *s = (struct s3c24xx_clkcon_state_s *)opaque;
  93     int i;
  94
  95     for (i = 0; i < ARRAY_SIZE(s->clkcon_reg); i ++) {
  96         qemu_put_be32s(f, &s->clkcon_reg[i]);
  97     }
  98 }
  99
 100 static int s3c24xx_clkcon_load(QEMUFile *f, void *opaque, int version_id)
 101 {
 102     struct s3c24xx_clkcon_state_s *s = opaque;
 103     int i;
 104
 105     for (i = 0; i < ARRAY_SIZE(s->clkcon_reg); i ++) {
 106         qemu_get_be32s(f, &s->clkcon_reg[i]);
 107     }
 108
 109     return 0;
 110 }
 111
 112 struct s3c24xx_clkcon_state_s *
 113 s3c24xx_clkcon_init(S3CState *soc, hwaddr base_addr, uint32_t ref_freq)
 114 {
 115     struct s3c24xx_clkcon_state_s *s = g_new0(struct s3c24xx_clkcon_state_s, 1);
 116
 117     memory_region_init_io(&s->mmio, OBJECT(s), &s3c24xx_clkcon_ops, s,
 118                           "s3c24xx.clkcon", ARRAY_SIZE(s->clkcon_reg) * 4);
 119     memory_region_add_subregion(get_system_memory(), base_addr, &s->mmio);
 120     register_savevm(NULL, "s3c24xx_clkcon", 0, 0, s3c24xx_clkcon_save, s3c24xx_clkcon_load, s);
 121
 122     s->cpu_env = &soc->cpu->env;
 123     s->ref_freq = ref_freq;
 124
 125     /* initialise register values to power on defaults */
 126     s->clkcon_reg[S3C_REG_LOCKTIME] = 0x00FFFFFF;
 127     s->clkcon_reg[S3C_REG_MPLLCON] = 0x0005C080;
 128     s->clkcon_reg[S3C_REG_UPLLCON] = 0x00028080;
 129     s->clkcon_reg[S3C_REG_CLKCON] = 0x0007FFF0;
 130     s->clkcon_reg[S3C_REG_CLKSLOW] = 0x00000004;
 131     s->clkcon_reg[S3C_REG_CLKDIVN] = 0x00000000;
 132
 133     return s;
 134 }