hw/ppc/spapr_iommu.c

   1 /*
   2  * QEMU sPAPR IOMMU (TCE) code
   3  *
   4  * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "hw/hw.h"
  20 #include "sysemu/kvm.h"
  21 #include "hw/qdev.h"
  22 #include "kvm_ppc.h"
  23 #include "sysemu/dma.h"
  24 #include "exec/address-spaces.h"
  25 #include "trace.h"
  26
  27 #include "hw/ppc/spapr.h"
  28 #include "hw/ppc/spapr_vio.h"
  29
  30 #include <libfdt.h>
  31
  32 enum sPAPRTCEAccess {
  33     SPAPR_TCE_FAULT = 0,
  34     SPAPR_TCE_RO = 1,
  35     SPAPR_TCE_WO = 2,
  36     SPAPR_TCE_RW = 3,
  37 };
  38
  39 #define IOMMU_PAGE_SIZE(shift)      (1ULL << (shift))
  40 #define IOMMU_PAGE_MASK(shift)      (~(IOMMU_PAGE_SIZE(shift) - 1))
  41
  42 static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
  43
  44 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
  45 {
  46     sPAPRTCETable *tcet;
  47
  48     if (liobn & 0xFFFFFFFF00000000ULL) {
  49         hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
  50                       liobn);
  51         return NULL;
  52     }
  53
  54     QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
  55         if (tcet->liobn == (uint32_t)liobn) {
  56             return tcet;
  57         }
  58     }
  59
  60     return NULL;
  61 }
  62
  63 static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
  64 {
  65     switch (tce & SPAPR_TCE_RW) {
  66     case SPAPR_TCE_FAULT:
  67         return IOMMU_NONE;
  68     case SPAPR_TCE_RO:
  69         return IOMMU_RO;
  70     case SPAPR_TCE_WO:
  71         return IOMMU_WO;
  72     default: /* SPAPR_TCE_RW */
  73         return IOMMU_RW;
  74     }
  75 }
  76
  77 /* Called from RCU critical section */
  78 static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr,
  79                                                bool is_write)
  80 {
  81     sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
  82     uint64_t tce;
  83     IOMMUTLBEntry ret = {
  84         .target_as = &address_space_memory,
  85         .iova = 0,
  86         .translated_addr = 0,
  87         .addr_mask = ~(hwaddr)0,
  88         .perm = IOMMU_NONE,
  89     };
  90
  91     if ((addr >> tcet->page_shift) < tcet->nb_table) {
  92         /* Check if we are in bound */
  93         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
  94
  95         tce = tcet->table[addr >> tcet->page_shift];
  96         ret.iova = addr & page_mask;
  97         ret.translated_addr = tce & page_mask;
  98         ret.addr_mask = ~page_mask;
  99         ret.perm = spapr_tce_iommu_access_flags(tce);
 100     }
 101     trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
 102                             ret.addr_mask);
 103
 104     return ret;
 105 }
 106
 107 static int spapr_tce_table_post_load(void *opaque, int version_id)
 108 {
 109     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
 110
 111     if (tcet->vdev) {
 112         spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
 113     }
 114
 115     return 0;
 116 }
 117
 118 static const VMStateDescription vmstate_spapr_tce_table = {
 119     .name = "spapr_iommu",
 120     .version_id = 2,
 121     .minimum_version_id = 2,
 122     .post_load = spapr_tce_table_post_load,
 123     .fields      = (VMStateField []) {
 124         /* Sanity check */
 125         VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable),
 126         VMSTATE_UINT32_EQUAL(nb_table, sPAPRTCETable),
 127
 128         /* IOMMU state */
 129         VMSTATE_BOOL(bypass, sPAPRTCETable),
 130         VMSTATE_VARRAY_UINT32(table, sPAPRTCETable, nb_table, 0, vmstate_info_uint64, uint64_t),
 131
 132         VMSTATE_END_OF_LIST()
 133     },
 134 };
 135
 136 static MemoryRegionIOMMUOps spapr_iommu_ops = {
 137     .translate = spapr_tce_translate_iommu,
 138 };
 139
 140 static int spapr_tce_table_realize(DeviceState *dev)
 141 {
 142     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
 143     uint64_t window_size = (uint64_t)tcet->nb_table << tcet->page_shift;
 144
 145     if (kvm_enabled() && !(window_size >> 32)) {
 146         tcet->table = kvmppc_create_spapr_tce(tcet->liobn,
 147                                               window_size,
 148                                               &tcet->fd,
 149                                               tcet->vfio_accel);
 150     }
 151
 152     if (!tcet->table) {
 153         size_t table_size = tcet->nb_table * sizeof(uint64_t);
 154         tcet->table = g_malloc0(table_size);
 155     }
 156
 157     trace_spapr_iommu_new_table(tcet->liobn, tcet, tcet->table, tcet->fd);
 158
 159     memory_region_init_iommu(&tcet->iommu, OBJECT(dev), &spapr_iommu_ops,
 160                              "iommu-spapr",
 161                              (uint64_t)tcet->nb_table << tcet->page_shift);
 162
 163     QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
 164
 165     vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
 166                      tcet);
 167
 168     return 0;
 169 }
 170
 171 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
 172                                    uint64_t bus_offset,
 173                                    uint32_t page_shift,
 174                                    uint32_t nb_table,
 175                                    bool vfio_accel)
 176 {
 177     sPAPRTCETable *tcet;
 178     char tmp[64];
 179
 180     if (spapr_tce_find_by_liobn(liobn)) {
 181         fprintf(stderr, "Attempted to create TCE table with duplicate"
 182                 " LIOBN 0x%x\n", liobn);
 183         return NULL;
 184     }
 185
 186     if (!nb_table) {
 187         return NULL;
 188     }
 189
 190     tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
 191     tcet->liobn = liobn;
 192     tcet->bus_offset = bus_offset;
 193     tcet->page_shift = page_shift;
 194     tcet->nb_table = nb_table;
 195     tcet->vfio_accel = vfio_accel;
 196
 197     snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn);
 198     object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
 199
 200     object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
 201
 202     return tcet;
 203 }
 204
 205 static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
 206 {
 207     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
 208
 209     QLIST_REMOVE(tcet, list);
 210
 211     if (!kvm_enabled() ||
 212         (kvmppc_remove_spapr_tce(tcet->table, tcet->fd,
 213                                  tcet->nb_table) != 0)) {
 214         g_free(tcet->table);
 215     }
 216 }
 217
 218 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
 219 {
 220     return &tcet->iommu;
 221 }
 222
 223 static void spapr_tce_reset(DeviceState *dev)
 224 {
 225     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
 226     size_t table_size = tcet->nb_table * sizeof(uint64_t);
 227
 228     memset(tcet->table, 0, table_size);
 229 }
 230
 231 static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
 232                                 target_ulong tce)
 233 {
 234     IOMMUTLBEntry entry;
 235     hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 236     unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
 237
 238     if (index >= tcet->nb_table) {
 239         hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
 240                       TARGET_FMT_lx "\n", ioba);
 241         return H_PARAMETER;
 242     }
 243
 244     tcet->table[index] = tce;
 245
 246     entry.target_as = &address_space_memory,
 247     entry.iova = ioba & page_mask;
 248     entry.translated_addr = tce & page_mask;
 249     entry.addr_mask = ~page_mask;
 250     entry.perm = spapr_tce_iommu_access_flags(tce);
 251     memory_region_notify_iommu(&tcet->iommu, entry);
 252
 253     return H_SUCCESS;
 254 }
 255
 256 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
 257                                        sPAPRMachineState *spapr,
 258                                        target_ulong opcode, target_ulong *args)
 259 {
 260     int i;
 261     target_ulong liobn = args[0];
 262     target_ulong ioba = args[1];
 263     target_ulong ioba1 = ioba;
 264     target_ulong tce_list = args[2];
 265     target_ulong npages = args[3];
 266     target_ulong ret = H_PARAMETER, tce = 0;
 267     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 268     CPUState *cs = CPU(cpu);
 269     hwaddr page_mask, page_size;
 270
 271     if (!tcet) {
 272         return H_PARAMETER;
 273     }
 274
 275     if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
 276         return H_PARAMETER;
 277     }
 278
 279     page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 280     page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
 281     ioba &= page_mask;
 282
 283     for (i = 0; i < npages; ++i, ioba += page_size) {
 284         tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
 285
 286         ret = put_tce_emu(tcet, ioba, tce);
 287         if (ret) {
 288             break;
 289         }
 290     }
 291
 292     /* Trace last successful or the first problematic entry */
 293     i = i ? (i - 1) : 0;
 294     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 295         trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
 296     } else {
 297         trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
 298     }
 299     return ret;
 300 }
 301
 302 static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 303                               target_ulong opcode, target_ulong *args)
 304 {
 305     int i;
 306     target_ulong liobn = args[0];
 307     target_ulong ioba = args[1];
 308     target_ulong tce_value = args[2];
 309     target_ulong npages = args[3];
 310     target_ulong ret = H_PARAMETER;
 311     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 312     hwaddr page_mask, page_size;
 313
 314     if (!tcet) {
 315         return H_PARAMETER;
 316     }
 317
 318     if (npages > tcet->nb_table) {
 319         return H_PARAMETER;
 320     }
 321
 322     page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 323     page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
 324     ioba &= page_mask;
 325
 326     for (i = 0; i < npages; ++i, ioba += page_size) {
 327         ret = put_tce_emu(tcet, ioba, tce_value);
 328         if (ret) {
 329             break;
 330         }
 331     }
 332     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 333         trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
 334     } else {
 335         trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
 336     }
 337
 338     return ret;
 339 }
 340
 341 static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 342                               target_ulong opcode, target_ulong *args)
 343 {
 344     target_ulong liobn = args[0];
 345     target_ulong ioba = args[1];
 346     target_ulong tce = args[2];
 347     target_ulong ret = H_PARAMETER;
 348     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 349
 350     if (tcet) {
 351         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 352
 353         ioba &= page_mask;
 354
 355         ret = put_tce_emu(tcet, ioba, tce);
 356     }
 357     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 358         trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
 359     } else {
 360         trace_spapr_iommu_put(liobn, ioba, tce, ret);
 361     }
 362
 363     return ret;
 364 }
 365
 366 static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
 367                                 target_ulong *tce)
 368 {
 369     unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
 370
 371     if (index >= tcet->nb_table) {
 372         hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
 373                       TARGET_FMT_lx "\n", ioba);
 374         return H_PARAMETER;
 375     }
 376
 377     *tce = tcet->table[index];
 378
 379     return H_SUCCESS;
 380 }
 381
 382 static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 383                               target_ulong opcode, target_ulong *args)
 384 {
 385     target_ulong liobn = args[0];
 386     target_ulong ioba = args[1];
 387     target_ulong tce = 0;
 388     target_ulong ret = H_PARAMETER;
 389     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 390
 391     if (tcet) {
 392         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 393
 394         ioba &= page_mask;
 395
 396         ret = get_tce_emu(tcet, ioba, &tce);
 397         if (!ret) {
 398             args[0] = tce;
 399         }
 400     }
 401     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 402         trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
 403     } else {
 404         trace_spapr_iommu_get(liobn, ioba, ret, tce);
 405     }
 406
 407     return ret;
 408 }
 409
 410 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 411                  uint32_t liobn, uint64_t window, uint32_t size)
 412 {
 413     uint32_t dma_prop[5];
 414     int ret;
 415
 416     dma_prop[0] = cpu_to_be32(liobn);
 417     dma_prop[1] = cpu_to_be32(window >> 32);
 418     dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
 419     dma_prop[3] = 0; /* window size is 32 bits */
 420     dma_prop[4] = cpu_to_be32(size);
 421
 422     ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
 423     if (ret < 0) {
 424         return ret;
 425     }
 426
 427     ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
 428     if (ret < 0) {
 429         return ret;
 430     }
 431
 432     ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
 433     if (ret < 0) {
 434         return ret;
 435     }
 436
 437     return 0;
 438 }
 439
 440 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 441                       sPAPRTCETable *tcet)
 442 {
 443     if (!tcet) {
 444         return 0;
 445     }
 446
 447     return spapr_dma_dt(fdt, node_off, propname,
 448                         tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
 449 }
 450
 451 static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
 452 {
 453     DeviceClass *dc = DEVICE_CLASS(klass);
 454     dc->init = spapr_tce_table_realize;
 455     dc->reset = spapr_tce_reset;
 456     dc->unrealize = spapr_tce_table_unrealize;
 457
 458     QLIST_INIT(&spapr_tce_tables);
 459
 460     /* hcall-tce */
 461     spapr_register_hypercall(H_PUT_TCE, h_put_tce);
 462     spapr_register_hypercall(H_GET_TCE, h_get_tce);
 463     spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
 464     spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
 465 }
 466
 467 static TypeInfo spapr_tce_table_info = {
 468     .name = TYPE_SPAPR_TCE_TABLE,
 469     .parent = TYPE_DEVICE,
 470     .instance_size = sizeof(sPAPRTCETable),
 471     .class_init = spapr_tce_table_class_init,
 472 };
 473
 474 static void register_types(void)
 475 {
 476     type_register_static(&spapr_tce_table_info);
 477 }
 478
 479 type_init(register_types);