scsi: pvscsi: limit process IO loop to ring size
[qemu/ar7.git] / hw / nvram / spapr_nvram.c
blob4de5f705d8e129cba9bc803400e2021d4f19b6d8
1 /*
2 * QEMU sPAPR NVRAM emulation
4 * Copyright (C) 2012 David Gibson, IBM Corporation.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include <libfdt.h>
31 #include "sysemu/block-backend.h"
32 #include "sysemu/device_tree.h"
33 #include "hw/sysbus.h"
34 #include "hw/ppc/spapr.h"
35 #include "hw/ppc/spapr_vio.h"
37 typedef struct sPAPRNVRAM {
38 VIOsPAPRDevice sdev;
39 uint32_t size;
40 uint8_t *buf;
41 BlockBackend *blk;
42 VMChangeStateEntry *vmstate;
43 } sPAPRNVRAM;
45 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
46 #define VIO_SPAPR_NVRAM(obj) \
47 OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM)
49 #define MIN_NVRAM_SIZE 8192
50 #define DEFAULT_NVRAM_SIZE 65536
51 #define MAX_NVRAM_SIZE 1048576
53 static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr,
54 uint32_t token, uint32_t nargs,
55 target_ulong args,
56 uint32_t nret, target_ulong rets)
58 sPAPRNVRAM *nvram = spapr->nvram;
59 hwaddr offset, buffer, len;
60 void *membuf;
62 if ((nargs != 3) || (nret != 2)) {
63 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
64 return;
67 if (!nvram) {
68 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
69 rtas_st(rets, 1, 0);
70 return;
73 offset = rtas_ld(args, 0);
74 buffer = rtas_ld(args, 1);
75 len = rtas_ld(args, 2);
77 if (((offset + len) < offset)
78 || ((offset + len) > nvram->size)) {
79 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
80 rtas_st(rets, 1, 0);
81 return;
84 assert(nvram->buf);
86 membuf = cpu_physical_memory_map(buffer, &len, 1);
87 memcpy(membuf, nvram->buf + offset, len);
88 cpu_physical_memory_unmap(membuf, len, 1, len);
90 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
91 rtas_st(rets, 1, len);
94 static void rtas_nvram_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
95 uint32_t token, uint32_t nargs,
96 target_ulong args,
97 uint32_t nret, target_ulong rets)
99 sPAPRNVRAM *nvram = spapr->nvram;
100 hwaddr offset, buffer, len;
101 int alen;
102 void *membuf;
104 if ((nargs != 3) || (nret != 2)) {
105 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
106 return;
109 if (!nvram) {
110 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
111 return;
114 offset = rtas_ld(args, 0);
115 buffer = rtas_ld(args, 1);
116 len = rtas_ld(args, 2);
118 if (((offset + len) < offset)
119 || ((offset + len) > nvram->size)) {
120 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
121 return;
124 membuf = cpu_physical_memory_map(buffer, &len, 0);
126 alen = len;
127 if (nvram->blk) {
128 alen = blk_pwrite(nvram->blk, offset, membuf, len, 0);
131 assert(nvram->buf);
132 memcpy(nvram->buf + offset, membuf, len);
134 cpu_physical_memory_unmap(membuf, len, 0, len);
136 rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS);
137 rtas_st(rets, 1, (alen < 0) ? 0 : alen);
140 static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp)
142 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
144 if (nvram->blk) {
145 nvram->size = blk_getlength(nvram->blk);
146 } else {
147 nvram->size = DEFAULT_NVRAM_SIZE;
150 nvram->buf = g_malloc0(nvram->size);
152 if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
153 error_setg(errp, "spapr-nvram must be between %d and %d bytes in size",
154 MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
155 return;
158 if (nvram->blk) {
159 int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size);
161 if (alen != nvram->size) {
162 error_setg(errp, "can't read spapr-nvram contents");
163 return;
167 spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch);
168 spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store);
171 static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
173 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev);
175 return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
178 static int spapr_nvram_pre_load(void *opaque)
180 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
182 g_free(nvram->buf);
183 nvram->buf = NULL;
184 nvram->size = 0;
186 return 0;
189 static void postload_update_cb(void *opaque, int running, RunState state)
191 sPAPRNVRAM *nvram = opaque;
193 /* This is called after bdrv_invalidate_cache_all. */
195 qemu_del_vm_change_state_handler(nvram->vmstate);
196 nvram->vmstate = NULL;
198 blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0);
201 static int spapr_nvram_post_load(void *opaque, int version_id)
203 sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque);
205 if (nvram->blk) {
206 nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
207 nvram);
210 return 0;
213 static const VMStateDescription vmstate_spapr_nvram = {
214 .name = "spapr_nvram",
215 .version_id = 1,
216 .minimum_version_id = 1,
217 .pre_load = spapr_nvram_pre_load,
218 .post_load = spapr_nvram_post_load,
219 .fields = (VMStateField[]) {
220 VMSTATE_UINT32(size, sPAPRNVRAM),
221 VMSTATE_VBUFFER_ALLOC_UINT32(buf, sPAPRNVRAM, 1, NULL, 0, size),
222 VMSTATE_END_OF_LIST()
226 static Property spapr_nvram_properties[] = {
227 DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev),
228 DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, blk),
229 DEFINE_PROP_END_OF_LIST(),
232 static void spapr_nvram_class_init(ObjectClass *klass, void *data)
234 DeviceClass *dc = DEVICE_CLASS(klass);
235 VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
237 k->realize = spapr_nvram_realize;
238 k->devnode = spapr_nvram_devnode;
239 k->dt_name = "nvram";
240 k->dt_type = "nvram";
241 k->dt_compatible = "qemu,spapr-nvram";
242 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
243 dc->props = spapr_nvram_properties;
244 dc->vmsd = &vmstate_spapr_nvram;
247 static const TypeInfo spapr_nvram_type_info = {
248 .name = TYPE_VIO_SPAPR_NVRAM,
249 .parent = TYPE_VIO_SPAPR_DEVICE,
250 .instance_size = sizeof(sPAPRNVRAM),
251 .class_init = spapr_nvram_class_init,
254 static void spapr_nvram_register_types(void)
256 type_register_static(&spapr_nvram_type_info);
259 type_init(spapr_nvram_register_types)