target-mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23
  24
  25 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  26 {
  27     MIPSCPU *cpu = MIPS_CPU(cs);
  28     CPUMIPSState *env = &cpu->env;
  29
  30     env->active_tc.PC = value & ~(target_ulong)1;
  31     if (value & 1) {
  32         env->hflags |= MIPS_HFLAG_M16;
  33     } else {
  34         env->hflags &= ~(MIPS_HFLAG_M16);
  35     }
  36 }
  37
  38 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  39 {
  40     MIPSCPU *cpu = MIPS_CPU(cs);
  41     CPUMIPSState *env = &cpu->env;
  42
  43     env->active_tc.PC = tb->pc;
  44     env->hflags &= ~MIPS_HFLAG_BMASK;
  45     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  46 }
  47
  48 /* CPUClass::reset() */
  49 static void mips_cpu_reset(CPUState *s)
  50 {
  51     MIPSCPU *cpu = MIPS_CPU(s);
  52     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  53     CPUMIPSState *env = &cpu->env;
  54
  55     mcc->parent_reset(s);
  56
  57     memset(env, 0, offsetof(CPUMIPSState, breakpoints));
  58     tlb_flush(env, 1);
  59
  60     cpu_state_reset(env);
  61 }
  62
  63 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
  64 {
  65     CPUState *cs = CPU(dev);
  66     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
  67
  68     cpu_reset(cs);
  69     qemu_init_vcpu(cs);
  70
  71     mcc->parent_realize(dev, errp);
  72 }
  73
  74 static void mips_cpu_initfn(Object *obj)
  75 {
  76     CPUState *cs = CPU(obj);
  77     MIPSCPU *cpu = MIPS_CPU(obj);
  78     CPUMIPSState *env = &cpu->env;
  79
  80     cs->env_ptr = env;
  81     cpu_exec_init(env);
  82
  83     if (tcg_enabled()) {
  84         mips_tcg_init();
  85     }
  86 }
  87
  88 static void mips_cpu_class_init(ObjectClass *c, void *data)
  89 {
  90     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
  91     CPUClass *cc = CPU_CLASS(c);
  92     DeviceClass *dc = DEVICE_CLASS(c);
  93
  94     mcc->parent_realize = dc->realize;
  95     dc->realize = mips_cpu_realizefn;
  96
  97     mcc->parent_reset = cc->reset;
  98     cc->reset = mips_cpu_reset;
  99
 100     cc->do_interrupt = mips_cpu_do_interrupt;
 101     cc->dump_state = mips_cpu_dump_state;
 102     cc->set_pc = mips_cpu_set_pc;
 103     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 104     cc->gdb_read_register = mips_cpu_gdb_read_register;
 105     cc->gdb_write_register = mips_cpu_gdb_write_register;
 106 #ifndef CONFIG_USER_ONLY
 107     cc->do_unassigned_access = mips_cpu_unassigned_access;
 108     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 109 #endif
 110
 111     cc->gdb_num_core_regs = 73;
 112 }
 113
 114 static const TypeInfo mips_cpu_type_info = {
 115     .name = TYPE_MIPS_CPU,
 116     .parent = TYPE_CPU,
 117     .instance_size = sizeof(MIPSCPU),
 118     .instance_init = mips_cpu_initfn,
 119     .abstract = false,
 120     .class_size = sizeof(MIPSCPUClass),
 121     .class_init = mips_cpu_class_init,
 122 };
 123
 124 static void mips_cpu_register_types(void)
 125 {
 126     type_register_static(&mips_cpu_type_info);
 127 }
 128
 129 type_init(mips_cpu_register_types)