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qemu-ga: qmp_guest_shutdown(): improve error reporting
[qemu/ar7.git] / target-i386 / cpu.c
blob78bd61e18fdd481e449ac80e309f00a3dbb34521
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi/visitor.h"
32 #include "sysemu/arch_init.h"
33
34 #include "hyperv.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #ifndef CONFIG_USER_ONLY
43 #include "hw/xen.h"
44 #include "hw/sysbus.h"
45 #include "hw/apic_internal.h"
46 #endif
47
48 /* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52 static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61 };
62 static const char *ext_feature_name[] = {
63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
64 "ds_cpl", "vmx", "smx", "est",
65 "tm2", "ssse3", "cid", NULL,
66 "fma", "cx16", "xtpr", "pdcm",
67 NULL, "pcid", "dca", "sse4.1|sse4_1",
68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
69 "tsc-deadline", "aes", "xsave", "osxsave",
70 "avx", "f16c", "rdrand", "hypervisor",
71 };
72 /* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
77 static const char *ext2_feature_name[] = {
78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
85 NULL, "lm|i64", "3dnowext", "3dnow",
86 };
87 static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
90 "3dnowprefetch", "osvw", "ibs", "xop",
91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 };
97
98 static const char *kvm_feature_name[] = {
99 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
100 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
101 NULL, NULL, NULL, NULL,
102 NULL, NULL, NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 };
108
109 static const char *svm_feature_name[] = {
110 "npt", "lbrv", "svm_lock", "nrip_save",
111 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
112 NULL, NULL, "pause_filter", NULL,
113 "pfthreshold", NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 };
119
120 static const char *cpuid_7_0_ebx_feature_name[] = {
121 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
122 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
123 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
124 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
125 };
126
127 const char *get_register_name_32(unsigned int reg)
128 {
129 static const char *reg_names[CPU_NB_REGS32] = {
130 [R_EAX] = "EAX",
131 [R_ECX] = "ECX",
132 [R_EDX] = "EDX",
133 [R_EBX] = "EBX",
134 [R_ESP] = "ESP",
135 [R_EBP] = "EBP",
136 [R_ESI] = "ESI",
137 [R_EDI] = "EDI",
138 };
139
140 if (reg > CPU_NB_REGS32) {
141 return NULL;
142 }
143 return reg_names[reg];
144 }
145
146 /* collects per-function cpuid data
147 */
148 typedef struct model_features_t {
149 uint32_t *guest_feat;
150 uint32_t *host_feat;
151 const char **flag_names;
152 uint32_t cpuid;
153 int reg;
154 } model_features_t;
155
156 int check_cpuid = 0;
157 int enforce_cpuid = 0;
158
159 #if defined(CONFIG_KVM)
160 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
161 (1 << KVM_FEATURE_NOP_IO_DELAY) |
162 (1 << KVM_FEATURE_MMU_OP) |
163 (1 << KVM_FEATURE_CLOCKSOURCE2) |
164 (1 << KVM_FEATURE_ASYNC_PF) |
165 (1 << KVM_FEATURE_STEAL_TIME) |
166 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
167 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
168 #else
169 static uint32_t kvm_default_features = 0;
170 static const uint32_t kvm_pv_eoi_features = 0;
171 #endif
172
173 void enable_kvm_pv_eoi(void)
174 {
175 kvm_default_features |= kvm_pv_eoi_features;
176 }
177
178 void host_cpuid(uint32_t function, uint32_t count,
179 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
180 {
181 #if defined(CONFIG_KVM)
182 uint32_t vec[4];
183
184 #ifdef __x86_64__
185 asm volatile("cpuid"
186 : "=a"(vec[0]), "=b"(vec[1]),
187 "=c"(vec[2]), "=d"(vec[3])
188 : "0"(function), "c"(count) : "cc");
189 #else
190 asm volatile("pusha \n\t"
191 "cpuid \n\t"
192 "mov %%eax, 0(%2) \n\t"
193 "mov %%ebx, 4(%2) \n\t"
194 "mov %%ecx, 8(%2) \n\t"
195 "mov %%edx, 12(%2) \n\t"
196 "popa"
197 : : "a"(function), "c"(count), "S"(vec)
198 : "memory", "cc");
199 #endif
200
201 if (eax)
202 *eax = vec[0];
203 if (ebx)
204 *ebx = vec[1];
205 if (ecx)
206 *ecx = vec[2];
207 if (edx)
208 *edx = vec[3];
209 #endif
210 }
211
212 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
213
214 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
215 * a substring. ex if !NULL points to the first char after a substring,
216 * otherwise the string is assumed to sized by a terminating nul.
217 * Return lexical ordering of *s1:*s2.
218 */
219 static int sstrcmp(const char *s1, const char *e1, const char *s2,
220 const char *e2)
221 {
222 for (;;) {
223 if (!*s1 || !*s2 || *s1 != *s2)
224 return (*s1 - *s2);
225 ++s1, ++s2;
226 if (s1 == e1 && s2 == e2)
227 return (0);
228 else if (s1 == e1)
229 return (*s2);
230 else if (s2 == e2)
231 return (*s1);
232 }
233 }
234
235 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
236 * '|' delimited (possibly empty) strings in which case search for a match
237 * within the alternatives proceeds left to right. Return 0 for success,
238 * non-zero otherwise.
239 */
240 static int altcmp(const char *s, const char *e, const char *altstr)
241 {
242 const char *p, *q;
243
244 for (q = p = altstr; ; ) {
245 while (*p && *p != '|')
246 ++p;
247 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
248 return (0);
249 if (!*p)
250 return (1);
251 else
252 q = ++p;
253 }
254 }
255
256 /* search featureset for flag *[s..e), if found set corresponding bit in
257 * *pval and return true, otherwise return false
258 */
259 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
260 const char **featureset)
261 {
262 uint32_t mask;
263 const char **ppc;
264 bool found = false;
265
266 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
267 if (*ppc && !altcmp(s, e, *ppc)) {
268 *pval |= mask;
269 found = true;
270 }
271 }
272 return found;
273 }
274
275 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
276 uint32_t *ext_features,
277 uint32_t *ext2_features,
278 uint32_t *ext3_features,
279 uint32_t *kvm_features,
280 uint32_t *svm_features,
281 uint32_t *cpuid_7_0_ebx_features)
282 {
283 if (!lookup_feature(features, flagname, NULL, feature_name) &&
284 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
285 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
286 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
287 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
288 !lookup_feature(svm_features, flagname, NULL, svm_feature_name) &&
289 !lookup_feature(cpuid_7_0_ebx_features, flagname, NULL,
290 cpuid_7_0_ebx_feature_name))
291 fprintf(stderr, "CPU feature %s not found\n", flagname);
292 }
293
294 typedef struct x86_def_t {
295 struct x86_def_t *next;
296 const char *name;
297 uint32_t level;
298 uint32_t vendor1, vendor2, vendor3;
299 int family;
300 int model;
301 int stepping;
302 int tsc_khz;
303 uint32_t features, ext_features, ext2_features, ext3_features;
304 uint32_t kvm_features, svm_features;
305 uint32_t xlevel;
306 char model_id[48];
307 int vendor_override;
308 /* Store the results of Centaur's CPUID instructions */
309 uint32_t ext4_features;
310 uint32_t xlevel2;
311 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
312 uint32_t cpuid_7_0_ebx_features;
313 } x86_def_t;
314
315 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
316 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
317 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
318 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
319 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
320 CPUID_PSE36 | CPUID_FXSR)
321 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
322 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
323 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
324 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
325 CPUID_PAE | CPUID_SEP | CPUID_APIC)
326
327 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
328 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
329 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
330 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
331 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
332 /* partly implemented:
333 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
334 CPUID_PSE36 (needed for Solaris) */
335 /* missing:
336 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
337 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
338 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
339 CPUID_EXT_HYPERVISOR)
340 /* missing:
341 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
342 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
343 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
344 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
345 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
346 /* missing:
347 CPUID_EXT2_PDPE1GB */
348 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
349 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
350 #define TCG_SVM_FEATURES 0
351 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
352
353 /* maintains list of cpu model definitions
354 */
355 static x86_def_t *x86_defs = {NULL};
356
357 /* built-in cpu model definitions (deprecated)
358 */
359 static x86_def_t builtin_x86_defs[] = {
360 {
361 .name = "qemu64",
362 .level = 4,
363 .vendor1 = CPUID_VENDOR_AMD_1,
364 .vendor2 = CPUID_VENDOR_AMD_2,
365 .vendor3 = CPUID_VENDOR_AMD_3,
366 .family = 6,
367 .model = 2,
368 .stepping = 3,
369 .features = PPRO_FEATURES |
370 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
371 CPUID_PSE36,
372 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
373 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
374 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
375 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
376 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
377 .xlevel = 0x8000000A,
378 },
379 {
380 .name = "phenom",
381 .level = 5,
382 .vendor1 = CPUID_VENDOR_AMD_1,
383 .vendor2 = CPUID_VENDOR_AMD_2,
384 .vendor3 = CPUID_VENDOR_AMD_3,
385 .family = 16,
386 .model = 2,
387 .stepping = 3,
388 .features = PPRO_FEATURES |
389 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
390 CPUID_PSE36 | CPUID_VME | CPUID_HT,
391 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
392 CPUID_EXT_POPCNT,
393 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
394 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
395 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
396 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
397 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
398 CPUID_EXT3_CR8LEG,
399 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
400 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
401 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
402 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
403 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
404 .xlevel = 0x8000001A,
405 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
406 },
407 {
408 .name = "core2duo",
409 .level = 10,
410 .vendor1 = CPUID_VENDOR_INTEL_1,
411 .vendor2 = CPUID_VENDOR_INTEL_2,
412 .vendor3 = CPUID_VENDOR_INTEL_3,
413 .family = 6,
414 .model = 15,
415 .stepping = 11,
416 .features = PPRO_FEATURES |
417 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
418 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
419 CPUID_HT | CPUID_TM | CPUID_PBE,
420 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
421 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
422 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
423 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
424 .ext3_features = CPUID_EXT3_LAHF_LM,
425 .xlevel = 0x80000008,
426 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
427 },
428 {
429 .name = "kvm64",
430 .level = 5,
431 .vendor1 = CPUID_VENDOR_INTEL_1,
432 .vendor2 = CPUID_VENDOR_INTEL_2,
433 .vendor3 = CPUID_VENDOR_INTEL_3,
434 .family = 15,
435 .model = 6,
436 .stepping = 1,
437 /* Missing: CPUID_VME, CPUID_HT */
438 .features = PPRO_FEATURES |
439 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
440 CPUID_PSE36,
441 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
442 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
443 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
444 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
445 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
446 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
447 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
448 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
449 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
450 .ext3_features = 0,
451 .xlevel = 0x80000008,
452 .model_id = "Common KVM processor"
453 },
454 {
455 .name = "qemu32",
456 .level = 4,
457 .vendor1 = CPUID_VENDOR_INTEL_1,
458 .vendor2 = CPUID_VENDOR_INTEL_2,
459 .vendor3 = CPUID_VENDOR_INTEL_3,
460 .family = 6,
461 .model = 3,
462 .stepping = 3,
463 .features = PPRO_FEATURES,
464 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
465 .xlevel = 0x80000004,
466 },
467 {
468 .name = "kvm32",
469 .level = 5,
470 .vendor1 = CPUID_VENDOR_INTEL_1,
471 .vendor2 = CPUID_VENDOR_INTEL_2,
472 .vendor3 = CPUID_VENDOR_INTEL_3,
473 .family = 15,
474 .model = 6,
475 .stepping = 1,
476 .features = PPRO_FEATURES |
477 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
478 .ext_features = CPUID_EXT_SSE3,
479 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
480 .ext3_features = 0,
481 .xlevel = 0x80000008,
482 .model_id = "Common 32-bit KVM processor"
483 },
484 {
485 .name = "coreduo",
486 .level = 10,
487 .vendor1 = CPUID_VENDOR_INTEL_1,
488 .vendor2 = CPUID_VENDOR_INTEL_2,
489 .vendor3 = CPUID_VENDOR_INTEL_3,
490 .family = 6,
491 .model = 14,
492 .stepping = 8,
493 .features = PPRO_FEATURES | CPUID_VME |
494 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
495 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
496 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
497 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
498 .ext2_features = CPUID_EXT2_NX,
499 .xlevel = 0x80000008,
500 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
501 },
502 {
503 .name = "486",
504 .level = 1,
505 .vendor1 = CPUID_VENDOR_INTEL_1,
506 .vendor2 = CPUID_VENDOR_INTEL_2,
507 .vendor3 = CPUID_VENDOR_INTEL_3,
508 .family = 4,
509 .model = 0,
510 .stepping = 0,
511 .features = I486_FEATURES,
512 .xlevel = 0,
513 },
514 {
515 .name = "pentium",
516 .level = 1,
517 .vendor1 = CPUID_VENDOR_INTEL_1,
518 .vendor2 = CPUID_VENDOR_INTEL_2,
519 .vendor3 = CPUID_VENDOR_INTEL_3,
520 .family = 5,
521 .model = 4,
522 .stepping = 3,
523 .features = PENTIUM_FEATURES,
524 .xlevel = 0,
525 },
526 {
527 .name = "pentium2",
528 .level = 2,
529 .vendor1 = CPUID_VENDOR_INTEL_1,
530 .vendor2 = CPUID_VENDOR_INTEL_2,
531 .vendor3 = CPUID_VENDOR_INTEL_3,
532 .family = 6,
533 .model = 5,
534 .stepping = 2,
535 .features = PENTIUM2_FEATURES,
536 .xlevel = 0,
537 },
538 {
539 .name = "pentium3",
540 .level = 2,
541 .vendor1 = CPUID_VENDOR_INTEL_1,
542 .vendor2 = CPUID_VENDOR_INTEL_2,
543 .vendor3 = CPUID_VENDOR_INTEL_3,
544 .family = 6,
545 .model = 7,
546 .stepping = 3,
547 .features = PENTIUM3_FEATURES,
548 .xlevel = 0,
549 },
550 {
551 .name = "athlon",
552 .level = 2,
553 .vendor1 = CPUID_VENDOR_AMD_1,
554 .vendor2 = CPUID_VENDOR_AMD_2,
555 .vendor3 = CPUID_VENDOR_AMD_3,
556 .family = 6,
557 .model = 2,
558 .stepping = 3,
559 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
560 CPUID_MCA,
561 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
562 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
563 .xlevel = 0x80000008,
564 },
565 {
566 .name = "n270",
567 /* original is on level 10 */
568 .level = 5,
569 .vendor1 = CPUID_VENDOR_INTEL_1,
570 .vendor2 = CPUID_VENDOR_INTEL_2,
571 .vendor3 = CPUID_VENDOR_INTEL_3,
572 .family = 6,
573 .model = 28,
574 .stepping = 2,
575 .features = PPRO_FEATURES |
576 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
577 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
578 /* Some CPUs got no CPUID_SEP */
579 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
580 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
581 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
582 CPUID_EXT2_NX,
583 .ext3_features = CPUID_EXT3_LAHF_LM,
584 .xlevel = 0x8000000A,
585 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
586 },
587 {
588 .name = "Conroe",
589 .level = 2,
590 .vendor1 = CPUID_VENDOR_INTEL_1,
591 .vendor2 = CPUID_VENDOR_INTEL_2,
592 .vendor3 = CPUID_VENDOR_INTEL_3,
593 .family = 6,
594 .model = 2,
595 .stepping = 3,
596 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
597 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
598 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
599 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
600 CPUID_DE | CPUID_FP87,
601 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
602 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
603 .ext3_features = CPUID_EXT3_LAHF_LM,
604 .xlevel = 0x8000000A,
605 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
606 },
607 {
608 .name = "Penryn",
609 .level = 2,
610 .vendor1 = CPUID_VENDOR_INTEL_1,
611 .vendor2 = CPUID_VENDOR_INTEL_2,
612 .vendor3 = CPUID_VENDOR_INTEL_3,
613 .family = 6,
614 .model = 2,
615 .stepping = 3,
616 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
617 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
618 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
619 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
620 CPUID_DE | CPUID_FP87,
621 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
622 CPUID_EXT_SSE3,
623 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
624 .ext3_features = CPUID_EXT3_LAHF_LM,
625 .xlevel = 0x8000000A,
626 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
627 },
628 {
629 .name = "Nehalem",
630 .level = 2,
631 .vendor1 = CPUID_VENDOR_INTEL_1,
632 .vendor2 = CPUID_VENDOR_INTEL_2,
633 .vendor3 = CPUID_VENDOR_INTEL_3,
634 .family = 6,
635 .model = 2,
636 .stepping = 3,
637 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
638 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
639 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
640 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
641 CPUID_DE | CPUID_FP87,
642 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
643 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
644 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
645 .ext3_features = CPUID_EXT3_LAHF_LM,
646 .xlevel = 0x8000000A,
647 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
648 },
649 {
650 .name = "Westmere",
651 .level = 11,
652 .vendor1 = CPUID_VENDOR_INTEL_1,
653 .vendor2 = CPUID_VENDOR_INTEL_2,
654 .vendor3 = CPUID_VENDOR_INTEL_3,
655 .family = 6,
656 .model = 44,
657 .stepping = 1,
658 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
662 CPUID_DE | CPUID_FP87,
663 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
664 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
665 CPUID_EXT_SSE3,
666 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
667 .ext3_features = CPUID_EXT3_LAHF_LM,
668 .xlevel = 0x8000000A,
669 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
670 },
671 {
672 .name = "SandyBridge",
673 .level = 0xd,
674 .vendor1 = CPUID_VENDOR_INTEL_1,
675 .vendor2 = CPUID_VENDOR_INTEL_2,
676 .vendor3 = CPUID_VENDOR_INTEL_3,
677 .family = 6,
678 .model = 42,
679 .stepping = 1,
680 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
681 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
682 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
683 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
684 CPUID_DE | CPUID_FP87,
685 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
686 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
687 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
688 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
689 CPUID_EXT_SSE3,
690 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
691 CPUID_EXT2_SYSCALL,
692 .ext3_features = CPUID_EXT3_LAHF_LM,
693 .xlevel = 0x8000000A,
694 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
695 },
696 {
697 .name = "Haswell",
698 .level = 0xd,
699 .vendor1 = CPUID_VENDOR_INTEL_1,
700 .vendor2 = CPUID_VENDOR_INTEL_2,
701 .vendor3 = CPUID_VENDOR_INTEL_3,
702 .family = 6,
703 .model = 60,
704 .stepping = 1,
705 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
706 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
707 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
708 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
709 CPUID_DE | CPUID_FP87,
710 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
711 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
712 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
713 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
714 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
715 CPUID_EXT_PCID,
716 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
717 CPUID_EXT2_SYSCALL,
718 .ext3_features = CPUID_EXT3_LAHF_LM,
719 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
720 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
721 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
722 CPUID_7_0_EBX_RTM,
723 .xlevel = 0x8000000A,
724 .model_id = "Intel Core Processor (Haswell)",
725 },
726 {
727 .name = "Opteron_G1",
728 .level = 5,
729 .vendor1 = CPUID_VENDOR_AMD_1,
730 .vendor2 = CPUID_VENDOR_AMD_2,
731 .vendor3 = CPUID_VENDOR_AMD_3,
732 .family = 15,
733 .model = 6,
734 .stepping = 1,
735 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
736 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
737 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
738 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
739 CPUID_DE | CPUID_FP87,
740 .ext_features = CPUID_EXT_SSE3,
741 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
742 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
743 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
744 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
745 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
746 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
747 .xlevel = 0x80000008,
748 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
749 },
750 {
751 .name = "Opteron_G2",
752 .level = 5,
753 .vendor1 = CPUID_VENDOR_AMD_1,
754 .vendor2 = CPUID_VENDOR_AMD_2,
755 .vendor3 = CPUID_VENDOR_AMD_3,
756 .family = 15,
757 .model = 6,
758 .stepping = 1,
759 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
760 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
761 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
762 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
763 CPUID_DE | CPUID_FP87,
764 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
765 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
766 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
767 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
768 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
769 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
770 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
771 CPUID_EXT2_DE | CPUID_EXT2_FPU,
772 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
773 .xlevel = 0x80000008,
774 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
775 },
776 {
777 .name = "Opteron_G3",
778 .level = 5,
779 .vendor1 = CPUID_VENDOR_AMD_1,
780 .vendor2 = CPUID_VENDOR_AMD_2,
781 .vendor3 = CPUID_VENDOR_AMD_3,
782 .family = 15,
783 .model = 6,
784 .stepping = 1,
785 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
786 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
787 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
788 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
789 CPUID_DE | CPUID_FP87,
790 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
791 CPUID_EXT_SSE3,
792 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
793 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
794 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
795 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
796 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
797 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
798 CPUID_EXT2_DE | CPUID_EXT2_FPU,
799 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
800 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
801 .xlevel = 0x80000008,
802 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
803 },
804 {
805 .name = "Opteron_G4",
806 .level = 0xd,
807 .vendor1 = CPUID_VENDOR_AMD_1,
808 .vendor2 = CPUID_VENDOR_AMD_2,
809 .vendor3 = CPUID_VENDOR_AMD_3,
810 .family = 21,
811 .model = 1,
812 .stepping = 2,
813 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
814 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
815 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
816 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
817 CPUID_DE | CPUID_FP87,
818 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
819 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
820 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
821 CPUID_EXT_SSE3,
822 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
823 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
824 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
825 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
826 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
827 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
828 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
829 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
830 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
831 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
832 CPUID_EXT3_LAHF_LM,
833 .xlevel = 0x8000001A,
834 .model_id = "AMD Opteron 62xx class CPU",
835 },
836 {
837 .name = "Opteron_G5",
838 .level = 0xd,
839 .vendor1 = CPUID_VENDOR_AMD_1,
840 .vendor2 = CPUID_VENDOR_AMD_2,
841 .vendor3 = CPUID_VENDOR_AMD_3,
842 .family = 21,
843 .model = 2,
844 .stepping = 0,
845 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
846 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
847 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
848 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
849 CPUID_DE | CPUID_FP87,
850 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
851 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
852 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
853 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
854 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
855 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
856 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
857 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
858 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
859 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
860 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
861 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
862 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
863 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
864 CPUID_EXT3_LAHF_LM,
865 .xlevel = 0x8000001A,
866 .model_id = "AMD Opteron 63xx class CPU",
867 },
868 };
869
870 #ifdef CONFIG_KVM
871 static int cpu_x86_fill_model_id(char *str)
872 {
873 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
874 int i;
875
876 for (i = 0; i < 3; i++) {
877 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
878 memcpy(str + i * 16 + 0, &eax, 4);
879 memcpy(str + i * 16 + 4, &ebx, 4);
880 memcpy(str + i * 16 + 8, &ecx, 4);
881 memcpy(str + i * 16 + 12, &edx, 4);
882 }
883 return 0;
884 }
885 #endif
886
887 /* Fill a x86_def_t struct with information about the host CPU, and
888 * the CPU features supported by the host hardware + host kernel
889 *
890 * This function may be called only if KVM is enabled.
891 */
892 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
893 {
894 #ifdef CONFIG_KVM
895 KVMState *s = kvm_state;
896 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
897
898 assert(kvm_enabled());
899
900 x86_cpu_def->name = "host";
901 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
902 x86_cpu_def->vendor1 = ebx;
903 x86_cpu_def->vendor2 = edx;
904 x86_cpu_def->vendor3 = ecx;
905
906 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
907 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
908 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
909 x86_cpu_def->stepping = eax & 0x0F;
910
911 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
912 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
913 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
914
915 if (x86_cpu_def->level >= 7) {
916 x86_cpu_def->cpuid_7_0_ebx_features =
917 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
918 } else {
919 x86_cpu_def->cpuid_7_0_ebx_features = 0;
920 }
921
922 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
923 x86_cpu_def->ext2_features =
924 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
925 x86_cpu_def->ext3_features =
926 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
927
928 cpu_x86_fill_model_id(x86_cpu_def->model_id);
929 x86_cpu_def->vendor_override = 0;
930
931 /* Call Centaur's CPUID instruction. */
932 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
933 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
934 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
935 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
936 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
937 if (eax >= 0xC0000001) {
938 /* Support VIA max extended level */
939 x86_cpu_def->xlevel2 = eax;
940 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
941 x86_cpu_def->ext4_features =
942 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
943 }
944 }
945
946 /* Other KVM-specific feature fields: */
947 x86_cpu_def->svm_features =
948 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
949 x86_cpu_def->kvm_features =
950 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
951
952 #endif /* CONFIG_KVM */
953 }
954
955 static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
956 {
957 int i;
958
959 for (i = 0; i < 32; ++i)
960 if (1 << i & mask) {
961 const char *reg = get_register_name_32(f->reg);
962 assert(reg);
963 fprintf(stderr, "warning: host doesn't support requested feature: "
964 "CPUID.%02XH:%s%s%s [bit %d]\n",
965 f->cpuid, reg,
966 f->flag_names[i] ? "." : "",
967 f->flag_names[i] ? f->flag_names[i] : "", i);
968 break;
969 }
970 return 0;
971 }
972
973 /* best effort attempt to inform user requested cpu flags aren't making
974 * their way to the guest.
975 *
976 * This function may be called only if KVM is enabled.
977 */
978 static int kvm_check_features_against_host(x86_def_t *guest_def)
979 {
980 x86_def_t host_def;
981 uint32_t mask;
982 int rv, i;
983 struct model_features_t ft[] = {
984 {&guest_def->features, &host_def.features,
985 feature_name, 0x00000001, R_EDX},
986 {&guest_def->ext_features, &host_def.ext_features,
987 ext_feature_name, 0x00000001, R_ECX},
988 {&guest_def->ext2_features, &host_def.ext2_features,
989 ext2_feature_name, 0x80000001, R_EDX},
990 {&guest_def->ext3_features, &host_def.ext3_features,
991 ext3_feature_name, 0x80000001, R_ECX}
992 };
993
994 assert(kvm_enabled());
995
996 kvm_cpu_fill_host(&host_def);
997 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
998 for (mask = 1; mask; mask <<= 1)
999 if (*ft[i].guest_feat & mask &&
1000 !(*ft[i].host_feat & mask)) {
1001 unavailable_host_feature(&ft[i], mask);
1002 rv = 1;
1003 }
1004 return rv;
1005 }
1006
1007 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1008 const char *name, Error **errp)
1009 {
1010 X86CPU *cpu = X86_CPU(obj);
1011 CPUX86State *env = &cpu->env;
1012 int64_t value;
1013
1014 value = (env->cpuid_version >> 8) & 0xf;
1015 if (value == 0xf) {
1016 value += (env->cpuid_version >> 20) & 0xff;
1017 }
1018 visit_type_int(v, &value, name, errp);
1019 }
1020
1021 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1022 const char *name, Error **errp)
1023 {
1024 X86CPU *cpu = X86_CPU(obj);
1025 CPUX86State *env = &cpu->env;
1026 const int64_t min = 0;
1027 const int64_t max = 0xff + 0xf;
1028 int64_t value;
1029
1030 visit_type_int(v, &value, name, errp);
1031 if (error_is_set(errp)) {
1032 return;
1033 }
1034 if (value < min || value > max) {
1035 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1036 name ? name : "null", value, min, max);
1037 return;
1038 }
1039
1040 env->cpuid_version &= ~0xff00f00;
1041 if (value > 0x0f) {
1042 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1043 } else {
1044 env->cpuid_version |= value << 8;
1045 }
1046 }
1047
1048 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1049 const char *name, Error **errp)
1050 {
1051 X86CPU *cpu = X86_CPU(obj);
1052 CPUX86State *env = &cpu->env;
1053 int64_t value;
1054
1055 value = (env->cpuid_version >> 4) & 0xf;
1056 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1057 visit_type_int(v, &value, name, errp);
1058 }
1059
1060 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1061 const char *name, Error **errp)
1062 {
1063 X86CPU *cpu = X86_CPU(obj);
1064 CPUX86State *env = &cpu->env;
1065 const int64_t min = 0;
1066 const int64_t max = 0xff;
1067 int64_t value;
1068
1069 visit_type_int(v, &value, name, errp);
1070 if (error_is_set(errp)) {
1071 return;
1072 }
1073 if (value < min || value > max) {
1074 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1075 name ? name : "null", value, min, max);
1076 return;
1077 }
1078
1079 env->cpuid_version &= ~0xf00f0;
1080 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1081 }
1082
1083 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1084 void *opaque, const char *name,
1085 Error **errp)
1086 {
1087 X86CPU *cpu = X86_CPU(obj);
1088 CPUX86State *env = &cpu->env;
1089 int64_t value;
1090
1091 value = env->cpuid_version & 0xf;
1092 visit_type_int(v, &value, name, errp);
1093 }
1094
1095 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1096 void *opaque, const char *name,
1097 Error **errp)
1098 {
1099 X86CPU *cpu = X86_CPU(obj);
1100 CPUX86State *env = &cpu->env;
1101 const int64_t min = 0;
1102 const int64_t max = 0xf;
1103 int64_t value;
1104
1105 visit_type_int(v, &value, name, errp);
1106 if (error_is_set(errp)) {
1107 return;
1108 }
1109 if (value < min || value > max) {
1110 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1111 name ? name : "null", value, min, max);
1112 return;
1113 }
1114
1115 env->cpuid_version &= ~0xf;
1116 env->cpuid_version |= value & 0xf;
1117 }
1118
1119 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1120 const char *name, Error **errp)
1121 {
1122 X86CPU *cpu = X86_CPU(obj);
1123
1124 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1125 }
1126
1127 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1128 const char *name, Error **errp)
1129 {
1130 X86CPU *cpu = X86_CPU(obj);
1131
1132 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1133 }
1134
1135 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1136 const char *name, Error **errp)
1137 {
1138 X86CPU *cpu = X86_CPU(obj);
1139
1140 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1141 }
1142
1143 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1144 const char *name, Error **errp)
1145 {
1146 X86CPU *cpu = X86_CPU(obj);
1147
1148 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1149 }
1150
1151 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1152 {
1153 X86CPU *cpu = X86_CPU(obj);
1154 CPUX86State *env = &cpu->env;
1155 char *value;
1156 int i;
1157
1158 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1159 for (i = 0; i < 4; i++) {
1160 value[i ] = env->cpuid_vendor1 >> (8 * i);
1161 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1162 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1163 }
1164 value[CPUID_VENDOR_SZ] = '\0';
1165 return value;
1166 }
1167
1168 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1169 Error **errp)
1170 {
1171 X86CPU *cpu = X86_CPU(obj);
1172 CPUX86State *env = &cpu->env;
1173 int i;
1174
1175 if (strlen(value) != CPUID_VENDOR_SZ) {
1176 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1177 "vendor", value);
1178 return;
1179 }
1180
1181 env->cpuid_vendor1 = 0;
1182 env->cpuid_vendor2 = 0;
1183 env->cpuid_vendor3 = 0;
1184 for (i = 0; i < 4; i++) {
1185 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1186 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1187 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1188 }
1189 env->cpuid_vendor_override = 1;
1190 }
1191
1192 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1193 {
1194 X86CPU *cpu = X86_CPU(obj);
1195 CPUX86State *env = &cpu->env;
1196 char *value;
1197 int i;
1198
1199 value = g_malloc(48 + 1);
1200 for (i = 0; i < 48; i++) {
1201 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1202 }
1203 value[48] = '\0';
1204 return value;
1205 }
1206
1207 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1208 Error **errp)
1209 {
1210 X86CPU *cpu = X86_CPU(obj);
1211 CPUX86State *env = &cpu->env;
1212 int c, len, i;
1213
1214 if (model_id == NULL) {
1215 model_id = "";
1216 }
1217 len = strlen(model_id);
1218 memset(env->cpuid_model, 0, 48);
1219 for (i = 0; i < 48; i++) {
1220 if (i >= len) {
1221 c = '\0';
1222 } else {
1223 c = (uint8_t)model_id[i];
1224 }
1225 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1226 }
1227 }
1228
1229 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1230 const char *name, Error **errp)
1231 {
1232 X86CPU *cpu = X86_CPU(obj);
1233 int64_t value;
1234
1235 value = cpu->env.tsc_khz * 1000;
1236 visit_type_int(v, &value, name, errp);
1237 }
1238
1239 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1240 const char *name, Error **errp)
1241 {
1242 X86CPU *cpu = X86_CPU(obj);
1243 const int64_t min = 0;
1244 const int64_t max = INT64_MAX;
1245 int64_t value;
1246
1247 visit_type_int(v, &value, name, errp);
1248 if (error_is_set(errp)) {
1249 return;
1250 }
1251 if (value < min || value > max) {
1252 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1253 name ? name : "null", value, min, max);
1254 return;
1255 }
1256
1257 cpu->env.tsc_khz = value / 1000;
1258 }
1259
1260 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1261 {
1262 x86_def_t *def;
1263
1264 for (def = x86_defs; def; def = def->next) {
1265 if (name && !strcmp(name, def->name)) {
1266 break;
1267 }
1268 }
1269 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1270 kvm_cpu_fill_host(x86_cpu_def);
1271 } else if (!def) {
1272 return -1;
1273 } else {
1274 memcpy(x86_cpu_def, def, sizeof(*def));
1275 }
1276
1277 return 0;
1278 }
1279
1280 /* Parse "+feature,-feature,feature=foo" CPU feature string
1281 */
1282 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1283 {
1284 unsigned int i;
1285 char *featurestr; /* Single 'key=value" string being parsed */
1286 /* Features to be added */
1287 uint32_t plus_features = 0, plus_ext_features = 0;
1288 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
1289 uint32_t plus_kvm_features = kvm_default_features, plus_svm_features = 0;
1290 uint32_t plus_7_0_ebx_features = 0;
1291 /* Features to be removed */
1292 uint32_t minus_features = 0, minus_ext_features = 0;
1293 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
1294 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
1295 uint32_t minus_7_0_ebx_features = 0;
1296 uint32_t numvalue;
1297
1298 add_flagname_to_bitmaps("hypervisor", &plus_features,
1299 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
1300 &plus_kvm_features, &plus_svm_features, &plus_7_0_ebx_features);
1301
1302 featurestr = features ? strtok(features, ",") : NULL;
1303
1304 while (featurestr) {
1305 char *val;
1306 if (featurestr[0] == '+') {
1307 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
1308 &plus_ext_features, &plus_ext2_features,
1309 &plus_ext3_features, &plus_kvm_features,
1310 &plus_svm_features, &plus_7_0_ebx_features);
1311 } else if (featurestr[0] == '-') {
1312 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
1313 &minus_ext_features, &minus_ext2_features,
1314 &minus_ext3_features, &minus_kvm_features,
1315 &minus_svm_features, &minus_7_0_ebx_features);
1316 } else if ((val = strchr(featurestr, '='))) {
1317 *val = 0; val++;
1318 if (!strcmp(featurestr, "family")) {
1319 char *err;
1320 numvalue = strtoul(val, &err, 0);
1321 if (!*val || *err || numvalue > 0xff + 0xf) {
1322 fprintf(stderr, "bad numerical value %s\n", val);
1323 goto error;
1324 }
1325 x86_cpu_def->family = numvalue;
1326 } else if (!strcmp(featurestr, "model")) {
1327 char *err;
1328 numvalue = strtoul(val, &err, 0);
1329 if (!*val || *err || numvalue > 0xff) {
1330 fprintf(stderr, "bad numerical value %s\n", val);
1331 goto error;
1332 }
1333 x86_cpu_def->model = numvalue;
1334 } else if (!strcmp(featurestr, "stepping")) {
1335 char *err;
1336 numvalue = strtoul(val, &err, 0);
1337 if (!*val || *err || numvalue > 0xf) {
1338 fprintf(stderr, "bad numerical value %s\n", val);
1339 goto error;
1340 }
1341 x86_cpu_def->stepping = numvalue ;
1342 } else if (!strcmp(featurestr, "level")) {
1343 char *err;
1344 numvalue = strtoul(val, &err, 0);
1345 if (!*val || *err) {
1346 fprintf(stderr, "bad numerical value %s\n", val);
1347 goto error;
1348 }
1349 x86_cpu_def->level = numvalue;
1350 } else if (!strcmp(featurestr, "xlevel")) {
1351 char *err;
1352 numvalue = strtoul(val, &err, 0);
1353 if (!*val || *err) {
1354 fprintf(stderr, "bad numerical value %s\n", val);
1355 goto error;
1356 }
1357 if (numvalue < 0x80000000) {
1358 numvalue += 0x80000000;
1359 }
1360 x86_cpu_def->xlevel = numvalue;
1361 } else if (!strcmp(featurestr, "vendor")) {
1362 if (strlen(val) != 12) {
1363 fprintf(stderr, "vendor string must be 12 chars long\n");
1364 goto error;
1365 }
1366 x86_cpu_def->vendor1 = 0;
1367 x86_cpu_def->vendor2 = 0;
1368 x86_cpu_def->vendor3 = 0;
1369 for(i = 0; i < 4; i++) {
1370 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1371 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1372 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1373 }
1374 x86_cpu_def->vendor_override = 1;
1375 } else if (!strcmp(featurestr, "model_id")) {
1376 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1377 val);
1378 } else if (!strcmp(featurestr, "tsc_freq")) {
1379 int64_t tsc_freq;
1380 char *err;
1381
1382 tsc_freq = strtosz_suffix_unit(val, &err,
1383 STRTOSZ_DEFSUFFIX_B, 1000);
1384 if (tsc_freq < 0 || *err) {
1385 fprintf(stderr, "bad numerical value %s\n", val);
1386 goto error;
1387 }
1388 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1389 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1390 char *err;
1391 numvalue = strtoul(val, &err, 0);
1392 if (!*val || *err) {
1393 fprintf(stderr, "bad numerical value %s\n", val);
1394 goto error;
1395 }
1396 hyperv_set_spinlock_retries(numvalue);
1397 } else {
1398 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1399 goto error;
1400 }
1401 } else if (!strcmp(featurestr, "check")) {
1402 check_cpuid = 1;
1403 } else if (!strcmp(featurestr, "enforce")) {
1404 check_cpuid = enforce_cpuid = 1;
1405 } else if (!strcmp(featurestr, "hv_relaxed")) {
1406 hyperv_enable_relaxed_timing(true);
1407 } else if (!strcmp(featurestr, "hv_vapic")) {
1408 hyperv_enable_vapic_recommended(true);
1409 } else {
1410 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1411 goto error;
1412 }
1413 featurestr = strtok(NULL, ",");
1414 }
1415 x86_cpu_def->features |= plus_features;
1416 x86_cpu_def->ext_features |= plus_ext_features;
1417 x86_cpu_def->ext2_features |= plus_ext2_features;
1418 x86_cpu_def->ext3_features |= plus_ext3_features;
1419 x86_cpu_def->kvm_features |= plus_kvm_features;
1420 x86_cpu_def->svm_features |= plus_svm_features;
1421 x86_cpu_def->cpuid_7_0_ebx_features |= plus_7_0_ebx_features;
1422 x86_cpu_def->features &= ~minus_features;
1423 x86_cpu_def->ext_features &= ~minus_ext_features;
1424 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1425 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1426 x86_cpu_def->kvm_features &= ~minus_kvm_features;
1427 x86_cpu_def->svm_features &= ~minus_svm_features;
1428 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features;
1429 if (check_cpuid && kvm_enabled()) {
1430 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1431 goto error;
1432 }
1433 return 0;
1434
1435 error:
1436 return -1;
1437 }
1438
1439 /* generate a composite string into buf of all cpuid names in featureset
1440 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1441 * if flags, suppress names undefined in featureset.
1442 */
1443 static void listflags(char *buf, int bufsize, uint32_t fbits,
1444 const char **featureset, uint32_t flags)
1445 {
1446 const char **p = &featureset[31];
1447 char *q, *b, bit;
1448 int nc;
1449
1450 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1451 *buf = '\0';
1452 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1453 if (fbits & 1 << bit && (*p || !flags)) {
1454 if (*p)
1455 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1456 else
1457 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1458 if (bufsize <= nc) {
1459 if (b) {
1460 memcpy(b, "...", sizeof("..."));
1461 }
1462 return;
1463 }
1464 q += nc;
1465 bufsize -= nc;
1466 }
1467 }
1468
1469 /* generate CPU information. */
1470 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1471 {
1472 x86_def_t *def;
1473 char buf[256];
1474
1475 for (def = x86_defs; def; def = def->next) {
1476 snprintf(buf, sizeof(buf), "%s", def->name);
1477 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1478 }
1479 if (kvm_enabled()) {
1480 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1481 }
1482 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1483 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1484 (*cpu_fprintf)(f, " %s\n", buf);
1485 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1486 (*cpu_fprintf)(f, " %s\n", buf);
1487 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1488 (*cpu_fprintf)(f, " %s\n", buf);
1489 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1490 (*cpu_fprintf)(f, " %s\n", buf);
1491 }
1492
1493 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1494 {
1495 CpuDefinitionInfoList *cpu_list = NULL;
1496 x86_def_t *def;
1497
1498 for (def = x86_defs; def; def = def->next) {
1499 CpuDefinitionInfoList *entry;
1500 CpuDefinitionInfo *info;
1501
1502 info = g_malloc0(sizeof(*info));
1503 info->name = g_strdup(def->name);
1504
1505 entry = g_malloc0(sizeof(*entry));
1506 entry->value = info;
1507 entry->next = cpu_list;
1508 cpu_list = entry;
1509 }
1510
1511 return cpu_list;
1512 }
1513
1514 #ifdef CONFIG_KVM
1515 static void filter_features_for_kvm(X86CPU *cpu)
1516 {
1517 CPUX86State *env = &cpu->env;
1518 KVMState *s = kvm_state;
1519
1520 env->cpuid_features &=
1521 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1522 env->cpuid_ext_features &=
1523 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1524 env->cpuid_ext2_features &=
1525 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1526 env->cpuid_ext3_features &=
1527 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1528 env->cpuid_svm_features &=
1529 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1530 env->cpuid_7_0_ebx_features &=
1531 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1532 env->cpuid_kvm_features &=
1533 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1534 env->cpuid_ext4_features &=
1535 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1536
1537 }
1538 #endif
1539
1540 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1541 {
1542 CPUX86State *env = &cpu->env;
1543 x86_def_t def1, *def = &def1;
1544 Error *error = NULL;
1545 char *name, *features;
1546 gchar **model_pieces;
1547
1548 memset(def, 0, sizeof(*def));
1549
1550 model_pieces = g_strsplit(cpu_model, ",", 2);
1551 if (!model_pieces[0]) {
1552 goto error;
1553 }
1554 name = model_pieces[0];
1555 features = model_pieces[1];
1556
1557 if (cpu_x86_find_by_name(def, name) < 0) {
1558 goto error;
1559 }
1560
1561 if (cpu_x86_parse_featurestr(def, features) < 0) {
1562 goto error;
1563 }
1564 assert(def->vendor1);
1565 env->cpuid_vendor1 = def->vendor1;
1566 env->cpuid_vendor2 = def->vendor2;
1567 env->cpuid_vendor3 = def->vendor3;
1568 env->cpuid_vendor_override = def->vendor_override;
1569 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1570 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1571 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1572 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1573 env->cpuid_features = def->features;
1574 env->cpuid_ext_features = def->ext_features;
1575 env->cpuid_ext2_features = def->ext2_features;
1576 env->cpuid_ext3_features = def->ext3_features;
1577 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1578 env->cpuid_kvm_features = def->kvm_features;
1579 env->cpuid_svm_features = def->svm_features;
1580 env->cpuid_ext4_features = def->ext4_features;
1581 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1582 env->cpuid_xlevel2 = def->xlevel2;
1583 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1584 "tsc-frequency", &error);
1585
1586 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1587 if (error) {
1588 fprintf(stderr, "%s\n", error_get_pretty(error));
1589 error_free(error);
1590 goto error;
1591 }
1592
1593 g_strfreev(model_pieces);
1594 return 0;
1595 error:
1596 g_strfreev(model_pieces);
1597 return -1;
1598 }
1599
1600 #if !defined(CONFIG_USER_ONLY)
1601
1602 void cpu_clear_apic_feature(CPUX86State *env)
1603 {
1604 env->cpuid_features &= ~CPUID_APIC;
1605 }
1606
1607 #endif /* !CONFIG_USER_ONLY */
1608
1609 /* Initialize list of CPU models, filling some non-static fields if necessary
1610 */
1611 void x86_cpudef_setup(void)
1612 {
1613 int i, j;
1614 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1615
1616 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1617 x86_def_t *def = &builtin_x86_defs[i];
1618 def->next = x86_defs;
1619
1620 /* Look for specific "cpudef" models that */
1621 /* have the QEMU version in .model_id */
1622 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1623 if (strcmp(model_with_versions[j], def->name) == 0) {
1624 pstrcpy(def->model_id, sizeof(def->model_id),
1625 "QEMU Virtual CPU version ");
1626 pstrcat(def->model_id, sizeof(def->model_id),
1627 qemu_get_version());
1628 break;
1629 }
1630 }
1631
1632 x86_defs = def;
1633 }
1634 }
1635
1636 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1637 uint32_t *ecx, uint32_t *edx)
1638 {
1639 *ebx = env->cpuid_vendor1;
1640 *edx = env->cpuid_vendor2;
1641 *ecx = env->cpuid_vendor3;
1642
1643 /* sysenter isn't supported on compatibility mode on AMD, syscall
1644 * isn't supported in compatibility mode on Intel.
1645 * Normally we advertise the actual cpu vendor, but you can override
1646 * this if you want to use KVM's sysenter/syscall emulation
1647 * in compatibility mode and when doing cross vendor migration
1648 */
1649 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1650 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1651 }
1652 }
1653
1654 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1655 uint32_t *eax, uint32_t *ebx,
1656 uint32_t *ecx, uint32_t *edx)
1657 {
1658 X86CPU *cpu = x86_env_get_cpu(env);
1659 CPUState *cs = CPU(cpu);
1660
1661 /* test if maximum index reached */
1662 if (index & 0x80000000) {
1663 if (index > env->cpuid_xlevel) {
1664 if (env->cpuid_xlevel2 > 0) {
1665 /* Handle the Centaur's CPUID instruction. */
1666 if (index > env->cpuid_xlevel2) {
1667 index = env->cpuid_xlevel2;
1668 } else if (index < 0xC0000000) {
1669 index = env->cpuid_xlevel;
1670 }
1671 } else {
1672 /* Intel documentation states that invalid EAX input will
1673 * return the same information as EAX=cpuid_level
1674 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1675 */
1676 index = env->cpuid_level;
1677 }
1678 }
1679 } else {
1680 if (index > env->cpuid_level)
1681 index = env->cpuid_level;
1682 }
1683
1684 switch(index) {
1685 case 0:
1686 *eax = env->cpuid_level;
1687 get_cpuid_vendor(env, ebx, ecx, edx);
1688 break;
1689 case 1:
1690 *eax = env->cpuid_version;
1691 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1692 *ecx = env->cpuid_ext_features;
1693 *edx = env->cpuid_features;
1694 if (env->nr_cores * env->nr_threads > 1) {
1695 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1696 *edx |= 1 << 28; /* HTT bit */
1697 }
1698 break;
1699 case 2:
1700 /* cache info: needed for Pentium Pro compatibility */
1701 *eax = 1;
1702 *ebx = 0;
1703 *ecx = 0;
1704 *edx = 0x2c307d;
1705 break;
1706 case 4:
1707 /* cache info: needed for Core compatibility */
1708 if (env->nr_cores > 1) {
1709 *eax = (env->nr_cores - 1) << 26;
1710 } else {
1711 *eax = 0;
1712 }
1713 switch (count) {
1714 case 0: /* L1 dcache info */
1715 *eax |= 0x0000121;
1716 *ebx = 0x1c0003f;
1717 *ecx = 0x000003f;
1718 *edx = 0x0000001;
1719 break;
1720 case 1: /* L1 icache info */
1721 *eax |= 0x0000122;
1722 *ebx = 0x1c0003f;
1723 *ecx = 0x000003f;
1724 *edx = 0x0000001;
1725 break;
1726 case 2: /* L2 cache info */
1727 *eax |= 0x0000143;
1728 if (env->nr_threads > 1) {
1729 *eax |= (env->nr_threads - 1) << 14;
1730 }
1731 *ebx = 0x3c0003f;
1732 *ecx = 0x0000fff;
1733 *edx = 0x0000001;
1734 break;
1735 default: /* end of info */
1736 *eax = 0;
1737 *ebx = 0;
1738 *ecx = 0;
1739 *edx = 0;
1740 break;
1741 }
1742 break;
1743 case 5:
1744 /* mwait info: needed for Core compatibility */
1745 *eax = 0; /* Smallest monitor-line size in bytes */
1746 *ebx = 0; /* Largest monitor-line size in bytes */
1747 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1748 *edx = 0;
1749 break;
1750 case 6:
1751 /* Thermal and Power Leaf */
1752 *eax = 0;
1753 *ebx = 0;
1754 *ecx = 0;
1755 *edx = 0;
1756 break;
1757 case 7:
1758 /* Structured Extended Feature Flags Enumeration Leaf */
1759 if (count == 0) {
1760 *eax = 0; /* Maximum ECX value for sub-leaves */
1761 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1762 *ecx = 0; /* Reserved */
1763 *edx = 0; /* Reserved */
1764 } else {
1765 *eax = 0;
1766 *ebx = 0;
1767 *ecx = 0;
1768 *edx = 0;
1769 }
1770 break;
1771 case 9:
1772 /* Direct Cache Access Information Leaf */
1773 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1774 *ebx = 0;
1775 *ecx = 0;
1776 *edx = 0;
1777 break;
1778 case 0xA:
1779 /* Architectural Performance Monitoring Leaf */
1780 if (kvm_enabled()) {
1781 KVMState *s = cs->kvm_state;
1782
1783 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1784 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1785 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1786 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1787 } else {
1788 *eax = 0;
1789 *ebx = 0;
1790 *ecx = 0;
1791 *edx = 0;
1792 }
1793 break;
1794 case 0xD:
1795 /* Processor Extended State */
1796 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1797 *eax = 0;
1798 *ebx = 0;
1799 *ecx = 0;
1800 *edx = 0;
1801 break;
1802 }
1803 if (kvm_enabled()) {
1804 KVMState *s = cs->kvm_state;
1805
1806 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1807 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1808 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1809 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1810 } else {
1811 *eax = 0;
1812 *ebx = 0;
1813 *ecx = 0;
1814 *edx = 0;
1815 }
1816 break;
1817 case 0x80000000:
1818 *eax = env->cpuid_xlevel;
1819 *ebx = env->cpuid_vendor1;
1820 *edx = env->cpuid_vendor2;
1821 *ecx = env->cpuid_vendor3;
1822 break;
1823 case 0x80000001:
1824 *eax = env->cpuid_version;
1825 *ebx = 0;
1826 *ecx = env->cpuid_ext3_features;
1827 *edx = env->cpuid_ext2_features;
1828
1829 /* The Linux kernel checks for the CMPLegacy bit and
1830 * discards multiple thread information if it is set.
1831 * So dont set it here for Intel to make Linux guests happy.
1832 */
1833 if (env->nr_cores * env->nr_threads > 1) {
1834 uint32_t tebx, tecx, tedx;
1835 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1836 if (tebx != CPUID_VENDOR_INTEL_1 ||
1837 tedx != CPUID_VENDOR_INTEL_2 ||
1838 tecx != CPUID_VENDOR_INTEL_3) {
1839 *ecx |= 1 << 1; /* CmpLegacy bit */
1840 }
1841 }
1842 break;
1843 case 0x80000002:
1844 case 0x80000003:
1845 case 0x80000004:
1846 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1847 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1848 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1849 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1850 break;
1851 case 0x80000005:
1852 /* cache info (L1 cache) */
1853 *eax = 0x01ff01ff;
1854 *ebx = 0x01ff01ff;
1855 *ecx = 0x40020140;
1856 *edx = 0x40020140;
1857 break;
1858 case 0x80000006:
1859 /* cache info (L2 cache) */
1860 *eax = 0;
1861 *ebx = 0x42004200;
1862 *ecx = 0x02008140;
1863 *edx = 0;
1864 break;
1865 case 0x80000008:
1866 /* virtual & phys address size in low 2 bytes. */
1867 /* XXX: This value must match the one used in the MMU code. */
1868 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1869 /* 64 bit processor */
1870 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1871 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1872 } else {
1873 if (env->cpuid_features & CPUID_PSE36)
1874 *eax = 0x00000024; /* 36 bits physical */
1875 else
1876 *eax = 0x00000020; /* 32 bits physical */
1877 }
1878 *ebx = 0;
1879 *ecx = 0;
1880 *edx = 0;
1881 if (env->nr_cores * env->nr_threads > 1) {
1882 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1883 }
1884 break;
1885 case 0x8000000A:
1886 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1887 *eax = 0x00000001; /* SVM Revision */
1888 *ebx = 0x00000010; /* nr of ASIDs */
1889 *ecx = 0;
1890 *edx = env->cpuid_svm_features; /* optional features */
1891 } else {
1892 *eax = 0;
1893 *ebx = 0;
1894 *ecx = 0;
1895 *edx = 0;
1896 }
1897 break;
1898 case 0xC0000000:
1899 *eax = env->cpuid_xlevel2;
1900 *ebx = 0;
1901 *ecx = 0;
1902 *edx = 0;
1903 break;
1904 case 0xC0000001:
1905 /* Support for VIA CPU's CPUID instruction */
1906 *eax = env->cpuid_version;
1907 *ebx = 0;
1908 *ecx = 0;
1909 *edx = env->cpuid_ext4_features;
1910 break;
1911 case 0xC0000002:
1912 case 0xC0000003:
1913 case 0xC0000004:
1914 /* Reserved for the future, and now filled with zero */
1915 *eax = 0;
1916 *ebx = 0;
1917 *ecx = 0;
1918 *edx = 0;
1919 break;
1920 default:
1921 /* reserved values: zero */
1922 *eax = 0;
1923 *ebx = 0;
1924 *ecx = 0;
1925 *edx = 0;
1926 break;
1927 }
1928 }
1929
1930 /* CPUClass::reset() */
1931 static void x86_cpu_reset(CPUState *s)
1932 {
1933 X86CPU *cpu = X86_CPU(s);
1934 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1935 CPUX86State *env = &cpu->env;
1936 int i;
1937
1938 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1939 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1940 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1941 }
1942
1943 xcc->parent_reset(s);
1944
1945
1946 memset(env, 0, offsetof(CPUX86State, breakpoints));
1947
1948 tlb_flush(env, 1);
1949
1950 env->old_exception = -1;
1951
1952 /* init to reset state */
1953
1954 #ifdef CONFIG_SOFTMMU
1955 env->hflags |= HF_SOFTMMU_MASK;
1956 #endif
1957 env->hflags2 |= HF2_GIF_MASK;
1958
1959 cpu_x86_update_cr0(env, 0x60000010);
1960 env->a20_mask = ~0x0;
1961 env->smbase = 0x30000;
1962
1963 env->idt.limit = 0xffff;
1964 env->gdt.limit = 0xffff;
1965 env->ldt.limit = 0xffff;
1966 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1967 env->tr.limit = 0xffff;
1968 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1969
1970 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1971 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1972 DESC_R_MASK | DESC_A_MASK);
1973 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1974 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1975 DESC_A_MASK);
1976 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1977 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1978 DESC_A_MASK);
1979 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1980 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1981 DESC_A_MASK);
1982 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1983 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1984 DESC_A_MASK);
1985 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1986 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1987 DESC_A_MASK);
1988
1989 env->eip = 0xfff0;
1990 env->regs[R_EDX] = env->cpuid_version;
1991
1992 env->eflags = 0x2;
1993
1994 /* FPU init */
1995 for (i = 0; i < 8; i++) {
1996 env->fptags[i] = 1;
1997 }
1998 env->fpuc = 0x37f;
1999
2000 env->mxcsr = 0x1f80;
2001
2002 env->pat = 0x0007040600070406ULL;
2003 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2004
2005 memset(env->dr, 0, sizeof(env->dr));
2006 env->dr[6] = DR6_FIXED_1;
2007 env->dr[7] = DR7_FIXED_1;
2008 cpu_breakpoint_remove_all(env, BP_CPU);
2009 cpu_watchpoint_remove_all(env, BP_CPU);
2010
2011 #if !defined(CONFIG_USER_ONLY)
2012 /* We hard-wire the BSP to the first CPU. */
2013 if (env->cpu_index == 0) {
2014 apic_designate_bsp(env->apic_state);
2015 }
2016
2017 env->halted = !cpu_is_bsp(cpu);
2018 #endif
2019 }
2020
2021 #ifndef CONFIG_USER_ONLY
2022 bool cpu_is_bsp(X86CPU *cpu)
2023 {
2024 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2025 }
2026
2027 /* TODO: remove me, when reset over QOM tree is implemented */
2028 static void x86_cpu_machine_reset_cb(void *opaque)
2029 {
2030 X86CPU *cpu = opaque;
2031 cpu_reset(CPU(cpu));
2032 }
2033 #endif
2034
2035 static void mce_init(X86CPU *cpu)
2036 {
2037 CPUX86State *cenv = &cpu->env;
2038 unsigned int bank;
2039
2040 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2041 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2042 (CPUID_MCE | CPUID_MCA)) {
2043 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2044 cenv->mcg_ctl = ~(uint64_t)0;
2045 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2046 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2047 }
2048 }
2049 }
2050
2051 #define MSI_ADDR_BASE 0xfee00000
2052
2053 #ifndef CONFIG_USER_ONLY
2054 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2055 {
2056 static int apic_mapped;
2057 CPUX86State *env = &cpu->env;
2058 APICCommonState *apic;
2059 const char *apic_type = "apic";
2060
2061 if (kvm_irqchip_in_kernel()) {
2062 apic_type = "kvm-apic";
2063 } else if (xen_enabled()) {
2064 apic_type = "xen-apic";
2065 }
2066
2067 env->apic_state = qdev_try_create(NULL, apic_type);
2068 if (env->apic_state == NULL) {
2069 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2070 return;
2071 }
2072
2073 object_property_add_child(OBJECT(cpu), "apic",
2074 OBJECT(env->apic_state), NULL);
2075 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2076 /* TODO: convert to link<> */
2077 apic = APIC_COMMON(env->apic_state);
2078 apic->cpu = cpu;
2079
2080 if (qdev_init(env->apic_state)) {
2081 error_setg(errp, "APIC device '%s' could not be initialized",
2082 object_get_typename(OBJECT(env->apic_state)));
2083 return;
2084 }
2085
2086 /* XXX: mapping more APICs at the same memory location */
2087 if (apic_mapped == 0) {
2088 /* NOTE: the APIC is directly connected to the CPU - it is not
2089 on the global memory bus. */
2090 /* XXX: what if the base changes? */
2091 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2092 apic_mapped = 1;
2093 }
2094 }
2095 #endif
2096
2097 void x86_cpu_realize(Object *obj, Error **errp)
2098 {
2099 X86CPU *cpu = X86_CPU(obj);
2100 CPUX86State *env = &cpu->env;
2101
2102 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2103 env->cpuid_level = 7;
2104 }
2105
2106 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2107 * CPUID[1].EDX.
2108 */
2109 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2110 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2111 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2112 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2113 env->cpuid_ext2_features |= (env->cpuid_features
2114 & CPUID_EXT2_AMD_ALIASES);
2115 }
2116
2117 if (!kvm_enabled()) {
2118 env->cpuid_features &= TCG_FEATURES;
2119 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2120 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2121 #ifdef TARGET_X86_64
2122 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2123 #endif
2124 );
2125 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2126 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2127 } else {
2128 #ifdef CONFIG_KVM
2129 filter_features_for_kvm(cpu);
2130 #endif
2131 }
2132
2133 #ifndef CONFIG_USER_ONLY
2134 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2135
2136 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2137 x86_cpu_apic_init(cpu, errp);
2138 if (error_is_set(errp)) {
2139 return;
2140 }
2141 }
2142 #endif
2143
2144 mce_init(cpu);
2145 qemu_init_vcpu(&cpu->env);
2146 cpu_reset(CPU(cpu));
2147 }
2148
2149 static void x86_cpu_initfn(Object *obj)
2150 {
2151 X86CPU *cpu = X86_CPU(obj);
2152 CPUX86State *env = &cpu->env;
2153 static int inited;
2154
2155 cpu_exec_init(env);
2156
2157 object_property_add(obj, "family", "int",
2158 x86_cpuid_version_get_family,
2159 x86_cpuid_version_set_family, NULL, NULL, NULL);
2160 object_property_add(obj, "model", "int",
2161 x86_cpuid_version_get_model,
2162 x86_cpuid_version_set_model, NULL, NULL, NULL);
2163 object_property_add(obj, "stepping", "int",
2164 x86_cpuid_version_get_stepping,
2165 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2166 object_property_add(obj, "level", "int",
2167 x86_cpuid_get_level,
2168 x86_cpuid_set_level, NULL, NULL, NULL);
2169 object_property_add(obj, "xlevel", "int",
2170 x86_cpuid_get_xlevel,
2171 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2172 object_property_add_str(obj, "vendor",
2173 x86_cpuid_get_vendor,
2174 x86_cpuid_set_vendor, NULL);
2175 object_property_add_str(obj, "model-id",
2176 x86_cpuid_get_model_id,
2177 x86_cpuid_set_model_id, NULL);
2178 object_property_add(obj, "tsc-frequency", "int",
2179 x86_cpuid_get_tsc_freq,
2180 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2181
2182 env->cpuid_apic_id = env->cpu_index;
2183
2184 /* init various static tables used in TCG mode */
2185 if (tcg_enabled() && !inited) {
2186 inited = 1;
2187 optimize_flags_init();
2188 #ifndef CONFIG_USER_ONLY
2189 cpu_set_debug_excp_handler(breakpoint_handler);
2190 #endif
2191 }
2192 }
2193
2194 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2195 {
2196 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2197 CPUClass *cc = CPU_CLASS(oc);
2198
2199 xcc->parent_reset = cc->reset;
2200 cc->reset = x86_cpu_reset;
2201 }
2202
2203 static const TypeInfo x86_cpu_type_info = {
2204 .name = TYPE_X86_CPU,
2205 .parent = TYPE_CPU,
2206 .instance_size = sizeof(X86CPU),
2207 .instance_init = x86_cpu_initfn,
2208 .abstract = false,
2209 .class_size = sizeof(X86CPUClass),
2210 .class_init = x86_cpu_common_class_init,
2211 };
2212
2213 static void x86_cpu_register_types(void)
2214 {
2215 type_register_static(&x86_cpu_type_info);
2216 }
2217
2218 type_init(x86_cpu_register_types)
AR7 emulation for QEMU