2 * Helpers for emulation of CP0-related MIPS instructions.
4 * Copyright (C) 2004-2005 Jocelyn Mayer
5 * Copyright (C) 2020 Wave Computing, Inc.
6 * Copyright (C) 2020 Aleksandar Markovic <amarkovic@wavecomp.com>
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qemu/main-loop.h"
27 #include "qemu/host-utils.h"
28 #include "exec/helper-proto.h"
29 #include "exec/exec-all.h"
30 #include "exec/cpu_ldst.h"
31 #include "exec/memop.h"
32 #include "sysemu/kvm.h"
35 #ifndef CONFIG_USER_ONLY
37 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
39 CPUState
*cpu
= CPU(c
);
40 CPUMIPSState
*env
= &c
->env
;
43 * If the VPE is halted but otherwise active, it means it's waiting for
46 return cpu
->halted
&& mips_vpe_active(env
);
49 static bool mips_vp_is_wfi(MIPSCPU
*c
)
51 CPUState
*cpu
= CPU(c
);
52 CPUMIPSState
*env
= &c
->env
;
54 return cpu
->halted
&& mips_vp_active(env
);
57 static inline void mips_vpe_wake(MIPSCPU
*c
)
60 * Don't set ->halted = 0 directly, let it be done via cpu_has_work
61 * because there might be other conditions that state that c should
64 qemu_mutex_lock_iothread();
65 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
66 qemu_mutex_unlock_iothread();
69 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
71 CPUState
*cs
= CPU(cpu
);
74 * The VPE was shut off, really go to bed.
75 * Reset any old _WAKE requests.
78 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
81 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
83 CPUMIPSState
*c
= &cpu
->env
;
85 /* FIXME: TC reschedule. */
86 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
91 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
93 CPUMIPSState
*c
= &cpu
->env
;
95 /* FIXME: TC reschedule. */
96 if (!mips_vpe_active(c
)) {
103 * @env: CPU from which mapping is performed.
104 * @tc: Should point to an int with the value of the global TC index.
106 * This function will transform @tc into a local index within the
107 * returned #CPUMIPSState.
111 * FIXME: This code assumes that all VPEs have the same number of TCs,
112 * which depends on runtime setup. Can probably be fixed by
113 * walking the list of CPUMIPSStates.
115 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
123 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
124 /* Not allowed to address other CPUs. */
125 *tc
= env
->current_tc
;
130 vpe_idx
= tc_idx
/ cs
->nr_threads
;
131 *tc
= tc_idx
% cs
->nr_threads
;
132 other_cs
= qemu_get_cpu(vpe_idx
);
133 if (other_cs
== NULL
) {
136 cpu
= MIPS_CPU(other_cs
);
141 * The per VPE CP0_Status register shares some fields with the per TC
142 * CP0_TCStatus registers. These fields are wired to the same registers,
143 * so changes to either of them should be reflected on both registers.
145 * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
147 * These helper call synchronizes the regs for a given cpu.
151 * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c.
152 * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
156 /* Called for updates to CP0_TCStatus. */
157 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
161 uint32_t tcu
, tmx
, tasid
, tksu
;
162 uint32_t mask
= ((1U << CP0St_CU3
)
169 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
170 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
171 tasid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
172 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
174 status
= tcu
<< CP0St_CU0
;
175 status
|= tmx
<< CP0St_MX
;
176 status
|= tksu
<< CP0St_KSU
;
178 cpu
->CP0_Status
&= ~mask
;
179 cpu
->CP0_Status
|= status
;
181 /* Sync the TASID with EntryHi. */
182 cpu
->CP0_EntryHi
&= ~cpu
->CP0_EntryHi_ASID_mask
;
183 cpu
->CP0_EntryHi
|= tasid
;
188 /* Called for updates to CP0_EntryHi. */
189 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
192 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
194 asid
= v
& cpu
->CP0_EntryHi_ASID_mask
;
196 if (tc
== cpu
->current_tc
) {
197 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
199 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
202 *tcst
&= ~cpu
->CP0_EntryHi_ASID_mask
;
206 /* XXX: do not use a global */
207 uint32_t cpu_mips_get_random(CPUMIPSState
*env
)
209 static uint32_t seed
= 1;
210 static uint32_t prev_idx
;
212 uint32_t nb_rand_tlb
= env
->tlb
->nb_tlb
- env
->CP0_Wired
;
214 if (nb_rand_tlb
== 1) {
215 return env
->tlb
->nb_tlb
- 1;
218 /* Don't return same value twice, so get another value */
221 * Use a simple algorithm of Linear Congruential Generator
222 * from ISO/IEC 9899 standard.
224 seed
= 1103515245 * seed
+ 12345;
225 idx
= (seed
>> 16) % nb_rand_tlb
+ env
->CP0_Wired
;
226 } while (idx
== prev_idx
);
232 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
234 return env
->mvp
->CP0_MVPControl
;
237 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
239 return env
->mvp
->CP0_MVPConf0
;
242 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
244 return env
->mvp
->CP0_MVPConf1
;
247 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
249 return (int32_t)cpu_mips_get_random(env
);
252 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
254 return env
->active_tc
.CP0_TCStatus
;
257 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
259 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
260 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
262 if (other_tc
== other
->current_tc
) {
263 return other
->active_tc
.CP0_TCStatus
;
265 return other
->tcs
[other_tc
].CP0_TCStatus
;
269 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
271 return env
->active_tc
.CP0_TCBind
;
274 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
276 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
277 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
279 if (other_tc
== other
->current_tc
) {
280 return other
->active_tc
.CP0_TCBind
;
282 return other
->tcs
[other_tc
].CP0_TCBind
;
286 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
288 return env
->active_tc
.PC
;
291 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
293 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
294 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
296 if (other_tc
== other
->current_tc
) {
297 return other
->active_tc
.PC
;
299 return other
->tcs
[other_tc
].PC
;
303 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
305 return env
->active_tc
.CP0_TCHalt
;
308 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
310 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
311 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
313 if (other_tc
== other
->current_tc
) {
314 return other
->active_tc
.CP0_TCHalt
;
316 return other
->tcs
[other_tc
].CP0_TCHalt
;
320 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
322 return env
->active_tc
.CP0_TCContext
;
325 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
327 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
328 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
330 if (other_tc
== other
->current_tc
) {
331 return other
->active_tc
.CP0_TCContext
;
333 return other
->tcs
[other_tc
].CP0_TCContext
;
337 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
339 return env
->active_tc
.CP0_TCSchedule
;
342 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
344 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
345 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
347 if (other_tc
== other
->current_tc
) {
348 return other
->active_tc
.CP0_TCSchedule
;
350 return other
->tcs
[other_tc
].CP0_TCSchedule
;
354 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
356 return env
->active_tc
.CP0_TCScheFBack
;
359 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
361 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
362 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
364 if (other_tc
== other
->current_tc
) {
365 return other
->active_tc
.CP0_TCScheFBack
;
367 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
371 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
373 return (int32_t)cpu_mips_get_count(env
);
376 target_ulong
helper_mfc0_saar(CPUMIPSState
*env
)
378 if ((env
->CP0_SAARI
& 0x3f) < 2) {
379 return (int32_t) env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f];
384 target_ulong
helper_mfhc0_saar(CPUMIPSState
*env
)
386 if ((env
->CP0_SAARI
& 0x3f) < 2) {
387 return env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f] >> 32;
392 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
394 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
395 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
397 return other
->CP0_EntryHi
;
400 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
402 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
403 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
405 return other
->CP0_Cause
;
408 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
410 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
411 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
413 return other
->CP0_Status
;
416 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
418 return (int32_t)(env
->CP0_LLAddr
>> env
->CP0_LLAddr_shift
);
421 target_ulong
helper_mfc0_maar(CPUMIPSState
*env
)
423 return (int32_t) env
->CP0_MAAR
[env
->CP0_MAARI
];
426 target_ulong
helper_mfhc0_maar(CPUMIPSState
*env
)
428 return env
->CP0_MAAR
[env
->CP0_MAARI
] >> 32;
431 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
433 return (int32_t)env
->CP0_WatchLo
[sel
];
436 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
438 return (int32_t) env
->CP0_WatchHi
[sel
];
441 target_ulong
helper_mfhc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
443 return env
->CP0_WatchHi
[sel
] >> 32;
446 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
448 target_ulong t0
= env
->CP0_Debug
;
449 if (env
->hflags
& MIPS_HFLAG_DM
) {
456 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
458 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
460 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
462 if (other_tc
== other
->current_tc
) {
463 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
465 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
468 /* XXX: Might be wrong, check with EJTAG spec. */
469 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
470 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
473 #if defined(TARGET_MIPS64)
474 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
476 return env
->active_tc
.PC
;
479 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
481 return env
->active_tc
.CP0_TCHalt
;
484 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
486 return env
->active_tc
.CP0_TCContext
;
489 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
491 return env
->active_tc
.CP0_TCSchedule
;
494 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
496 return env
->active_tc
.CP0_TCScheFBack
;
499 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
501 return env
->CP0_LLAddr
>> env
->CP0_LLAddr_shift
;
504 target_ulong
helper_dmfc0_maar(CPUMIPSState
*env
)
506 return env
->CP0_MAAR
[env
->CP0_MAARI
];
509 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
511 return env
->CP0_WatchLo
[sel
];
514 target_ulong
helper_dmfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
516 return env
->CP0_WatchHi
[sel
];
519 target_ulong
helper_dmfc0_saar(CPUMIPSState
*env
)
521 if ((env
->CP0_SAARI
& 0x3f) < 2) {
522 return env
->CP0_SAAR
[env
->CP0_SAARI
& 0x3f];
526 #endif /* TARGET_MIPS64 */
528 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
530 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
531 uint32_t tlb_index
= arg1
& 0x7fffffff;
532 if (tlb_index
< env
->tlb
->nb_tlb
) {
533 if (env
->insn_flags
& ISA_MIPS32R6
) {
534 index_p
|= arg1
& 0x80000000;
536 env
->CP0_Index
= index_p
| tlb_index
;
540 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
545 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
546 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
549 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
)) {
550 mask
|= (1 << CP0MVPCo_STLB
);
552 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
554 /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
556 env
->mvp
->CP0_MVPControl
= newval
;
559 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
564 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
565 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
566 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
569 * Yield scheduler intercept not implemented.
570 * Gating storage scheduler intercept not implemented.
573 /* TODO: Enable/disable TCs. */
575 env
->CP0_VPEControl
= newval
;
578 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
580 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
581 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
585 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
586 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
587 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
589 /* TODO: Enable/disable TCs. */
591 other
->CP0_VPEControl
= newval
;
594 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
596 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
597 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
598 /* FIXME: Mask away return zero on read bits. */
599 return other
->CP0_VPEControl
;
602 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
604 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
605 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
607 return other
->CP0_VPEConf0
;
610 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
615 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
616 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
)) {
617 mask
|= (0xff << CP0VPEC0_XTC
);
619 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
621 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
623 /* TODO: TC exclusive handling due to ERL/EXL. */
625 env
->CP0_VPEConf0
= newval
;
628 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
630 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
631 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
635 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
636 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
638 /* TODO: TC exclusive handling due to ERL/EXL. */
639 other
->CP0_VPEConf0
= newval
;
642 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
647 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
648 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
649 (0xff << CP0VPEC1_NCP1
);
650 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
652 /* UDI not implemented. */
653 /* CP2 not implemented. */
655 /* TODO: Handle FPU (CP1) binding. */
657 env
->CP0_VPEConf1
= newval
;
660 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
662 /* Yield qualifier inputs not implemented. */
663 env
->CP0_YQMask
= 0x00000000;
666 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
668 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
671 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
673 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
675 /* 1k pages not implemented */
676 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
677 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
678 | (rxi
<< (CP0EnLo_XI
- 30));
681 #if defined(TARGET_MIPS64)
682 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
684 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
686 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
687 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
691 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
693 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
696 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
698 env
->active_tc
.CP0_TCStatus
= newval
;
699 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
702 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
704 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
705 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
707 if (other_tc
== other
->current_tc
) {
708 other
->active_tc
.CP0_TCStatus
= arg1
;
710 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
712 sync_c0_tcstatus(other
, other_tc
, arg1
);
715 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
717 uint32_t mask
= (1 << CP0TCBd_TBE
);
720 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
)) {
721 mask
|= (1 << CP0TCBd_CurVPE
);
723 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
724 env
->active_tc
.CP0_TCBind
= newval
;
727 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
729 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
730 uint32_t mask
= (1 << CP0TCBd_TBE
);
732 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
734 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
)) {
735 mask
|= (1 << CP0TCBd_CurVPE
);
737 if (other_tc
== other
->current_tc
) {
738 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
739 other
->active_tc
.CP0_TCBind
= newval
;
741 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
742 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
746 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
748 env
->active_tc
.PC
= arg1
;
749 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
752 /* MIPS16 not implemented. */
755 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
757 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
758 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
760 if (other_tc
== other
->current_tc
) {
761 other
->active_tc
.PC
= arg1
;
762 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
763 other
->CP0_LLAddr
= 0;
765 /* MIPS16 not implemented. */
767 other
->tcs
[other_tc
].PC
= arg1
;
768 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
769 other
->CP0_LLAddr
= 0;
771 /* MIPS16 not implemented. */
775 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
777 MIPSCPU
*cpu
= env_archcpu(env
);
779 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
781 /* TODO: Halt TC / Restart (if allocated+active) TC. */
782 if (env
->active_tc
.CP0_TCHalt
& 1) {
783 mips_tc_sleep(cpu
, env
->current_tc
);
785 mips_tc_wake(cpu
, env
->current_tc
);
789 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
791 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
792 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
793 MIPSCPU
*other_cpu
= env_archcpu(other
);
795 /* TODO: Halt TC / Restart (if allocated+active) TC. */
797 if (other_tc
== other
->current_tc
) {
798 other
->active_tc
.CP0_TCHalt
= arg1
;
800 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
804 mips_tc_sleep(other_cpu
, other_tc
);
806 mips_tc_wake(other_cpu
, other_tc
);
810 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
812 env
->active_tc
.CP0_TCContext
= arg1
;
815 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
817 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
818 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
820 if (other_tc
== other
->current_tc
) {
821 other
->active_tc
.CP0_TCContext
= arg1
;
823 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
827 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
829 env
->active_tc
.CP0_TCSchedule
= arg1
;
832 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
834 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
835 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
837 if (other_tc
== other
->current_tc
) {
838 other
->active_tc
.CP0_TCSchedule
= arg1
;
840 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
844 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
846 env
->active_tc
.CP0_TCScheFBack
= arg1
;
849 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
851 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
852 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
854 if (other_tc
== other
->current_tc
) {
855 other
->active_tc
.CP0_TCScheFBack
= arg1
;
857 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
861 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
863 /* 1k pages not implemented */
864 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
865 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
866 | (rxi
<< (CP0EnLo_XI
- 30));
869 #if defined(TARGET_MIPS64)
870 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
872 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
873 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
877 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
879 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
882 void helper_mtc0_memorymapid(CPUMIPSState
*env
, target_ulong arg1
)
885 old
= env
->CP0_MemoryMapID
;
886 env
->CP0_MemoryMapID
= (int32_t) arg1
;
887 /* If the MemoryMapID changes, flush qemu's TLB. */
888 if (old
!= env
->CP0_MemoryMapID
) {
889 cpu_mips_tlb_flush(env
);
893 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
)
898 /* Don't care MASKX as we don't support 1KB page */
899 mask
= extract32((uint32_t)arg1
, CP0PM_MASK
, 16);
900 maskbits
= cto32(mask
);
902 /* Ensure no more set bit after first zero */
903 if ((mask
>> maskbits
) != 0) {
906 /* We don't support VTLB entry smaller than target page */
907 if ((maskbits
+ 12) < TARGET_PAGE_BITS
) {
910 env
->CP0_PageMask
= mask
<< CP0PM_MASK
;
915 /* When invalid, set to default target page size. */
916 env
->CP0_PageMask
= (~TARGET_PAGE_MASK
>> 12) << CP0PM_MASK
;
919 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
921 update_pagemask(env
, arg1
, &env
->CP0_PageMask
);
924 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
926 /* SmartMIPS not implemented */
927 /* 1k pages not implemented */
928 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
929 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
934 void helper_mtc0_segctl0(CPUMIPSState
*env
, target_ulong arg1
)
936 CPUState
*cs
= env_cpu(env
);
938 env
->CP0_SegCtl0
= arg1
& CP0SC0_MASK
;
942 void helper_mtc0_segctl1(CPUMIPSState
*env
, target_ulong arg1
)
944 CPUState
*cs
= env_cpu(env
);
946 env
->CP0_SegCtl1
= arg1
& CP0SC1_MASK
;
950 void helper_mtc0_segctl2(CPUMIPSState
*env
, target_ulong arg1
)
952 CPUState
*cs
= env_cpu(env
);
954 env
->CP0_SegCtl2
= arg1
& CP0SC2_MASK
;
958 void helper_mtc0_pwfield(CPUMIPSState
*env
, target_ulong arg1
)
960 #if defined(TARGET_MIPS64)
961 uint64_t mask
= 0x3F3FFFFFFFULL
;
962 uint32_t old_ptei
= (env
->CP0_PWField
>> CP0PF_PTEI
) & 0x3FULL
;
963 uint32_t new_ptei
= (arg1
>> CP0PF_PTEI
) & 0x3FULL
;
965 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
966 if (((arg1
>> CP0PF_BDI
) & 0x3FULL
) < 12) {
967 mask
&= ~(0x3FULL
<< CP0PF_BDI
);
969 if (((arg1
>> CP0PF_GDI
) & 0x3FULL
) < 12) {
970 mask
&= ~(0x3FULL
<< CP0PF_GDI
);
972 if (((arg1
>> CP0PF_UDI
) & 0x3FULL
) < 12) {
973 mask
&= ~(0x3FULL
<< CP0PF_UDI
);
975 if (((arg1
>> CP0PF_MDI
) & 0x3FULL
) < 12) {
976 mask
&= ~(0x3FULL
<< CP0PF_MDI
);
978 if (((arg1
>> CP0PF_PTI
) & 0x3FULL
) < 12) {
979 mask
&= ~(0x3FULL
<< CP0PF_PTI
);
982 env
->CP0_PWField
= arg1
& mask
;
984 if ((new_ptei
>= 32) ||
985 ((env
->insn_flags
& ISA_MIPS32R6
) &&
986 (new_ptei
== 0 || new_ptei
== 1))) {
987 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3FULL
) |
988 (old_ptei
<< CP0PF_PTEI
);
991 uint32_t mask
= 0x3FFFFFFF;
992 uint32_t old_ptew
= (env
->CP0_PWField
>> CP0PF_PTEW
) & 0x3F;
993 uint32_t new_ptew
= (arg1
>> CP0PF_PTEW
) & 0x3F;
995 if ((env
->insn_flags
& ISA_MIPS32R6
)) {
996 if (((arg1
>> CP0PF_GDW
) & 0x3F) < 12) {
997 mask
&= ~(0x3F << CP0PF_GDW
);
999 if (((arg1
>> CP0PF_UDW
) & 0x3F) < 12) {
1000 mask
&= ~(0x3F << CP0PF_UDW
);
1002 if (((arg1
>> CP0PF_MDW
) & 0x3F) < 12) {
1003 mask
&= ~(0x3F << CP0PF_MDW
);
1005 if (((arg1
>> CP0PF_PTW
) & 0x3F) < 12) {
1006 mask
&= ~(0x3F << CP0PF_PTW
);
1009 env
->CP0_PWField
= arg1
& mask
;
1011 if ((new_ptew
>= 32) ||
1012 ((env
->insn_flags
& ISA_MIPS32R6
) &&
1013 (new_ptew
== 0 || new_ptew
== 1))) {
1014 env
->CP0_PWField
= (env
->CP0_PWField
& ~0x3F) |
1015 (old_ptew
<< CP0PF_PTEW
);
1020 void helper_mtc0_pwsize(CPUMIPSState
*env
, target_ulong arg1
)
1022 #if defined(TARGET_MIPS64)
1023 env
->CP0_PWSize
= arg1
& 0x3F7FFFFFFFULL
;
1025 env
->CP0_PWSize
= arg1
& 0x3FFFFFFF;
1029 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1031 if (env
->insn_flags
& ISA_MIPS32R6
) {
1032 if (arg1
< env
->tlb
->nb_tlb
) {
1033 env
->CP0_Wired
= arg1
;
1036 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1040 void helper_mtc0_pwctl(CPUMIPSState
*env
, target_ulong arg1
)
1042 #if defined(TARGET_MIPS64)
1043 /* PWEn = 0. Hardware page table walking is not implemented. */
1044 env
->CP0_PWCtl
= (env
->CP0_PWCtl
& 0x000000C0) | (arg1
& 0x5C00003F);
1046 env
->CP0_PWCtl
= (arg1
& 0x800000FF);
1050 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1052 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1055 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1057 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1060 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1062 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1065 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1067 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1070 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1072 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1075 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1077 uint32_t mask
= 0x0000000F;
1079 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1080 (env
->insn_flags
& ISA_MIPS32R6
)) {
1083 if (env
->insn_flags
& ISA_MIPS32R6
) {
1086 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1089 if (arg1
& (1 << 29)) {
1090 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1092 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1096 env
->CP0_HWREna
= arg1
& mask
;
1099 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1101 cpu_mips_store_count(env
, arg1
);
1104 void helper_mtc0_saari(CPUMIPSState
*env
, target_ulong arg1
)
1106 uint32_t target
= arg1
& 0x3f;
1108 env
->CP0_SAARI
= target
;
1112 void helper_mtc0_saar(CPUMIPSState
*env
, target_ulong arg1
)
1114 uint32_t target
= env
->CP0_SAARI
& 0x3f;
1116 env
->CP0_SAAR
[target
] = arg1
& 0x00000ffffffff03fULL
;
1120 itc_reconfigure(env
->itu
);
1127 void helper_mthc0_saar(CPUMIPSState
*env
, target_ulong arg1
)
1129 uint32_t target
= env
->CP0_SAARI
& 0x3f;
1131 env
->CP0_SAAR
[target
] =
1132 (((uint64_t) arg1
<< 32) & 0x00000fff00000000ULL
) |
1133 (env
->CP0_SAAR
[target
] & 0x00000000ffffffffULL
);
1137 itc_reconfigure(env
->itu
);
1144 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1146 target_ulong old
, val
, mask
;
1147 mask
= (TARGET_PAGE_MASK
<< 1) | env
->CP0_EntryHi_ASID_mask
;
1148 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1149 mask
|= 1 << CP0EnHi_EHINV
;
1152 /* 1k pages not implemented */
1153 #if defined(TARGET_MIPS64)
1154 if (env
->insn_flags
& ISA_MIPS32R6
) {
1155 int entryhi_r
= extract64(arg1
, 62, 2);
1156 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1157 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1158 if ((entryhi_r
== 2) ||
1159 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1160 /* skip EntryHi.R field if new value is reserved */
1161 mask
&= ~(0x3ull
<< 62);
1164 mask
&= env
->SEGMask
;
1166 old
= env
->CP0_EntryHi
;
1167 val
= (arg1
& mask
) | (old
& ~mask
);
1168 env
->CP0_EntryHi
= val
;
1169 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1170 sync_c0_entryhi(env
, env
->current_tc
);
1172 /* If the ASID changes, flush qemu's TLB. */
1173 if ((old
& env
->CP0_EntryHi_ASID_mask
) !=
1174 (val
& env
->CP0_EntryHi_ASID_mask
)) {
1175 tlb_flush(env_cpu(env
));
1179 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1181 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1182 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1184 other
->CP0_EntryHi
= arg1
;
1185 sync_c0_entryhi(other
, other_tc
);
1188 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1190 cpu_mips_store_compare(env
, arg1
);
1193 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1197 old
= env
->CP0_Status
;
1198 cpu_mips_store_status(env
, arg1
);
1199 val
= env
->CP0_Status
;
1201 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1202 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1203 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1204 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1206 switch (cpu_mmu_index(env
, false)) {
1208 qemu_log(", ERL\n");
1220 cpu_abort(env_cpu(env
), "Invalid MMU mode!\n");
1226 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1228 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1229 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1230 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1232 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1233 sync_c0_status(env
, other
, other_tc
);
1236 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1238 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1241 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1243 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1244 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1247 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1249 cpu_mips_store_cause(env
, arg1
);
1252 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1254 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1255 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1257 cpu_mips_store_cause(other
, arg1
);
1260 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1262 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1263 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1265 return other
->CP0_EPC
;
1268 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1270 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1271 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1273 return other
->CP0_EBase
;
1276 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1278 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1279 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1280 mask
|= ~0x3FFFFFFF;
1282 env
->CP0_EBase
= (env
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1285 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1287 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1288 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1289 target_ulong mask
= 0x3FFFF000 | env
->CP0_EBaseWG_rw_bitmask
;
1290 if (arg1
& env
->CP0_EBaseWG_rw_bitmask
) {
1291 mask
|= ~0x3FFFFFFF;
1293 other
->CP0_EBase
= (other
->CP0_EBase
& ~mask
) | (arg1
& mask
);
1296 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1298 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1299 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1302 case 0: return other
->CP0_Config0
;
1303 case 1: return other
->CP0_Config1
;
1304 case 2: return other
->CP0_Config2
;
1305 case 3: return other
->CP0_Config3
;
1306 /* 4 and 5 are reserved. */
1307 case 6: return other
->CP0_Config6
;
1308 case 7: return other
->CP0_Config7
;
1315 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1317 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1320 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1322 /* tertiary/secondary caches not implemented */
1323 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1326 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1328 if (env
->insn_flags
& ASE_MICROMIPS
) {
1329 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1330 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1334 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1336 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1337 (arg1
& env
->CP0_Config4_rw_bitmask
);
1340 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1342 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1343 (arg1
& env
->CP0_Config5_rw_bitmask
);
1344 env
->CP0_EntryHi_ASID_mask
= (env
->CP0_Config5
& (1 << CP0C5_MI
)) ?
1345 0x0 : (env
->CP0_Config4
& (1 << CP0C4_AE
)) ? 0x3ff : 0xff;
1346 compute_hflags(env
);
1349 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1351 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1352 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1353 env
->CP0_LLAddr
= (env
->CP0_LLAddr
& ~mask
) | (arg1
& mask
);
1356 #define MTC0_MAAR_MASK(env) \
1357 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1359 void helper_mtc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1361 env
->CP0_MAAR
[env
->CP0_MAARI
] = arg1
& MTC0_MAAR_MASK(env
);
1364 void helper_mthc0_maar(CPUMIPSState
*env
, target_ulong arg1
)
1366 env
->CP0_MAAR
[env
->CP0_MAARI
] =
1367 (((uint64_t) arg1
<< 32) & MTC0_MAAR_MASK(env
)) |
1368 (env
->CP0_MAAR
[env
->CP0_MAARI
] & 0x00000000ffffffffULL
);
1371 void helper_mtc0_maari(CPUMIPSState
*env
, target_ulong arg1
)
1373 int index
= arg1
& 0x3f;
1374 if (index
== 0x3f) {
1376 * Software may write all ones to INDEX to determine the
1377 * maximum value supported.
1379 env
->CP0_MAARI
= MIPS_MAAR_MAX
- 1;
1380 } else if (index
< MIPS_MAAR_MAX
) {
1381 env
->CP0_MAARI
= index
;
1384 * Other than the all ones, if the value written is not supported,
1385 * then INDEX is unchanged from its previous value.
1389 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1392 * Watch exceptions for instructions, data loads, data stores
1395 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1398 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1400 uint64_t mask
= 0x40000FF8 | (env
->CP0_EntryHi_ASID_mask
<< CP0WH_ASID
);
1401 if ((env
->CP0_Config5
>> CP0C5_MI
) & 1) {
1402 mask
|= 0xFFFFFFFF00000000ULL
; /* MMID */
1404 env
->CP0_WatchHi
[sel
] = arg1
& mask
;
1405 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1408 void helper_mthc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1410 env
->CP0_WatchHi
[sel
] = ((uint64_t) (arg1
) << 32) |
1411 (env
->CP0_WatchHi
[sel
] & 0x00000000ffffffffULL
);
1414 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1416 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1417 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1420 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1422 env
->CP0_Framemask
= arg1
; /* XXX */
1425 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1427 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1428 if (arg1
& (1 << CP0DB_DM
)) {
1429 env
->hflags
|= MIPS_HFLAG_DM
;
1431 env
->hflags
&= ~MIPS_HFLAG_DM
;
1435 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1437 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1438 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1439 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1441 /* XXX: Might be wrong, check with EJTAG spec. */
1442 if (other_tc
== other
->current_tc
) {
1443 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1445 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1447 other
->CP0_Debug
= (other
->CP0_Debug
&
1448 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1449 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1452 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1454 env
->CP0_Performance0
= arg1
& 0x000007ff;
1457 void helper_mtc0_errctl(CPUMIPSState
*env
, target_ulong arg1
)
1459 int32_t wst
= arg1
& (1 << CP0EC_WST
);
1460 int32_t spr
= arg1
& (1 << CP0EC_SPR
);
1461 int32_t itc
= env
->itc_tag
? (arg1
& (1 << CP0EC_ITC
)) : 0;
1463 env
->CP0_ErrCtl
= wst
| spr
| itc
;
1465 if (itc
&& !wst
&& !spr
) {
1466 env
->hflags
|= MIPS_HFLAG_ITC_CACHE
;
1468 env
->hflags
&= ~MIPS_HFLAG_ITC_CACHE
;
1472 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1474 if (env
->hflags
& MIPS_HFLAG_ITC_CACHE
) {
1476 * If CACHE instruction is configured for ITC tags then make all
1477 * CP0.TagLo bits writable. The actual write to ITC Configuration
1478 * Tag will take care of the read-only bits.
1480 env
->CP0_TagLo
= arg1
;
1482 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1486 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1488 env
->CP0_DataLo
= arg1
; /* XXX */
1491 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1493 env
->CP0_TagHi
= arg1
; /* XXX */
1496 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1498 env
->CP0_DataHi
= arg1
; /* XXX */
1501 /* MIPS MT functions */
1502 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1504 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1505 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1507 if (other_tc
== other
->current_tc
) {
1508 return other
->active_tc
.gpr
[sel
];
1510 return other
->tcs
[other_tc
].gpr
[sel
];
1514 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1516 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1517 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1519 if (other_tc
== other
->current_tc
) {
1520 return other
->active_tc
.LO
[sel
];
1522 return other
->tcs
[other_tc
].LO
[sel
];
1526 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1528 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1529 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1531 if (other_tc
== other
->current_tc
) {
1532 return other
->active_tc
.HI
[sel
];
1534 return other
->tcs
[other_tc
].HI
[sel
];
1538 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1540 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1541 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1543 if (other_tc
== other
->current_tc
) {
1544 return other
->active_tc
.ACX
[sel
];
1546 return other
->tcs
[other_tc
].ACX
[sel
];
1550 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1552 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1553 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1555 if (other_tc
== other
->current_tc
) {
1556 return other
->active_tc
.DSPControl
;
1558 return other
->tcs
[other_tc
].DSPControl
;
1562 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1564 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1565 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1567 if (other_tc
== other
->current_tc
) {
1568 other
->active_tc
.gpr
[sel
] = arg1
;
1570 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1574 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1576 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1577 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1579 if (other_tc
== other
->current_tc
) {
1580 other
->active_tc
.LO
[sel
] = arg1
;
1582 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1586 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1588 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1589 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1591 if (other_tc
== other
->current_tc
) {
1592 other
->active_tc
.HI
[sel
] = arg1
;
1594 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1598 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1600 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1601 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1603 if (other_tc
== other
->current_tc
) {
1604 other
->active_tc
.ACX
[sel
] = arg1
;
1606 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1610 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1612 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1613 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1615 if (other_tc
== other
->current_tc
) {
1616 other
->active_tc
.DSPControl
= arg1
;
1618 other
->tcs
[other_tc
].DSPControl
= arg1
;
1622 /* MIPS MT functions */
1623 target_ulong
helper_dmt(void)
1629 target_ulong
helper_emt(void)
1635 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1637 CPUState
*other_cs
= first_cpu
;
1638 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1640 CPU_FOREACH(other_cs
) {
1641 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1642 /* Turn off all VPEs except the one executing the dvpe. */
1643 if (&other_cpu
->env
!= env
) {
1644 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1645 mips_vpe_sleep(other_cpu
);
1651 target_ulong
helper_evpe(CPUMIPSState
*env
)
1653 CPUState
*other_cs
= first_cpu
;
1654 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1656 CPU_FOREACH(other_cs
) {
1657 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1659 if (&other_cpu
->env
!= env
1660 /* If the VPE is WFI, don't disturb its sleep. */
1661 && !mips_vpe_is_wfi(other_cpu
)) {
1662 /* Enable the VPE. */
1663 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1664 mips_vpe_wake(other_cpu
); /* And wake it up. */
1669 #endif /* !CONFIG_USER_ONLY */
1671 /* R6 Multi-threading */
1672 #ifndef CONFIG_USER_ONLY
1673 target_ulong
helper_dvp(CPUMIPSState
*env
)
1675 CPUState
*other_cs
= first_cpu
;
1676 target_ulong prev
= env
->CP0_VPControl
;
1678 if (!((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
1679 CPU_FOREACH(other_cs
) {
1680 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1681 /* Turn off all VPs except the one executing the dvp. */
1682 if (&other_cpu
->env
!= env
) {
1683 mips_vpe_sleep(other_cpu
);
1686 env
->CP0_VPControl
|= (1 << CP0VPCtl_DIS
);
1691 target_ulong
helper_evp(CPUMIPSState
*env
)
1693 CPUState
*other_cs
= first_cpu
;
1694 target_ulong prev
= env
->CP0_VPControl
;
1696 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
1697 CPU_FOREACH(other_cs
) {
1698 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1699 if ((&other_cpu
->env
!= env
) && !mips_vp_is_wfi(other_cpu
)) {
1701 * If the VP is WFI, don't disturb its sleep.
1702 * Otherwise, wake it up.
1704 mips_vpe_wake(other_cpu
);
1707 env
->CP0_VPControl
&= ~(1 << CP0VPCtl_DIS
);
1711 #endif /* !CONFIG_USER_ONLY */