4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
29 #include "libqos/libqos-pc.h"
30 #include "libqos/ahci.h"
31 #include "libqos/pci-pc.h"
33 #include "qemu-common.h"
34 #include "qapi/qmp/qdict.h"
35 #include "qemu/host-utils.h"
37 #include "hw/pci/pci_ids.h"
38 #include "hw/pci/pci_regs.h"
40 /* TODO actually test the results and get rid of this */
41 #define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__))
43 /* Test images sizes in MB */
44 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
45 #define TEST_IMAGE_SIZE_MB_SMALL 64
48 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
49 static char debug_path
[] = "/tmp/qtest-blkdebug.XXXXXX";
50 static char mig_socket
[] = "/tmp/qtest-migration.XXXXXX";
51 static bool ahci_pedantic
;
52 static const char *imgfmt
;
53 static unsigned test_image_size_mb
;
55 /*** Function Declarations ***/
56 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
57 static void ahci_test_pci_spec(AHCIQState
*ahci
);
58 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
60 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
61 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
62 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
66 static uint64_t mb_to_sectors(uint64_t image_size_mb
)
68 return (image_size_mb
* 1024 * 1024) / AHCI_SECTOR_SIZE
;
71 static void string_bswap16(uint16_t *s
, size_t bytes
)
73 g_assert_cmphex((bytes
& 1), ==, 0);
83 * Verify that the transfer did not corrupt our state at all.
85 static void verify_state(AHCIQState
*ahci
, uint64_t hba_old
)
88 uint32_t ahci_fingerprint
;
90 AHCICommandHeader cmd
;
92 ahci_fingerprint
= qpci_config_readl(ahci
->dev
, PCI_VENDOR_ID
);
93 g_assert_cmphex(ahci_fingerprint
, ==, ahci
->fingerprint
);
95 /* If we haven't initialized, this is as much as can be validated. */
100 hba_base
= (uint64_t)qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
101 g_assert_cmphex(hba_base
, ==, hba_old
);
103 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP
), ==, ahci
->cap
);
104 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP2
), ==, ahci
->cap2
);
106 for (i
= 0; i
< 32; i
++) {
107 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_FB
), ==,
109 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_CLB
), ==,
111 for (j
= 0; j
< 32; j
++) {
112 ahci_get_command_header(ahci
, i
, j
, &cmd
);
113 g_assert_cmphex(cmd
.prdtl
, ==, ahci
->port
[i
].prdtl
[j
]);
114 g_assert_cmphex(cmd
.ctba
, ==, ahci
->port
[i
].ctba
[j
]);
119 static void ahci_migrate(AHCIQState
*from
, AHCIQState
*to
, const char *uri
)
121 QOSState
*tmp
= to
->parent
;
122 QPCIDevice
*dev
= to
->dev
;
123 char *uri_local
= NULL
;
127 uri_local
= g_strdup_printf("%s%s", "unix:", mig_socket
);
131 hba_old
= (uint64_t)qpci_config_readl(from
->dev
, PCI_BASE_ADDRESS_5
);
133 /* context will be 'to' after completion. */
134 migrate(from
->parent
, to
->parent
, uri
);
136 /* We'd like for the AHCIState objects to still point
137 * to information specific to its specific parent
138 * instance, but otherwise just inherit the new data. */
139 memcpy(to
, from
, sizeof(AHCIQState
));
145 memset(from
, 0x00, sizeof(AHCIQState
));
149 verify_state(to
, hba_old
);
153 /*** Test Setup & Teardown ***/
156 * Start a Q35 machine and bookmark a handle to the AHCI device.
158 static GCC_FMT_ATTR(1, 0)
159 AHCIQState
*ahci_vboot(const char *cli
, va_list ap
)
163 s
= g_new0(AHCIQState
, 1);
164 s
->parent
= qtest_pc_vboot(cli
, ap
);
165 global_qtest
= s
->parent
->qts
;
166 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
168 /* Verify that we have an AHCI device present. */
169 s
->dev
= get_ahci_device(s
->parent
->qts
, &s
->fingerprint
);
175 * Start a Q35 machine and bookmark a handle to the AHCI device.
177 static GCC_FMT_ATTR(1, 0)
178 AHCIQState
*ahci_boot(const char *cli
, ...)
185 s
= ahci_vboot(cli
, ap
);
188 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,format=%s"
190 "-device ide-hd,drive=drive0 "
191 "-global ide-hd.serial=%s "
192 "-global ide-hd.ver=%s";
193 s
= ahci_boot(cli
, tmp_path
, imgfmt
, "testdisk", "version");
200 * Clean up the PCI device, then terminate the QEMU instance.
202 static void ahci_shutdown(AHCIQState
*ahci
)
204 QOSState
*qs
= ahci
->parent
;
207 ahci_clean_mem(ahci
);
208 free_ahci_device(ahci
->dev
);
214 * Boot and fully enable the HBA device.
215 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
217 static GCC_FMT_ATTR(1, 0)
218 AHCIQState
*ahci_boot_and_enable(const char *cli
, ...)
228 ahci
= ahci_vboot(cli
, ap
);
231 ahci
= ahci_boot(NULL
);
234 ahci_pci_enable(ahci
);
235 ahci_hba_enable(ahci
);
236 /* Initialize test device */
237 port
= ahci_port_select(ahci
);
238 ahci_port_clear(ahci
, port
);
239 if (is_atapi(ahci
, port
)) {
240 hello
= CMD_PACKET_ID
;
242 hello
= CMD_IDENTIFY
;
244 ahci_io(ahci
, port
, hello
, &buff
, sizeof(buff
), 0);
249 /*** Specification Adherence Tests ***/
252 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
254 static void ahci_test_pci_spec(AHCIQState
*ahci
)
260 /* Most of these bits should start cleared until we turn them on. */
261 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
262 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
263 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
264 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
265 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
266 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
267 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
268 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
269 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
270 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
271 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
273 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
274 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
275 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
276 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
277 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
278 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
279 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
280 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
281 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
282 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
283 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
285 /* RID occupies the low byte, CCs occupy the high three. */
286 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
288 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
289 * Though in practice this is likely seldom true. */
290 ASSERT_BIT_CLEAR(datal
, 0xFF);
293 /* BCC *must* equal 0x01. */
294 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
295 if (PCI_SCC(datal
) == 0x01) {
297 ASSERT_BIT_SET(0x80000000, datal
);
298 ASSERT_BIT_CLEAR(0x60000000, datal
);
299 } else if (PCI_SCC(datal
) == 0x04) {
301 g_assert_cmphex(PCI_PI(datal
), ==, 0);
302 } else if (PCI_SCC(datal
) == 0x06) {
304 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
306 g_assert_not_reached();
309 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
310 g_assert_cmphex(datab
, ==, 0);
312 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
313 g_assert_cmphex(datab
, ==, 0);
315 /* Only the bottom 7 bits must be off. */
316 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
317 ASSERT_BIT_CLEAR(datab
, 0x7F);
319 /* BIST is optional, but the low 7 bits must always start off regardless. */
320 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
321 ASSERT_BIT_CLEAR(datab
, 0x7F);
323 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
324 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
325 g_assert_cmphex(datal
, ==, 0);
327 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
328 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
329 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
330 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
331 ASSERT_BIT_CLEAR(datal
, 0xFF);
333 /* Capability list MUST be present, */
334 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
335 /* But these bits are reserved. */
336 ASSERT_BIT_CLEAR(datal
, ~0xFF);
337 g_assert_cmphex(datal
, !=, 0);
339 /* Check specification adherence for capability extenstions. */
340 data
= qpci_config_readw(ahci
->dev
, datal
);
342 switch (ahci
->fingerprint
) {
343 case AHCI_INTEL_ICH9
:
344 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
345 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
348 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
349 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
352 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
355 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
356 g_assert_cmphex(datal
, ==, 0);
358 /* IPIN might vary, but ILINE must be off. */
359 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
360 g_assert_cmphex(datab
, ==, 0);
364 * Test PCI capabilities for AHCI specification adherence.
366 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
369 uint8_t cid
= header
& 0xFF;
370 uint8_t next
= header
>> 8;
372 g_test_message("CID: %02x; next: %02x", cid
, next
);
376 ahci_test_pmcap(ahci
, offset
);
379 ahci_test_msicap(ahci
, offset
);
381 case PCI_CAP_ID_SATA
:
382 ahci_test_satacap(ahci
, offset
);
386 g_test_message("Unknown CAP 0x%02x", cid
);
390 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
395 * Test SATA PCI capabilitity for AHCI specification adherence.
397 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
402 g_test_message("Verifying SATACAP");
404 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
405 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
406 g_assert_cmphex(dataw
, ==, 0x10);
408 /* Grab the SATACR1 register. */
409 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
411 switch (datal
& 0x0F) {
412 case 0x04: /* BAR0 */
413 case 0x05: /* BAR1 */
417 case 0x09: /* BAR5 */
418 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
421 /* Invalid BARLOC for the Index Data Pair. */
422 g_assert_not_reached();
426 g_assert_cmphex((datal
>> 24), ==, 0x00);
430 * Test MSI PCI capability for AHCI specification adherence.
432 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
437 g_test_message("Verifying MSICAP");
439 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
440 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
441 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
442 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
444 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
445 g_assert_cmphex(datal
, ==, 0);
447 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
448 g_test_message("MSICAP is 64bit");
449 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
450 g_assert_cmphex(datal
, ==, 0);
451 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
452 g_assert_cmphex(dataw
, ==, 0);
454 g_test_message("MSICAP is 32bit");
455 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
456 g_assert_cmphex(dataw
, ==, 0);
461 * Test Power Management PCI capability for AHCI specification adherence.
463 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
467 g_test_message("Verifying PMCAP");
469 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
470 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
471 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
472 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
473 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
475 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
476 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
477 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
478 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
479 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
482 static void ahci_test_hba_spec(AHCIQState
*ahci
)
490 g_assert(ahci
!= NULL
);
493 * Note that the AHCI spec does expect the BIOS to set up a few things:
494 * CAP.SSS - Support for staggered spin-up (t/f)
495 * CAP.SMPS - Support for mechanical presence switches (t/f)
496 * PI - Ports Implemented (1-32)
497 * PxCMD.HPCP - Hot Plug Capable Port
498 * PxCMD.MPSP - Mechanical Presence Switch Present
499 * PxCMD.CPD - Cold Presence Detection support
501 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
502 * Foreach Port Implemented:
503 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
504 * -PxCLB/U and PxFB/U are set to valid regions in memory
505 * -PxSUD is set to 1.
506 * -PxSSTS.DET is polled for presence; if detected, we continue:
507 * -PxSERR is cleared with 1's.
508 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
509 * the device is ready.
512 /* 1 CAP - Capabilities Register */
513 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
514 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
516 /* 2 GHC - Global Host Control */
517 reg
= ahci_rreg(ahci
, AHCI_GHC
);
518 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
519 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
520 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
521 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
522 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
523 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
525 g_test_message("Supports AHCI/Legacy mix.");
526 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
529 /* 3 IS - Interrupt Status */
530 reg
= ahci_rreg(ahci
, AHCI_IS
);
531 g_assert_cmphex(reg
, ==, 0);
533 /* 4 PI - Ports Implemented */
534 ports
= ahci_rreg(ahci
, AHCI_PI
);
535 /* Ports Implemented must be non-zero. */
536 g_assert_cmphex(ports
, !=, 0);
537 /* Ports Implemented must be <= Number of Ports. */
538 nports_impl
= ctpopl(ports
);
539 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
541 /* Ports must be within the proper range. Given a mapping of SIZE,
542 * 256 bytes are used for global HBA control, and the rest is used
543 * for ports data, at 0x80 bytes each. */
544 g_assert_cmphex(ahci
->barsize
, >, 0);
545 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
546 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
547 g_assert_cmphex((reg
>> maxports
), ==, 0);
550 reg
= ahci_rreg(ahci
, AHCI_VS
);
552 case AHCI_VERSION_0_95
:
553 case AHCI_VERSION_1_0
:
554 case AHCI_VERSION_1_1
:
555 case AHCI_VERSION_1_2
:
556 case AHCI_VERSION_1_3
:
559 g_assert_not_reached();
562 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
563 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
564 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
565 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
566 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
567 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
568 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
570 g_assert_cmphex(reg
, ==, 0);
574 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
575 /* Must be zeroes initially regardless of CAP.CCCS */
576 g_assert_cmphex(reg
, ==, 0);
579 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
580 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
581 g_assert_cmphex(reg
, ==, 0);
585 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
586 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
587 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
588 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
589 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
590 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
592 g_assert_cmphex(reg
, ==, 0);
595 /* 10 CAP2 -- Capabilities Extended */
596 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
597 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
599 /* 11 BOHC -- Bios/OS Handoff Control */
600 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
601 g_assert_cmphex(reg
, ==, 0);
603 /* 12 -- 23: Reserved */
604 g_test_message("Verifying HBA reserved area is empty.");
605 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
606 reg
= ahci_rreg(ahci
, i
);
607 g_assert_cmphex(reg
, ==, 0);
610 /* 24 -- 39: NVMHCI */
611 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
612 g_test_message("Verifying HBA/NVMHCI area is empty.");
613 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
614 reg
= ahci_rreg(ahci
, i
);
615 g_assert_cmphex(reg
, ==, 0);
619 /* 40 -- 63: Vendor */
620 g_test_message("Verifying HBA/Vendor area is empty.");
621 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
622 reg
= ahci_rreg(ahci
, i
);
623 g_assert_cmphex(reg
, ==, 0);
626 /* 64 -- XX: Port Space */
627 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
628 if (BITSET(ports
, 0x1)) {
629 g_test_message("Testing port %u for spec", i
);
630 ahci_test_port_spec(ahci
, i
);
633 uint16_t low
= AHCI_PORTS
+ (32 * i
);
634 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
635 g_test_message("Asserting unimplemented port %u "
636 "(reg [%u-%u]) is empty.",
638 for (j
= low
; j
< high
; ++j
) {
639 reg
= ahci_rreg(ahci
, j
);
640 g_assert_cmphex(reg
, ==, 0);
647 * Test the memory space for one port for specification adherence.
649 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
655 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
656 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
659 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
660 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
661 g_assert_cmphex(reg
, ==, 0);
665 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
666 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
669 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
670 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
671 g_assert_cmphex(reg
, ==, 0);
675 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
676 g_assert_cmphex(reg
, ==, 0);
679 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
680 g_assert_cmphex(reg
, ==, 0);
683 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
684 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
685 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
686 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
687 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
688 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
689 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
690 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
691 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
692 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
693 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
694 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
695 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
696 /* If CPDetect support does not exist, CPState must be off. */
697 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
698 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
700 /* If MPSPresence is not set, MPSState must be off. */
701 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
702 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
704 /* If we do not support MPS, MPSS and MPSP must be off. */
705 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
706 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
707 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
709 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
710 if (BITANY(reg
, AHCI_PX_CMD_CPD
| AHCI_PX_CMD_MPSP
)) {
711 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
713 /* HPCP and ESP cannot both be active. */
714 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
715 /* If CAP.FBSS is not set, FBSCP must not be set. */
716 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
717 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
721 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
722 g_assert_cmphex(reg
, ==, 0);
725 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
726 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
727 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
728 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
729 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
730 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
731 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
732 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
733 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
734 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
737 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
738 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
739 * D2H register FIS and update the signature asynchronously,
740 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
742 /* (10) SSTS / SCR0: SStatus */
743 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
744 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
745 /* Even though the register should be 0 at boot, it is asynchronous and
746 * prone to change, so we cannot test any well known value. */
748 /* (11) SCTL / SCR2: SControl */
749 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
750 g_assert_cmphex(reg
, ==, 0);
752 /* (12) SERR / SCR1: SError */
753 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
754 g_assert_cmphex(reg
, ==, 0);
756 /* (13) SACT / SCR3: SActive */
757 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
758 g_assert_cmphex(reg
, ==, 0);
761 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
762 g_assert_cmphex(reg
, ==, 0);
765 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
766 g_assert_cmphex(reg
, ==, 0);
769 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
770 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
771 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
772 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
773 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
774 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
775 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
776 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
777 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
778 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
781 /* [17 -- 27] RESERVED */
782 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
783 reg
= ahci_px_rreg(ahci
, port
, i
);
784 g_assert_cmphex(reg
, ==, 0);
787 /* [28 -- 31] Vendor-Specific */
788 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
789 reg
= ahci_px_rreg(ahci
, port
, i
);
791 g_test_message("INFO: Vendor register %u non-empty", i
);
797 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
798 * device we see, then read and check the response.
800 static void ahci_test_identify(AHCIQState
*ahci
)
806 const size_t buffsize
= 512;
808 g_assert(ahci
!= NULL
);
811 * This serves as a bit of a tutorial on AHCI device programming:
813 * (1) Create a data buffer for the IDENTIFY response to be sent to
814 * (2) Create a Command Table buffer, where we will store the
815 * command and PRDT (Physical Region Descriptor Table)
816 * (3) Construct an FIS host-to-device command structure, and write it to
817 * the top of the Command Table buffer.
818 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
819 * a location in memory where data may be stored/retrieved.
820 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
821 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
822 * header that points to a Command Table buffer. Pick an unused slot
823 * and update it to point to the Command Table we have built.
824 * (7) Now: Command #n points to our Command Table, and our Command Table
825 * contains the FIS (that describes our command) and the PRDTL, which
826 * describes our buffer.
827 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
828 * #n is ready for processing.
831 /* Pick the first implemented and running port */
832 px
= ahci_port_select(ahci
);
833 g_test_message("Selected port %u for test", px
);
835 /* Clear out the FIS Receive area and any pending interrupts. */
836 ahci_port_clear(ahci
, px
);
838 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
839 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
, 0);
841 /* Check serial number/version in the buffer */
842 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
843 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
844 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
845 * as a consequence, only needs to unchunk the data on LE machines. */
846 string_bswap16(&buff
[10], 20);
847 rc
= memcmp(&buff
[10], "testdisk ", 20);
848 g_assert_cmphex(rc
, ==, 0);
850 string_bswap16(&buff
[23], 8);
851 rc
= memcmp(&buff
[23], "version ", 8);
852 g_assert_cmphex(rc
, ==, 0);
854 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
855 g_assert_cmphex(sect_size
, ==, AHCI_SECTOR_SIZE
);
858 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
859 uint64_t sector
, uint8_t read_cmd
,
864 unsigned char *tx
= g_malloc(bufsize
);
865 unsigned char *rx
= g_malloc0(bufsize
);
867 g_assert(ahci
!= NULL
);
869 /* Pick the first running port and clear it. */
870 port
= ahci_port_select(ahci
);
871 ahci_port_clear(ahci
, port
);
873 /*** Create pattern and transfer to guest ***/
874 /* Data buffer in the guest */
875 ptr
= ahci_alloc(ahci
, bufsize
);
878 /* Write some indicative pattern to our buffer. */
879 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
880 bufwrite(ptr
, tx
, bufsize
);
882 /* Write this buffer to disk, then read it back to the DMA buffer. */
883 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
, sector
);
884 qmemset(ptr
, 0x00, bufsize
);
885 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
, sector
);
887 /*** Read back the Data ***/
888 bufread(ptr
, rx
, bufsize
);
889 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
891 ahci_free(ahci
, ptr
);
896 static uint8_t ahci_test_nondata(AHCIQState
*ahci
, uint8_t ide_cmd
)
901 port
= ahci_port_select(ahci
);
902 ahci_port_clear(ahci
, port
);
904 ahci_io(ahci
, port
, ide_cmd
, NULL
, 0, 0);
909 static void ahci_test_flush(AHCIQState
*ahci
)
911 ahci_test_nondata(ahci
, CMD_FLUSH_CACHE
);
914 static void ahci_test_max(AHCIQState
*ahci
)
916 RegD2HFIS
*d2h
= g_malloc0(0x20);
920 uint64_t config_sect
= mb_to_sectors(test_image_size_mb
) - 1;
922 if (config_sect
> 0xFFFFFF) {
923 cmd
= CMD_READ_MAX_EXT
;
928 port
= ahci_test_nondata(ahci
, cmd
);
929 memread(ahci
->port
[port
].fb
+ 0x40, d2h
, 0x20);
930 nsect
= (uint64_t)d2h
->lba_hi
[2] << 40 |
931 (uint64_t)d2h
->lba_hi
[1] << 32 |
932 (uint64_t)d2h
->lba_hi
[0] << 24 |
933 (uint64_t)d2h
->lba_lo
[2] << 16 |
934 (uint64_t)d2h
->lba_lo
[1] << 8 |
935 (uint64_t)d2h
->lba_lo
[0];
937 g_assert_cmphex(nsect
, ==, config_sect
);
942 /******************************************************************************/
943 /* Test Interfaces */
944 /******************************************************************************/
947 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
949 static void test_sanity(void)
952 ahci
= ahci_boot(NULL
);
957 * Ensure that the PCI configuration space for the AHCI device is in-line with
958 * the AHCI 1.3 specification for initial values.
960 static void test_pci_spec(void)
963 ahci
= ahci_boot(NULL
);
964 ahci_test_pci_spec(ahci
);
969 * Engage the PCI AHCI device and sanity check the response.
970 * Perform additional PCI config space bringup for the HBA.
972 static void test_pci_enable(void)
975 ahci
= ahci_boot(NULL
);
976 ahci_pci_enable(ahci
);
981 * Investigate the memory mapped regions of the HBA,
982 * and test them for AHCI specification adherence.
984 static void test_hba_spec(void)
988 ahci
= ahci_boot(NULL
);
989 ahci_pci_enable(ahci
);
990 ahci_test_hba_spec(ahci
);
995 * Engage the HBA functionality of the AHCI PCI device,
996 * and bring it into a functional idle state.
998 static void test_hba_enable(void)
1002 ahci
= ahci_boot(NULL
);
1003 ahci_pci_enable(ahci
);
1004 ahci_hba_enable(ahci
);
1005 ahci_shutdown(ahci
);
1009 * Bring up the device and issue an IDENTIFY command.
1010 * Inspect the state of the HBA device and the data returned.
1012 static void test_identify(void)
1016 ahci
= ahci_boot_and_enable(NULL
);
1017 ahci_test_identify(ahci
);
1018 ahci_shutdown(ahci
);
1022 * Fragmented DMA test: Perform a standard 4K DMA read/write
1023 * test, but make sure the physical regions are fragmented to
1024 * be very small, each just 32 bytes, to see how AHCI performs
1025 * with chunks defined to be much less than a sector.
1027 static void test_dma_fragmented(void)
1032 size_t bufsize
= 4096;
1033 unsigned char *tx
= g_malloc(bufsize
);
1034 unsigned char *rx
= g_malloc0(bufsize
);
1037 ahci
= ahci_boot_and_enable(NULL
);
1038 px
= ahci_port_select(ahci
);
1039 ahci_port_clear(ahci
, px
);
1041 /* create pattern */
1042 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1044 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1045 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
1047 bufwrite(ptr
, tx
, bufsize
);
1049 cmd
= ahci_command_create(CMD_WRITE_DMA
);
1050 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1051 ahci_command_commit(ahci
, cmd
, px
);
1052 ahci_command_issue(ahci
, cmd
);
1053 ahci_command_verify(ahci
, cmd
);
1054 ahci_command_free(cmd
);
1056 cmd
= ahci_command_create(CMD_READ_DMA
);
1057 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1058 ahci_command_commit(ahci
, cmd
, px
);
1059 ahci_command_issue(ahci
, cmd
);
1060 ahci_command_verify(ahci
, cmd
);
1061 ahci_command_free(cmd
);
1063 /* Read back the guest's receive buffer into local memory */
1064 bufread(ptr
, rx
, bufsize
);
1065 guest_free(ahci
->parent
->alloc
, ptr
);
1067 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1069 ahci_shutdown(ahci
);
1076 * Write sector 1 with random data to make AHCI storage dirty
1077 * Needed for flush tests so that flushes actually go though the block layer
1079 static void make_dirty(AHCIQState
* ahci
, uint8_t port
)
1082 unsigned bufsize
= 512;
1084 ptr
= ahci_alloc(ahci
, bufsize
);
1087 ahci_guest_io(ahci
, port
, CMD_WRITE_DMA
, ptr
, bufsize
, 1);
1088 ahci_free(ahci
, ptr
);
1091 static void test_flush(void)
1096 ahci
= ahci_boot_and_enable(NULL
);
1098 port
= ahci_port_select(ahci
);
1099 ahci_port_clear(ahci
, port
);
1101 make_dirty(ahci
, port
);
1103 ahci_test_flush(ahci
);
1104 ahci_shutdown(ahci
);
1107 static void test_flush_retry(void)
1113 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1114 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1115 "format=%s,cache=writeback,"
1116 "rerror=stop,werror=stop "
1118 "-device ide-hd,drive=drive0 ",
1122 port
= ahci_port_select(ahci
);
1123 ahci_port_clear(ahci
, port
);
1125 /* Issue write so that flush actually goes to disk */
1126 make_dirty(ahci
, port
);
1128 /* Issue Flush Command and wait for error */
1129 cmd
= ahci_guest_io_halt(ahci
, port
, CMD_FLUSH_CACHE
, 0, 0, 0);
1130 ahci_guest_io_resume(ahci
, cmd
);
1132 ahci_shutdown(ahci
);
1136 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1138 static void test_migrate_sanity(void)
1140 AHCIQState
*src
, *dst
;
1141 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1143 src
= ahci_boot("-m 384 -M q35 "
1144 "-drive if=ide,file=%s,format=%s ", tmp_path
, imgfmt
);
1145 dst
= ahci_boot("-m 384 -M q35 "
1146 "-drive if=ide,file=%s,format=%s "
1147 "-incoming %s", tmp_path
, imgfmt
, uri
);
1149 ahci_migrate(src
, dst
, uri
);
1157 * Simple migration test: Write a pattern, migrate, then read.
1159 static void ahci_migrate_simple(uint8_t cmd_read
, uint8_t cmd_write
)
1161 AHCIQState
*src
, *dst
;
1163 size_t bufsize
= 4096;
1164 unsigned char *tx
= g_malloc(bufsize
);
1165 unsigned char *rx
= g_malloc0(bufsize
);
1166 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1168 src
= ahci_boot_and_enable("-m 384 -M q35 "
1169 "-drive if=ide,format=%s,file=%s ",
1171 dst
= ahci_boot("-m 384 -M q35 "
1172 "-drive if=ide,format=%s,file=%s "
1173 "-incoming %s", imgfmt
, tmp_path
, uri
);
1175 set_context(src
->parent
);
1178 px
= ahci_port_select(src
);
1179 ahci_port_clear(src
, px
);
1181 /* create pattern */
1182 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1184 /* Write, migrate, then read. */
1185 ahci_io(src
, px
, cmd_write
, tx
, bufsize
, 0);
1186 ahci_migrate(src
, dst
, uri
);
1187 ahci_io(dst
, px
, cmd_read
, rx
, bufsize
, 0);
1189 /* Verify pattern */
1190 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1199 static void test_migrate_dma(void)
1201 ahci_migrate_simple(CMD_READ_DMA
, CMD_WRITE_DMA
);
1204 static void test_migrate_ncq(void)
1206 ahci_migrate_simple(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1210 * Halted IO Error Test
1212 * Simulate an error on first write, Try to write a pattern,
1213 * Confirm the VM has stopped, resume the VM, verify command
1214 * has completed, then read back the data and verify.
1216 static void ahci_halted_io_test(uint8_t cmd_read
, uint8_t cmd_write
)
1220 size_t bufsize
= 4096;
1221 unsigned char *tx
= g_malloc(bufsize
);
1222 unsigned char *rx
= g_malloc0(bufsize
);
1226 prepare_blkdebug_script(debug_path
, "write_aio");
1228 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1229 "format=%s,cache=writeback,"
1230 "rerror=stop,werror=stop "
1232 "-device ide-hd,drive=drive0 ",
1236 /* Initialize and prepare */
1237 port
= ahci_port_select(ahci
);
1238 ahci_port_clear(ahci
, port
);
1240 /* create DMA source buffer and write pattern */
1241 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1242 ptr
= ahci_alloc(ahci
, bufsize
);
1244 memwrite(ptr
, tx
, bufsize
);
1246 /* Attempt to write (and fail) */
1247 cmd
= ahci_guest_io_halt(ahci
, port
, cmd_write
,
1250 /* Attempt to resume the command */
1251 ahci_guest_io_resume(ahci
, cmd
);
1252 ahci_free(ahci
, ptr
);
1254 /* Read back and verify */
1255 ahci_io(ahci
, port
, cmd_read
, rx
, bufsize
, 0);
1256 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1258 /* Cleanup and go home */
1259 ahci_shutdown(ahci
);
1264 static void test_halted_dma(void)
1266 ahci_halted_io_test(CMD_READ_DMA
, CMD_WRITE_DMA
);
1269 static void test_halted_ncq(void)
1271 ahci_halted_io_test(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1275 * IO Error Migration Test
1277 * Simulate an error on first write, Try to write a pattern,
1278 * Confirm the VM has stopped, migrate, resume the VM,
1279 * verify command has completed, then read back the data and verify.
1281 static void ahci_migrate_halted_io(uint8_t cmd_read
, uint8_t cmd_write
)
1283 AHCIQState
*src
, *dst
;
1285 size_t bufsize
= 4096;
1286 unsigned char *tx
= g_malloc(bufsize
);
1287 unsigned char *rx
= g_malloc0(bufsize
);
1290 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1292 prepare_blkdebug_script(debug_path
, "write_aio");
1294 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1295 "format=%s,cache=writeback,"
1296 "rerror=stop,werror=stop "
1298 "-device ide-hd,drive=drive0 ",
1302 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1303 "format=%s,cache=writeback,"
1304 "rerror=stop,werror=stop "
1306 "-device ide-hd,drive=drive0 "
1308 tmp_path
, imgfmt
, uri
);
1310 set_context(src
->parent
);
1312 /* Initialize and prepare */
1313 port
= ahci_port_select(src
);
1314 ahci_port_clear(src
, port
);
1315 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1317 /* create DMA source buffer and write pattern */
1318 ptr
= ahci_alloc(src
, bufsize
);
1320 memwrite(ptr
, tx
, bufsize
);
1322 /* Write, trigger the VM to stop, migrate, then resume. */
1323 cmd
= ahci_guest_io_halt(src
, port
, cmd_write
,
1325 ahci_migrate(src
, dst
, uri
);
1326 ahci_guest_io_resume(dst
, cmd
);
1327 ahci_free(dst
, ptr
);
1330 ahci_io(dst
, port
, cmd_read
, rx
, bufsize
, 0);
1332 /* Verify TX and RX are identical */
1333 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1335 /* Cleanup and go home. */
1343 static void test_migrate_halted_dma(void)
1345 ahci_migrate_halted_io(CMD_READ_DMA
, CMD_WRITE_DMA
);
1348 static void test_migrate_halted_ncq(void)
1350 ahci_migrate_halted_io(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1354 * Migration test: Try to flush, migrate, then resume.
1356 static void test_flush_migrate(void)
1358 AHCIQState
*src
, *dst
;
1361 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1363 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1365 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1366 "cache=writeback,rerror=stop,werror=stop,"
1369 "-device ide-hd,drive=drive0 ",
1370 debug_path
, tmp_path
, imgfmt
);
1371 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1372 "cache=writeback,rerror=stop,werror=stop,"
1375 "-device ide-hd,drive=drive0 "
1376 "-incoming %s", tmp_path
, imgfmt
, uri
);
1378 set_context(src
->parent
);
1380 px
= ahci_port_select(src
);
1381 ahci_port_clear(src
, px
);
1383 /* Dirty device so that flush reaches disk */
1384 make_dirty(src
, px
);
1386 /* Issue Flush Command */
1387 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1388 ahci_command_commit(src
, cmd
, px
);
1389 ahci_command_issue_async(src
, cmd
);
1390 qmp_eventwait("STOP");
1393 ahci_migrate(src
, dst
, uri
);
1395 /* Complete the command */
1396 qmp_send("{'execute':'cont' }");
1397 qmp_eventwait("RESUME");
1398 ahci_command_wait(dst
, cmd
);
1399 ahci_command_verify(dst
, cmd
);
1401 ahci_command_free(cmd
);
1407 static void test_max(void)
1411 ahci
= ahci_boot_and_enable(NULL
);
1412 ahci_test_max(ahci
);
1413 ahci_shutdown(ahci
);
1416 static void test_reset(void)
1421 ahci
= ahci_boot(NULL
);
1422 ahci_test_pci_spec(ahci
);
1423 ahci_pci_enable(ahci
);
1425 for (i
= 0; i
< 2; i
++) {
1426 ahci_test_hba_spec(ahci
);
1427 ahci_hba_enable(ahci
);
1428 ahci_test_identify(ahci
);
1429 ahci_test_io_rw_simple(ahci
, 4096, 0,
1432 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_HR
);
1433 ahci_clean_mem(ahci
);
1436 ahci_shutdown(ahci
);
1439 static void test_ncq_simple(void)
1443 ahci
= ahci_boot_and_enable(NULL
);
1444 ahci_test_io_rw_simple(ahci
, 4096, 0,
1446 WRITE_FPDMA_QUEUED
);
1447 ahci_shutdown(ahci
);
1450 static int prepare_iso(size_t size
, unsigned char **buf
, char **name
)
1452 char cdrom_path
[] = "/tmp/qtest.iso.XXXXXX";
1453 unsigned char *patt
;
1455 int fd
= mkstemp(cdrom_path
);
1459 patt
= g_malloc(size
);
1461 /* Generate a pattern and build a CDROM image to read from */
1462 generate_pattern(patt
, size
, ATAPI_SECTOR_SIZE
);
1463 ret
= write(fd
, patt
, size
);
1464 g_assert(ret
== size
);
1466 *name
= g_strdup(cdrom_path
);
1471 static void remove_iso(int fd
, char *name
)
1478 static int ahci_cb_cmp_buff(AHCIQState
*ahci
, AHCICommand
*cmd
,
1479 const AHCIOpts
*opts
)
1481 unsigned char *tx
= opts
->opaque
;
1488 rx
= g_malloc0(opts
->size
);
1489 bufread(opts
->buffer
, rx
, opts
->size
);
1490 g_assert_cmphex(memcmp(tx
, rx
, opts
->size
), ==, 0);
1496 static void ahci_test_cdrom(int nsectors
, bool dma
, uint8_t cmd
,
1497 bool override_bcl
, uint16_t bcl
)
1504 .size
= (ATAPI_SECTOR_SIZE
* nsectors
),
1507 .post_cb
= ahci_cb_cmp_buff
,
1508 .set_bcl
= override_bcl
,
1511 uint64_t iso_size
= ATAPI_SECTOR_SIZE
* (nsectors
+ 1);
1513 /* Prepare ISO and fill 'tx' buffer */
1514 fd
= prepare_iso(iso_size
, &tx
, &iso
);
1517 /* Standard startup wonkery, but use ide-cd and our special iso file */
1518 ahci
= ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1520 "-device ide-cd,drive=drive0 ", iso
);
1522 /* Build & Send AHCI command */
1523 ahci_exec(ahci
, ahci_port_select(ahci
), cmd
, &opts
);
1527 ahci_shutdown(ahci
);
1528 remove_iso(fd
, iso
);
1531 static void ahci_test_cdrom_read10(int nsectors
, bool dma
)
1533 ahci_test_cdrom(nsectors
, dma
, CMD_ATAPI_READ_10
, false, 0);
1536 static void test_cdrom_dma(void)
1538 ahci_test_cdrom_read10(1, true);
1541 static void test_cdrom_dma_multi(void)
1543 ahci_test_cdrom_read10(3, true);
1546 static void test_cdrom_pio(void)
1548 ahci_test_cdrom_read10(1, false);
1551 static void test_cdrom_pio_multi(void)
1553 ahci_test_cdrom_read10(3, false);
1556 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0
1557 * completes as a NOP instead of erroring out. */
1558 static void test_atapi_bcl(void)
1560 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD
, true, 0);
1564 static void atapi_wait_tray(bool open
)
1566 QDict
*rsp
= qmp_eventwait_ref("DEVICE_TRAY_MOVED");
1567 QDict
*data
= qdict_get_qdict(rsp
, "data");
1569 g_assert(qdict_get_bool(data
, "tray-open"));
1571 g_assert(!qdict_get_bool(data
, "tray-open"));
1576 static void test_atapi_tray(void)
1582 uint8_t port
, sense
, asc
;
1583 uint64_t iso_size
= ATAPI_SECTOR_SIZE
;
1586 fd
= prepare_iso(iso_size
, &tx
, &iso
);
1587 ahci
= ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1589 "-device ide-cd,id=cd0,drive=drive0 ", iso
);
1590 port
= ahci_port_select(ahci
);
1592 ahci_atapi_eject(ahci
, port
);
1593 atapi_wait_tray(true);
1595 ahci_atapi_load(ahci
, port
);
1596 atapi_wait_tray(false);
1599 qmp_send("{'execute': 'blockdev-open-tray',"
1600 " 'arguments': {'id': 'cd0'}}");
1601 atapi_wait_tray(true);
1602 rsp
= qmp_receive();
1605 qmp_discard_response("{'execute': 'blockdev-remove-medium', "
1606 "'arguments': {'id': 'cd0'}}");
1608 /* Test the tray without a medium */
1609 ahci_atapi_load(ahci
, port
);
1610 atapi_wait_tray(false);
1612 ahci_atapi_eject(ahci
, port
);
1613 atapi_wait_tray(true);
1615 /* Re-insert media */
1616 qmp_discard_response("{'execute': 'blockdev-add', "
1617 "'arguments': {'node-name': 'node0', "
1619 "'file': { 'driver': 'file', "
1620 "'filename': %s }}}", iso
);
1621 qmp_discard_response("{'execute': 'blockdev-insert-medium',"
1622 "'arguments': { 'id': 'cd0', "
1623 "'node-name': 'node0' }}");
1625 /* Again, the event shows up first */
1626 qmp_send("{'execute': 'blockdev-close-tray',"
1627 " 'arguments': {'id': 'cd0'}}");
1628 atapi_wait_tray(false);
1629 rsp
= qmp_receive();
1632 /* Now, to convince ATAPI we understand the media has changed... */
1633 ahci_atapi_test_ready(ahci
, port
, false, SENSE_NOT_READY
);
1634 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1635 g_assert_cmpuint(sense
, ==, SENSE_NOT_READY
);
1636 g_assert_cmpuint(asc
, ==, ASC_MEDIUM_NOT_PRESENT
);
1638 ahci_atapi_test_ready(ahci
, port
, false, SENSE_UNIT_ATTENTION
);
1639 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1640 g_assert_cmpuint(sense
, ==, SENSE_UNIT_ATTENTION
);
1641 g_assert_cmpuint(asc
, ==, ASC_MEDIUM_MAY_HAVE_CHANGED
);
1643 ahci_atapi_test_ready(ahci
, port
, true, SENSE_NO_SENSE
);
1644 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1645 g_assert_cmpuint(sense
, ==, SENSE_NO_SENSE
);
1647 /* Final tray test. */
1648 ahci_atapi_eject(ahci
, port
);
1649 atapi_wait_tray(true);
1651 ahci_atapi_load(ahci
, port
);
1652 atapi_wait_tray(false);
1656 ahci_shutdown(ahci
);
1657 remove_iso(fd
, iso
);
1660 /******************************************************************************/
1661 /* AHCI I/O Test Matrix Definitions */
1665 LEN_SIMPLE
= LEN_BEGIN
,
1672 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
1676 ADDR_MODE_BEGIN
= 0,
1677 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
1682 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
1686 MODE_PIO
= MODE_BEGIN
,
1691 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
1702 OFFSET_ZERO
= OFFSET_BEGIN
,
1708 static const char *offset_str
[NUM_OFFSETS
] = { "zero", "low", "high" };
1710 typedef struct AHCIIOTestOptions
{
1711 enum BuffLen length
;
1712 enum AddrMode address_type
;
1713 enum IOMode io_type
;
1714 enum OffsetType offset
;
1715 } AHCIIOTestOptions
;
1717 static uint64_t offset_sector(enum OffsetType ofst
,
1718 enum AddrMode addr_type
,
1730 ceil
= (addr_type
== ADDR_MODE_LBA28
) ? 0xfffffff : 0xffffffffffff;
1731 ceil
= MIN(ceil
, mb_to_sectors(test_image_size_mb
) - 1);
1732 nsectors
= buffsize
/ AHCI_SECTOR_SIZE
;
1733 return ceil
- nsectors
+ 1;
1735 g_assert_not_reached();
1740 * Table of possible I/O ATA commands given a set of enumerations.
1742 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
1744 [ADDR_MODE_LBA28
] = {
1745 [IO_READ
] = CMD_READ_PIO
,
1746 [IO_WRITE
] = CMD_WRITE_PIO
},
1747 [ADDR_MODE_LBA48
] = {
1748 [IO_READ
] = CMD_READ_PIO_EXT
,
1749 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
1752 [ADDR_MODE_LBA28
] = {
1753 [IO_READ
] = CMD_READ_DMA
,
1754 [IO_WRITE
] = CMD_WRITE_DMA
},
1755 [ADDR_MODE_LBA48
] = {
1756 [IO_READ
] = CMD_READ_DMA_EXT
,
1757 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
1762 * Test a Read/Write pattern using various commands, addressing modes,
1763 * transfer modes, and buffer sizes.
1765 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
1766 unsigned bufsize
, uint64_t sector
)
1770 ahci
= ahci_boot_and_enable(NULL
);
1771 ahci_test_io_rw_simple(ahci
, bufsize
, sector
,
1772 io_cmds
[dma
][lba48
][IO_READ
],
1773 io_cmds
[dma
][lba48
][IO_WRITE
]);
1774 ahci_shutdown(ahci
);
1778 * Demultiplex the test data and invoke the actual test routine.
1780 static void test_io_interface(gconstpointer opaque
)
1782 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1786 switch (opts
->length
) {
1794 bufsize
= 4096 * 64;
1800 g_assert_not_reached();
1803 sector
= offset_sector(opts
->offset
, opts
->address_type
, bufsize
);
1804 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
, sector
);
1809 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1810 enum BuffLen len
, enum OffsetType offset
)
1813 AHCIIOTestOptions
*opts
;
1815 opts
= g_new(AHCIIOTestOptions
, 1);
1817 opts
->address_type
= addr
;
1818 opts
->io_type
= type
;
1819 opts
->offset
= offset
;
1821 name
= g_strdup_printf("ahci/io/%s/%s/%s/%s",
1823 addr_mode_str
[addr
],
1825 offset_str
[offset
]);
1827 if ((addr
== ADDR_MODE_LBA48
) && (offset
== OFFSET_HIGH
) &&
1828 (mb_to_sectors(test_image_size_mb
) <= 0xFFFFFFF)) {
1829 g_test_message("%s: skipped; test image too small", name
);
1835 qtest_add_data_func(name
, opts
, test_io_interface
);
1839 /******************************************************************************/
1841 int main(int argc
, char **argv
)
1849 static struct option long_options
[] = {
1850 {"pedantic", no_argument
, 0, 'p' },
1854 /* Should be first to utilize g_test functionality, So we can see errors. */
1855 g_test_init(&argc
, &argv
, NULL
);
1858 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1869 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1870 g_assert_not_reached();
1874 /* Check architecture */
1875 arch
= qtest_get_arch();
1876 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1877 g_test_message("Skipping test for non-x86");
1881 /* Create a temporary image */
1882 fd
= mkstemp(tmp_path
);
1884 if (have_qemu_img()) {
1886 test_image_size_mb
= TEST_IMAGE_SIZE_MB_LARGE
;
1887 mkqcow2(tmp_path
, TEST_IMAGE_SIZE_MB_LARGE
);
1889 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1890 "skipping LBA48 high-sector tests");
1892 test_image_size_mb
= TEST_IMAGE_SIZE_MB_SMALL
;
1893 ret
= ftruncate(fd
, test_image_size_mb
* 1024 * 1024);
1898 /* Create temporary blkdebug instructions */
1899 fd
= mkstemp(debug_path
);
1903 /* Reserve a hollow file to use as a socket for migration tests */
1904 fd
= mkstemp(mig_socket
);
1909 qtest_add_func("/ahci/sanity", test_sanity
);
1910 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1911 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1912 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1913 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1914 qtest_add_func("/ahci/identify", test_identify
);
1916 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1917 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1918 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1919 for (m
= OFFSET_BEGIN
; m
< NUM_OFFSETS
; m
++) {
1920 create_ahci_io_test(i
, j
, k
, m
);
1926 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);
1928 qtest_add_func("/ahci/flush/simple", test_flush
);
1929 qtest_add_func("/ahci/flush/retry", test_flush_retry
);
1930 qtest_add_func("/ahci/flush/migrate", test_flush_migrate
);
1932 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity
);
1933 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma
);
1934 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma
);
1935 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma
);
1937 qtest_add_func("/ahci/max", test_max
);
1938 qtest_add_func("/ahci/reset", test_reset
);
1940 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple
);
1941 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq
);
1942 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq
);
1943 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq
);
1945 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma
);
1946 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi
);
1947 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio
);
1948 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi
);
1950 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl
);
1951 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray
);