target/mips/cpu.h

   1 #ifndef MIPS_CPU_H
   2 #define MIPS_CPU_H
   3
   4 #define ALIGNED_ONLY
   5
   6 #define CPUArchState struct CPUMIPSState
   7
   8 #include "qemu-common.h"
   9 #include "cpu-qom.h"
  10 #include "mips-defs.h"
  11 #include "exec/cpu-defs.h"
  12 #include "fpu/softfloat.h"
  13
  14 struct CPUMIPSState;
  15
  16 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  17
  18 /* MSA Context */
  19 #define MSA_WRLEN (128)
  20
  21 typedef union wr_t wr_t;
  22 union wr_t {
  23     int8_t  b[MSA_WRLEN/8];
  24     int16_t h[MSA_WRLEN/16];
  25     int32_t w[MSA_WRLEN/32];
  26     int64_t d[MSA_WRLEN/64];
  27 };
  28
  29 typedef union fpr_t fpr_t;
  30 union fpr_t {
  31     float64  fd;   /* ieee double precision */
  32     float32  fs[2];/* ieee single precision */
  33     uint64_t d;    /* binary double fixed-point */
  34     uint32_t w[2]; /* binary single fixed-point */
  35 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  36     wr_t     wr;   /* vector data */
  37 };
  38 /* define FP_ENDIAN_IDX to access the same location
  39  * in the fpr_t union regardless of the host endianness
  40  */
  41 #if defined(HOST_WORDS_BIGENDIAN)
  42 #  define FP_ENDIAN_IDX 1
  43 #else
  44 #  define FP_ENDIAN_IDX 0
  45 #endif
  46
  47 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  48 struct CPUMIPSFPUContext {
  49     /* Floating point registers */
  50     fpr_t fpr[32];
  51     float_status fp_status;
  52     /* fpu implementation/revision register (fir) */
  53     uint32_t fcr0;
  54 #define FCR0_FREP 29
  55 #define FCR0_UFRP 28
  56 #define FCR0_HAS2008 23
  57 #define FCR0_F64 22
  58 #define FCR0_L 21
  59 #define FCR0_W 20
  60 #define FCR0_3D 19
  61 #define FCR0_PS 18
  62 #define FCR0_D 17
  63 #define FCR0_S 16
  64 #define FCR0_PRID 8
  65 #define FCR0_REV 0
  66     /* fcsr */
  67     uint32_t fcr31_rw_bitmask;
  68     uint32_t fcr31;
  69 #define FCR31_FS 24
  70 #define FCR31_ABS2008 19
  71 #define FCR31_NAN2008 18
  72 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  73 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  74 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
  75 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  76 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  77 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  78 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
  79 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
  80 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
  81 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
  82 #define FP_INEXACT        1
  83 #define FP_UNDERFLOW      2
  84 #define FP_OVERFLOW       4
  85 #define FP_DIV0           8
  86 #define FP_INVALID        16
  87 #define FP_UNIMPLEMENTED  32
  88 };
  89
  90 #define NB_MMU_MODES 4
  91 #define TARGET_INSN_START_EXTRA_WORDS 2
  92
  93 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
  94 struct CPUMIPSMVPContext {
  95     int32_t CP0_MVPControl;
  96 #define CP0MVPCo_CPA    3
  97 #define CP0MVPCo_STLB   2
  98 #define CP0MVPCo_VPC    1
  99 #define CP0MVPCo_EVP    0
 100     int32_t CP0_MVPConf0;
 101 #define CP0MVPC0_M      31
 102 #define CP0MVPC0_TLBS   29
 103 #define CP0MVPC0_GS     28
 104 #define CP0MVPC0_PCP    27
 105 #define CP0MVPC0_PTLBE  16
 106 #define CP0MVPC0_TCA    15
 107 #define CP0MVPC0_PVPE   10
 108 #define CP0MVPC0_PTC    0
 109     int32_t CP0_MVPConf1;
 110 #define CP0MVPC1_CIM    31
 111 #define CP0MVPC1_CIF    30
 112 #define CP0MVPC1_PCX    20
 113 #define CP0MVPC1_PCP2   10
 114 #define CP0MVPC1_PCP1   0
 115 };
 116
 117 typedef struct mips_def_t mips_def_t;
 118
 119 #define MIPS_SHADOW_SET_MAX 16
 120 #define MIPS_TC_MAX 5
 121 #define MIPS_FPU_MAX 1
 122 #define MIPS_DSP_ACC 4
 123 #define MIPS_KSCRATCH_NUM 6
 124 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 125
 126 typedef struct TCState TCState;
 127 struct TCState {
 128     target_ulong gpr[32];
 129     target_ulong PC;
 130     target_ulong HI[MIPS_DSP_ACC];
 131     target_ulong LO[MIPS_DSP_ACC];
 132     target_ulong ACX[MIPS_DSP_ACC];
 133     target_ulong DSPControl;
 134     int32_t CP0_TCStatus;
 135 #define CP0TCSt_TCU3    31
 136 #define CP0TCSt_TCU2    30
 137 #define CP0TCSt_TCU1    29
 138 #define CP0TCSt_TCU0    28
 139 #define CP0TCSt_TMX     27
 140 #define CP0TCSt_RNST    23
 141 #define CP0TCSt_TDS     21
 142 #define CP0TCSt_DT      20
 143 #define CP0TCSt_DA      15
 144 #define CP0TCSt_A       13
 145 #define CP0TCSt_TKSU    11
 146 #define CP0TCSt_IXMT    10
 147 #define CP0TCSt_TASID   0
 148     int32_t CP0_TCBind;
 149 #define CP0TCBd_CurTC   21
 150 #define CP0TCBd_TBE     17
 151 #define CP0TCBd_CurVPE  0
 152     target_ulong CP0_TCHalt;
 153     target_ulong CP0_TCContext;
 154     target_ulong CP0_TCSchedule;
 155     target_ulong CP0_TCScheFBack;
 156     int32_t CP0_Debug_tcstatus;
 157     target_ulong CP0_UserLocal;
 158
 159     int32_t msacsr;
 160
 161 #define MSACSR_FS       24
 162 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 163 #define MSACSR_NX       18
 164 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 165 #define MSACSR_CEF      2
 166 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 167 #define MSACSR_RM       0
 168 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 169 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 170         MSACSR_FS_MASK)
 171
 172     float_status msa_fp_status;
 173
 174 #define NUMBER_OF_MXU_REGISTERS 16
 175     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
 176     target_ulong mxu_cr;
 177 #define MXU_CR_LC       31
 178 #define MXU_CR_RC       30
 179 #define MXU_CR_BIAS     2
 180 #define MXU_CR_RD_EN    1
 181 #define MXU_CR_MXU_EN   0
 182
 183 };
 184
 185 typedef struct CPUMIPSState CPUMIPSState;
 186 struct CPUMIPSState {
 187     TCState active_tc;
 188     CPUMIPSFPUContext active_fpu;
 189
 190     uint32_t current_tc;
 191     uint32_t current_fpu;
 192
 193     uint32_t SEGBITS;
 194     uint32_t PABITS;
 195 #if defined(TARGET_MIPS64)
 196 # define PABITS_BASE 36
 197 #else
 198 # define PABITS_BASE 32
 199 #endif
 200     target_ulong SEGMask;
 201     uint64_t PAMask;
 202 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 203
 204     int32_t msair;
 205 #define MSAIR_ProcID    8
 206 #define MSAIR_Rev       0
 207
 208 /*
 209  *     Summary of CP0 registers
 210  *     ========================
 211  *
 212  *
 213  *     Register 0        Register 1        Register 2        Register 3
 214  *     ----------        ----------        ----------        ----------
 215  *
 216  * 0   Index             Random            EntryLo0          EntryLo1
 217  * 1   MVPControl        VPEControl        TCStatus          GlobalNumber
 218  * 2   MVPConf0          VPEConf0          TCBind
 219  * 3   MVPConf1          VPEConf1          TCRestart
 220  * 4   VPControl         YQMask            TCHalt
 221  * 5                     VPESchedule       TCContext
 222  * 6                     VPEScheFBack      TCSchedule
 223  * 7                     VPEOpt            TCScheFBack       TCOpt
 224  *
 225  *
 226  *     Register 4        Register 5        Register 6        Register 7
 227  *     ----------        ----------        ----------        ----------
 228  *
 229  * 0   Context           PageMask          Wired             HWREna
 230  * 1   ContextConfig     PageGrain         SRSConf0
 231  * 2   UserLocal         SegCtl0           SRSConf1
 232  * 3   XContextConfig    SegCtl1           SRSConf2
 233  * 4   DebugContextID    SegCtl2           SRSConf3
 234  * 5   MemoryMapID       PWBase            SRSConf4
 235  * 6                     PWField           PWCtl
 236  * 7                     PWSize
 237  *
 238  *
 239  *     Register 8        Register 9        Register 10       Register 11
 240  *     ----------        ----------        -----------       -----------
 241  *
 242  * 0   BadVAddr          Count             EntryHi           Compare
 243  * 1   BadInstr
 244  * 2   BadInstrP
 245  * 3   BadInstrX
 246  * 4                                       GuestCtl1         GuestCtl0Ext
 247  * 5                                       GuestCtl2
 248  * 6                                       GuestCtl3
 249  * 7
 250  *
 251  *
 252  *     Register 12       Register 13       Register 14       Register 15
 253  *     -----------       -----------       -----------       -----------
 254  *
 255  * 0   Status            Cause             EPC               PRId
 256  * 1   IntCtl                                                EBase
 257  * 2   SRSCtl                              NestedEPC         CDMMBase
 258  * 3   SRSMap                                                CMGCRBase
 259  * 4   View_IPL          View_RIPL                           BEVVA
 260  * 5   SRSMap2           NestedExc
 261  * 6   GuestCtl0
 262  * 7   GTOffset
 263  *
 264  *
 265  *     Register 16       Register 17       Register 18       Register 19
 266  *     -----------       -----------       -----------       -----------
 267  *
 268  * 0   Config            LLAddr            WatchLo           WatchHi
 269  * 1   Config1           MAAR              WatchLo           WatchHi
 270  * 2   Config2           MAARI             WatchLo           WatchHi
 271  * 3   Config3                             WatchLo           WatchHi
 272  * 4   Config4                             WatchLo           WatchHi
 273  * 5   Config5                             WatchLo           WatchHi
 274  * 6                                       WatchLo           WatchHi
 275  * 7                                       WatchLo           WatchHi
 276  *
 277  *
 278  *     Register 20       Register 21       Register 22       Register 23
 279  *     -----------       -----------       -----------       -----------
 280  *
 281  * 0   XContext                                              Debug
 282  * 1                                                         TraceControl
 283  * 2                                                         TraceControl2
 284  * 3                                                         UserTraceData1
 285  * 4                                                         TraceIBPC
 286  * 5                                                         TraceDBPC
 287  * 6                                                         Debug2
 288  * 7
 289  *
 290  *
 291  *     Register 24       Register 25       Register 26       Register 27
 292  *     -----------       -----------       -----------       -----------
 293  *
 294  * 0   DEPC              PerfCnt            ErrCtl          CacheErr
 295  * 1                     PerfCnt
 296  * 2   TraceControl3     PerfCnt
 297  * 3   UserTraceData2    PerfCnt
 298  * 4                     PerfCnt
 299  * 5                     PerfCnt
 300  * 6                     PerfCnt
 301  * 7                     PerfCnt
 302  *
 303  *
 304  *     Register 28       Register 29       Register 30       Register 31
 305  *     -----------       -----------       -----------       -----------
 306  *
 307  * 0   DataLo            DataHi            ErrorEPC          DESAVE
 308  * 1   TagLo             TagHi
 309  * 2   DataLo            DataHi                              KScratch<n>
 310  * 3   TagLo             TagHi                               KScratch<n>
 311  * 4   DataLo            DataHi                              KScratch<n>
 312  * 5   TagLo             TagHi                               KScratch<n>
 313  * 6   DataLo            DataHi                              KScratch<n>
 314  * 7   TagLo             TagHi                               KScratch<n>
 315  *
 316  */
 317 /*
 318  * CP0 Register 0
 319  */
 320     int32_t CP0_Index;
 321     /* CP0_MVP* are per MVP registers. */
 322     int32_t CP0_VPControl;
 323 #define CP0VPCtl_DIS    0
 324 /*
 325  * CP0 Register 1
 326  */
 327     int32_t CP0_Random;
 328     int32_t CP0_VPEControl;
 329 #define CP0VPECo_YSI    21
 330 #define CP0VPECo_GSI    20
 331 #define CP0VPECo_EXCPT  16
 332 #define CP0VPECo_TE     15
 333 #define CP0VPECo_TargTC 0
 334     int32_t CP0_VPEConf0;
 335 #define CP0VPEC0_M      31
 336 #define CP0VPEC0_XTC    21
 337 #define CP0VPEC0_TCS    19
 338 #define CP0VPEC0_SCS    18
 339 #define CP0VPEC0_DSC    17
 340 #define CP0VPEC0_ICS    16
 341 #define CP0VPEC0_MVP    1
 342 #define CP0VPEC0_VPA    0
 343     int32_t CP0_VPEConf1;
 344 #define CP0VPEC1_NCX    20
 345 #define CP0VPEC1_NCP2   10
 346 #define CP0VPEC1_NCP1   0
 347     target_ulong CP0_YQMask;
 348     target_ulong CP0_VPESchedule;
 349     target_ulong CP0_VPEScheFBack;
 350     int32_t CP0_VPEOpt;
 351 #define CP0VPEOpt_IWX7  15
 352 #define CP0VPEOpt_IWX6  14
 353 #define CP0VPEOpt_IWX5  13
 354 #define CP0VPEOpt_IWX4  12
 355 #define CP0VPEOpt_IWX3  11
 356 #define CP0VPEOpt_IWX2  10
 357 #define CP0VPEOpt_IWX1  9
 358 #define CP0VPEOpt_IWX0  8
 359 #define CP0VPEOpt_DWX7  7
 360 #define CP0VPEOpt_DWX6  6
 361 #define CP0VPEOpt_DWX5  5
 362 #define CP0VPEOpt_DWX4  4
 363 #define CP0VPEOpt_DWX3  3
 364 #define CP0VPEOpt_DWX2  2
 365 #define CP0VPEOpt_DWX1  1
 366 #define CP0VPEOpt_DWX0  0
 367 /*
 368  * CP0 Register 2
 369  */
 370     uint64_t CP0_EntryLo0;
 371 /*
 372  * CP0 Register 3
 373  */
 374     uint64_t CP0_EntryLo1;
 375 #if defined(TARGET_MIPS64)
 376 # define CP0EnLo_RI 63
 377 # define CP0EnLo_XI 62
 378 #else
 379 # define CP0EnLo_RI 31
 380 # define CP0EnLo_XI 30
 381 #endif
 382     int32_t CP0_GlobalNumber;
 383 #define CP0GN_VPId 0
 384 /*
 385  * CP0 Register 4
 386  */
 387     target_ulong CP0_Context;
 388     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 389 /*
 390  * CP0 Register 5
 391  */
 392     int32_t CP0_PageMask;
 393     int32_t CP0_PageGrain_rw_bitmask;
 394     int32_t CP0_PageGrain;
 395 #define CP0PG_RIE 31
 396 #define CP0PG_XIE 30
 397 #define CP0PG_ELPA 29
 398 #define CP0PG_IEC 27
 399     target_ulong CP0_SegCtl0;
 400     target_ulong CP0_SegCtl1;
 401     target_ulong CP0_SegCtl2;
 402 #define CP0SC_PA        9
 403 #define CP0SC_PA_MASK   (0x7FULL << CP0SC_PA)
 404 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
 405 #define CP0SC_AM        4
 406 #define CP0SC_AM_MASK   (0x7ULL << CP0SC_AM)
 407 #define CP0SC_AM_UK     0ULL
 408 #define CP0SC_AM_MK     1ULL
 409 #define CP0SC_AM_MSK    2ULL
 410 #define CP0SC_AM_MUSK   3ULL
 411 #define CP0SC_AM_MUSUK  4ULL
 412 #define CP0SC_AM_USK    5ULL
 413 #define CP0SC_AM_UUSK   7ULL
 414 #define CP0SC_EU        3
 415 #define CP0SC_EU_MASK   (1ULL << CP0SC_EU)
 416 #define CP0SC_C         0
 417 #define CP0SC_C_MASK    (0x7ULL << CP0SC_C)
 418 #define CP0SC_MASK      (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 419                          CP0SC_PA_MASK)
 420 #define CP0SC_1GMASK    (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 421                          CP0SC_PA_1GMASK)
 422 #define CP0SC0_MASK     (CP0SC_MASK | (CP0SC_MASK << 16))
 423 #define CP0SC1_XAM      59
 424 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
 425 #define CP0SC1_MASK     (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
 426 #define CP0SC2_XR       56
 427 #define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)
 428 #define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
 429     target_ulong CP0_PWBase;
 430     target_ulong CP0_PWField;
 431 #if defined(TARGET_MIPS64)
 432 #define CP0PF_BDI  32    /* 37..32 */
 433 #define CP0PF_GDI  24    /* 29..24 */
 434 #define CP0PF_UDI  18    /* 23..18 */
 435 #define CP0PF_MDI  12    /* 17..12 */
 436 #define CP0PF_PTI  6     /* 11..6  */
 437 #define CP0PF_PTEI 0     /*  5..0  */
 438 #else
 439 #define CP0PF_GDW  24    /* 29..24 */
 440 #define CP0PF_UDW  18    /* 23..18 */
 441 #define CP0PF_MDW  12    /* 17..12 */
 442 #define CP0PF_PTW  6     /* 11..6  */
 443 #define CP0PF_PTEW 0     /*  5..0  */
 444 #endif
 445     target_ulong CP0_PWSize;
 446 #if defined(TARGET_MIPS64)
 447 #define CP0PS_BDW  32    /* 37..32 */
 448 #endif
 449 #define CP0PS_PS   30
 450 #define CP0PS_GDW  24    /* 29..24 */
 451 #define CP0PS_UDW  18    /* 23..18 */
 452 #define CP0PS_MDW  12    /* 17..12 */
 453 #define CP0PS_PTW  6     /* 11..6  */
 454 #define CP0PS_PTEW 0     /*  5..0  */
 455 /*
 456  * CP0 Register 6
 457  */
 458     int32_t CP0_Wired;
 459     int32_t CP0_PWCtl;
 460 #define CP0PC_PWEN      31
 461 #if defined(TARGET_MIPS64)
 462 #define CP0PC_PWDIREXT  30
 463 #define CP0PC_XK        28
 464 #define CP0PC_XS        27
 465 #define CP0PC_XU        26
 466 #endif
 467 #define CP0PC_DPH       7
 468 #define CP0PC_HUGEPG    6
 469 #define CP0PC_PSN       0     /*  5..0  */
 470     int32_t CP0_SRSConf0_rw_bitmask;
 471     int32_t CP0_SRSConf0;
 472 #define CP0SRSC0_M      31
 473 #define CP0SRSC0_SRS3   20
 474 #define CP0SRSC0_SRS2   10
 475 #define CP0SRSC0_SRS1   0
 476     int32_t CP0_SRSConf1_rw_bitmask;
 477     int32_t CP0_SRSConf1;
 478 #define CP0SRSC1_M      31
 479 #define CP0SRSC1_SRS6   20
 480 #define CP0SRSC1_SRS5   10
 481 #define CP0SRSC1_SRS4   0
 482     int32_t CP0_SRSConf2_rw_bitmask;
 483     int32_t CP0_SRSConf2;
 484 #define CP0SRSC2_M      31
 485 #define CP0SRSC2_SRS9   20
 486 #define CP0SRSC2_SRS8   10
 487 #define CP0SRSC2_SRS7   0
 488     int32_t CP0_SRSConf3_rw_bitmask;
 489     int32_t CP0_SRSConf3;
 490 #define CP0SRSC3_M      31
 491 #define CP0SRSC3_SRS12  20
 492 #define CP0SRSC3_SRS11  10
 493 #define CP0SRSC3_SRS10  0
 494     int32_t CP0_SRSConf4_rw_bitmask;
 495     int32_t CP0_SRSConf4;
 496 #define CP0SRSC4_SRS15  20
 497 #define CP0SRSC4_SRS14  10
 498 #define CP0SRSC4_SRS13  0
 499 /*
 500  * CP0 Register 7
 501  */
 502     int32_t CP0_HWREna;
 503 /*
 504  * CP0 Register 8
 505  */
 506     target_ulong CP0_BadVAddr;
 507     uint32_t CP0_BadInstr;
 508     uint32_t CP0_BadInstrP;
 509     uint32_t CP0_BadInstrX;
 510 /*
 511  * CP0 Register 9
 512  */
 513     int32_t CP0_Count;
 514 /*
 515  * CP0 Register 10
 516  */
 517     target_ulong CP0_EntryHi;
 518 #define CP0EnHi_EHINV 10
 519     target_ulong CP0_EntryHi_ASID_mask;
 520 /*
 521  * CP0 Register 11
 522  */
 523     int32_t CP0_Compare;
 524 /*
 525  * CP0 Register 12
 526  */
 527     int32_t CP0_Status;
 528 #define CP0St_CU3   31
 529 #define CP0St_CU2   30
 530 #define CP0St_CU1   29
 531 #define CP0St_CU0   28
 532 #define CP0St_RP    27
 533 #define CP0St_FR    26
 534 #define CP0St_RE    25
 535 #define CP0St_MX    24
 536 #define CP0St_PX    23
 537 #define CP0St_BEV   22
 538 #define CP0St_TS    21
 539 #define CP0St_SR    20
 540 #define CP0St_NMI   19
 541 #define CP0St_IM    8
 542 #define CP0St_KX    7
 543 #define CP0St_SX    6
 544 #define CP0St_UX    5
 545 #define CP0St_KSU   3
 546 #define CP0St_ERL   2
 547 #define CP0St_EXL   1
 548 #define CP0St_IE    0
 549     int32_t CP0_IntCtl;
 550 #define CP0IntCtl_IPTI 29
 551 #define CP0IntCtl_IPPCI 26
 552 #define CP0IntCtl_VS 5
 553     int32_t CP0_SRSCtl;
 554 #define CP0SRSCtl_HSS 26
 555 #define CP0SRSCtl_EICSS 18
 556 #define CP0SRSCtl_ESS 12
 557 #define CP0SRSCtl_PSS 6
 558 #define CP0SRSCtl_CSS 0
 559     int32_t CP0_SRSMap;
 560 #define CP0SRSMap_SSV7 28
 561 #define CP0SRSMap_SSV6 24
 562 #define CP0SRSMap_SSV5 20
 563 #define CP0SRSMap_SSV4 16
 564 #define CP0SRSMap_SSV3 12
 565 #define CP0SRSMap_SSV2 8
 566 #define CP0SRSMap_SSV1 4
 567 #define CP0SRSMap_SSV0 0
 568 /*
 569  * CP0 Register 13
 570  */
 571     int32_t CP0_Cause;
 572 #define CP0Ca_BD   31
 573 #define CP0Ca_TI   30
 574 #define CP0Ca_CE   28
 575 #define CP0Ca_DC   27
 576 #define CP0Ca_PCI  26
 577 #define CP0Ca_IV   23
 578 #define CP0Ca_WP   22
 579 #define CP0Ca_IP    8
 580 #define CP0Ca_IP_mask 0x0000FF00
 581 #define CP0Ca_EC    2
 582 /*
 583  * CP0 Register 14
 584  */
 585     target_ulong CP0_EPC;
 586 /*
 587  * CP0 Register 15
 588  */
 589     int32_t CP0_PRid;
 590     target_ulong CP0_EBase;
 591     target_ulong CP0_EBaseWG_rw_bitmask;
 592 #define CP0EBase_WG 11
 593     target_ulong CP0_CMGCRBase;
 594 /*
 595  * CP0 Register 16
 596  */
 597     int32_t CP0_Config0;
 598 #define CP0C0_M    31
 599 #define CP0C0_K23  28    /* 30..28 */
 600 #define CP0C0_KU   25    /* 27..25 */
 601 #define CP0C0_SB   21
 602 #define CP0C0_MDU  20
 603 #define CP0C0_MM   18
 604 #define CP0C0_BM   16
 605 #define CP0C0_Impl 16    /* 24..16 */
 606 #define CP0C0_BE   15
 607 #define CP0C0_AT   13    /* 14..13 */
 608 #define CP0C0_AR   10    /* 12..10 */
 609 #define CP0C0_MT   7     /*  9..7  */
 610 #define CP0C0_VI   3
 611 #define CP0C0_K0   0     /*  2..0  */
 612     int32_t CP0_Config1;
 613 #define CP0C1_M    31
 614 #define CP0C1_MMU  25    /* 30..25 */
 615 #define CP0C1_IS   22    /* 24..22 */
 616 #define CP0C1_IL   19    /* 21..19 */
 617 #define CP0C1_IA   16    /* 18..16 */
 618 #define CP0C1_DS   13    /* 15..13 */
 619 #define CP0C1_DL   10    /* 12..10 */
 620 #define CP0C1_DA   7     /*  9..7  */
 621 #define CP0C1_C2   6
 622 #define CP0C1_MD   5
 623 #define CP0C1_PC   4
 624 #define CP0C1_WR   3
 625 #define CP0C1_CA   2
 626 #define CP0C1_EP   1
 627 #define CP0C1_FP   0
 628     int32_t CP0_Config2;
 629 #define CP0C2_M    31
 630 #define CP0C2_TU   28    /* 30..28 */
 631 #define CP0C2_TS   24    /* 27..24 */
 632 #define CP0C2_TL   20    /* 23..20 */
 633 #define CP0C2_TA   16    /* 19..16 */
 634 #define CP0C2_SU   12    /* 15..12 */
 635 #define CP0C2_SS   8     /* 11..8  */
 636 #define CP0C2_SL   4     /*  7..4  */
 637 #define CP0C2_SA   0     /*  3..0  */
 638     int32_t CP0_Config3;
 639 #define CP0C3_M            31
 640 #define CP0C3_BPG          30
 641 #define CP0C3_CMGCR        29
 642 #define CP0C3_MSAP         28
 643 #define CP0C3_BP           27
 644 #define CP0C3_BI           26
 645 #define CP0C3_SC           25
 646 #define CP0C3_PW           24
 647 #define CP0C3_VZ           23
 648 #define CP0C3_IPLV         21    /* 22..21 */
 649 #define CP0C3_MMAR         18    /* 20..18 */
 650 #define CP0C3_MCU          17
 651 #define CP0C3_ISA_ON_EXC   16
 652 #define CP0C3_ISA          14    /* 15..14 */
 653 #define CP0C3_ULRI         13
 654 #define CP0C3_RXI          12
 655 #define CP0C3_DSP2P        11
 656 #define CP0C3_DSPP         10
 657 #define CP0C3_CTXTC        9
 658 #define CP0C3_ITL          8
 659 #define CP0C3_LPA          7
 660 #define CP0C3_VEIC         6
 661 #define CP0C3_VInt         5
 662 #define CP0C3_SP           4
 663 #define CP0C3_CDMM         3
 664 #define CP0C3_MT           2
 665 #define CP0C3_SM           1
 666 #define CP0C3_TL           0
 667     int32_t CP0_Config4;
 668     int32_t CP0_Config4_rw_bitmask;
 669 #define CP0C4_M            31
 670 #define CP0C4_IE           29    /* 30..29 */
 671 #define CP0C4_AE           28
 672 #define CP0C4_VTLBSizeExt  24    /* 27..24 */
 673 #define CP0C4_KScrExist    16
 674 #define CP0C4_MMUExtDef    14
 675 #define CP0C4_FTLBPageSize 8     /* 12..8  */
 676 /* bit layout if MMUExtDef=1 */
 677 #define CP0C4_MMUSizeExt   0     /*  7..0  */
 678 /* bit layout if MMUExtDef=2 */
 679 #define CP0C4_FTLBWays     4     /*  7..4  */
 680 #define CP0C4_FTLBSets     0     /*  3..0  */
 681     int32_t CP0_Config5;
 682     int32_t CP0_Config5_rw_bitmask;
 683 #define CP0C5_M            31
 684 #define CP0C5_K            30
 685 #define CP0C5_CV           29
 686 #define CP0C5_EVA          28
 687 #define CP0C5_MSAEn        27
 688 #define CP0C5_PMJ          23    /* 25..23 */
 689 #define CP0C5_WR2          22
 690 #define CP0C5_NMS          21
 691 #define CP0C5_ULS          20
 692 #define CP0C5_XPA          19
 693 #define CP0C5_CRCP         18
 694 #define CP0C5_MI           17
 695 #define CP0C5_GI           15    /* 16..15 */
 696 #define CP0C5_CA2          14
 697 #define CP0C5_XNP          13
 698 #define CP0C5_DEC          11
 699 #define CP0C5_L2C          10
 700 #define CP0C5_UFE          9
 701 #define CP0C5_FRE          8
 702 #define CP0C5_VP           7
 703 #define CP0C5_SBRI         6
 704 #define CP0C5_MVH          5
 705 #define CP0C5_LLB          4
 706 #define CP0C5_MRP          3
 707 #define CP0C5_UFR          2
 708 #define CP0C5_NFExists     0
 709     int32_t CP0_Config6;
 710     int32_t CP0_Config7;
 711     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 712     int32_t CP0_MAARI;
 713     /* XXX: Maybe make LLAddr per-TC? */
 714 /*
 715  * CP0 Register 17
 716  */
 717     uint64_t lladdr;
 718     target_ulong llval;
 719     target_ulong llnewval;
 720     uint64_t llval_wp;
 721     uint32_t llnewval_wp;
 722     target_ulong llreg;
 723     uint64_t CP0_LLAddr_rw_bitmask;
 724     int CP0_LLAddr_shift;
 725 /*
 726  * CP0 Register 18
 727  */
 728     target_ulong CP0_WatchLo[8];
 729 /*
 730  * CP0 Register 19
 731  */
 732     int32_t CP0_WatchHi[8];
 733 #define CP0WH_ASID 16
 734 /*
 735  * CP0 Register 20
 736  */
 737     target_ulong CP0_XContext;
 738     int32_t CP0_Framemask;
 739 /*
 740  * CP0 Register 23
 741  */
 742     int32_t CP0_Debug;
 743 #define CP0DB_DBD  31
 744 #define CP0DB_DM   30
 745 #define CP0DB_LSNM 28
 746 #define CP0DB_Doze 27
 747 #define CP0DB_Halt 26
 748 #define CP0DB_CNT  25
 749 #define CP0DB_IBEP 24
 750 #define CP0DB_DBEP 21
 751 #define CP0DB_IEXI 20
 752 #define CP0DB_VER  15
 753 #define CP0DB_DEC  10
 754 #define CP0DB_SSt  8
 755 #define CP0DB_DINT 5
 756 #define CP0DB_DIB  4
 757 #define CP0DB_DDBS 3
 758 #define CP0DB_DDBL 2
 759 #define CP0DB_DBp  1
 760 #define CP0DB_DSS  0
 761 /*
 762  * CP0 Register 24
 763  */
 764     target_ulong CP0_DEPC;
 765 /*
 766  * CP0 Register 25
 767  */
 768     int32_t CP0_Performance0;
 769 /*
 770  * CP0 Register 26
 771  */
 772     int32_t CP0_ErrCtl;
 773 #define CP0EC_WST 29
 774 #define CP0EC_SPR 28
 775 #define CP0EC_ITC 26
 776 /*
 777  * CP0 Register 28
 778  */
 779     uint64_t CP0_TagLo;
 780     int32_t CP0_DataLo;
 781 /*
 782  * CP0 Register 29
 783  */
 784     int32_t CP0_TagHi;
 785     int32_t CP0_DataHi;
 786 /*
 787  * CP0 Register 30
 788  */
 789     target_ulong CP0_ErrorEPC;
 790 /*
 791  * CP0 Register 31
 792  */
 793     int32_t CP0_DESAVE;
 794
 795     /* We waste some space so we can handle shadow registers like TCs. */
 796     TCState tcs[MIPS_SHADOW_SET_MAX];
 797     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 798     /* QEMU */
 799     int error_code;
 800 #define EXCP_TLB_NOMATCH   0x1
 801 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 802     uint32_t hflags;    /* CPU State */
 803     /* TMASK defines different execution modes */
 804 #define MIPS_HFLAG_TMASK  0x1F5807FF
 805 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 806     /* The KSU flags must be the lowest bits in hflags. The flag order
 807        must be the same as defined for CP0 Status. This allows to use
 808        the bits as the value of mmu_idx. */
 809 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 810 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 811 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 812 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 813 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 814 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 815 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 816 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 817 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 818     /* True if the MIPS IV COP1X instructions can be used.  This also
 819        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 820        and RSQRT.D.  */
 821 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 822 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 823 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 824 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 825 #define MIPS_HFLAG_M16_SHIFT 10
 826     /* If translation is interrupted between the branch instruction and
 827      * the delay slot, record what type of branch it is so that we can
 828      * resume translation properly.  It might be possible to reduce
 829      * this from three bits to two.  */
 830 #define MIPS_HFLAG_BMASK_BASE  0x803800
 831 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 832 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 833 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 834 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 835     /* Extra flags about the current pending branch.  */
 836 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 837 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 838 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 839 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 840 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 841 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 842 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 843     /* MIPS DSP resources access. */
 844 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
 845 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
 846 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
 847     /* Extra flag about HWREna register. */
 848 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 849 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 850 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 851 #define MIPS_HFLAG_MSA   0x1000000
 852 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 853 #define MIPS_HFLAG_ELPA  0x4000000
 854 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
 855 #define MIPS_HFLAG_ERL   0x10000000 /* error level flag */
 856     target_ulong btarget;        /* Jump / branch target               */
 857     target_ulong bcond;          /* Branch condition (if needed)       */
 858
 859     int SYNCI_Step; /* Address step size for SYNCI */
 860     int CCRes; /* Cycle count resolution/divisor */
 861     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 862     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 863     uint64_t insn_flags; /* Supported instruction set */
 864
 865     /* Fields up to this point are cleared by a CPU reset */
 866     struct {} end_reset_fields;
 867
 868     CPU_COMMON
 869
 870     /* Fields from here on are preserved across CPU reset. */
 871     CPUMIPSMVPContext *mvp;
 872 #if !defined(CONFIG_USER_ONLY)
 873     CPUMIPSTLBContext *tlb;
 874 #endif
 875
 876     const mips_def_t *cpu_model;
 877     void *irq[8];
 878     QEMUTimer *timer; /* Internal timer */
 879     MemoryRegion *itc_tag; /* ITC Configuration Tags */
 880     target_ulong exception_base; /* ExceptionBase input to the core */
 881 };
 882
 883 /**
 884  * MIPSCPU:
 885  * @env: #CPUMIPSState
 886  *
 887  * A MIPS CPU.
 888  */
 889 struct MIPSCPU {
 890     /*< private >*/
 891     CPUState parent_obj;
 892     /*< public >*/
 893
 894     CPUMIPSState env;
 895 };
 896
 897 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
 898 {
 899     return container_of(env, MIPSCPU, env);
 900 }
 901
 902 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
 903
 904 #define ENV_OFFSET offsetof(MIPSCPU, env)
 905
 906 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 907
 908 #define cpu_signal_handler cpu_mips_signal_handler
 909 #define cpu_list mips_cpu_list
 910
 911 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 912 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 913
 914 /* MMU modes definitions. We carefully match the indices with our
 915    hflags layout. */
 916 #define MMU_MODE0_SUFFIX _kernel
 917 #define MMU_MODE1_SUFFIX _super
 918 #define MMU_MODE2_SUFFIX _user
 919 #define MMU_MODE3_SUFFIX _error
 920 #define MMU_USER_IDX 2
 921
 922 static inline int hflags_mmu_index(uint32_t hflags)
 923 {
 924     if (hflags & MIPS_HFLAG_ERL) {
 925         return 3; /* ERL */
 926     } else {
 927         return hflags & MIPS_HFLAG_KSU;
 928     }
 929 }
 930
 931 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 932 {
 933     return hflags_mmu_index(env->hflags);
 934 }
 935
 936 #include "exec/cpu-all.h"
 937
 938 /* Memory access type :
 939  * may be needed for precise access rights control and precise exceptions.
 940  */
 941 enum {
 942     /* 1 bit to define user level / supervisor access */
 943     ACCESS_USER  = 0x00,
 944     ACCESS_SUPER = 0x01,
 945     /* 1 bit to indicate direction */
 946     ACCESS_STORE = 0x02,
 947     /* Type of instruction that generated the access */
 948     ACCESS_CODE  = 0x10, /* Code fetch access                */
 949     ACCESS_INT   = 0x20, /* Integer load/store access        */
 950     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 951 };
 952
 953 /* Exceptions */
 954 enum {
 955     EXCP_NONE          = -1,
 956     EXCP_RESET         = 0,
 957     EXCP_SRESET,
 958     EXCP_DSS,
 959     EXCP_DINT,
 960     EXCP_DDBL,
 961     EXCP_DDBS,
 962     EXCP_NMI,
 963     EXCP_MCHECK,
 964     EXCP_EXT_INTERRUPT, /* 8 */
 965     EXCP_DFWATCH,
 966     EXCP_DIB,
 967     EXCP_IWATCH,
 968     EXCP_AdEL,
 969     EXCP_AdES,
 970     EXCP_TLBF,
 971     EXCP_IBE,
 972     EXCP_DBp, /* 16 */
 973     EXCP_SYSCALL,
 974     EXCP_BREAK,
 975     EXCP_CpU,
 976     EXCP_RI,
 977     EXCP_OVERFLOW,
 978     EXCP_TRAP,
 979     EXCP_FPE,
 980     EXCP_DWATCH, /* 24 */
 981     EXCP_LTLBL,
 982     EXCP_TLBL,
 983     EXCP_TLBS,
 984     EXCP_DBE,
 985     EXCP_THREAD,
 986     EXCP_MDMX,
 987     EXCP_C2E,
 988     EXCP_CACHE, /* 32 */
 989     EXCP_DSPDIS,
 990     EXCP_MSADIS,
 991     EXCP_MSAFPE,
 992     EXCP_TLBXI,
 993     EXCP_TLBRI,
 994
 995     EXCP_LAST = EXCP_TLBRI,
 996 };
 997 /* Dummy exception for conditional stores.  */
 998 #define EXCP_SC 0x100
 999
1000 /*
1001  * This is an internally generated WAKE request line.
1002  * It is driven by the CPU itself. Raised when the MT
1003  * block wants to wake a VPE from an inactive state and
1004  * cleared when VPE goes from active to inactive.
1005  */
1006 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1007
1008 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1009
1010 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1011 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1012 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1013
1014 bool cpu_supports_cps_smp(const char *cpu_type);
1015 bool cpu_supports_isa(const char *cpu_type, unsigned int isa);
1016 void cpu_set_exception_base(int vp_index, target_ulong address);
1017
1018 /* mips_int.c */
1019 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1020
1021 /* helper.c */
1022 target_ulong exception_resume_pc (CPUMIPSState *env);
1023
1024 static inline void restore_snan_bit_mode(CPUMIPSState *env)
1025 {
1026     set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
1027                         &env->active_fpu.fp_status);
1028 }
1029
1030 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1031                                         target_ulong *cs_base, uint32_t *flags)
1032 {
1033     *pc = env->active_tc.PC;
1034     *cs_base = 0;
1035     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1036                             MIPS_HFLAG_HWRENA_ULR);
1037 }
1038
1039 #endif /* MIPS_CPU_H */